1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "mt7915.h" 7 #include "../dma.h" 8 #include "mac.h" 9 #include "mcu.h" 10 11 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 12 13 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 14 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 15 IEEE80211_RADIOTAP_HE_##f) 16 17 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 18 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 19 .radar_pattern = { 20 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 21 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 22 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 23 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 24 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 25 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 26 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 27 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 28 }, 29 }; 30 31 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 32 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 33 .radar_pattern = { 34 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 35 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 36 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 37 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 38 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 39 }, 40 }; 41 42 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 43 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 44 .radar_pattern = { 45 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 46 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 47 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 48 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 49 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 50 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 51 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 52 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 53 }, 54 }; 55 56 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 57 u16 idx, bool unicast) 58 { 59 struct mt7915_sta *sta; 60 struct mt76_wcid *wcid; 61 62 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 63 return NULL; 64 65 wcid = rcu_dereference(dev->mt76.wcid[idx]); 66 if (unicast || !wcid) 67 return wcid; 68 69 if (!wcid->sta) 70 return NULL; 71 72 sta = container_of(wcid, struct mt7915_sta, wcid); 73 if (!sta->vif) 74 return NULL; 75 76 return &sta->vif->sta.wcid; 77 } 78 79 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 80 { 81 } 82 83 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 84 { 85 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 86 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 87 88 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 89 0, 5000); 90 } 91 92 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 93 { 94 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 95 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 96 97 return MT_WTBL_LMAC_OFFS(wcid, dw); 98 } 99 100 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 101 { 102 static const u8 ac_to_tid[] = { 103 [IEEE80211_AC_BE] = 0, 104 [IEEE80211_AC_BK] = 1, 105 [IEEE80211_AC_VI] = 4, 106 [IEEE80211_AC_VO] = 6 107 }; 108 struct ieee80211_sta *sta; 109 struct mt7915_sta *msta; 110 struct rate_info *rate; 111 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 112 LIST_HEAD(sta_poll_list); 113 int i; 114 115 spin_lock_bh(&dev->sta_poll_lock); 116 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 117 spin_unlock_bh(&dev->sta_poll_lock); 118 119 rcu_read_lock(); 120 121 while (true) { 122 bool clear = false; 123 u32 addr, val; 124 u16 idx; 125 u8 bw; 126 127 spin_lock_bh(&dev->sta_poll_lock); 128 if (list_empty(&sta_poll_list)) { 129 spin_unlock_bh(&dev->sta_poll_lock); 130 break; 131 } 132 msta = list_first_entry(&sta_poll_list, 133 struct mt7915_sta, poll_list); 134 list_del_init(&msta->poll_list); 135 spin_unlock_bh(&dev->sta_poll_lock); 136 137 idx = msta->wcid.idx; 138 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 139 140 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 141 u32 tx_last = msta->airtime_ac[i]; 142 u32 rx_last = msta->airtime_ac[i + 4]; 143 144 msta->airtime_ac[i] = mt76_rr(dev, addr); 145 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 146 147 tx_time[i] = msta->airtime_ac[i] - tx_last; 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 q = mt76_connac_lmac_mapping(i); 169 u32 tx_cur = tx_time[q]; 170 u32 rx_cur = rx_time[q]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 } 217 218 rcu_read_unlock(); 219 } 220 221 static void 222 mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 223 struct ieee80211_radiotap_he *he, 224 __le32 *rxv) 225 { 226 u32 ru_h, ru_l; 227 u8 ru, offs = 0; 228 229 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0])); 230 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1])); 231 ru = (u8)(ru_l | ru_h << 4); 232 233 status->bw = RATE_INFO_BW_HE_RU; 234 235 switch (ru) { 236 case 0 ... 36: 237 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 238 offs = ru; 239 break; 240 case 37 ... 52: 241 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 242 offs = ru - 37; 243 break; 244 case 53 ... 60: 245 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 246 offs = ru - 53; 247 break; 248 case 61 ... 64: 249 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 250 offs = ru - 61; 251 break; 252 case 65 ... 66: 253 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 254 offs = ru - 65; 255 break; 256 case 67: 257 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 258 break; 259 case 68: 260 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 261 break; 262 } 263 264 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 265 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 266 le16_encode_bits(offs, 267 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 268 } 269 270 static void 271 mt7915_mac_decode_he_mu_radiotap(struct sk_buff *skb, __le32 *rxv) 272 { 273 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 274 static const struct ieee80211_radiotap_he_mu mu_known = { 275 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | 276 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | 277 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | 278 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN), 279 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN), 280 }; 281 struct ieee80211_radiotap_he_mu *he_mu = NULL; 282 283 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 284 285 he_mu = skb_push(skb, sizeof(mu_known)); 286 memcpy(he_mu, &mu_known, sizeof(mu_known)); 287 288 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) 289 290 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); 291 if (status->he_dcm) 292 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); 293 294 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | 295 MU_PREP(FLAGS2_SIG_B_SYMS_USERS, 296 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); 297 298 he_mu->ru_ch1[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU0); 299 300 if (status->bw >= RATE_INFO_BW_40) { 301 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); 302 he_mu->ru_ch2[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU1); 303 } 304 305 if (status->bw >= RATE_INFO_BW_80) { 306 he_mu->ru_ch1[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU2); 307 he_mu->ru_ch2[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU3); 308 } 309 } 310 311 static void 312 mt7915_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, u32 mode) 313 { 314 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 315 static const struct ieee80211_radiotap_he known = { 316 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 317 HE_BITS(DATA1_DATA_DCM_KNOWN) | 318 HE_BITS(DATA1_STBC_KNOWN) | 319 HE_BITS(DATA1_CODING_KNOWN) | 320 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 321 HE_BITS(DATA1_DOPPLER_KNOWN) | 322 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 323 HE_BITS(DATA1_BSS_COLOR_KNOWN), 324 .data2 = HE_BITS(DATA2_GI_KNOWN) | 325 HE_BITS(DATA2_TXBF_KNOWN) | 326 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 327 HE_BITS(DATA2_TXOP_KNOWN), 328 }; 329 struct ieee80211_radiotap_he *he = NULL; 330 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 331 332 status->flag |= RX_FLAG_RADIOTAP_HE; 333 334 he = skb_push(skb, sizeof(known)); 335 memcpy(he, &known, sizeof(known)); 336 337 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 338 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 339 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 340 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 341 le16_encode_bits(ltf_size, 342 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 343 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) 344 he->data5 |= HE_BITS(DATA5_TXBF); 345 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 346 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 347 348 switch (mode) { 349 case MT_PHY_TYPE_HE_SU: 350 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 351 HE_BITS(DATA1_UL_DL_KNOWN) | 352 HE_BITS(DATA1_BEAM_CHANGE_KNOWN); 353 354 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 355 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 356 break; 357 case MT_PHY_TYPE_HE_EXT_SU: 358 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 359 HE_BITS(DATA1_UL_DL_KNOWN); 360 361 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 362 break; 363 case MT_PHY_TYPE_HE_MU: 364 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 365 HE_BITS(DATA1_UL_DL_KNOWN); 366 367 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 368 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); 369 370 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 371 mt7915_mac_decode_he_mu_radiotap(skb, rxv); 372 break; 373 case MT_PHY_TYPE_HE_TB: 374 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 375 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 376 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 377 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 378 379 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | 380 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 381 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 382 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 383 384 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 385 break; 386 default: 387 break; 388 } 389 } 390 391 /* The HW does not translate the mac header to 802.3 for mesh point */ 392 static int mt7915_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 393 { 394 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 395 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 396 struct mt7915_sta *msta = (struct mt7915_sta *)status->wcid; 397 __le32 *rxd = (__le32 *)skb->data; 398 struct ieee80211_sta *sta; 399 struct ieee80211_vif *vif; 400 struct ieee80211_hdr hdr; 401 __le32 qos_ctrl, ht_ctrl; 402 403 if (FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, le32_to_cpu(rxd[3])) != 404 MT_RXD3_NORMAL_U2M) 405 return -EINVAL; 406 407 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 408 return -EINVAL; 409 410 if (!msta || !msta->vif) 411 return -EINVAL; 412 413 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 414 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 415 416 /* store the info from RXD and ethhdr to avoid being overridden */ 417 hdr.frame_control = FIELD_GET(MT_RXD6_FRAME_CONTROL, rxd[6]); 418 hdr.seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, rxd[8]); 419 qos_ctrl = FIELD_GET(MT_RXD8_QOS_CTL, rxd[8]); 420 ht_ctrl = FIELD_GET(MT_RXD9_HT_CONTROL, rxd[9]); 421 422 hdr.duration_id = 0; 423 ether_addr_copy(hdr.addr1, vif->addr); 424 ether_addr_copy(hdr.addr2, sta->addr); 425 switch (le16_to_cpu(hdr.frame_control) & 426 (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) { 427 case 0: 428 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 429 break; 430 case IEEE80211_FCTL_FROMDS: 431 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 432 break; 433 case IEEE80211_FCTL_TODS: 434 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 435 break; 436 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 437 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 438 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 439 break; 440 default: 441 break; 442 } 443 444 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 445 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 446 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 447 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 448 else if (eth_hdr->h_proto >= cpu_to_be16(ETH_P_802_3_MIN)) 449 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 450 else 451 skb_pull(skb, 2); 452 453 if (ieee80211_has_order(hdr.frame_control)) 454 memcpy(skb_push(skb, 2), &ht_ctrl, 2); 455 if (ieee80211_is_data_qos(hdr.frame_control)) 456 memcpy(skb_push(skb, 2), &qos_ctrl, 2); 457 if (ieee80211_has_a4(hdr.frame_control)) 458 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 459 else 460 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 461 462 return 0; 463 } 464 465 static int 466 mt7915_mac_fill_rx_rate(struct mt7915_dev *dev, 467 struct mt76_rx_status *status, 468 struct ieee80211_supported_band *sband, 469 __le32 *rxv) 470 { 471 u32 v0, v2; 472 u8 stbc, gi, bw, dcm, mode, nss; 473 int i, idx; 474 bool cck = false; 475 476 v0 = le32_to_cpu(rxv[0]); 477 v2 = le32_to_cpu(rxv[2]); 478 479 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); 480 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; 481 482 if (!is_mt7915(&dev->mt76)) { 483 stbc = FIELD_GET(MT_PRXV_HT_STBC, v0); 484 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v0); 485 mode = FIELD_GET(MT_PRXV_TX_MODE, v0); 486 dcm = FIELD_GET(MT_PRXV_DCM, v0); 487 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v0); 488 } else { 489 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2); 490 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2); 491 mode = FIELD_GET(MT_CRXV_TX_MODE, v2); 492 dcm = !!(idx & GENMASK(3, 0) & MT_PRXV_TX_DCM); 493 bw = FIELD_GET(MT_CRXV_FRAME_MODE, v2); 494 } 495 496 switch (mode) { 497 case MT_PHY_TYPE_CCK: 498 cck = true; 499 fallthrough; 500 case MT_PHY_TYPE_OFDM: 501 i = mt76_get_rate(&dev->mt76, sband, i, cck); 502 break; 503 case MT_PHY_TYPE_HT_GF: 504 case MT_PHY_TYPE_HT: 505 status->encoding = RX_ENC_HT; 506 if (gi) 507 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 508 if (i > 31) 509 return -EINVAL; 510 break; 511 case MT_PHY_TYPE_VHT: 512 status->nss = nss; 513 status->encoding = RX_ENC_VHT; 514 if (gi) 515 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 516 if (i > 9) 517 return -EINVAL; 518 break; 519 case MT_PHY_TYPE_HE_MU: 520 case MT_PHY_TYPE_HE_SU: 521 case MT_PHY_TYPE_HE_EXT_SU: 522 case MT_PHY_TYPE_HE_TB: 523 status->nss = nss; 524 status->encoding = RX_ENC_HE; 525 i &= GENMASK(3, 0); 526 527 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 528 status->he_gi = gi; 529 530 status->he_dcm = dcm; 531 break; 532 default: 533 return -EINVAL; 534 } 535 status->rate_idx = i; 536 537 switch (bw) { 538 case IEEE80211_STA_RX_BW_20: 539 break; 540 case IEEE80211_STA_RX_BW_40: 541 if (mode & MT_PHY_TYPE_HE_EXT_SU && 542 (idx & MT_PRXV_TX_ER_SU_106T)) { 543 status->bw = RATE_INFO_BW_HE_RU; 544 status->he_ru = 545 NL80211_RATE_INFO_HE_RU_ALLOC_106; 546 } else { 547 status->bw = RATE_INFO_BW_40; 548 } 549 break; 550 case IEEE80211_STA_RX_BW_80: 551 status->bw = RATE_INFO_BW_80; 552 break; 553 case IEEE80211_STA_RX_BW_160: 554 status->bw = RATE_INFO_BW_160; 555 break; 556 default: 557 return -EINVAL; 558 } 559 560 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 561 if (mode < MT_PHY_TYPE_HE_SU && gi) 562 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 563 564 return 0; 565 } 566 567 static int 568 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) 569 { 570 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 571 struct mt76_phy *mphy = &dev->mt76.phy; 572 struct mt7915_phy *phy = &dev->phy; 573 struct ieee80211_supported_band *sband; 574 __le32 *rxd = (__le32 *)skb->data; 575 __le32 *rxv = NULL; 576 u32 mode = 0; 577 u32 rxd0 = le32_to_cpu(rxd[0]); 578 u32 rxd1 = le32_to_cpu(rxd[1]); 579 u32 rxd2 = le32_to_cpu(rxd[2]); 580 u32 rxd3 = le32_to_cpu(rxd[3]); 581 u32 rxd4 = le32_to_cpu(rxd[4]); 582 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 583 bool unicast, insert_ccmp_hdr = false; 584 u8 remove_pad, amsdu_info; 585 bool hdr_trans; 586 u16 hdr_gap; 587 u16 seq_ctrl = 0; 588 u8 qos_ctl = 0; 589 __le16 fc = 0; 590 int i, idx; 591 592 memset(status, 0, sizeof(*status)); 593 594 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) { 595 mphy = dev->mt76.phy2; 596 if (!mphy) 597 return -EINVAL; 598 599 phy = mphy->priv; 600 status->ext_phy = true; 601 } 602 603 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 604 return -EINVAL; 605 606 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 607 return -EINVAL; 608 609 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 610 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 611 return -EINVAL; 612 613 /* ICV error or CCMP/BIP/WPI MIC error */ 614 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 615 status->flag |= RX_FLAG_ONLY_MONITOR; 616 617 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 618 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 619 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 620 621 if (status->wcid) { 622 struct mt7915_sta *msta; 623 624 msta = container_of(status->wcid, struct mt7915_sta, wcid); 625 spin_lock_bh(&dev->sta_poll_lock); 626 if (list_empty(&msta->poll_list)) 627 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 628 spin_unlock_bh(&dev->sta_poll_lock); 629 } 630 631 status->freq = mphy->chandef.chan->center_freq; 632 status->band = mphy->chandef.chan->band; 633 if (status->band == NL80211_BAND_5GHZ) 634 sband = &mphy->sband_5g.sband; 635 else 636 sband = &mphy->sband_2g.sband; 637 638 if (!sband->channels) 639 return -EINVAL; 640 641 if ((rxd0 & csum_mask) == csum_mask) 642 skb->ip_summed = CHECKSUM_UNNECESSARY; 643 644 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 645 status->flag |= RX_FLAG_FAILED_FCS_CRC; 646 647 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 648 status->flag |= RX_FLAG_MMIC_ERROR; 649 650 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 651 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 652 status->flag |= RX_FLAG_DECRYPTED; 653 status->flag |= RX_FLAG_IV_STRIPPED; 654 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 655 } 656 657 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 658 659 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 660 return -EINVAL; 661 662 rxd += 6; 663 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 664 u32 v0 = le32_to_cpu(rxd[0]); 665 u32 v2 = le32_to_cpu(rxd[2]); 666 667 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 668 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 669 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 670 671 rxd += 4; 672 if ((u8 *)rxd - skb->data >= skb->len) 673 return -EINVAL; 674 } 675 676 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 677 u8 *data = (u8 *)rxd; 678 679 if (status->flag & RX_FLAG_DECRYPTED) { 680 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 681 case MT_CIPHER_AES_CCMP: 682 case MT_CIPHER_CCMP_CCX: 683 case MT_CIPHER_CCMP_256: 684 insert_ccmp_hdr = 685 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 686 fallthrough; 687 case MT_CIPHER_TKIP: 688 case MT_CIPHER_TKIP_NO_MIC: 689 case MT_CIPHER_GCMP: 690 case MT_CIPHER_GCMP_256: 691 status->iv[0] = data[5]; 692 status->iv[1] = data[4]; 693 status->iv[2] = data[3]; 694 status->iv[3] = data[2]; 695 status->iv[4] = data[1]; 696 status->iv[5] = data[0]; 697 break; 698 default: 699 break; 700 } 701 } 702 rxd += 4; 703 if ((u8 *)rxd - skb->data >= skb->len) 704 return -EINVAL; 705 } 706 707 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 708 status->timestamp = le32_to_cpu(rxd[0]); 709 status->flag |= RX_FLAG_MACTIME_START; 710 711 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 712 status->flag |= RX_FLAG_AMPDU_DETAILS; 713 714 /* all subframes of an A-MPDU have the same timestamp */ 715 if (phy->rx_ampdu_ts != status->timestamp) { 716 if (!++phy->ampdu_ref) 717 phy->ampdu_ref++; 718 } 719 phy->rx_ampdu_ts = status->timestamp; 720 721 status->ampdu_ref = phy->ampdu_ref; 722 } 723 724 rxd += 2; 725 if ((u8 *)rxd - skb->data >= skb->len) 726 return -EINVAL; 727 } 728 729 /* RXD Group 3 - P-RXV */ 730 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 731 u32 v0, v1; 732 int ret; 733 734 rxv = rxd; 735 rxd += 2; 736 if ((u8 *)rxd - skb->data >= skb->len) 737 return -EINVAL; 738 739 v0 = le32_to_cpu(rxv[0]); 740 v1 = le32_to_cpu(rxv[1]); 741 742 if (v0 & MT_PRXV_HT_AD_CODE) 743 status->enc_flags |= RX_ENC_FLAG_LDPC; 744 745 status->chains = mphy->antenna_mask; 746 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 747 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 748 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 749 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 750 status->signal = status->chain_signal[0]; 751 752 for (i = 1; i < hweight8(mphy->antenna_mask); i++) { 753 if (!(status->chains & BIT(i))) 754 continue; 755 756 status->signal = max(status->signal, 757 status->chain_signal[i]); 758 } 759 760 /* RXD Group 5 - C-RXV */ 761 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 762 rxd += 18; 763 if ((u8 *)rxd - skb->data >= skb->len) 764 return -EINVAL; 765 } 766 767 if (!is_mt7915(&dev->mt76) || 768 (is_mt7915(&dev->mt76) && 769 (rxd1 & MT_RXD1_NORMAL_GROUP_5))) { 770 ret = mt7915_mac_fill_rx_rate(dev, status, sband, rxv); 771 if (ret < 0) 772 return ret; 773 } 774 } 775 776 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 777 status->amsdu = !!amsdu_info; 778 if (status->amsdu) { 779 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 780 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 781 } 782 783 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 784 if (hdr_trans && ieee80211_has_morefrags(fc)) { 785 if (mt7915_reverse_frag0_hdr_trans(skb, hdr_gap)) 786 return -EINVAL; 787 hdr_trans = false; 788 } else { 789 int pad_start = 0; 790 791 skb_pull(skb, hdr_gap); 792 if (!hdr_trans && status->amsdu) { 793 pad_start = ieee80211_get_hdrlen_from_skb(skb); 794 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 795 /* 796 * When header translation failure is indicated, 797 * the hardware will insert an extra 2-byte field 798 * containing the data length after the protocol 799 * type field. 800 */ 801 pad_start = 12; 802 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 803 pad_start += 4; 804 805 if (get_unaligned_be16(skb->data + pad_start) != 806 skb->len - pad_start - 2) 807 pad_start = 0; 808 } 809 810 if (pad_start) { 811 memmove(skb->data + 2, skb->data, pad_start); 812 skb_pull(skb, 2); 813 } 814 } 815 816 if (!hdr_trans) { 817 struct ieee80211_hdr *hdr; 818 819 if (insert_ccmp_hdr) { 820 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 821 822 mt76_insert_ccmp_hdr(skb, key_id); 823 } 824 825 hdr = mt76_skb_get_hdr(skb); 826 fc = hdr->frame_control; 827 if (ieee80211_is_data_qos(fc)) { 828 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 829 qos_ctl = *ieee80211_get_qos_ctl(hdr); 830 } 831 } else { 832 status->flag |= RX_FLAG_8023; 833 } 834 835 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 836 mt7915_mac_decode_he_radiotap(skb, rxv, mode); 837 838 if (!status->wcid || !ieee80211_is_data_qos(fc)) 839 return 0; 840 841 /* drop no data frame */ 842 if (fc & cpu_to_le16(IEEE80211_STYPE_NULLFUNC)) 843 return -EINVAL; 844 845 status->aggr = unicast && 846 !ieee80211_is_qos_nullfunc(fc); 847 status->qos_ctl = qos_ctl; 848 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 849 850 return 0; 851 } 852 853 static void 854 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 855 { 856 #ifdef CONFIG_NL80211_TESTMODE 857 struct mt7915_phy *phy = &dev->phy; 858 __le32 *rxd = (__le32 *)skb->data; 859 __le32 *rxv_hdr = rxd + 2; 860 __le32 *rxv = rxd + 4; 861 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 862 bool ext_phy; 863 s32 foe; 864 u8 snr; 865 int i; 866 867 ext_phy = FIELD_GET(MT_RXV_HDR_BAND_IDX, le32_to_cpu(rxv_hdr[1])); 868 if (ext_phy) 869 phy = mt7915_ext_phy(dev); 870 871 rcpi = le32_to_cpu(rxv[6]); 872 ib_rssi = le32_to_cpu(rxv[7]); 873 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 874 875 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 876 if (i == 3) 877 wb_rssi = le32_to_cpu(rxv[9]); 878 879 phy->test.last_rcpi[i] = rcpi & 0xff; 880 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 881 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 882 } 883 884 v20 = le32_to_cpu(rxv[20]); 885 v21 = le32_to_cpu(rxv[21]); 886 887 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 888 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 889 890 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 891 892 phy->test.last_freq_offset = foe; 893 phy->test.last_snr = snr; 894 #endif 895 896 dev_kfree_skb(skb); 897 } 898 899 static void 900 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 901 struct sk_buff *skb) 902 { 903 #ifdef CONFIG_NL80211_TESTMODE 904 struct mt76_testmode_data *td = &phy->mt76->test; 905 const struct ieee80211_rate *r; 906 u8 bw, mode, nss = td->tx_rate_nss; 907 u8 rate_idx = td->tx_rate_idx; 908 u16 rateval = 0; 909 u32 val; 910 bool cck = false; 911 int band; 912 913 if (skb != phy->mt76->test.tx_skb) 914 return; 915 916 switch (td->tx_rate_mode) { 917 case MT76_TM_TX_MODE_HT: 918 nss = 1 + (rate_idx >> 3); 919 mode = MT_PHY_TYPE_HT; 920 break; 921 case MT76_TM_TX_MODE_VHT: 922 mode = MT_PHY_TYPE_VHT; 923 break; 924 case MT76_TM_TX_MODE_HE_SU: 925 mode = MT_PHY_TYPE_HE_SU; 926 break; 927 case MT76_TM_TX_MODE_HE_EXT_SU: 928 mode = MT_PHY_TYPE_HE_EXT_SU; 929 break; 930 case MT76_TM_TX_MODE_HE_TB: 931 mode = MT_PHY_TYPE_HE_TB; 932 break; 933 case MT76_TM_TX_MODE_HE_MU: 934 mode = MT_PHY_TYPE_HE_MU; 935 break; 936 case MT76_TM_TX_MODE_CCK: 937 cck = true; 938 fallthrough; 939 case MT76_TM_TX_MODE_OFDM: 940 band = phy->mt76->chandef.chan->band; 941 if (band == NL80211_BAND_2GHZ && !cck) 942 rate_idx += 4; 943 944 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 945 val = cck ? r->hw_value_short : r->hw_value; 946 947 mode = val >> 8; 948 rate_idx = val & 0xff; 949 break; 950 default: 951 mode = MT_PHY_TYPE_OFDM; 952 break; 953 } 954 955 switch (phy->mt76->chandef.width) { 956 case NL80211_CHAN_WIDTH_40: 957 bw = 1; 958 break; 959 case NL80211_CHAN_WIDTH_80: 960 bw = 2; 961 break; 962 case NL80211_CHAN_WIDTH_80P80: 963 case NL80211_CHAN_WIDTH_160: 964 bw = 3; 965 break; 966 default: 967 bw = 0; 968 break; 969 } 970 971 if (td->tx_rate_stbc && nss == 1) { 972 nss++; 973 rateval |= MT_TX_RATE_STBC; 974 } 975 976 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 977 FIELD_PREP(MT_TX_RATE_MODE, mode) | 978 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 979 980 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 981 982 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 983 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 984 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 985 986 val = MT_TXD6_FIXED_BW | 987 FIELD_PREP(MT_TXD6_BW, bw) | 988 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 989 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 990 991 /* for HE_SU/HE_EXT_SU PPDU 992 * - 1x, 2x, 4x LTF + 0.8us GI 993 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 994 * for HE_MU PPDU 995 * - 2x, 4x LTF + 0.8us GI 996 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 997 * for HE_TB PPDU 998 * - 1x, 2x LTF + 1.6us GI 999 * - 4x LTF + 3.2us GI 1000 */ 1001 if (mode >= MT_PHY_TYPE_HE_SU) 1002 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 1003 1004 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 1005 val |= MT_TXD6_LDPC; 1006 1007 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 1008 txwi[6] |= cpu_to_le32(val); 1009 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 1010 phy->test.spe_idx)); 1011 #endif 1012 } 1013 1014 static void 1015 mt7915_mac_write_txwi_8023(struct mt7915_dev *dev, __le32 *txwi, 1016 struct sk_buff *skb, struct mt76_wcid *wcid) 1017 { 1018 1019 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1020 u8 fc_type, fc_stype; 1021 bool wmm = false; 1022 u32 val; 1023 1024 if (wcid->sta) { 1025 struct ieee80211_sta *sta; 1026 1027 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 1028 wmm = sta->wme; 1029 } 1030 1031 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 1032 FIELD_PREP(MT_TXD1_TID, tid); 1033 1034 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN) 1035 val |= MT_TXD1_ETH_802_3; 1036 1037 txwi[1] |= cpu_to_le32(val); 1038 1039 fc_type = IEEE80211_FTYPE_DATA >> 2; 1040 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 1041 1042 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 1043 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 1044 1045 txwi[2] |= cpu_to_le32(val); 1046 1047 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 1048 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 1049 txwi[7] |= cpu_to_le32(val); 1050 } 1051 1052 static void 1053 mt7915_mac_write_txwi_80211(struct mt7915_dev *dev, __le32 *txwi, 1054 struct sk_buff *skb, struct ieee80211_key_conf *key, 1055 bool *mcast) 1056 { 1057 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1058 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1059 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1060 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1061 __le16 fc = hdr->frame_control; 1062 u8 fc_type, fc_stype; 1063 u32 val; 1064 1065 *mcast = is_multicast_ether_addr(hdr->addr1); 1066 1067 if (ieee80211_is_action(fc) && 1068 mgmt->u.action.category == WLAN_CATEGORY_BACK && 1069 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 1070 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 1071 1072 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA); 1073 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK; 1074 } else if (ieee80211_is_back_req(hdr->frame_control)) { 1075 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr; 1076 u16 control = le16_to_cpu(bar->control); 1077 1078 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control); 1079 } 1080 1081 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 1082 FIELD_PREP(MT_TXD1_HDR_INFO, 1083 ieee80211_get_hdrlen_from_skb(skb) / 2) | 1084 FIELD_PREP(MT_TXD1_TID, tid); 1085 txwi[1] |= cpu_to_le32(val); 1086 1087 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 1088 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 1089 1090 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 1091 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 1092 FIELD_PREP(MT_TXD2_MULTICAST, *mcast); 1093 1094 if (key && *mcast && ieee80211_is_robust_mgmt_frame(skb) && 1095 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 1096 val |= MT_TXD2_BIP; 1097 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 1098 } 1099 1100 if (!ieee80211_is_data(fc) || *mcast || 1101 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 1102 val |= MT_TXD2_FIX_RATE; 1103 1104 txwi[2] |= cpu_to_le32(val); 1105 1106 if (ieee80211_is_beacon(fc)) { 1107 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 1108 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 1109 } 1110 1111 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 1112 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 1113 1114 if (ieee80211_is_back_req(hdr->frame_control)) { 1115 struct ieee80211_bar *bar; 1116 1117 bar = (struct ieee80211_bar *)skb->data; 1118 seqno = le16_to_cpu(bar->start_seq_num); 1119 } 1120 1121 val = MT_TXD3_SN_VALID | 1122 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 1123 txwi[3] |= cpu_to_le32(val); 1124 } 1125 1126 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 1127 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 1128 txwi[7] |= cpu_to_le32(val); 1129 } 1130 1131 static u16 1132 mt7915_mac_tx_rate_val(struct mt76_phy *mphy, struct ieee80211_vif *vif, 1133 bool beacon, bool mcast) 1134 { 1135 u8 mode = 0, band = mphy->chandef.chan->band; 1136 int rateidx = 0, mcast_rate; 1137 1138 if (beacon) { 1139 struct cfg80211_bitrate_mask *mask; 1140 1141 mask = &vif->bss_conf.beacon_tx_rate; 1142 if (hweight16(mask->control[band].he_mcs[0]) == 1) { 1143 rateidx = ffs(mask->control[band].he_mcs[0]) - 1; 1144 mode = MT_PHY_TYPE_HE_SU; 1145 goto out; 1146 } else if (hweight16(mask->control[band].vht_mcs[0]) == 1) { 1147 rateidx = ffs(mask->control[band].vht_mcs[0]) - 1; 1148 mode = MT_PHY_TYPE_VHT; 1149 goto out; 1150 } else if (hweight8(mask->control[band].ht_mcs[0]) == 1) { 1151 rateidx = ffs(mask->control[band].ht_mcs[0]) - 1; 1152 mode = MT_PHY_TYPE_HT; 1153 goto out; 1154 } else if (hweight32(mask->control[band].legacy) == 1) { 1155 rateidx = ffs(mask->control[band].legacy) - 1; 1156 goto legacy; 1157 } 1158 } 1159 1160 mcast_rate = vif->bss_conf.mcast_rate[band]; 1161 if (mcast && mcast_rate > 0) 1162 rateidx = mcast_rate - 1; 1163 else 1164 rateidx = ffs(vif->bss_conf.basic_rates) - 1; 1165 1166 legacy: 1167 rateidx = mt76_calculate_default_rate(mphy, rateidx); 1168 mode = rateidx >> 8; 1169 rateidx &= GENMASK(7, 0); 1170 1171 out: 1172 return FIELD_PREP(MT_TX_RATE_IDX, rateidx) | 1173 FIELD_PREP(MT_TX_RATE_MODE, mode); 1174 } 1175 1176 void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, 1177 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 1178 struct ieee80211_key_conf *key, bool beacon) 1179 { 1180 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1181 struct ieee80211_vif *vif = info->control.vif; 1182 struct mt76_phy *mphy = &dev->mphy; 1183 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY; 1184 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 1185 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1186 bool mcast = false; 1187 u16 tx_count = 15; 1188 u32 val; 1189 1190 if (vif) { 1191 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 1192 1193 omac_idx = mvif->mt76.omac_idx; 1194 wmm_idx = mvif->mt76.wmm_idx; 1195 } 1196 1197 if (ext_phy && dev->mt76.phy2) 1198 mphy = dev->mt76.phy2; 1199 1200 if (beacon) { 1201 p_fmt = MT_TX_TYPE_FW; 1202 q_idx = MT_LMAC_BCN0; 1203 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 1204 p_fmt = MT_TX_TYPE_CT; 1205 q_idx = MT_LMAC_ALTX0; 1206 } else { 1207 p_fmt = MT_TX_TYPE_CT; 1208 q_idx = wmm_idx * MT7915_MAX_WMM_SETS + 1209 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 1210 } 1211 1212 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 1213 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 1214 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 1215 txwi[0] = cpu_to_le32(val); 1216 1217 val = MT_TXD1_LONG_FORMAT | MT_TXD1_VTA | 1218 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 1219 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 1220 1221 if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) 1222 val |= MT_TXD1_TGID; 1223 1224 txwi[1] = cpu_to_le32(val); 1225 1226 txwi[2] = 0; 1227 1228 val = MT_TXD3_SW_POWER_MGMT | 1229 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 1230 if (key) 1231 val |= MT_TXD3_PROTECT_FRAME; 1232 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1233 val |= MT_TXD3_NO_ACK; 1234 1235 txwi[3] = cpu_to_le32(val); 1236 txwi[4] = 0; 1237 1238 val = FIELD_PREP(MT_TXD5_PID, pid); 1239 if (pid >= MT_PACKET_ID_FIRST) 1240 val |= MT_TXD5_TX_STATUS_HOST; 1241 txwi[5] = cpu_to_le32(val); 1242 1243 txwi[6] = 0; 1244 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0; 1245 1246 if (is_8023) 1247 mt7915_mac_write_txwi_8023(dev, txwi, skb, wcid); 1248 else 1249 mt7915_mac_write_txwi_80211(dev, txwi, skb, key, &mcast); 1250 1251 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) { 1252 u16 rate = mt7915_mac_tx_rate_val(mphy, vif, beacon, mcast); 1253 1254 /* hardware won't add HTC for mgmt/ctrl frame */ 1255 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); 1256 1257 val = MT_TXD6_FIXED_BW | 1258 FIELD_PREP(MT_TXD6_TX_RATE, rate); 1259 txwi[6] |= cpu_to_le32(val); 1260 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 1261 } 1262 1263 if (mt76_testmode_enabled(mphy)) 1264 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 1265 } 1266 1267 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1268 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1269 struct ieee80211_sta *sta, 1270 struct mt76_tx_info *tx_info) 1271 { 1272 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 1273 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1274 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1275 struct ieee80211_key_conf *key = info->control.hw_key; 1276 struct ieee80211_vif *vif = info->control.vif; 1277 struct mt76_txwi_cache *t; 1278 struct mt7915_txp *txp; 1279 int id, i, nbuf = tx_info->nbuf - 1; 1280 u8 *txwi = (u8 *)txwi_ptr; 1281 int pid; 1282 1283 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 1284 return -EINVAL; 1285 1286 if (!wcid) 1287 wcid = &dev->mt76.global_wcid; 1288 1289 if (sta) { 1290 struct mt7915_sta *msta; 1291 1292 msta = (struct mt7915_sta *)sta->drv_priv; 1293 1294 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 1295 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 1296 msta->jiffies = jiffies; 1297 } 1298 } 1299 1300 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 1301 t->skb = tx_info->skb; 1302 1303 id = mt76_token_consume(mdev, &t); 1304 if (id < 0) 1305 return id; 1306 1307 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1308 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, pid, key, 1309 false); 1310 1311 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE); 1312 for (i = 0; i < nbuf; i++) { 1313 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1314 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 1315 } 1316 txp->nbuf = nbuf; 1317 1318 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 1319 1320 if (!key) 1321 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1322 1323 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 1324 ieee80211_is_mgmt(hdr->frame_control)) 1325 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1326 1327 if (vif) { 1328 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 1329 1330 txp->bss_idx = mvif->mt76.idx; 1331 } 1332 1333 txp->token = cpu_to_le16(id); 1334 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 1335 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 1336 else 1337 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 1338 tx_info->skb = DMA_DUMMY_DATA; 1339 1340 /* pass partial skb header to fw */ 1341 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1342 tx_info->buf[1].skip_unmap = true; 1343 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1344 1345 return 0; 1346 } 1347 1348 static void 1349 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1350 { 1351 struct mt7915_sta *msta; 1352 u16 fc, tid; 1353 u32 val; 1354 1355 if (!sta || !sta->ht_cap.ht_supported) 1356 return; 1357 1358 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1])); 1359 if (tid >= 6) /* skip VO queue */ 1360 return; 1361 1362 val = le32_to_cpu(txwi[2]); 1363 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1364 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1365 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1366 return; 1367 1368 msta = (struct mt7915_sta *)sta->drv_priv; 1369 if (!test_and_set_bit(tid, &msta->ampdu_state)) 1370 ieee80211_start_tx_ba_session(sta, tid, 0); 1371 } 1372 1373 static void 1374 mt7915_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1375 { 1376 struct mt7915_txp *txp; 1377 int i; 1378 1379 txp = mt7915_txwi_to_txp(dev, t); 1380 for (i = 0; i < txp->nbuf; i++) 1381 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), 1382 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); 1383 } 1384 1385 static void 1386 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t, 1387 struct ieee80211_sta *sta, struct list_head *free_list) 1388 { 1389 struct mt76_dev *mdev = &dev->mt76; 1390 struct mt76_wcid *wcid; 1391 __le32 *txwi; 1392 u16 wcid_idx; 1393 1394 mt7915_txp_skb_unmap(mdev, t); 1395 if (!t->skb) 1396 goto out; 1397 1398 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1399 if (sta) { 1400 wcid = (struct mt76_wcid *)sta->drv_priv; 1401 wcid_idx = wcid->idx; 1402 1403 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1404 mt7915_tx_check_aggr(sta, txwi); 1405 } else { 1406 wcid_idx = FIELD_GET(MT_TXD1_WLAN_IDX, le32_to_cpu(txwi[1])); 1407 } 1408 1409 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1410 1411 out: 1412 t->skb = NULL; 1413 mt76_put_txwi(mdev, t); 1414 } 1415 1416 static void 1417 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 1418 { 1419 struct mt7915_tx_free *free = (struct mt7915_tx_free *)data; 1420 struct mt76_dev *mdev = &dev->mt76; 1421 struct mt76_phy *mphy_ext = mdev->phy2; 1422 struct mt76_txwi_cache *txwi; 1423 struct ieee80211_sta *sta = NULL; 1424 LIST_HEAD(free_list); 1425 struct sk_buff *skb, *tmp; 1426 void *end = data + len; 1427 bool v3, wake = false; 1428 u16 total, count = 0; 1429 u32 txd = le32_to_cpu(free->txd); 1430 u32 *cur_info; 1431 1432 /* clean DMA queues and unmap buffers first */ 1433 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1434 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1435 if (mphy_ext) { 1436 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 1437 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 1438 } 1439 1440 /* 1441 * TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE, 1442 * to the time ack is received or dropped by hw (air + hw queue time). 1443 * Should avoid accessing WTBL to get Tx airtime, and use it instead. 1444 */ 1445 total = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl)); 1446 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 1447 if (WARN_ON_ONCE((void *)&free->info[total >> v3] > end)) 1448 return; 1449 1450 for (cur_info = &free->info[0]; count < total; cur_info++) { 1451 u32 msdu, info = le32_to_cpu(*cur_info); 1452 u8 i; 1453 1454 /* 1455 * 1'b1: new wcid pair. 1456 * 1'b0: msdu_id with the same 'wcid pair' as above. 1457 */ 1458 if (info & MT_TX_FREE_PAIR) { 1459 struct mt7915_sta *msta; 1460 struct mt76_wcid *wcid; 1461 u16 idx; 1462 1463 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 1464 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1465 sta = wcid_to_sta(wcid); 1466 if (!sta) 1467 continue; 1468 1469 msta = container_of(wcid, struct mt7915_sta, wcid); 1470 spin_lock_bh(&dev->sta_poll_lock); 1471 if (list_empty(&msta->poll_list)) 1472 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1473 spin_unlock_bh(&dev->sta_poll_lock); 1474 continue; 1475 } 1476 1477 if (v3 && (info & MT_TX_FREE_MPDU_HEADER)) 1478 continue; 1479 1480 for (i = 0; i < 1 + v3; i++) { 1481 if (v3) { 1482 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 1483 if (msdu == MT_TX_FREE_MSDU_ID_V3) 1484 continue; 1485 } else { 1486 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 1487 } 1488 count++; 1489 txwi = mt76_token_release(mdev, msdu, &wake); 1490 if (!txwi) 1491 continue; 1492 1493 mt7915_txwi_free(dev, txwi, sta, &free_list); 1494 } 1495 } 1496 1497 mt7915_mac_sta_poll(dev); 1498 1499 if (wake) 1500 mt76_set_tx_blocked(&dev->mt76, false); 1501 1502 mt76_worker_schedule(&dev->mt76.tx_worker); 1503 1504 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1505 skb_list_del_init(skb); 1506 napi_consume_skb(skb, 1); 1507 } 1508 } 1509 1510 static bool 1511 mt7915_mac_add_txs_skb(struct mt7915_dev *dev, struct mt76_wcid *wcid, int pid, 1512 __le32 *txs_data, struct mt76_sta_stats *stats) 1513 { 1514 struct ieee80211_supported_band *sband; 1515 struct mt76_dev *mdev = &dev->mt76; 1516 struct mt76_phy *mphy; 1517 struct ieee80211_tx_info *info; 1518 struct sk_buff_head list; 1519 struct rate_info rate = {}; 1520 struct sk_buff *skb; 1521 bool cck = false; 1522 u32 txrate, txs, mode; 1523 1524 mt76_tx_status_lock(mdev, &list); 1525 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1526 if (!skb) 1527 goto out_no_skb; 1528 1529 txs = le32_to_cpu(txs_data[0]); 1530 1531 info = IEEE80211_SKB_CB(skb); 1532 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1533 info->flags |= IEEE80211_TX_STAT_ACK; 1534 1535 info->status.ampdu_len = 1; 1536 info->status.ampdu_ack_len = !!(info->flags & 1537 IEEE80211_TX_STAT_ACK); 1538 1539 info->status.rates[0].idx = -1; 1540 1541 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1542 1543 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1544 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1545 1546 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1547 stats->tx_nss[rate.nss - 1]++; 1548 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1549 stats->tx_mcs[rate.mcs]++; 1550 1551 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1552 switch (mode) { 1553 case MT_PHY_TYPE_CCK: 1554 cck = true; 1555 fallthrough; 1556 case MT_PHY_TYPE_OFDM: 1557 mphy = &dev->mphy; 1558 if (wcid->ext_phy && dev->mt76.phy2) 1559 mphy = dev->mt76.phy2; 1560 1561 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1562 sband = &mphy->sband_5g.sband; 1563 else 1564 sband = &mphy->sband_2g.sband; 1565 1566 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1567 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1568 break; 1569 case MT_PHY_TYPE_HT: 1570 case MT_PHY_TYPE_HT_GF: 1571 if (rate.mcs > 31) 1572 goto out; 1573 1574 rate.flags = RATE_INFO_FLAGS_MCS; 1575 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1576 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1577 break; 1578 case MT_PHY_TYPE_VHT: 1579 if (rate.mcs > 9) 1580 goto out; 1581 1582 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1583 break; 1584 case MT_PHY_TYPE_HE_SU: 1585 case MT_PHY_TYPE_HE_EXT_SU: 1586 case MT_PHY_TYPE_HE_TB: 1587 case MT_PHY_TYPE_HE_MU: 1588 if (rate.mcs > 11) 1589 goto out; 1590 1591 rate.he_gi = wcid->rate.he_gi; 1592 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1593 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1594 break; 1595 default: 1596 goto out; 1597 } 1598 1599 stats->tx_mode[mode]++; 1600 1601 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1602 case IEEE80211_STA_RX_BW_160: 1603 rate.bw = RATE_INFO_BW_160; 1604 stats->tx_bw[3]++; 1605 break; 1606 case IEEE80211_STA_RX_BW_80: 1607 rate.bw = RATE_INFO_BW_80; 1608 stats->tx_bw[2]++; 1609 break; 1610 case IEEE80211_STA_RX_BW_40: 1611 rate.bw = RATE_INFO_BW_40; 1612 stats->tx_bw[1]++; 1613 break; 1614 default: 1615 rate.bw = RATE_INFO_BW_20; 1616 stats->tx_bw[0]++; 1617 break; 1618 } 1619 wcid->rate = rate; 1620 1621 out: 1622 mt76_tx_status_skb_done(mdev, skb, &list); 1623 1624 out_no_skb: 1625 mt76_tx_status_unlock(mdev, &list); 1626 1627 return !!skb; 1628 } 1629 1630 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1631 { 1632 struct mt7915_sta *msta = NULL; 1633 struct mt76_wcid *wcid; 1634 __le32 *txs_data = data; 1635 u16 wcidx; 1636 u32 txs; 1637 u8 pid; 1638 1639 txs = le32_to_cpu(txs_data[0]); 1640 if (FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1) 1641 return; 1642 1643 txs = le32_to_cpu(txs_data[2]); 1644 wcidx = FIELD_GET(MT_TXS2_WCID, txs); 1645 1646 txs = le32_to_cpu(txs_data[3]); 1647 pid = FIELD_GET(MT_TXS3_PID, txs); 1648 1649 if (pid < MT_PACKET_ID_FIRST) 1650 return; 1651 1652 if (wcidx >= mt7915_wtbl_size(dev)) 1653 return; 1654 1655 rcu_read_lock(); 1656 1657 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1658 if (!wcid) 1659 goto out; 1660 1661 msta = container_of(wcid, struct mt7915_sta, wcid); 1662 1663 mt7915_mac_add_txs_skb(dev, wcid, pid, txs_data, &msta->stats); 1664 1665 if (!wcid->sta) 1666 goto out; 1667 1668 spin_lock_bh(&dev->sta_poll_lock); 1669 if (list_empty(&msta->poll_list)) 1670 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1671 spin_unlock_bh(&dev->sta_poll_lock); 1672 1673 out: 1674 rcu_read_unlock(); 1675 } 1676 1677 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1678 { 1679 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1680 __le32 *rxd = (__le32 *)data; 1681 __le32 *end = (__le32 *)&rxd[len / 4]; 1682 enum rx_pkt_type type; 1683 1684 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1685 switch (type) { 1686 case PKT_TYPE_TXRX_NOTIFY: 1687 mt7915_mac_tx_free(dev, data, len); 1688 return false; 1689 case PKT_TYPE_TXS: 1690 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1691 mt7915_mac_add_txs(dev, rxd); 1692 return false; 1693 case PKT_TYPE_RX_FW_MONITOR: 1694 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1695 return false; 1696 default: 1697 return true; 1698 } 1699 } 1700 1701 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1702 struct sk_buff *skb) 1703 { 1704 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1705 __le32 *rxd = (__le32 *)skb->data; 1706 __le32 *end = (__le32 *)&skb->data[skb->len]; 1707 enum rx_pkt_type type; 1708 1709 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1710 1711 switch (type) { 1712 case PKT_TYPE_TXRX_NOTIFY: 1713 mt7915_mac_tx_free(dev, skb->data, skb->len); 1714 napi_consume_skb(skb, 1); 1715 break; 1716 case PKT_TYPE_RX_EVENT: 1717 mt7915_mcu_rx_event(dev, skb); 1718 break; 1719 case PKT_TYPE_TXRXV: 1720 mt7915_mac_fill_rx_vector(dev, skb); 1721 break; 1722 case PKT_TYPE_TXS: 1723 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1724 mt7915_mac_add_txs(dev, rxd); 1725 dev_kfree_skb(skb); 1726 break; 1727 case PKT_TYPE_RX_FW_MONITOR: 1728 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1729 break; 1730 case PKT_TYPE_NORMAL: 1731 if (!mt7915_mac_fill_rx(dev, skb)) { 1732 mt76_rx(&dev->mt76, q, skb); 1733 return; 1734 } 1735 fallthrough; 1736 default: 1737 dev_kfree_skb(skb); 1738 break; 1739 } 1740 } 1741 1742 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 1743 { 1744 if (!e->txwi) { 1745 dev_kfree_skb_any(e->skb); 1746 return; 1747 } 1748 1749 /* error path */ 1750 if (e->skb == DMA_DUMMY_DATA) { 1751 struct mt76_txwi_cache *t; 1752 struct mt7915_txp *txp; 1753 1754 txp = mt7915_txwi_to_txp(mdev, e->txwi); 1755 t = mt76_token_put(mdev, le16_to_cpu(txp->token)); 1756 e->skb = t ? t->skb : NULL; 1757 } 1758 1759 if (e->skb) 1760 mt76_tx_complete_skb(mdev, e->wcid, e->skb); 1761 } 1762 1763 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1764 { 1765 struct mt7915_dev *dev = phy->dev; 1766 bool ext_phy = phy != &dev->phy; 1767 u32 reg = MT_WF_PHY_RX_CTRL1(ext_phy); 1768 1769 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1770 mt76_set(dev, reg, BIT(11) | BIT(9)); 1771 } 1772 1773 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1774 { 1775 struct mt7915_dev *dev = phy->dev; 1776 bool ext_phy = phy != &dev->phy; 1777 int i; 1778 1779 for (i = 0; i < 4; i++) { 1780 mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 1781 mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i)); 1782 } 1783 1784 if (ext_phy) { 1785 dev->mt76.phy2->survey_time = ktime_get_boottime(); 1786 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2; 1787 } else { 1788 dev->mt76.phy.survey_time = ktime_get_boottime(); 1789 i = 0; 1790 } 1791 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2); 1792 1793 /* reset airtime counters */ 1794 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(ext_phy), 1795 MT_WF_RMAC_MIB_RXTIME_CLR); 1796 1797 mt7915_mcu_get_chan_mib_info(phy, true); 1798 } 1799 1800 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1801 { 1802 s16 coverage_class = phy->coverage_class; 1803 struct mt7915_dev *dev = phy->dev; 1804 bool ext_phy = phy != &dev->phy; 1805 u32 val, reg_offset; 1806 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1807 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1808 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1809 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1810 int offset; 1811 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 1812 1813 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1814 return; 1815 1816 if (ext_phy) { 1817 coverage_class = max_t(s16, dev->phy.coverage_class, 1818 coverage_class); 1819 } else { 1820 struct mt7915_phy *phy_ext = mt7915_ext_phy(dev); 1821 1822 if (phy_ext) 1823 coverage_class = max_t(s16, phy_ext->coverage_class, 1824 coverage_class); 1825 } 1826 mt76_set(dev, MT_ARB_SCR(ext_phy), 1827 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1828 udelay(1); 1829 1830 offset = 3 * coverage_class; 1831 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1832 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1833 1834 mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset); 1835 mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset); 1836 mt76_wr(dev, MT_TMAC_ICR0(ext_phy), 1837 FIELD_PREP(MT_IFS_EIFS_OFDM, is_5ghz ? 84 : 78) | 1838 FIELD_PREP(MT_IFS_RIFS, 2) | 1839 FIELD_PREP(MT_IFS_SIFS, 10) | 1840 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1841 1842 mt76_wr(dev, MT_TMAC_ICR1(ext_phy), 1843 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1844 1845 if (phy->slottime < 20 || is_5ghz) 1846 val = MT7915_CFEND_RATE_DEFAULT; 1847 else 1848 val = MT7915_CFEND_RATE_11B; 1849 1850 mt76_rmw_field(dev, MT_AGG_ACR0(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 1851 mt76_clear(dev, MT_ARB_SCR(ext_phy), 1852 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1853 } 1854 1855 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy) 1856 { 1857 mt76_set(dev, MT_WF_PHY_RXTD12(ext_phy), 1858 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1859 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1860 1861 mt76_set(dev, MT_WF_PHY_RX_CTRL1(ext_phy), 1862 FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1863 } 1864 1865 static u8 1866 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1867 { 1868 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1869 struct mt7915_dev *dev = phy->dev; 1870 u32 val, sum = 0, n = 0; 1871 int nss, i; 1872 1873 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1874 u32 reg = MT_WF_IRPI(nss + (idx << dev->dbdc_support)); 1875 1876 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1877 val = mt76_rr(dev, reg); 1878 sum += val * nf_power[i]; 1879 n += val; 1880 } 1881 } 1882 1883 if (!n) 1884 return 0; 1885 1886 return sum / n; 1887 } 1888 1889 void mt7915_update_channel(struct mt76_phy *mphy) 1890 { 1891 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv; 1892 struct mt76_channel_state *state = mphy->chan_state; 1893 bool ext_phy = phy != &phy->dev->phy; 1894 int nf; 1895 1896 mt7915_mcu_get_chan_mib_info(phy, false); 1897 1898 nf = mt7915_phy_get_nf(phy, ext_phy); 1899 if (!phy->noise) 1900 phy->noise = nf << 4; 1901 else if (nf) 1902 phy->noise += nf - (phy->noise >> 4); 1903 1904 state->noise = -(phy->noise >> 4); 1905 } 1906 1907 static bool 1908 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1909 { 1910 bool ret; 1911 1912 ret = wait_event_timeout(dev->reset_wait, 1913 (READ_ONCE(dev->reset_state) & state), 1914 MT7915_RESET_TIMEOUT); 1915 1916 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1917 return ret; 1918 } 1919 1920 static void 1921 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1922 { 1923 struct ieee80211_hw *hw = priv; 1924 1925 switch (vif->type) { 1926 case NL80211_IFTYPE_MESH_POINT: 1927 case NL80211_IFTYPE_ADHOC: 1928 case NL80211_IFTYPE_AP: 1929 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); 1930 break; 1931 default: 1932 break; 1933 } 1934 } 1935 1936 static void 1937 mt7915_update_beacons(struct mt7915_dev *dev) 1938 { 1939 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1940 IEEE80211_IFACE_ITER_RESUME_ALL, 1941 mt7915_update_vif_beacon, dev->mt76.hw); 1942 1943 if (!dev->mt76.phy2) 1944 return; 1945 1946 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw, 1947 IEEE80211_IFACE_ITER_RESUME_ALL, 1948 mt7915_update_vif_beacon, dev->mt76.phy2->hw); 1949 } 1950 1951 static void 1952 mt7915_dma_reset(struct mt7915_dev *dev) 1953 { 1954 struct mt76_phy *mphy_ext = dev->mt76.phy2; 1955 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 1956 int i; 1957 1958 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 1959 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1960 mt76_clear(dev, MT_WFDMA1_GLO_CFG, 1961 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 1962 if (dev->hif2) { 1963 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1964 (MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1965 MT_WFDMA0_GLO_CFG_RX_DMA_EN)); 1966 mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 1967 (MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1968 MT_WFDMA1_GLO_CFG_RX_DMA_EN)); 1969 } 1970 1971 usleep_range(1000, 2000); 1972 1973 for (i = 0; i < __MT_TXQ_MAX; i++) { 1974 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 1975 if (mphy_ext) 1976 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true); 1977 } 1978 1979 for (i = 0; i < __MT_MCUQ_MAX; i++) 1980 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); 1981 1982 mt76_for_each_q_rx(&dev->mt76, i) 1983 mt76_queue_rx_reset(dev, i); 1984 1985 mt76_tx_status_check(&dev->mt76, true); 1986 1987 /* re-init prefetch settings after reset */ 1988 mt7915_dma_prefetch(dev); 1989 1990 mt76_set(dev, MT_WFDMA0_GLO_CFG, 1991 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1992 mt76_set(dev, MT_WFDMA1_GLO_CFG, 1993 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN | 1994 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 1995 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 1996 if (dev->hif2) { 1997 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1998 (MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1999 MT_WFDMA0_GLO_CFG_RX_DMA_EN)); 2000 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 2001 (MT_WFDMA1_GLO_CFG_TX_DMA_EN | 2002 MT_WFDMA1_GLO_CFG_RX_DMA_EN | 2003 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 2004 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO)); 2005 } 2006 } 2007 2008 void mt7915_tx_token_put(struct mt7915_dev *dev) 2009 { 2010 struct mt76_txwi_cache *txwi; 2011 int id; 2012 2013 spin_lock_bh(&dev->mt76.token_lock); 2014 idr_for_each_entry(&dev->mt76.token, txwi, id) { 2015 mt7915_txwi_free(dev, txwi, NULL, NULL); 2016 dev->mt76.token_count--; 2017 } 2018 spin_unlock_bh(&dev->mt76.token_lock); 2019 idr_destroy(&dev->mt76.token); 2020 } 2021 2022 /* system error recovery */ 2023 void mt7915_mac_reset_work(struct work_struct *work) 2024 { 2025 struct mt7915_phy *phy2; 2026 struct mt76_phy *ext_phy; 2027 struct mt7915_dev *dev; 2028 2029 dev = container_of(work, struct mt7915_dev, reset_work); 2030 ext_phy = dev->mt76.phy2; 2031 phy2 = ext_phy ? ext_phy->priv : NULL; 2032 2033 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA)) 2034 return; 2035 2036 ieee80211_stop_queues(mt76_hw(dev)); 2037 if (ext_phy) 2038 ieee80211_stop_queues(ext_phy->hw); 2039 2040 set_bit(MT76_RESET, &dev->mphy.state); 2041 set_bit(MT76_MCU_RESET, &dev->mphy.state); 2042 wake_up(&dev->mt76.mcu.wait); 2043 cancel_delayed_work_sync(&dev->mphy.mac_work); 2044 if (phy2) { 2045 set_bit(MT76_RESET, &phy2->mt76->state); 2046 cancel_delayed_work_sync(&phy2->mt76->mac_work); 2047 } 2048 mt76_worker_disable(&dev->mt76.tx_worker); 2049 napi_disable(&dev->mt76.napi[0]); 2050 napi_disable(&dev->mt76.napi[1]); 2051 napi_disable(&dev->mt76.napi[2]); 2052 napi_disable(&dev->mt76.tx_napi); 2053 2054 mutex_lock(&dev->mt76.mutex); 2055 2056 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 2057 2058 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 2059 mt7915_dma_reset(dev); 2060 2061 mt7915_tx_token_put(dev); 2062 idr_init(&dev->mt76.token); 2063 2064 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 2065 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 2066 } 2067 2068 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 2069 clear_bit(MT76_RESET, &dev->mphy.state); 2070 if (phy2) 2071 clear_bit(MT76_RESET, &phy2->mt76->state); 2072 2073 local_bh_disable(); 2074 napi_enable(&dev->mt76.napi[0]); 2075 napi_schedule(&dev->mt76.napi[0]); 2076 2077 napi_enable(&dev->mt76.napi[1]); 2078 napi_schedule(&dev->mt76.napi[1]); 2079 2080 napi_enable(&dev->mt76.napi[2]); 2081 napi_schedule(&dev->mt76.napi[2]); 2082 local_bh_enable(); 2083 2084 tasklet_schedule(&dev->irq_tasklet); 2085 2086 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 2087 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 2088 2089 mt76_worker_enable(&dev->mt76.tx_worker); 2090 2091 napi_enable(&dev->mt76.tx_napi); 2092 napi_schedule(&dev->mt76.tx_napi); 2093 2094 ieee80211_wake_queues(mt76_hw(dev)); 2095 if (ext_phy) 2096 ieee80211_wake_queues(ext_phy->hw); 2097 2098 mutex_unlock(&dev->mt76.mutex); 2099 2100 mt7915_update_beacons(dev); 2101 2102 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 2103 MT7915_WATCHDOG_TIME); 2104 if (phy2) 2105 ieee80211_queue_delayed_work(ext_phy->hw, 2106 &phy2->mt76->mac_work, 2107 MT7915_WATCHDOG_TIME); 2108 } 2109 2110 void mt7915_mac_update_stats(struct mt7915_phy *phy) 2111 { 2112 struct mt7915_dev *dev = phy->dev; 2113 struct mib_stats *mib = &phy->mib; 2114 bool ext_phy = phy != &dev->phy; 2115 int i, aggr0, aggr1, cnt; 2116 u32 val; 2117 2118 cnt = mt76_rr(dev, MT_MIB_SDR3(ext_phy)); 2119 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 2120 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 2121 2122 cnt = mt76_rr(dev, MT_MIB_SDR4(ext_phy)); 2123 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 2124 2125 cnt = mt76_rr(dev, MT_MIB_SDR5(ext_phy)); 2126 mib->rx_mpdu_cnt += cnt; 2127 2128 cnt = mt76_rr(dev, MT_MIB_SDR6(ext_phy)); 2129 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 2130 2131 cnt = mt76_rr(dev, MT_MIB_SDR7(ext_phy)); 2132 mib->rx_vector_mismatch_cnt += FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 2133 2134 cnt = mt76_rr(dev, MT_MIB_SDR8(ext_phy)); 2135 mib->rx_delimiter_fail_cnt += FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 2136 2137 cnt = mt76_rr(dev, MT_MIB_SDR11(ext_phy)); 2138 mib->rx_len_mismatch_cnt += FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 2139 2140 cnt = mt76_rr(dev, MT_MIB_SDR12(ext_phy)); 2141 mib->tx_ampdu_cnt += cnt; 2142 2143 cnt = mt76_rr(dev, MT_MIB_SDR13(ext_phy)); 2144 mib->tx_stop_q_empty_cnt += FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 2145 2146 cnt = mt76_rr(dev, MT_MIB_SDR14(ext_phy)); 2147 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 2148 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 2149 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 2150 2151 cnt = mt76_rr(dev, MT_MIB_SDR15(ext_phy)); 2152 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 2153 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 2154 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 2155 2156 cnt = mt76_rr(dev, MT_MIB_SDR22(ext_phy)); 2157 mib->rx_ampdu_cnt += cnt; 2158 2159 cnt = mt76_rr(dev, MT_MIB_SDR23(ext_phy)); 2160 mib->rx_ampdu_bytes_cnt += cnt; 2161 2162 cnt = mt76_rr(dev, MT_MIB_SDR24(ext_phy)); 2163 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 2164 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 2165 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 2166 2167 cnt = mt76_rr(dev, MT_MIB_SDR25(ext_phy)); 2168 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 2169 2170 cnt = mt76_rr(dev, MT_MIB_SDR27(ext_phy)); 2171 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 2172 2173 cnt = mt76_rr(dev, MT_MIB_SDR28(ext_phy)); 2174 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 2175 2176 cnt = mt76_rr(dev, MT_MIB_SDR29(ext_phy)); 2177 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 2178 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 2179 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 2180 2181 cnt = mt76_rr(dev, MT_MIB_SDRVEC(ext_phy)); 2182 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 2183 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 2184 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 2185 2186 cnt = mt76_rr(dev, MT_MIB_SDR31(ext_phy)); 2187 mib->rx_ba_cnt += cnt; 2188 2189 cnt = mt76_rr(dev, MT_MIB_SDR32(ext_phy)); 2190 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK, cnt); 2191 2192 if (is_mt7915(&dev->mt76)) 2193 cnt = mt76_rr(dev, MT_MIB_SDR33(ext_phy)); 2194 mib->tx_pkt_ibf_cnt += is_mt7915(&dev->mt76) ? 2195 FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK, cnt) : 2196 FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK_MT7916, cnt); 2197 2198 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(ext_phy)); 2199 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 2200 2201 cnt = mt76_rr(dev, MT_MIB_DR8(ext_phy)); 2202 mib->tx_mu_mpdu_cnt += cnt; 2203 2204 cnt = mt76_rr(dev, MT_MIB_DR9(ext_phy)); 2205 mib->tx_mu_acked_mpdu_cnt += cnt; 2206 2207 cnt = mt76_rr(dev, MT_MIB_DR11(ext_phy)); 2208 mib->tx_su_acked_mpdu_cnt += cnt; 2209 2210 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(ext_phy)); 2211 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 2212 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 2213 2214 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(ext_phy)); 2215 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 2216 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 2217 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 2218 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 2219 2220 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(ext_phy)); 2221 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); 2222 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); 2223 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); 2224 2225 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(ext_phy)); 2226 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 2227 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 2228 2229 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2230 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2231 mib->tx_amsdu[i] += cnt; 2232 mib->tx_amsdu_cnt += cnt; 2233 } 2234 2235 aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 2236 if (is_mt7915(&dev->mt76)) { 2237 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { 2238 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, (i << 4))); 2239 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 2240 mib->ack_fail_cnt += 2241 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 2242 2243 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, (i << 4))); 2244 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 2245 mib->rts_retries_cnt += 2246 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 2247 2248 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 2249 dev->mt76.aggr_stats[aggr0++] += val & 0xffff; 2250 dev->mt76.aggr_stats[aggr0++] += val >> 16; 2251 2252 val = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i)); 2253 dev->mt76.aggr_stats[aggr1++] += val & 0xffff; 2254 dev->mt76.aggr_stats[aggr1++] += val >> 16; 2255 } 2256 } else { 2257 for (i = 0; i < 2; i++) { 2258 /* rts count */ 2259 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, (i << 2))); 2260 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 2261 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 2262 2263 /* rts retry count */ 2264 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, (i << 2))); 2265 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 2266 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 2267 2268 /* ba miss count */ 2269 val = mt76_rr(dev, MT_MIB_MB_SDR2(ext_phy, (i << 2))); 2270 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 2271 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 2272 2273 /* ack fail count */ 2274 val = mt76_rr(dev, MT_MIB_MB_BFTF(ext_phy, (i << 2))); 2275 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 2276 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 2277 } 2278 2279 for (i = 0; i < 8; i++) { 2280 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 2281 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 2282 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 2283 } 2284 } 2285 } 2286 2287 void mt7915_mac_sta_rc_work(struct work_struct *work) 2288 { 2289 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 2290 struct ieee80211_sta *sta; 2291 struct ieee80211_vif *vif; 2292 struct mt7915_sta *msta; 2293 u32 changed; 2294 LIST_HEAD(list); 2295 2296 spin_lock_bh(&dev->sta_poll_lock); 2297 list_splice_init(&dev->sta_rc_list, &list); 2298 2299 while (!list_empty(&list)) { 2300 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 2301 list_del_init(&msta->rc_list); 2302 changed = msta->changed; 2303 msta->changed = 0; 2304 spin_unlock_bh(&dev->sta_poll_lock); 2305 2306 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2307 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2308 2309 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2310 IEEE80211_RC_NSS_CHANGED | 2311 IEEE80211_RC_BW_CHANGED)) 2312 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 2313 2314 if (changed & IEEE80211_RC_SMPS_CHANGED) 2315 mt7915_mcu_add_smps(dev, vif, sta); 2316 2317 spin_lock_bh(&dev->sta_poll_lock); 2318 } 2319 2320 spin_unlock_bh(&dev->sta_poll_lock); 2321 } 2322 2323 void mt7915_mac_work(struct work_struct *work) 2324 { 2325 struct mt7915_phy *phy; 2326 struct mt76_phy *mphy; 2327 2328 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2329 mac_work.work); 2330 phy = mphy->priv; 2331 2332 mutex_lock(&mphy->dev->mutex); 2333 2334 mt76_update_survey(mphy); 2335 if (++mphy->mac_work_count == 5) { 2336 mphy->mac_work_count = 0; 2337 2338 mt7915_mac_update_stats(phy); 2339 } 2340 2341 mutex_unlock(&mphy->dev->mutex); 2342 2343 mt76_tx_status_check(mphy->dev, false); 2344 2345 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2346 MT7915_WATCHDOG_TIME); 2347 } 2348 2349 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2350 { 2351 struct mt7915_dev *dev = phy->dev; 2352 2353 if (phy->rdd_state & BIT(0)) 2354 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2355 MT_RX_SEL0, 0); 2356 if (phy->rdd_state & BIT(1)) 2357 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2358 MT_RX_SEL0, 0); 2359 } 2360 2361 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 2362 { 2363 int err; 2364 2365 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2366 MT_RX_SEL0, 0); 2367 if (err < 0) 2368 return err; 2369 2370 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2371 MT_RX_SEL0, 1); 2372 } 2373 2374 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2375 { 2376 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2377 struct mt7915_dev *dev = phy->dev; 2378 bool ext_phy = phy != &dev->phy; 2379 int err; 2380 2381 /* start CAC */ 2382 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, ext_phy, 2383 MT_RX_SEL0, 0); 2384 if (err < 0) 2385 return err; 2386 2387 err = mt7915_dfs_start_rdd(dev, ext_phy); 2388 if (err < 0) 2389 return err; 2390 2391 phy->rdd_state |= BIT(ext_phy); 2392 2393 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2394 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2395 err = mt7915_dfs_start_rdd(dev, 1); 2396 if (err < 0) 2397 return err; 2398 2399 phy->rdd_state |= BIT(1); 2400 } 2401 2402 return 0; 2403 } 2404 2405 static int 2406 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2407 { 2408 const struct mt7915_dfs_radar_spec *radar_specs; 2409 struct mt7915_dev *dev = phy->dev; 2410 int err, i; 2411 2412 switch (dev->mt76.region) { 2413 case NL80211_DFS_FCC: 2414 radar_specs = &fcc_radar_specs; 2415 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2416 if (err < 0) 2417 return err; 2418 break; 2419 case NL80211_DFS_ETSI: 2420 radar_specs = &etsi_radar_specs; 2421 break; 2422 case NL80211_DFS_JP: 2423 radar_specs = &jp_radar_specs; 2424 break; 2425 default: 2426 return -EINVAL; 2427 } 2428 2429 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2430 err = mt7915_mcu_set_radar_th(dev, i, 2431 &radar_specs->radar_pattern[i]); 2432 if (err < 0) 2433 return err; 2434 } 2435 2436 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2437 } 2438 2439 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2440 { 2441 struct mt7915_dev *dev = phy->dev; 2442 bool ext_phy = phy != &dev->phy; 2443 enum mt76_dfs_state dfs_state, prev_state; 2444 int err; 2445 2446 prev_state = phy->mt76->dfs_state; 2447 dfs_state = mt76_phy_dfs_state(phy->mt76); 2448 2449 if (prev_state == dfs_state) 2450 return 0; 2451 2452 if (prev_state == MT_DFS_STATE_UNKNOWN) 2453 mt7915_dfs_stop_radar_detector(phy); 2454 2455 if (dfs_state == MT_DFS_STATE_DISABLED) 2456 goto stop; 2457 2458 if (prev_state <= MT_DFS_STATE_DISABLED) { 2459 err = mt7915_dfs_init_radar_specs(phy); 2460 if (err < 0) 2461 return err; 2462 2463 err = mt7915_dfs_start_radar_detector(phy); 2464 if (err < 0) 2465 return err; 2466 2467 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2468 } 2469 2470 if (dfs_state == MT_DFS_STATE_CAC) 2471 return 0; 2472 2473 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2474 ext_phy, MT_RX_SEL0, 0); 2475 if (err < 0) { 2476 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2477 return err; 2478 } 2479 2480 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2481 return 0; 2482 2483 stop: 2484 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, ext_phy, 2485 MT_RX_SEL0, 0); 2486 if (err < 0) 2487 return err; 2488 2489 mt7915_dfs_stop_radar_detector(phy); 2490 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2491 2492 return 0; 2493 } 2494 2495 static int 2496 mt7915_mac_twt_duration_align(int duration) 2497 { 2498 return duration << 8; 2499 } 2500 2501 static u64 2502 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2503 struct mt7915_twt_flow *flow) 2504 { 2505 struct mt7915_twt_flow *iter, *iter_next; 2506 u32 duration = flow->duration << 8; 2507 u64 start_tsf; 2508 2509 iter = list_first_entry_or_null(&dev->twt_list, 2510 struct mt7915_twt_flow, list); 2511 if (!iter || !iter->sched || iter->start_tsf > duration) { 2512 /* add flow as first entry in the list */ 2513 list_add(&flow->list, &dev->twt_list); 2514 return 0; 2515 } 2516 2517 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2518 start_tsf = iter->start_tsf + 2519 mt7915_mac_twt_duration_align(iter->duration); 2520 if (list_is_last(&iter->list, &dev->twt_list)) 2521 break; 2522 2523 if (!iter_next->sched || 2524 iter_next->start_tsf > start_tsf + duration) { 2525 list_add(&flow->list, &iter->list); 2526 goto out; 2527 } 2528 } 2529 2530 /* add flow as last entry in the list */ 2531 list_add_tail(&flow->list, &dev->twt_list); 2532 out: 2533 return start_tsf; 2534 } 2535 2536 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2537 { 2538 struct ieee80211_twt_params *twt_agrt; 2539 u64 interval, duration; 2540 u16 mantissa; 2541 u8 exp; 2542 2543 /* only individual agreement supported */ 2544 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2545 return -EOPNOTSUPP; 2546 2547 /* only 256us unit supported */ 2548 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2549 return -EOPNOTSUPP; 2550 2551 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2552 2553 /* explicit agreement not supported */ 2554 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2555 return -EOPNOTSUPP; 2556 2557 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2558 le16_to_cpu(twt_agrt->req_type)); 2559 mantissa = le16_to_cpu(twt_agrt->mantissa); 2560 duration = twt_agrt->min_twt_dur << 8; 2561 2562 interval = (u64)mantissa << exp; 2563 if (interval < duration) 2564 return -EOPNOTSUPP; 2565 2566 return 0; 2567 } 2568 2569 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2570 struct ieee80211_sta *sta, 2571 struct ieee80211_twt_setup *twt) 2572 { 2573 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2574 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2575 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2576 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2577 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2578 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2579 struct mt7915_twt_flow *flow; 2580 int flowid, table_id; 2581 u8 exp; 2582 2583 if (mt7915_mac_check_twt_req(twt)) 2584 goto out; 2585 2586 mutex_lock(&dev->mt76.mutex); 2587 2588 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2589 goto unlock; 2590 2591 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2592 goto unlock; 2593 2594 flowid = ffs(~msta->twt.flowid_mask) - 1; 2595 le16p_replace_bits(&twt_agrt->req_type, flowid, 2596 IEEE80211_TWT_REQTYPE_FLOWID); 2597 2598 table_id = ffs(~dev->twt.table_mask) - 1; 2599 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2600 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2601 2602 flow = &msta->twt.flow[flowid]; 2603 memset(flow, 0, sizeof(*flow)); 2604 INIT_LIST_HEAD(&flow->list); 2605 flow->wcid = msta->wcid.idx; 2606 flow->table_id = table_id; 2607 flow->id = flowid; 2608 flow->duration = twt_agrt->min_twt_dur; 2609 flow->mantissa = twt_agrt->mantissa; 2610 flow->exp = exp; 2611 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2612 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2613 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2614 2615 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2616 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2617 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2618 u64 flow_tsf, curr_tsf; 2619 u32 rem; 2620 2621 flow->sched = true; 2622 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2623 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2624 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2625 flow_tsf = curr_tsf + interval - rem; 2626 twt_agrt->twt = cpu_to_le64(flow_tsf); 2627 } else { 2628 list_add_tail(&flow->list, &dev->twt_list); 2629 } 2630 flow->tsf = le64_to_cpu(twt_agrt->twt); 2631 2632 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2633 goto unlock; 2634 2635 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2636 dev->twt.table_mask |= BIT(table_id); 2637 msta->twt.flowid_mask |= BIT(flowid); 2638 dev->twt.n_agrt++; 2639 2640 unlock: 2641 mutex_unlock(&dev->mt76.mutex); 2642 out: 2643 le16p_replace_bits(&twt_agrt->req_type, setup_cmd, 2644 IEEE80211_TWT_REQTYPE_SETUP_CMD); 2645 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2646 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2647 } 2648 2649 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2650 struct mt7915_sta *msta, 2651 u8 flowid) 2652 { 2653 struct mt7915_twt_flow *flow; 2654 2655 lockdep_assert_held(&dev->mt76.mutex); 2656 2657 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2658 return; 2659 2660 if (!(msta->twt.flowid_mask & BIT(flowid))) 2661 return; 2662 2663 flow = &msta->twt.flow[flowid]; 2664 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2665 MCU_TWT_AGRT_DELETE)) 2666 return; 2667 2668 list_del_init(&flow->list); 2669 msta->twt.flowid_mask &= ~BIT(flowid); 2670 dev->twt.table_mask &= ~BIT(flow->table_id); 2671 dev->twt.n_agrt--; 2672 } 2673