1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/of.h> 8 #include <linux/thermal.h> 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "mcu.h" 12 #include "coredump.h" 13 #include "eeprom.h" 14 15 static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }, { 26 .max = MT7915_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29 }; 30 31 static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7915_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 mutex_lock(&phy->dev->mt76.mutex); 57 temperature = mt7915_mcu_get_temperature(phy); 58 mutex_unlock(&phy->dev->mt76.mutex); 59 if (temperature < 0) 60 return temperature; 61 /* display in millidegree celcius */ 62 return sprintf(buf, "%u\n", temperature * 1000); 63 case 1: 64 case 2: 65 return sprintf(buf, "%u\n", 66 phy->throttle_temp[i - 1] * 1000); 67 case 3: 68 return sprintf(buf, "%hhu\n", phy->throttle_state); 69 default: 70 return -EINVAL; 71 } 72 } 73 74 static ssize_t mt7915_thermal_temp_store(struct device *dev, 75 struct device_attribute *attr, 76 const char *buf, size_t count) 77 { 78 struct mt7915_phy *phy = dev_get_drvdata(dev); 79 int ret, i = to_sensor_dev_attr(attr)->index; 80 long val; 81 82 ret = kstrtol(buf, 10, &val); 83 if (ret < 0) 84 return ret; 85 86 mutex_lock(&phy->dev->mt76.mutex); 87 val = DIV_ROUND_CLOSEST(clamp_val(val, 60 * 1000, 130 * 1000), 1000); 88 89 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 90 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 91 (i - 1 == MT7915_MAX_TEMP_IDX && 92 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 93 dev_err(phy->dev->mt76.dev, 94 "temp1_max shall be greater than temp1_crit."); 95 mutex_unlock(&phy->dev->mt76.mutex); 96 return -EINVAL; 97 } 98 99 phy->throttle_temp[i - 1] = val; 100 ret = mt7915_mcu_set_thermal_protect(phy); 101 mutex_unlock(&phy->dev->mt76.mutex); 102 if (ret) 103 return ret; 104 105 return count; 106 } 107 108 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 109 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 110 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 111 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 112 113 static struct attribute *mt7915_hwmon_attrs[] = { 114 &sensor_dev_attr_temp1_input.dev_attr.attr, 115 &sensor_dev_attr_temp1_crit.dev_attr.attr, 116 &sensor_dev_attr_temp1_max.dev_attr.attr, 117 &sensor_dev_attr_throttle1.dev_attr.attr, 118 NULL, 119 }; 120 ATTRIBUTE_GROUPS(mt7915_hwmon); 121 122 static int 123 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 124 unsigned long *state) 125 { 126 *state = MT7915_CDEV_THROTTLE_MAX; 127 128 return 0; 129 } 130 131 static int 132 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 133 unsigned long *state) 134 { 135 struct mt7915_phy *phy = cdev->devdata; 136 137 *state = phy->cdev_state; 138 139 return 0; 140 } 141 142 static int 143 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 144 unsigned long state) 145 { 146 struct mt7915_phy *phy = cdev->devdata; 147 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 148 int ret; 149 150 if (state > MT7915_CDEV_THROTTLE_MAX) { 151 dev_err(phy->dev->mt76.dev, 152 "please specify a valid throttling state\n"); 153 return -EINVAL; 154 } 155 156 if (state == phy->cdev_state) 157 return 0; 158 159 /* 160 * cooling_device convention: 0 = no cooling, more = more cooling 161 * mcu convention: 1 = max cooling, more = less cooling 162 */ 163 mutex_lock(&phy->dev->mt76.mutex); 164 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 165 mutex_unlock(&phy->dev->mt76.mutex); 166 if (ret) 167 return ret; 168 169 phy->cdev_state = state; 170 171 return 0; 172 } 173 174 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 175 .get_max_state = mt7915_thermal_get_max_throttle_state, 176 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 177 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 178 }; 179 180 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 181 { 182 struct wiphy *wiphy = phy->mt76->hw->wiphy; 183 184 if (!phy->cdev) 185 return; 186 187 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 188 thermal_cooling_device_unregister(phy->cdev); 189 } 190 191 static int mt7915_thermal_init(struct mt7915_phy *phy) 192 { 193 struct wiphy *wiphy = phy->mt76->hw->wiphy; 194 struct thermal_cooling_device *cdev; 195 struct device *hwmon; 196 const char *name; 197 198 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 199 wiphy_name(wiphy)); 200 if (!name) 201 return -ENOMEM; 202 203 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 204 if (!IS_ERR(cdev)) { 205 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 206 "cooling_device") < 0) 207 thermal_cooling_device_unregister(cdev); 208 else 209 phy->cdev = cdev; 210 } 211 212 /* initialize critical/maximum high temperature */ 213 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 214 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 215 216 if (!IS_REACHABLE(CONFIG_HWMON)) 217 return 0; 218 219 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 220 mt7915_hwmon_groups); 221 return PTR_ERR_OR_ZERO(hwmon); 222 } 223 224 static void mt7915_led_set_config(struct led_classdev *led_cdev, 225 u8 delay_on, u8 delay_off) 226 { 227 struct mt7915_dev *dev; 228 struct mt76_phy *mphy; 229 u32 val; 230 231 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 232 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 233 234 /* set PWM mode */ 235 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 236 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 237 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 238 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 239 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 240 241 /* enable LED */ 242 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 243 244 /* control LED */ 245 val = MT_LED_CTRL_KICK; 246 if (dev->mphy.leds.al) 247 val |= MT_LED_CTRL_POLARITY; 248 if (mphy->band_idx) 249 val |= MT_LED_CTRL_BAND; 250 251 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 252 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 253 } 254 255 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 256 unsigned long *delay_on, 257 unsigned long *delay_off) 258 { 259 u16 delta_on = 0, delta_off = 0; 260 261 #define HW_TICK 10 262 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 263 264 if (*delay_on) 265 delta_on = TO_HW_TICK(*delay_on); 266 if (*delay_off) 267 delta_off = TO_HW_TICK(*delay_off); 268 269 mt7915_led_set_config(led_cdev, delta_on, delta_off); 270 271 return 0; 272 } 273 274 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 275 enum led_brightness brightness) 276 { 277 if (!brightness) 278 mt7915_led_set_config(led_cdev, 0, 0xff); 279 else 280 mt7915_led_set_config(led_cdev, 0xff, 0); 281 } 282 283 static void __mt7915_init_txpower(struct mt7915_phy *phy, 284 struct ieee80211_supported_band *sband) 285 { 286 struct mt7915_dev *dev = phy->dev; 287 int i, n_chains = hweight16(phy->mt76->chainmask); 288 int nss_delta = mt76_tx_power_nss_delta(n_chains); 289 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 290 struct mt76_power_limits limits; 291 292 for (i = 0; i < sband->n_channels; i++) { 293 struct ieee80211_channel *chan = &sband->channels[i]; 294 u32 target_power = 0; 295 int j; 296 297 for (j = 0; j < n_chains; j++) { 298 u32 val; 299 300 val = mt7915_eeprom_get_target_power(dev, chan, j); 301 target_power = max(target_power, val); 302 } 303 304 target_power += pwr_delta; 305 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 306 &limits, 307 target_power); 308 target_power += nss_delta; 309 target_power = DIV_ROUND_UP(target_power, 2); 310 chan->max_power = min_t(int, chan->max_reg_power, 311 target_power); 312 chan->orig_mpwr = target_power; 313 } 314 } 315 316 void mt7915_init_txpower(struct mt7915_phy *phy) 317 { 318 if (!phy) 319 return; 320 321 if (phy->mt76->cap.has_2ghz) 322 __mt7915_init_txpower(phy, &phy->mt76->sband_2g.sband); 323 if (phy->mt76->cap.has_5ghz) 324 __mt7915_init_txpower(phy, &phy->mt76->sband_5g.sband); 325 if (phy->mt76->cap.has_6ghz) 326 __mt7915_init_txpower(phy, &phy->mt76->sband_6g.sband); 327 } 328 329 static void 330 mt7915_regd_notifier(struct wiphy *wiphy, 331 struct regulatory_request *request) 332 { 333 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 334 struct mt7915_dev *dev = mt7915_hw_dev(hw); 335 struct mt76_phy *mphy = hw->priv; 336 struct mt7915_phy *phy = mphy->priv; 337 338 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 339 dev->mt76.region = request->dfs_region; 340 341 if (dev->mt76.region == NL80211_DFS_UNSET) 342 mt7915_mcu_rdd_background_enable(phy, NULL); 343 344 mt7915_init_txpower(phy); 345 346 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 347 mt7915_dfs_init_radar_detector(phy); 348 } 349 350 static void 351 mt7915_init_wiphy(struct mt7915_phy *phy) 352 { 353 struct mt76_phy *mphy = phy->mt76; 354 struct ieee80211_hw *hw = mphy->hw; 355 struct mt76_dev *mdev = &phy->dev->mt76; 356 struct wiphy *wiphy = hw->wiphy; 357 struct mt7915_dev *dev = phy->dev; 358 359 hw->queues = 4; 360 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 361 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 362 hw->netdev_features = NETIF_F_RXCSUM; 363 364 if (mtk_wed_device_active(&mdev->mmio.wed)) 365 hw->netdev_features |= NETIF_F_HW_TC; 366 367 hw->radiotap_timestamp.units_pos = 368 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 369 370 phy->slottime = 9; 371 372 hw->sta_data_size = sizeof(struct mt7915_sta); 373 hw->vif_data_size = sizeof(struct mt7915_vif); 374 375 wiphy->iface_combinations = if_comb; 376 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 377 wiphy->reg_notifier = mt7915_regd_notifier; 378 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 379 wiphy->mbssid_max_interfaces = 16; 380 381 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 382 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 383 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 384 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 385 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 386 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 387 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 388 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 389 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 390 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 391 392 if (!is_mt7915(&dev->mt76)) 393 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 394 395 if (!mdev->dev->of_node || 396 !of_property_read_bool(mdev->dev->of_node, 397 "mediatek,disable-radar-background")) 398 wiphy_ext_feature_set(wiphy, 399 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 400 401 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 402 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 403 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 404 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 405 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 406 ieee80211_hw_set(hw, SUPPORTS_TX_FRAG); 407 408 hw->max_tx_fragments = 4; 409 410 if (phy->mt76->cap.has_2ghz) { 411 phy->mt76->sband_2g.sband.ht_cap.cap |= 412 IEEE80211_HT_CAP_LDPC_CODING | 413 IEEE80211_HT_CAP_MAX_AMSDU; 414 if (is_mt7915(&dev->mt76)) 415 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 416 IEEE80211_HT_MPDU_DENSITY_4; 417 else 418 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 419 IEEE80211_HT_MPDU_DENSITY_2; 420 } 421 422 if (phy->mt76->cap.has_5ghz) { 423 struct ieee80211_sta_vht_cap *vht_cap; 424 425 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 426 phy->mt76->sband_5g.sband.ht_cap.cap |= 427 IEEE80211_HT_CAP_LDPC_CODING | 428 IEEE80211_HT_CAP_MAX_AMSDU; 429 430 if (is_mt7915(&dev->mt76)) { 431 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 432 IEEE80211_HT_MPDU_DENSITY_4; 433 434 vht_cap->cap |= 435 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 436 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 437 438 if (!dev->dbdc_support) 439 vht_cap->cap |= 440 IEEE80211_VHT_CAP_SHORT_GI_160 | 441 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 442 } else { 443 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 444 IEEE80211_HT_MPDU_DENSITY_2; 445 446 vht_cap->cap |= 447 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 448 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 449 450 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 451 vht_cap->cap |= 452 IEEE80211_VHT_CAP_SHORT_GI_160 | 453 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 454 } 455 456 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 457 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 458 } 459 460 mt76_set_stream_caps(phy->mt76, true); 461 mt7915_set_stream_vht_txbf_caps(phy); 462 mt7915_set_stream_he_caps(phy); 463 mt7915_init_txpower(phy); 464 465 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 466 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 467 468 /* init led callbacks */ 469 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 470 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 471 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 472 } 473 } 474 475 static void 476 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 477 { 478 u32 mask, set; 479 480 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 481 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 482 mt76_set(dev, MT_TMAC_CTCR0(band), 483 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 484 MT_TMAC_CTCR0_INS_DDLMT_EN); 485 486 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 487 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 488 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 489 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 490 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 491 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 492 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 493 494 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 495 MT_MDP_RCFR1_RX_DROPPED_UCAST | 496 MT_MDP_RCFR1_RX_DROPPED_MCAST; 497 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 498 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 499 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 500 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 501 502 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 503 504 /* mt7915: disable rx rate report by default due to hw issues */ 505 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 506 507 /* clear estimated value of EIFS for Rx duration & OBSS time */ 508 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 509 510 /* clear backoff time for Rx duration */ 511 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 512 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 513 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 514 MT_WF_RMAC_MIB_QOS01_BACKOFF); 515 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 516 MT_WF_RMAC_MIB_QOS23_BACKOFF); 517 518 /* clear backoff time for Tx duration */ 519 mt76_clear(dev, MT_WTBLOFF_TOP_ACR(band), 520 MT_WTBLOFF_TOP_ADM_BACKOFFTIME); 521 522 /* exclude estimated backoff time for Tx duration on MT7915 */ 523 if (is_mt7915(&dev->mt76)) 524 mt76_set(dev, MT_AGG_ATCR0(band), 525 MT_AGG_ATCR_MAC_BFF_TIME_EN); 526 527 /* clear backoff time and set software compensation for OBSS time */ 528 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 529 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 530 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 531 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 532 533 /* filter out non-resp frames and get instanstaeous signal reporting */ 534 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 535 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 536 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 537 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 538 539 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 540 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 541 */ 542 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 543 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 544 } 545 546 static void 547 mt7915_init_led_mux(struct mt7915_dev *dev) 548 { 549 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 550 return; 551 552 if (dev->dbdc_support) { 553 switch (mt76_chip(&dev->mt76)) { 554 case 0x7915: 555 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 556 GENMASK(11, 8), 4); 557 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 558 GENMASK(11, 8), 4); 559 break; 560 case 0x7986: 561 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 562 GENMASK(7, 4), 1); 563 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 564 GENMASK(11, 8), 1); 565 break; 566 case 0x7916: 567 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 568 GENMASK(27, 24), 3); 569 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 570 GENMASK(31, 28), 3); 571 break; 572 default: 573 break; 574 } 575 } else if (dev->mphy.leds.pin) { 576 switch (mt76_chip(&dev->mt76)) { 577 case 0x7915: 578 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 579 GENMASK(11, 8), 4); 580 break; 581 case 0x7986: 582 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 583 GENMASK(11, 8), 1); 584 break; 585 case 0x7916: 586 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 587 GENMASK(31, 28), 3); 588 break; 589 default: 590 break; 591 } 592 } else { 593 switch (mt76_chip(&dev->mt76)) { 594 case 0x7915: 595 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 596 GENMASK(11, 8), 4); 597 break; 598 case 0x7986: 599 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 600 GENMASK(7, 4), 1); 601 break; 602 case 0x7916: 603 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 604 GENMASK(27, 24), 3); 605 break; 606 default: 607 break; 608 } 609 } 610 } 611 612 void mt7915_mac_init(struct mt7915_dev *dev) 613 { 614 int i; 615 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 616 617 /* config pse qid6 wfdma port selection */ 618 if (!is_mt7915(&dev->mt76) && dev->hif2) 619 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 620 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 621 622 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 623 624 if (!is_mt7915(&dev->mt76)) 625 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 626 else 627 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); 628 629 /* enable hardware de-agg */ 630 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 631 632 for (i = 0; i < mt7915_wtbl_size(dev); i++) 633 mt7915_mac_wtbl_update(dev, i, 634 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 635 for (i = 0; i < 2; i++) 636 mt7915_mac_init_band(dev, i); 637 638 mt7915_init_led_mux(dev); 639 } 640 641 int mt7915_txbf_init(struct mt7915_dev *dev) 642 { 643 int ret; 644 645 if (dev->dbdc_support) { 646 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 647 if (ret) 648 return ret; 649 } 650 651 /* trigger sounding packets */ 652 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 653 if (ret) 654 return ret; 655 656 /* enable eBF */ 657 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 658 } 659 660 static struct mt7915_phy * 661 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 662 { 663 struct mt7915_phy *phy; 664 struct mt76_phy *mphy; 665 666 if (!dev->dbdc_support) 667 return NULL; 668 669 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 670 if (!mphy) 671 return ERR_PTR(-ENOMEM); 672 673 phy = mphy->priv; 674 phy->dev = dev; 675 phy->mt76 = mphy; 676 677 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 678 phy->mt76->band_idx = 1; 679 680 return phy; 681 } 682 683 static int 684 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 685 { 686 struct mt76_phy *mphy = phy->mt76; 687 int ret; 688 689 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 690 691 mt7915_eeprom_parse_hw_cap(dev, phy); 692 693 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 694 ETH_ALEN); 695 /* Make the secondary PHY MAC address local without overlapping with 696 * the usual MAC address allocation scheme on multiple virtual interfaces 697 */ 698 if (!is_valid_ether_addr(mphy->macaddr)) { 699 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 700 ETH_ALEN); 701 mphy->macaddr[0] |= 2; 702 mphy->macaddr[0] ^= BIT(7); 703 } 704 mt76_eeprom_override(mphy); 705 706 /* init wiphy according to mphy and phy */ 707 mt7915_init_wiphy(phy); 708 709 ret = mt76_register_phy(mphy, true, mt76_rates, 710 ARRAY_SIZE(mt76_rates)); 711 if (ret) 712 return ret; 713 714 ret = mt7915_thermal_init(phy); 715 if (ret) 716 goto unreg; 717 718 mt7915_init_debugfs(phy); 719 720 return 0; 721 722 unreg: 723 mt76_unregister_phy(mphy); 724 return ret; 725 } 726 727 static void mt7915_init_work(struct work_struct *work) 728 { 729 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 730 init_work); 731 732 mt7915_mcu_set_eeprom(dev); 733 mt7915_mac_init(dev); 734 mt7915_txbf_init(dev); 735 } 736 737 void mt7915_wfsys_reset(struct mt7915_dev *dev) 738 { 739 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 740 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 741 742 if (is_mt7915(&dev->mt76)) { 743 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 744 745 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 746 747 /* change to software control */ 748 val |= MT_TOP_PWR_SW_RST; 749 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 750 751 /* reset wfsys */ 752 val &= ~MT_TOP_PWR_SW_RST; 753 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 754 755 /* release wfsys then mcu re-executes romcode */ 756 val |= MT_TOP_PWR_SW_RST; 757 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 758 759 /* switch to hw control */ 760 val &= ~MT_TOP_PWR_SW_RST; 761 val |= MT_TOP_PWR_HW_CTRL; 762 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 763 764 /* check whether mcu resets to default */ 765 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 766 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 767 1000)) { 768 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 769 return; 770 } 771 772 /* wfsys reset won't clear host registers */ 773 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 774 775 msleep(100); 776 } else if (is_mt798x(&dev->mt76)) { 777 mt7986_wmac_disable(dev); 778 msleep(20); 779 780 mt7986_wmac_enable(dev); 781 msleep(20); 782 } else { 783 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 784 msleep(20); 785 786 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 787 msleep(20); 788 } 789 } 790 791 static bool mt7915_band_config(struct mt7915_dev *dev) 792 { 793 bool ret = true; 794 795 dev->phy.mt76->band_idx = 0; 796 797 if (is_mt798x(&dev->mt76)) { 798 u32 sku = mt7915_check_adie(dev, true); 799 800 /* 801 * for mt7986, dbdc support is determined by the number 802 * of adie chips and the main phy is bound to band1 when 803 * dbdc is disabled. 804 */ 805 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 806 dev->phy.mt76->band_idx = 1; 807 ret = false; 808 } 809 } else { 810 ret = is_mt7915(&dev->mt76) ? 811 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 812 } 813 814 return ret; 815 } 816 817 static int 818 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 819 { 820 int ret, idx; 821 822 mt76_wr(dev, MT_INT_MASK_CSR, 0); 823 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 824 825 INIT_WORK(&dev->init_work, mt7915_init_work); 826 827 ret = mt7915_dma_init(dev, phy2); 828 if (ret) 829 return ret; 830 831 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 832 833 ret = mt7915_mcu_init(dev); 834 if (ret) 835 return ret; 836 837 ret = mt7915_eeprom_init(dev); 838 if (ret < 0) 839 return ret; 840 841 if (dev->cal) { 842 ret = mt7915_mcu_apply_group_cal(dev); 843 if (ret) 844 return ret; 845 } 846 847 /* Beacon and mgmt frames should occupy wcid 0 */ 848 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 849 if (idx) 850 return -ENOSPC; 851 852 dev->mt76.global_wcid.idx = idx; 853 dev->mt76.global_wcid.hw_key_idx = -1; 854 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 855 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 856 857 return 0; 858 } 859 860 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 861 { 862 int sts; 863 u32 *cap; 864 865 if (!phy->mt76->cap.has_5ghz) 866 return; 867 868 sts = hweight8(phy->mt76->chainmask); 869 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 870 871 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 872 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 873 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 874 sts - 1); 875 876 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 877 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 878 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 879 880 if (sts < 2) 881 return; 882 883 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 884 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 885 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 886 sts - 1); 887 } 888 889 static void 890 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 891 struct ieee80211_sta_he_cap *he_cap, int vif) 892 { 893 struct mt7915_dev *dev = phy->dev; 894 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 895 int sts = hweight8(phy->mt76->chainmask); 896 u8 c, sts_160 = sts; 897 898 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 899 if (is_mt7915(&dev->mt76)) { 900 if (!dev->dbdc_support) 901 sts_160 /= 2; 902 else 903 sts_160 = 0; 904 } 905 906 #ifdef CONFIG_MAC80211_MESH 907 if (vif == NL80211_IFTYPE_MESH_POINT) 908 return; 909 #endif 910 911 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 912 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 913 914 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 915 if (sts_160) 916 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 917 elem->phy_cap_info[5] &= ~c; 918 919 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 920 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 921 elem->phy_cap_info[6] &= ~c; 922 923 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 924 925 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 926 if (!is_mt7915(&dev->mt76)) 927 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 928 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 929 elem->phy_cap_info[2] |= c; 930 931 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 932 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 933 if (sts_160) 934 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 935 elem->phy_cap_info[4] |= c; 936 937 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 938 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 939 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 940 941 if (vif == NL80211_IFTYPE_STATION) 942 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 943 944 elem->phy_cap_info[6] |= c; 945 946 if (sts < 2) 947 return; 948 949 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 950 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 951 952 if (vif != NL80211_IFTYPE_AP && vif != NL80211_IFTYPE_STATION) 953 return; 954 955 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 956 957 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 958 sts - 1); 959 if (sts_160) 960 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 961 sts_160 - 1); 962 elem->phy_cap_info[5] |= c; 963 964 if (vif != NL80211_IFTYPE_AP) 965 return; 966 967 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 968 969 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 970 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 971 elem->phy_cap_info[6] |= c; 972 973 if (!is_mt7915(&dev->mt76)) { 974 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 975 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 976 elem->phy_cap_info[7] |= c; 977 } 978 } 979 980 static int 981 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 982 struct ieee80211_sband_iftype_data *data) 983 { 984 struct mt7915_dev *dev = phy->dev; 985 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 986 u16 mcs_map = 0; 987 u16 mcs_map_160 = 0; 988 u8 nss_160; 989 990 if (!is_mt7915(&dev->mt76)) 991 nss_160 = nss; 992 else if (!dev->dbdc_support) 993 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 994 nss_160 = nss / 2; 995 else 996 /* Can't do 160MHz with mt7915 dbdc */ 997 nss_160 = 0; 998 999 for (i = 0; i < 8; i++) { 1000 if (i < nss) 1001 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1002 else 1003 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1004 1005 if (i < nss_160) 1006 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1007 else 1008 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1009 } 1010 1011 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1012 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 1013 struct ieee80211_he_cap_elem *he_cap_elem = 1014 &he_cap->he_cap_elem; 1015 struct ieee80211_he_mcs_nss_supp *he_mcs = 1016 &he_cap->he_mcs_nss_supp; 1017 1018 switch (i) { 1019 case NL80211_IFTYPE_STATION: 1020 case NL80211_IFTYPE_AP: 1021 #ifdef CONFIG_MAC80211_MESH 1022 case NL80211_IFTYPE_MESH_POINT: 1023 #endif 1024 break; 1025 default: 1026 continue; 1027 } 1028 1029 data[idx].types_mask = BIT(i); 1030 he_cap->has_he = true; 1031 1032 he_cap_elem->mac_cap_info[0] = 1033 IEEE80211_HE_MAC_CAP0_HTC_HE; 1034 he_cap_elem->mac_cap_info[3] = 1035 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1036 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1037 he_cap_elem->mac_cap_info[4] = 1038 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1039 1040 if (band == NL80211_BAND_2GHZ) 1041 he_cap_elem->phy_cap_info[0] = 1042 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1043 else if (nss_160) 1044 he_cap_elem->phy_cap_info[0] = 1045 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1046 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1047 else 1048 he_cap_elem->phy_cap_info[0] = 1049 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1050 1051 he_cap_elem->phy_cap_info[1] = 1052 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1053 he_cap_elem->phy_cap_info[2] = 1054 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1055 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1056 1057 switch (i) { 1058 case NL80211_IFTYPE_AP: 1059 he_cap_elem->mac_cap_info[0] |= 1060 IEEE80211_HE_MAC_CAP0_TWT_RES; 1061 he_cap_elem->mac_cap_info[2] |= 1062 IEEE80211_HE_MAC_CAP2_BSR; 1063 he_cap_elem->mac_cap_info[4] |= 1064 IEEE80211_HE_MAC_CAP4_BQR; 1065 he_cap_elem->mac_cap_info[5] |= 1066 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1067 he_cap_elem->phy_cap_info[3] |= 1068 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1069 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1070 he_cap_elem->phy_cap_info[6] |= 1071 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1072 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1073 he_cap_elem->phy_cap_info[9] |= 1074 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1075 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1076 break; 1077 case NL80211_IFTYPE_STATION: 1078 he_cap_elem->mac_cap_info[1] |= 1079 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1080 1081 if (band == NL80211_BAND_2GHZ) 1082 he_cap_elem->phy_cap_info[0] |= 1083 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1084 else 1085 he_cap_elem->phy_cap_info[0] |= 1086 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1087 1088 he_cap_elem->phy_cap_info[1] |= 1089 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1090 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1091 he_cap_elem->phy_cap_info[3] |= 1092 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1093 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1094 he_cap_elem->phy_cap_info[6] |= 1095 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1096 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1097 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1098 he_cap_elem->phy_cap_info[7] |= 1099 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1100 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1101 he_cap_elem->phy_cap_info[8] |= 1102 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1103 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1104 if (nss_160) 1105 he_cap_elem->phy_cap_info[8] |= 1106 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1107 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1108 he_cap_elem->phy_cap_info[9] |= 1109 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1110 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1111 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1112 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1113 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1114 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1115 break; 1116 } 1117 1118 memset(he_mcs, 0, sizeof(*he_mcs)); 1119 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1120 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1121 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1122 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1123 1124 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1125 1126 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1127 if (he_cap_elem->phy_cap_info[6] & 1128 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1129 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1130 } else { 1131 he_cap_elem->phy_cap_info[9] |= 1132 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1133 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1134 } 1135 1136 if (band == NL80211_BAND_6GHZ) { 1137 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1138 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1139 1140 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1141 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1142 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1143 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1144 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1145 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1146 1147 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1148 } 1149 1150 idx++; 1151 } 1152 1153 return idx; 1154 } 1155 1156 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1157 { 1158 struct ieee80211_sband_iftype_data *data; 1159 struct ieee80211_supported_band *band; 1160 int n; 1161 1162 if (phy->mt76->cap.has_2ghz) { 1163 data = phy->iftype[NL80211_BAND_2GHZ]; 1164 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1165 1166 band = &phy->mt76->sband_2g.sband; 1167 _ieee80211_set_sband_iftype_data(band, data, n); 1168 } 1169 1170 if (phy->mt76->cap.has_5ghz) { 1171 data = phy->iftype[NL80211_BAND_5GHZ]; 1172 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1173 1174 band = &phy->mt76->sband_5g.sband; 1175 _ieee80211_set_sband_iftype_data(band, data, n); 1176 } 1177 1178 if (phy->mt76->cap.has_6ghz) { 1179 data = phy->iftype[NL80211_BAND_6GHZ]; 1180 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1181 1182 band = &phy->mt76->sband_6g.sband; 1183 _ieee80211_set_sband_iftype_data(band, data, n); 1184 } 1185 } 1186 1187 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1188 { 1189 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1190 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1191 1192 if (!phy) 1193 return; 1194 1195 mt7915_unregister_thermal(phy); 1196 mt76_unregister_phy(mphy); 1197 ieee80211_free_hw(mphy->hw); 1198 } 1199 1200 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1201 { 1202 mt7915_mcu_exit(dev); 1203 mt76_connac2_tx_token_put(&dev->mt76); 1204 mt7915_dma_cleanup(dev); 1205 tasklet_disable(&dev->mt76.irq_tasklet); 1206 1207 if (is_mt798x(&dev->mt76)) 1208 mt7986_wmac_disable(dev); 1209 } 1210 1211 int mt7915_register_device(struct mt7915_dev *dev) 1212 { 1213 struct mt7915_phy *phy2; 1214 int ret; 1215 1216 dev->phy.dev = dev; 1217 dev->phy.mt76 = &dev->mt76.phy; 1218 dev->mt76.phy.priv = &dev->phy; 1219 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1220 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1221 INIT_LIST_HEAD(&dev->sta_rc_list); 1222 INIT_LIST_HEAD(&dev->twt_list); 1223 1224 init_waitqueue_head(&dev->reset_wait); 1225 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1226 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1227 mutex_init(&dev->dump_mutex); 1228 1229 dev->dbdc_support = mt7915_band_config(dev); 1230 1231 phy2 = mt7915_alloc_ext_phy(dev); 1232 if (IS_ERR(phy2)) 1233 return PTR_ERR(phy2); 1234 1235 ret = mt7915_init_hardware(dev, phy2); 1236 if (ret) 1237 goto free_phy2; 1238 1239 mt7915_init_wiphy(&dev->phy); 1240 1241 #ifdef CONFIG_NL80211_TESTMODE 1242 dev->mt76.test_ops = &mt7915_testmode_ops; 1243 #endif 1244 1245 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1246 ARRAY_SIZE(mt76_rates)); 1247 if (ret) 1248 goto stop_hw; 1249 1250 ret = mt7915_thermal_init(&dev->phy); 1251 if (ret) 1252 goto unreg_dev; 1253 1254 if (phy2) { 1255 ret = mt7915_register_ext_phy(dev, phy2); 1256 if (ret) 1257 goto unreg_thermal; 1258 } 1259 1260 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1261 1262 dev->recovery.hw_init_done = true; 1263 1264 ret = mt7915_init_debugfs(&dev->phy); 1265 if (ret) 1266 goto unreg_thermal; 1267 1268 ret = mt7915_coredump_register(dev); 1269 if (ret) 1270 goto unreg_thermal; 1271 1272 return 0; 1273 1274 unreg_thermal: 1275 mt7915_unregister_thermal(&dev->phy); 1276 unreg_dev: 1277 mt76_unregister_device(&dev->mt76); 1278 stop_hw: 1279 mt7915_stop_hardware(dev); 1280 free_phy2: 1281 if (phy2) 1282 ieee80211_free_hw(phy2->mt76->hw); 1283 return ret; 1284 } 1285 1286 void mt7915_unregister_device(struct mt7915_dev *dev) 1287 { 1288 mt7915_unregister_ext_phy(dev); 1289 mt7915_coredump_unregister(dev); 1290 mt7915_unregister_thermal(&dev->phy); 1291 mt76_unregister_device(&dev->mt76); 1292 mt7915_stop_hardware(dev); 1293 1294 mt76_free_device(&dev->mt76); 1295 } 1296