1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/of.h> 8 #include <linux/thermal.h> 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "mcu.h" 12 #include "coredump.h" 13 #include "eeprom.h" 14 15 static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }, { 26 .max = MT7915_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29 }; 30 31 static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7915_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 temperature = mt7915_mcu_get_temperature(phy); 57 if (temperature < 0) 58 return temperature; 59 /* display in millidegree celcius */ 60 return sprintf(buf, "%u\n", temperature * 1000); 61 case 1: 62 case 2: 63 return sprintf(buf, "%u\n", 64 phy->throttle_temp[i - 1] * 1000); 65 case 3: 66 return sprintf(buf, "%hhu\n", phy->throttle_state); 67 default: 68 return -EINVAL; 69 } 70 } 71 72 static ssize_t mt7915_thermal_temp_store(struct device *dev, 73 struct device_attribute *attr, 74 const char *buf, size_t count) 75 { 76 struct mt7915_phy *phy = dev_get_drvdata(dev); 77 int ret, i = to_sensor_dev_attr(attr)->index; 78 long val; 79 80 ret = kstrtol(buf, 10, &val); 81 if (ret < 0) 82 return ret; 83 84 mutex_lock(&phy->dev->mt76.mutex); 85 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 86 87 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 88 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 89 (i - 1 == MT7915_MAX_TEMP_IDX && 90 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 91 dev_err(phy->dev->mt76.dev, 92 "temp1_max shall be greater than temp1_crit."); 93 mutex_unlock(&phy->dev->mt76.mutex); 94 return -EINVAL; 95 } 96 97 phy->throttle_temp[i - 1] = val; 98 mutex_unlock(&phy->dev->mt76.mutex); 99 100 ret = mt7915_mcu_set_thermal_protect(phy); 101 if (ret) 102 return ret; 103 104 return count; 105 } 106 107 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 108 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 109 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 110 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 111 112 static struct attribute *mt7915_hwmon_attrs[] = { 113 &sensor_dev_attr_temp1_input.dev_attr.attr, 114 &sensor_dev_attr_temp1_crit.dev_attr.attr, 115 &sensor_dev_attr_temp1_max.dev_attr.attr, 116 &sensor_dev_attr_throttle1.dev_attr.attr, 117 NULL, 118 }; 119 ATTRIBUTE_GROUPS(mt7915_hwmon); 120 121 static int 122 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 123 unsigned long *state) 124 { 125 *state = MT7915_CDEV_THROTTLE_MAX; 126 127 return 0; 128 } 129 130 static int 131 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 132 unsigned long *state) 133 { 134 struct mt7915_phy *phy = cdev->devdata; 135 136 *state = phy->cdev_state; 137 138 return 0; 139 } 140 141 static int 142 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 143 unsigned long state) 144 { 145 struct mt7915_phy *phy = cdev->devdata; 146 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 147 int ret; 148 149 if (state > MT7915_CDEV_THROTTLE_MAX) { 150 dev_err(phy->dev->mt76.dev, 151 "please specify a valid throttling state\n"); 152 return -EINVAL; 153 } 154 155 if (state == phy->cdev_state) 156 return 0; 157 158 /* 159 * cooling_device convention: 0 = no cooling, more = more cooling 160 * mcu convention: 1 = max cooling, more = less cooling 161 */ 162 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 163 if (ret) 164 return ret; 165 166 phy->cdev_state = state; 167 168 return 0; 169 } 170 171 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 172 .get_max_state = mt7915_thermal_get_max_throttle_state, 173 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 174 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 175 }; 176 177 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 178 { 179 struct wiphy *wiphy = phy->mt76->hw->wiphy; 180 181 if (!phy->cdev) 182 return; 183 184 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 185 thermal_cooling_device_unregister(phy->cdev); 186 } 187 188 static int mt7915_thermal_init(struct mt7915_phy *phy) 189 { 190 struct wiphy *wiphy = phy->mt76->hw->wiphy; 191 struct thermal_cooling_device *cdev; 192 struct device *hwmon; 193 const char *name; 194 195 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 196 wiphy_name(wiphy)); 197 198 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 199 if (!IS_ERR(cdev)) { 200 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 201 "cooling_device") < 0) 202 thermal_cooling_device_unregister(cdev); 203 else 204 phy->cdev = cdev; 205 } 206 207 /* initialize critical/maximum high temperature */ 208 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 209 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 210 211 if (!IS_REACHABLE(CONFIG_HWMON)) 212 return 0; 213 214 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 215 mt7915_hwmon_groups); 216 return PTR_ERR_OR_ZERO(hwmon); 217 } 218 219 static void mt7915_led_set_config(struct led_classdev *led_cdev, 220 u8 delay_on, u8 delay_off) 221 { 222 struct mt7915_dev *dev; 223 struct mt76_phy *mphy; 224 u32 val; 225 226 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 227 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 228 229 /* set PWM mode */ 230 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 231 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 232 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 233 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 234 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 235 236 /* enable LED */ 237 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 238 239 /* control LED */ 240 val = MT_LED_CTRL_KICK; 241 if (dev->mphy.leds.al) 242 val |= MT_LED_CTRL_POLARITY; 243 if (mphy->band_idx) 244 val |= MT_LED_CTRL_BAND; 245 246 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 247 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 248 } 249 250 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 251 unsigned long *delay_on, 252 unsigned long *delay_off) 253 { 254 u16 delta_on = 0, delta_off = 0; 255 256 #define HW_TICK 10 257 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 258 259 if (*delay_on) 260 delta_on = TO_HW_TICK(*delay_on); 261 if (*delay_off) 262 delta_off = TO_HW_TICK(*delay_off); 263 264 mt7915_led_set_config(led_cdev, delta_on, delta_off); 265 266 return 0; 267 } 268 269 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 270 enum led_brightness brightness) 271 { 272 if (!brightness) 273 mt7915_led_set_config(led_cdev, 0, 0xff); 274 else 275 mt7915_led_set_config(led_cdev, 0xff, 0); 276 } 277 278 void mt7915_init_txpower(struct mt7915_dev *dev, 279 struct ieee80211_supported_band *sband) 280 { 281 int i, n_chains = hweight8(dev->mphy.antenna_mask); 282 int nss_delta = mt76_tx_power_nss_delta(n_chains); 283 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 284 struct mt76_power_limits limits; 285 286 for (i = 0; i < sband->n_channels; i++) { 287 struct ieee80211_channel *chan = &sband->channels[i]; 288 u32 target_power = 0; 289 int j; 290 291 for (j = 0; j < n_chains; j++) { 292 u32 val; 293 294 val = mt7915_eeprom_get_target_power(dev, chan, j); 295 target_power = max(target_power, val); 296 } 297 298 target_power += pwr_delta; 299 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 300 &limits, 301 target_power); 302 target_power += nss_delta; 303 target_power = DIV_ROUND_UP(target_power, 2); 304 chan->max_power = min_t(int, chan->max_reg_power, 305 target_power); 306 chan->orig_mpwr = target_power; 307 } 308 } 309 310 static void 311 mt7915_regd_notifier(struct wiphy *wiphy, 312 struct regulatory_request *request) 313 { 314 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 315 struct mt7915_dev *dev = mt7915_hw_dev(hw); 316 struct mt76_phy *mphy = hw->priv; 317 struct mt7915_phy *phy = mphy->priv; 318 319 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 320 dev->mt76.region = request->dfs_region; 321 322 if (dev->mt76.region == NL80211_DFS_UNSET) 323 mt7915_mcu_rdd_background_enable(phy, NULL); 324 325 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 326 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 327 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 328 329 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 330 mt7915_dfs_init_radar_detector(phy); 331 } 332 333 static void 334 mt7915_init_wiphy(struct mt7915_phy *phy) 335 { 336 struct mt76_phy *mphy = phy->mt76; 337 struct ieee80211_hw *hw = mphy->hw; 338 struct mt76_dev *mdev = &phy->dev->mt76; 339 struct wiphy *wiphy = hw->wiphy; 340 struct mt7915_dev *dev = phy->dev; 341 342 hw->queues = 4; 343 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 344 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 345 hw->netdev_features = NETIF_F_RXCSUM; 346 347 if (mtk_wed_device_active(&mdev->mmio.wed)) 348 hw->netdev_features |= NETIF_F_HW_TC; 349 350 hw->radiotap_timestamp.units_pos = 351 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 352 353 phy->slottime = 9; 354 355 hw->sta_data_size = sizeof(struct mt7915_sta); 356 hw->vif_data_size = sizeof(struct mt7915_vif); 357 358 wiphy->iface_combinations = if_comb; 359 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 360 wiphy->reg_notifier = mt7915_regd_notifier; 361 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 362 wiphy->mbssid_max_interfaces = 16; 363 364 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 365 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 366 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 367 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 368 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 369 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 370 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 371 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 372 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 373 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 374 375 if (!is_mt7915(&dev->mt76)) 376 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 377 378 if (!mdev->dev->of_node || 379 !of_property_read_bool(mdev->dev->of_node, 380 "mediatek,disable-radar-background")) 381 wiphy_ext_feature_set(wiphy, 382 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 383 384 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 385 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 386 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 387 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 388 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 389 390 hw->max_tx_fragments = 4; 391 392 if (phy->mt76->cap.has_2ghz) { 393 phy->mt76->sband_2g.sband.ht_cap.cap |= 394 IEEE80211_HT_CAP_LDPC_CODING | 395 IEEE80211_HT_CAP_MAX_AMSDU; 396 if (is_mt7915(&dev->mt76)) 397 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 398 IEEE80211_HT_MPDU_DENSITY_4; 399 else 400 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 401 IEEE80211_HT_MPDU_DENSITY_2; 402 } 403 404 if (phy->mt76->cap.has_5ghz) { 405 struct ieee80211_sta_vht_cap *vht_cap; 406 407 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 408 phy->mt76->sband_5g.sband.ht_cap.cap |= 409 IEEE80211_HT_CAP_LDPC_CODING | 410 IEEE80211_HT_CAP_MAX_AMSDU; 411 412 if (is_mt7915(&dev->mt76)) { 413 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 414 IEEE80211_HT_MPDU_DENSITY_4; 415 416 vht_cap->cap |= 417 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 418 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 419 420 if (!dev->dbdc_support) 421 vht_cap->cap |= 422 IEEE80211_VHT_CAP_SHORT_GI_160 | 423 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 424 } else { 425 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 426 IEEE80211_HT_MPDU_DENSITY_2; 427 428 vht_cap->cap |= 429 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 430 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 431 432 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 433 vht_cap->cap |= 434 IEEE80211_VHT_CAP_SHORT_GI_160 | 435 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 436 } 437 438 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 439 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 440 } 441 442 mt76_set_stream_caps(phy->mt76, true); 443 mt7915_set_stream_vht_txbf_caps(phy); 444 mt7915_set_stream_he_caps(phy); 445 446 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 447 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 448 449 /* init led callbacks */ 450 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 451 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 452 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 453 } 454 } 455 456 static void 457 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 458 { 459 u32 mask, set; 460 461 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 462 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 463 mt76_set(dev, MT_TMAC_CTCR0(band), 464 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 465 MT_TMAC_CTCR0_INS_DDLMT_EN); 466 467 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 468 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 469 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 470 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 471 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 472 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 473 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 474 475 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 476 MT_MDP_RCFR1_RX_DROPPED_UCAST | 477 MT_MDP_RCFR1_RX_DROPPED_MCAST; 478 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 479 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 480 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 481 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 482 483 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 484 485 /* mt7915: disable rx rate report by default due to hw issues */ 486 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 487 488 /* clear estimated value of EIFS for Rx duration & OBSS time */ 489 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 490 491 /* clear backoff time for Rx duration */ 492 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 493 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 494 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 495 MT_WF_RMAC_MIB_QOS01_BACKOFF); 496 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 497 MT_WF_RMAC_MIB_QOS23_BACKOFF); 498 499 /* clear backoff time and set software compensation for OBSS time */ 500 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 501 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 502 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 503 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 504 505 /* filter out non-resp frames and get instanstaeous signal reporting */ 506 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 507 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 508 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 509 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 510 511 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 512 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 513 */ 514 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 515 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 516 } 517 518 static void 519 mt7915_init_led_mux(struct mt7915_dev *dev) 520 { 521 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 522 return; 523 524 if (dev->dbdc_support) { 525 switch (mt76_chip(&dev->mt76)) { 526 case 0x7915: 527 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 528 GENMASK(11, 8), 4); 529 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 530 GENMASK(11, 8), 4); 531 break; 532 case 0x7986: 533 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 534 GENMASK(7, 4), 1); 535 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 536 GENMASK(11, 8), 1); 537 break; 538 case 0x7916: 539 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 540 GENMASK(27, 24), 3); 541 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 542 GENMASK(31, 28), 3); 543 break; 544 default: 545 break; 546 } 547 } else if (dev->mphy.leds.pin) { 548 switch (mt76_chip(&dev->mt76)) { 549 case 0x7915: 550 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 551 GENMASK(11, 8), 4); 552 break; 553 case 0x7986: 554 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 555 GENMASK(11, 8), 1); 556 break; 557 case 0x7916: 558 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 559 GENMASK(31, 28), 3); 560 break; 561 default: 562 break; 563 } 564 } else { 565 switch (mt76_chip(&dev->mt76)) { 566 case 0x7915: 567 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 568 GENMASK(11, 8), 4); 569 break; 570 case 0x7986: 571 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 572 GENMASK(7, 4), 1); 573 break; 574 case 0x7916: 575 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 576 GENMASK(27, 24), 3); 577 break; 578 default: 579 break; 580 } 581 } 582 } 583 584 void mt7915_mac_init(struct mt7915_dev *dev) 585 { 586 int i; 587 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 588 589 /* config pse qid6 wfdma port selection */ 590 if (!is_mt7915(&dev->mt76) && dev->hif2) 591 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 592 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 593 594 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 595 596 if (!is_mt7915(&dev->mt76)) 597 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 598 else 599 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); 600 601 /* enable hardware de-agg */ 602 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 603 604 for (i = 0; i < mt7915_wtbl_size(dev); i++) 605 mt7915_mac_wtbl_update(dev, i, 606 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 607 for (i = 0; i < 2; i++) 608 mt7915_mac_init_band(dev, i); 609 610 mt7915_init_led_mux(dev); 611 } 612 613 int mt7915_txbf_init(struct mt7915_dev *dev) 614 { 615 int ret; 616 617 if (dev->dbdc_support) { 618 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 619 if (ret) 620 return ret; 621 } 622 623 /* trigger sounding packets */ 624 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 625 if (ret) 626 return ret; 627 628 /* enable eBF */ 629 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 630 } 631 632 static struct mt7915_phy * 633 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 634 { 635 struct mt7915_phy *phy; 636 struct mt76_phy *mphy; 637 638 if (!dev->dbdc_support) 639 return NULL; 640 641 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 642 if (!mphy) 643 return ERR_PTR(-ENOMEM); 644 645 phy = mphy->priv; 646 phy->dev = dev; 647 phy->mt76 = mphy; 648 649 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 650 phy->mt76->band_idx = 1; 651 652 return phy; 653 } 654 655 static int 656 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 657 { 658 struct mt76_phy *mphy = phy->mt76; 659 int ret; 660 661 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 662 663 mt7915_eeprom_parse_hw_cap(dev, phy); 664 665 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 666 ETH_ALEN); 667 /* Make the secondary PHY MAC address local without overlapping with 668 * the usual MAC address allocation scheme on multiple virtual interfaces 669 */ 670 if (!is_valid_ether_addr(mphy->macaddr)) { 671 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 672 ETH_ALEN); 673 mphy->macaddr[0] |= 2; 674 mphy->macaddr[0] ^= BIT(7); 675 } 676 mt76_eeprom_override(mphy); 677 678 /* init wiphy according to mphy and phy */ 679 mt7915_init_wiphy(phy); 680 681 ret = mt76_register_phy(mphy, true, mt76_rates, 682 ARRAY_SIZE(mt76_rates)); 683 if (ret) 684 return ret; 685 686 ret = mt7915_thermal_init(phy); 687 if (ret) 688 goto unreg; 689 690 mt7915_init_debugfs(phy); 691 692 return 0; 693 694 unreg: 695 mt76_unregister_phy(mphy); 696 return ret; 697 } 698 699 static void mt7915_init_work(struct work_struct *work) 700 { 701 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 702 init_work); 703 704 mt7915_mcu_set_eeprom(dev); 705 mt7915_mac_init(dev); 706 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 707 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 708 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 709 mt7915_txbf_init(dev); 710 } 711 712 void mt7915_wfsys_reset(struct mt7915_dev *dev) 713 { 714 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 715 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 716 717 if (is_mt7915(&dev->mt76)) { 718 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 719 720 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 721 722 /* change to software control */ 723 val |= MT_TOP_PWR_SW_RST; 724 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 725 726 /* reset wfsys */ 727 val &= ~MT_TOP_PWR_SW_RST; 728 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 729 730 /* release wfsys then mcu re-executes romcode */ 731 val |= MT_TOP_PWR_SW_RST; 732 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 733 734 /* switch to hw control */ 735 val &= ~MT_TOP_PWR_SW_RST; 736 val |= MT_TOP_PWR_HW_CTRL; 737 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 738 739 /* check whether mcu resets to default */ 740 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 741 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 742 1000)) { 743 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 744 return; 745 } 746 747 /* wfsys reset won't clear host registers */ 748 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 749 750 msleep(100); 751 } else if (is_mt798x(&dev->mt76)) { 752 mt7986_wmac_disable(dev); 753 msleep(20); 754 755 mt7986_wmac_enable(dev); 756 msleep(20); 757 } else { 758 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 759 msleep(20); 760 761 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 762 msleep(20); 763 } 764 } 765 766 static bool mt7915_band_config(struct mt7915_dev *dev) 767 { 768 bool ret = true; 769 770 dev->phy.mt76->band_idx = 0; 771 772 if (is_mt798x(&dev->mt76)) { 773 u32 sku = mt7915_check_adie(dev, true); 774 775 /* 776 * for mt7986, dbdc support is determined by the number 777 * of adie chips and the main phy is bound to band1 when 778 * dbdc is disabled. 779 */ 780 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 781 dev->phy.mt76->band_idx = 1; 782 ret = false; 783 } 784 } else { 785 ret = is_mt7915(&dev->mt76) ? 786 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 787 } 788 789 return ret; 790 } 791 792 static int 793 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 794 { 795 int ret, idx; 796 797 mt76_wr(dev, MT_INT_MASK_CSR, 0); 798 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 799 800 INIT_WORK(&dev->init_work, mt7915_init_work); 801 802 ret = mt7915_dma_init(dev, phy2); 803 if (ret) 804 return ret; 805 806 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 807 808 ret = mt7915_mcu_init(dev); 809 if (ret) 810 return ret; 811 812 ret = mt7915_eeprom_init(dev); 813 if (ret < 0) 814 return ret; 815 816 if (dev->flash_mode) { 817 ret = mt7915_mcu_apply_group_cal(dev); 818 if (ret) 819 return ret; 820 } 821 822 /* Beacon and mgmt frames should occupy wcid 0 */ 823 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 824 if (idx) 825 return -ENOSPC; 826 827 dev->mt76.global_wcid.idx = idx; 828 dev->mt76.global_wcid.hw_key_idx = -1; 829 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 830 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 831 832 return 0; 833 } 834 835 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 836 { 837 int sts; 838 u32 *cap; 839 840 if (!phy->mt76->cap.has_5ghz) 841 return; 842 843 sts = hweight8(phy->mt76->chainmask); 844 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 845 846 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 847 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 848 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 849 sts - 1); 850 851 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 852 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 853 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 854 855 if (sts < 2) 856 return; 857 858 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 859 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 860 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 861 sts - 1); 862 } 863 864 static void 865 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 866 struct ieee80211_sta_he_cap *he_cap, int vif) 867 { 868 struct mt7915_dev *dev = phy->dev; 869 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 870 int sts = hweight8(phy->mt76->chainmask); 871 u8 c, sts_160 = sts; 872 873 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 874 if (is_mt7915(&dev->mt76)) { 875 if (!dev->dbdc_support) 876 sts_160 /= 2; 877 else 878 sts_160 = 0; 879 } 880 881 #ifdef CONFIG_MAC80211_MESH 882 if (vif == NL80211_IFTYPE_MESH_POINT) 883 return; 884 #endif 885 886 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 887 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 888 889 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 890 if (sts_160) 891 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 892 elem->phy_cap_info[5] &= ~c; 893 894 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 895 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 896 elem->phy_cap_info[6] &= ~c; 897 898 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 899 900 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 901 if (!is_mt7915(&dev->mt76)) 902 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 903 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 904 elem->phy_cap_info[2] |= c; 905 906 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 907 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 908 if (sts_160) 909 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 910 elem->phy_cap_info[4] |= c; 911 912 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 913 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 914 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 915 916 if (vif == NL80211_IFTYPE_STATION) 917 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 918 919 elem->phy_cap_info[6] |= c; 920 921 if (sts < 2) 922 return; 923 924 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 925 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 926 927 if (vif != NL80211_IFTYPE_AP) 928 return; 929 930 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 931 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 932 933 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 934 sts - 1); 935 if (sts_160) 936 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 937 sts_160 - 1); 938 elem->phy_cap_info[5] |= c; 939 940 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 941 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 942 elem->phy_cap_info[6] |= c; 943 944 if (!is_mt7915(&dev->mt76)) { 945 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 946 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 947 elem->phy_cap_info[7] |= c; 948 } 949 } 950 951 static int 952 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 953 struct ieee80211_sband_iftype_data *data) 954 { 955 struct mt7915_dev *dev = phy->dev; 956 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 957 u16 mcs_map = 0; 958 u16 mcs_map_160 = 0; 959 u8 nss_160; 960 961 if (!is_mt7915(&dev->mt76)) 962 nss_160 = nss; 963 else if (!dev->dbdc_support) 964 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 965 nss_160 = nss / 2; 966 else 967 /* Can't do 160MHz with mt7915 dbdc */ 968 nss_160 = 0; 969 970 for (i = 0; i < 8; i++) { 971 if (i < nss) 972 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 973 else 974 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 975 976 if (i < nss_160) 977 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 978 else 979 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 980 } 981 982 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 983 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 984 struct ieee80211_he_cap_elem *he_cap_elem = 985 &he_cap->he_cap_elem; 986 struct ieee80211_he_mcs_nss_supp *he_mcs = 987 &he_cap->he_mcs_nss_supp; 988 989 switch (i) { 990 case NL80211_IFTYPE_STATION: 991 case NL80211_IFTYPE_AP: 992 #ifdef CONFIG_MAC80211_MESH 993 case NL80211_IFTYPE_MESH_POINT: 994 #endif 995 break; 996 default: 997 continue; 998 } 999 1000 data[idx].types_mask = BIT(i); 1001 he_cap->has_he = true; 1002 1003 he_cap_elem->mac_cap_info[0] = 1004 IEEE80211_HE_MAC_CAP0_HTC_HE; 1005 he_cap_elem->mac_cap_info[3] = 1006 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1007 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1008 he_cap_elem->mac_cap_info[4] = 1009 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1010 1011 if (band == NL80211_BAND_2GHZ) 1012 he_cap_elem->phy_cap_info[0] = 1013 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1014 else if (nss_160) 1015 he_cap_elem->phy_cap_info[0] = 1016 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1017 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1018 else 1019 he_cap_elem->phy_cap_info[0] = 1020 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1021 1022 he_cap_elem->phy_cap_info[1] = 1023 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1024 he_cap_elem->phy_cap_info[2] = 1025 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1026 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1027 1028 switch (i) { 1029 case NL80211_IFTYPE_AP: 1030 he_cap_elem->mac_cap_info[0] |= 1031 IEEE80211_HE_MAC_CAP0_TWT_RES; 1032 he_cap_elem->mac_cap_info[2] |= 1033 IEEE80211_HE_MAC_CAP2_BSR; 1034 he_cap_elem->mac_cap_info[4] |= 1035 IEEE80211_HE_MAC_CAP4_BQR; 1036 he_cap_elem->mac_cap_info[5] |= 1037 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1038 he_cap_elem->phy_cap_info[3] |= 1039 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1040 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1041 he_cap_elem->phy_cap_info[6] |= 1042 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1043 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1044 he_cap_elem->phy_cap_info[9] |= 1045 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1046 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1047 break; 1048 case NL80211_IFTYPE_STATION: 1049 he_cap_elem->mac_cap_info[1] |= 1050 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1051 1052 if (band == NL80211_BAND_2GHZ) 1053 he_cap_elem->phy_cap_info[0] |= 1054 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1055 else 1056 he_cap_elem->phy_cap_info[0] |= 1057 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1058 1059 he_cap_elem->phy_cap_info[1] |= 1060 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1061 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1062 he_cap_elem->phy_cap_info[3] |= 1063 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1064 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1065 he_cap_elem->phy_cap_info[6] |= 1066 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1067 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1068 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1069 he_cap_elem->phy_cap_info[7] |= 1070 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1071 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1072 he_cap_elem->phy_cap_info[8] |= 1073 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1074 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1075 if (nss_160) 1076 he_cap_elem->phy_cap_info[8] |= 1077 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1078 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1079 he_cap_elem->phy_cap_info[9] |= 1080 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1081 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1082 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1083 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1084 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1085 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1086 break; 1087 } 1088 1089 memset(he_mcs, 0, sizeof(*he_mcs)); 1090 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1091 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1092 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1093 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1094 1095 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1096 1097 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1098 if (he_cap_elem->phy_cap_info[6] & 1099 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1100 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1101 } else { 1102 he_cap_elem->phy_cap_info[9] |= 1103 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1104 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1105 } 1106 1107 if (band == NL80211_BAND_6GHZ) { 1108 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1109 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1110 1111 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1112 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1113 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1114 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1115 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1116 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1117 1118 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1119 } 1120 1121 idx++; 1122 } 1123 1124 return idx; 1125 } 1126 1127 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1128 { 1129 struct ieee80211_sband_iftype_data *data; 1130 struct ieee80211_supported_band *band; 1131 int n; 1132 1133 if (phy->mt76->cap.has_2ghz) { 1134 data = phy->iftype[NL80211_BAND_2GHZ]; 1135 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1136 1137 band = &phy->mt76->sband_2g.sband; 1138 _ieee80211_set_sband_iftype_data(band, data, n); 1139 } 1140 1141 if (phy->mt76->cap.has_5ghz) { 1142 data = phy->iftype[NL80211_BAND_5GHZ]; 1143 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1144 1145 band = &phy->mt76->sband_5g.sband; 1146 _ieee80211_set_sband_iftype_data(band, data, n); 1147 } 1148 1149 if (phy->mt76->cap.has_6ghz) { 1150 data = phy->iftype[NL80211_BAND_6GHZ]; 1151 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1152 1153 band = &phy->mt76->sband_6g.sband; 1154 _ieee80211_set_sband_iftype_data(band, data, n); 1155 } 1156 } 1157 1158 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1159 { 1160 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1161 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1162 1163 if (!phy) 1164 return; 1165 1166 mt7915_unregister_thermal(phy); 1167 mt76_unregister_phy(mphy); 1168 ieee80211_free_hw(mphy->hw); 1169 } 1170 1171 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1172 { 1173 mt7915_mcu_exit(dev); 1174 mt76_connac2_tx_token_put(&dev->mt76); 1175 mt7915_dma_cleanup(dev); 1176 tasklet_disable(&dev->mt76.irq_tasklet); 1177 1178 if (is_mt798x(&dev->mt76)) 1179 mt7986_wmac_disable(dev); 1180 } 1181 1182 int mt7915_register_device(struct mt7915_dev *dev) 1183 { 1184 struct mt7915_phy *phy2; 1185 int ret; 1186 1187 dev->phy.dev = dev; 1188 dev->phy.mt76 = &dev->mt76.phy; 1189 dev->mt76.phy.priv = &dev->phy; 1190 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1191 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1192 INIT_LIST_HEAD(&dev->sta_rc_list); 1193 INIT_LIST_HEAD(&dev->twt_list); 1194 1195 init_waitqueue_head(&dev->reset_wait); 1196 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1197 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1198 mutex_init(&dev->dump_mutex); 1199 1200 dev->dbdc_support = mt7915_band_config(dev); 1201 1202 phy2 = mt7915_alloc_ext_phy(dev); 1203 if (IS_ERR(phy2)) 1204 return PTR_ERR(phy2); 1205 1206 ret = mt7915_init_hardware(dev, phy2); 1207 if (ret) 1208 goto free_phy2; 1209 1210 mt7915_init_wiphy(&dev->phy); 1211 1212 #ifdef CONFIG_NL80211_TESTMODE 1213 dev->mt76.test_ops = &mt7915_testmode_ops; 1214 #endif 1215 1216 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1217 ARRAY_SIZE(mt76_rates)); 1218 if (ret) 1219 goto stop_hw; 1220 1221 ret = mt7915_thermal_init(&dev->phy); 1222 if (ret) 1223 goto unreg_dev; 1224 1225 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1226 1227 if (phy2) { 1228 ret = mt7915_register_ext_phy(dev, phy2); 1229 if (ret) 1230 goto unreg_thermal; 1231 } 1232 1233 dev->recovery.hw_init_done = true; 1234 1235 ret = mt7915_init_debugfs(&dev->phy); 1236 if (ret) 1237 goto unreg_thermal; 1238 1239 ret = mt7915_coredump_register(dev); 1240 if (ret) 1241 goto unreg_thermal; 1242 1243 return 0; 1244 1245 unreg_thermal: 1246 mt7915_unregister_thermal(&dev->phy); 1247 unreg_dev: 1248 mt76_unregister_device(&dev->mt76); 1249 stop_hw: 1250 mt7915_stop_hardware(dev); 1251 free_phy2: 1252 if (phy2) 1253 ieee80211_free_hw(phy2->mt76->hw); 1254 return ret; 1255 } 1256 1257 void mt7915_unregister_device(struct mt7915_dev *dev) 1258 { 1259 mt7915_unregister_ext_phy(dev); 1260 mt7915_coredump_unregister(dev); 1261 mt7915_unregister_thermal(&dev->phy); 1262 mt76_unregister_device(&dev->mt76); 1263 mt7915_stop_hardware(dev); 1264 1265 mt76_free_device(&dev->mt76); 1266 } 1267