1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/thermal.h> 8 #include "mt7915.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "eeprom.h" 12 13 static const struct ieee80211_iface_limit if_limits[] = { 14 { 15 .max = 1, 16 .types = BIT(NL80211_IFTYPE_ADHOC) 17 }, { 18 .max = 16, 19 .types = BIT(NL80211_IFTYPE_AP) 20 #ifdef CONFIG_MAC80211_MESH 21 | BIT(NL80211_IFTYPE_MESH_POINT) 22 #endif 23 }, { 24 .max = MT7915_MAX_INTERFACES, 25 .types = BIT(NL80211_IFTYPE_STATION) 26 } 27 }; 28 29 static const struct ieee80211_iface_combination if_comb[] = { 30 { 31 .limits = if_limits, 32 .n_limits = ARRAY_SIZE(if_limits), 33 .max_interfaces = MT7915_MAX_INTERFACES, 34 .num_different_channels = 1, 35 .beacon_int_infra_match = true, 36 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 37 BIT(NL80211_CHAN_WIDTH_20) | 38 BIT(NL80211_CHAN_WIDTH_40) | 39 BIT(NL80211_CHAN_WIDTH_80) | 40 BIT(NL80211_CHAN_WIDTH_160) | 41 BIT(NL80211_CHAN_WIDTH_80P80), 42 } 43 }; 44 45 static ssize_t mt7915_thermal_temp_show(struct device *dev, 46 struct device_attribute *attr, 47 char *buf) 48 { 49 struct mt7915_phy *phy = dev_get_drvdata(dev); 50 int i = to_sensor_dev_attr(attr)->index; 51 int temperature; 52 53 switch (i) { 54 case 0: 55 temperature = mt7915_mcu_get_temperature(phy); 56 if (temperature < 0) 57 return temperature; 58 /* display in millidegree celcius */ 59 return sprintf(buf, "%u\n", temperature * 1000); 60 case 1: 61 case 2: 62 return sprintf(buf, "%u\n", 63 phy->throttle_temp[i - 1] * 1000); 64 case 3: 65 return sprintf(buf, "%hhu\n", phy->throttle_state); 66 default: 67 return -EINVAL; 68 } 69 } 70 71 static ssize_t mt7915_thermal_temp_store(struct device *dev, 72 struct device_attribute *attr, 73 const char *buf, size_t count) 74 { 75 struct mt7915_phy *phy = dev_get_drvdata(dev); 76 int ret, i = to_sensor_dev_attr(attr)->index; 77 long val; 78 79 ret = kstrtol(buf, 10, &val); 80 if (ret < 0) 81 return ret; 82 83 mutex_lock(&phy->dev->mt76.mutex); 84 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 85 phy->throttle_temp[i - 1] = val; 86 mutex_unlock(&phy->dev->mt76.mutex); 87 88 return count; 89 } 90 91 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 92 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 93 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 94 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 95 96 static struct attribute *mt7915_hwmon_attrs[] = { 97 &sensor_dev_attr_temp1_input.dev_attr.attr, 98 &sensor_dev_attr_temp1_crit.dev_attr.attr, 99 &sensor_dev_attr_temp1_max.dev_attr.attr, 100 &sensor_dev_attr_throttle1.dev_attr.attr, 101 NULL, 102 }; 103 ATTRIBUTE_GROUPS(mt7915_hwmon); 104 105 static int 106 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 107 unsigned long *state) 108 { 109 *state = MT7915_CDEV_THROTTLE_MAX; 110 111 return 0; 112 } 113 114 static int 115 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 116 unsigned long *state) 117 { 118 struct mt7915_phy *phy = cdev->devdata; 119 120 *state = phy->cdev_state; 121 122 return 0; 123 } 124 125 static int 126 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 127 unsigned long state) 128 { 129 struct mt7915_phy *phy = cdev->devdata; 130 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 131 int ret; 132 133 if (state > MT7915_CDEV_THROTTLE_MAX) 134 return -EINVAL; 135 136 if (phy->throttle_temp[0] > phy->throttle_temp[1]) 137 return 0; 138 139 if (state == phy->cdev_state) 140 return 0; 141 142 /* 143 * cooling_device convention: 0 = no cooling, more = more cooling 144 * mcu convention: 1 = max cooling, more = less cooling 145 */ 146 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 147 if (ret) 148 return ret; 149 150 phy->cdev_state = state; 151 152 return 0; 153 } 154 155 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 156 .get_max_state = mt7915_thermal_get_max_throttle_state, 157 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 158 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 159 }; 160 161 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 162 { 163 struct wiphy *wiphy = phy->mt76->hw->wiphy; 164 165 if (!phy->cdev) 166 return; 167 168 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 169 thermal_cooling_device_unregister(phy->cdev); 170 } 171 172 static int mt7915_thermal_init(struct mt7915_phy *phy) 173 { 174 struct wiphy *wiphy = phy->mt76->hw->wiphy; 175 struct thermal_cooling_device *cdev; 176 struct device *hwmon; 177 const char *name; 178 179 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 180 wiphy_name(wiphy)); 181 182 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 183 if (!IS_ERR(cdev)) { 184 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 185 "cooling_device") < 0) 186 thermal_cooling_device_unregister(cdev); 187 else 188 phy->cdev = cdev; 189 } 190 191 if (!IS_REACHABLE(CONFIG_HWMON)) 192 return 0; 193 194 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 195 mt7915_hwmon_groups); 196 if (IS_ERR(hwmon)) 197 return PTR_ERR(hwmon); 198 199 /* initialize critical/maximum high temperature */ 200 phy->throttle_temp[0] = 110; 201 phy->throttle_temp[1] = 120; 202 203 return mt7915_mcu_set_thermal_throttling(phy, 204 MT7915_THERMAL_THROTTLE_MAX); 205 } 206 207 static void mt7915_led_set_config(struct led_classdev *led_cdev, 208 u8 delay_on, u8 delay_off) 209 { 210 struct mt7915_dev *dev; 211 struct mt76_dev *mt76; 212 u32 val; 213 214 mt76 = container_of(led_cdev, struct mt76_dev, led_cdev); 215 dev = container_of(mt76, struct mt7915_dev, mt76); 216 217 /* select TX blink mode, 2: only data frames */ 218 mt76_rmw_field(dev, MT_TMAC_TCR0(0), MT_TMAC_TCR0_TX_BLINK, 2); 219 220 /* enable LED */ 221 mt76_wr(dev, MT_LED_EN(0), 1); 222 223 /* set LED Tx blink on/off time */ 224 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 225 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 226 mt76_wr(dev, MT_LED_TX_BLINK(0), val); 227 228 /* control LED */ 229 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 230 if (dev->mt76.led_al) 231 val |= MT_LED_CTRL_POLARITY; 232 233 mt76_wr(dev, MT_LED_CTRL(0), val); 234 mt76_clear(dev, MT_LED_CTRL(0), MT_LED_CTRL_KICK); 235 } 236 237 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 238 unsigned long *delay_on, 239 unsigned long *delay_off) 240 { 241 u16 delta_on = 0, delta_off = 0; 242 243 #define HW_TICK 10 244 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 245 246 if (*delay_on) 247 delta_on = TO_HW_TICK(*delay_on); 248 if (*delay_off) 249 delta_off = TO_HW_TICK(*delay_off); 250 251 mt7915_led_set_config(led_cdev, delta_on, delta_off); 252 253 return 0; 254 } 255 256 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 257 enum led_brightness brightness) 258 { 259 if (!brightness) 260 mt7915_led_set_config(led_cdev, 0, 0xff); 261 else 262 mt7915_led_set_config(led_cdev, 0xff, 0); 263 } 264 265 void mt7915_init_txpower(struct mt7915_dev *dev, 266 struct ieee80211_supported_band *sband) 267 { 268 int i, n_chains = hweight8(dev->mphy.antenna_mask); 269 int nss_delta = mt76_tx_power_nss_delta(n_chains); 270 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 271 struct mt76_power_limits limits; 272 273 for (i = 0; i < sband->n_channels; i++) { 274 struct ieee80211_channel *chan = &sband->channels[i]; 275 u32 target_power = 0; 276 int j; 277 278 for (j = 0; j < n_chains; j++) { 279 u32 val; 280 281 val = mt7915_eeprom_get_target_power(dev, chan, j); 282 target_power = max(target_power, val); 283 } 284 285 target_power += pwr_delta; 286 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 287 &limits, 288 target_power); 289 target_power += nss_delta; 290 target_power = DIV_ROUND_UP(target_power, 2); 291 chan->max_power = min_t(int, chan->max_reg_power, 292 target_power); 293 chan->orig_mpwr = target_power; 294 } 295 } 296 297 static void 298 mt7915_regd_notifier(struct wiphy *wiphy, 299 struct regulatory_request *request) 300 { 301 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 302 struct mt7915_dev *dev = mt7915_hw_dev(hw); 303 struct mt76_phy *mphy = hw->priv; 304 struct mt7915_phy *phy = mphy->priv; 305 306 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 307 dev->mt76.region = request->dfs_region; 308 309 if (dev->mt76.region == NL80211_DFS_UNSET) 310 mt7915_mcu_rdd_background_enable(phy, NULL); 311 312 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 313 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 314 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 315 316 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 317 mt7915_dfs_init_radar_detector(phy); 318 } 319 320 static void 321 mt7915_init_wiphy(struct ieee80211_hw *hw) 322 { 323 struct mt7915_phy *phy = mt7915_hw_phy(hw); 324 struct mt76_dev *mdev = &phy->dev->mt76; 325 struct wiphy *wiphy = hw->wiphy; 326 struct mt7915_dev *dev = phy->dev; 327 328 hw->queues = 4; 329 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 330 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 331 hw->netdev_features = NETIF_F_RXCSUM; 332 333 hw->radiotap_timestamp.units_pos = 334 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 335 336 phy->slottime = 9; 337 338 hw->sta_data_size = sizeof(struct mt7915_sta); 339 hw->vif_data_size = sizeof(struct mt7915_vif); 340 341 wiphy->iface_combinations = if_comb; 342 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 343 wiphy->reg_notifier = mt7915_regd_notifier; 344 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 345 wiphy->mbssid_max_interfaces = 16; 346 347 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 348 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 349 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 350 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 351 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 352 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 353 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 354 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 355 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 356 357 if (!mdev->dev->of_node || 358 !of_property_read_bool(mdev->dev->of_node, 359 "mediatek,disable-radar-background")) 360 wiphy_ext_feature_set(wiphy, 361 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 362 363 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 364 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 365 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 366 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 367 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 368 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 369 370 hw->max_tx_fragments = 4; 371 372 if (phy->mt76->cap.has_2ghz) { 373 phy->mt76->sband_2g.sband.ht_cap.cap |= 374 IEEE80211_HT_CAP_LDPC_CODING | 375 IEEE80211_HT_CAP_MAX_AMSDU; 376 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 377 IEEE80211_HT_MPDU_DENSITY_4; 378 } 379 380 if (phy->mt76->cap.has_5ghz) { 381 phy->mt76->sband_5g.sband.ht_cap.cap |= 382 IEEE80211_HT_CAP_LDPC_CODING | 383 IEEE80211_HT_CAP_MAX_AMSDU; 384 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 385 IEEE80211_HT_MPDU_DENSITY_4; 386 387 if (is_mt7915(&dev->mt76)) { 388 phy->mt76->sband_5g.sband.vht_cap.cap |= 389 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 390 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 391 392 if (!dev->dbdc_support) 393 phy->mt76->sband_5g.sband.vht_cap.cap |= 394 IEEE80211_VHT_CAP_SHORT_GI_160 | 395 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ; 396 } else { 397 phy->mt76->sband_5g.sband.vht_cap.cap |= 398 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 399 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 400 401 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 402 phy->mt76->sband_5g.sband.vht_cap.cap |= 403 IEEE80211_VHT_CAP_SHORT_GI_160 | 404 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 405 } 406 } 407 408 mt76_set_stream_caps(phy->mt76, true); 409 mt7915_set_stream_vht_txbf_caps(phy); 410 mt7915_set_stream_he_caps(phy); 411 412 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 413 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 414 } 415 416 static void 417 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 418 { 419 u32 mask, set; 420 421 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 422 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 423 mt76_set(dev, MT_TMAC_CTCR0(band), 424 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 425 MT_TMAC_CTCR0_INS_DDLMT_EN); 426 427 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 428 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 429 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 430 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 431 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 432 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 433 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 434 435 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 436 MT_MDP_RCFR1_RX_DROPPED_UCAST | 437 MT_MDP_RCFR1_RX_DROPPED_MCAST; 438 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 439 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 440 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 441 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 442 443 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 444 445 /* mt7915: disable rx rate report by default due to hw issues */ 446 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 447 448 /* clear estimated value of EIFS for Rx duration & OBSS time */ 449 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 450 451 /* clear backoff time for Rx duration */ 452 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 453 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 454 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 455 MT_WF_RMAC_MIB_QOS01_BACKOFF); 456 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 457 MT_WF_RMAC_MIB_QOS23_BACKOFF); 458 459 /* clear backoff time and set software compensation for OBSS time */ 460 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 461 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 462 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 463 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 464 465 /* filter out non-resp frames and get instanstaeous signal reporting */ 466 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 467 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 468 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 469 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 470 } 471 472 void mt7915_mac_init(struct mt7915_dev *dev) 473 { 474 int i; 475 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 476 477 /* config pse qid6 wfdma port selection */ 478 if (!is_mt7915(&dev->mt76) && dev->hif2) 479 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 480 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 481 482 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 483 484 if (!is_mt7915(&dev->mt76)) 485 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 486 487 /* enable hardware de-agg */ 488 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 489 490 for (i = 0; i < mt7915_wtbl_size(dev); i++) 491 mt7915_mac_wtbl_update(dev, i, 492 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 493 for (i = 0; i < 2; i++) 494 mt7915_mac_init_band(dev, i); 495 496 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 497 i = dev->mt76.led_pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 498 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 499 } 500 } 501 502 int mt7915_txbf_init(struct mt7915_dev *dev) 503 { 504 int ret; 505 506 if (dev->dbdc_support) { 507 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 508 if (ret) 509 return ret; 510 } 511 512 /* trigger sounding packets */ 513 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 514 if (ret) 515 return ret; 516 517 /* enable eBF */ 518 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 519 } 520 521 static struct mt7915_phy * 522 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 523 { 524 struct mt7915_phy *phy; 525 struct mt76_phy *mphy; 526 527 if (!dev->dbdc_support) 528 return NULL; 529 530 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 531 if (!mphy) 532 return ERR_PTR(-ENOMEM); 533 534 phy = mphy->priv; 535 phy->dev = dev; 536 phy->mt76 = mphy; 537 538 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 539 phy->band_idx = 1; 540 541 return phy; 542 } 543 544 static int 545 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 546 { 547 struct mt76_phy *mphy = phy->mt76; 548 int ret; 549 550 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 551 552 mt7915_eeprom_parse_hw_cap(dev, phy); 553 554 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 555 ETH_ALEN); 556 /* Make the secondary PHY MAC address local without overlapping with 557 * the usual MAC address allocation scheme on multiple virtual interfaces 558 */ 559 if (!is_valid_ether_addr(mphy->macaddr)) { 560 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 561 ETH_ALEN); 562 mphy->macaddr[0] |= 2; 563 mphy->macaddr[0] ^= BIT(7); 564 } 565 mt76_eeprom_override(mphy); 566 567 /* init wiphy according to mphy and phy */ 568 mt7915_init_wiphy(mphy->hw); 569 570 ret = mt76_register_phy(mphy, true, mt76_rates, 571 ARRAY_SIZE(mt76_rates)); 572 if (ret) 573 return ret; 574 575 ret = mt7915_thermal_init(phy); 576 if (ret) 577 goto unreg; 578 579 mt7915_init_debugfs(phy); 580 581 return 0; 582 583 unreg: 584 mt76_unregister_phy(mphy); 585 return ret; 586 } 587 588 static void mt7915_init_work(struct work_struct *work) 589 { 590 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 591 init_work); 592 593 mt7915_mcu_set_eeprom(dev); 594 mt7915_mac_init(dev); 595 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 596 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 597 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 598 mt7915_txbf_init(dev); 599 } 600 601 void mt7915_wfsys_reset(struct mt7915_dev *dev) 602 { 603 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 604 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 605 606 if (is_mt7915(&dev->mt76)) { 607 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 608 609 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 610 611 /* change to software control */ 612 val |= MT_TOP_PWR_SW_RST; 613 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 614 615 /* reset wfsys */ 616 val &= ~MT_TOP_PWR_SW_RST; 617 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 618 619 /* release wfsys then mcu re-executes romcode */ 620 val |= MT_TOP_PWR_SW_RST; 621 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 622 623 /* switch to hw control */ 624 val &= ~MT_TOP_PWR_SW_RST; 625 val |= MT_TOP_PWR_HW_CTRL; 626 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 627 628 /* check whether mcu resets to default */ 629 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 630 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 631 1000)) { 632 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 633 return; 634 } 635 636 /* wfsys reset won't clear host registers */ 637 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 638 639 msleep(100); 640 } else if (is_mt7986(&dev->mt76)) { 641 mt7986_wmac_disable(dev); 642 msleep(20); 643 644 mt7986_wmac_enable(dev); 645 msleep(20); 646 } else { 647 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 648 msleep(20); 649 650 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 651 msleep(20); 652 } 653 } 654 655 static bool mt7915_band_config(struct mt7915_dev *dev) 656 { 657 bool ret = true; 658 659 dev->phy.band_idx = 0; 660 661 if (is_mt7986(&dev->mt76)) { 662 u32 sku = mt7915_check_adie(dev, true); 663 664 /* 665 * for mt7986, dbdc support is determined by the number 666 * of adie chips and the main phy is bound to band1 when 667 * dbdc is disabled. 668 */ 669 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 670 dev->phy.band_idx = 1; 671 ret = false; 672 } 673 } else { 674 ret = is_mt7915(&dev->mt76) ? 675 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 676 } 677 678 return ret; 679 } 680 681 static int 682 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 683 { 684 int ret, idx; 685 686 mt76_wr(dev, MT_INT_MASK_CSR, 0); 687 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 688 689 INIT_WORK(&dev->init_work, mt7915_init_work); 690 691 ret = mt7915_dma_init(dev, phy2); 692 if (ret) 693 return ret; 694 695 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 696 697 ret = mt7915_mcu_init(dev); 698 if (ret) 699 return ret; 700 701 ret = mt7915_eeprom_init(dev); 702 if (ret < 0) 703 return ret; 704 705 if (dev->flash_mode) { 706 ret = mt7915_mcu_apply_group_cal(dev); 707 if (ret) 708 return ret; 709 } 710 711 /* Beacon and mgmt frames should occupy wcid 0 */ 712 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 713 if (idx) 714 return -ENOSPC; 715 716 dev->mt76.global_wcid.idx = idx; 717 dev->mt76.global_wcid.hw_key_idx = -1; 718 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 719 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 720 721 return 0; 722 } 723 724 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 725 { 726 int sts; 727 u32 *cap; 728 729 if (!phy->mt76->cap.has_5ghz) 730 return; 731 732 sts = hweight8(phy->mt76->chainmask); 733 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 734 735 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 736 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 737 (3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 738 739 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 740 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 741 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 742 743 if (sts < 2) 744 return; 745 746 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 747 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 748 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 749 sts - 1); 750 } 751 752 static void 753 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 754 struct ieee80211_sta_he_cap *he_cap, int vif) 755 { 756 struct mt7915_dev *dev = phy->dev; 757 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 758 int sts = hweight8(phy->mt76->chainmask); 759 u8 c, sts_160 = sts; 760 761 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 762 if (is_mt7915(&dev->mt76) && !dev->dbdc_support) 763 sts_160 /= 2; 764 765 #ifdef CONFIG_MAC80211_MESH 766 if (vif == NL80211_IFTYPE_MESH_POINT) 767 return; 768 #endif 769 770 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 771 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 772 773 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 774 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 775 elem->phy_cap_info[5] &= ~c; 776 777 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 778 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 779 elem->phy_cap_info[6] &= ~c; 780 781 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 782 783 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 784 if (!is_mt7915(&dev->mt76)) 785 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 786 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 787 elem->phy_cap_info[2] |= c; 788 789 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 790 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 791 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 792 elem->phy_cap_info[4] |= c; 793 794 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 795 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 796 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 797 798 if (vif == NL80211_IFTYPE_STATION) 799 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 800 801 elem->phy_cap_info[6] |= c; 802 803 if (sts < 2) 804 return; 805 806 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 807 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 808 809 if (vif != NL80211_IFTYPE_AP) 810 return; 811 812 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 813 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 814 815 /* num_snd_dim 816 * for mt7915, max supported sts is 2 for bw > 80MHz 817 */ 818 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 819 sts - 1) | 820 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 821 sts_160 - 1); 822 elem->phy_cap_info[5] |= c; 823 824 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 825 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 826 elem->phy_cap_info[6] |= c; 827 828 if (!is_mt7915(&dev->mt76)) { 829 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 830 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 831 elem->phy_cap_info[7] |= c; 832 } 833 } 834 835 static void 836 mt7915_gen_ppe_thresh(u8 *he_ppet, int nss) 837 { 838 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */ 839 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71}; 840 841 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | 842 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, 843 ru_bit_mask); 844 845 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE * 846 nss * hweight8(ru_bit_mask) * 2; 847 ppet_size = DIV_ROUND_UP(ppet_bits, 8); 848 849 for (i = 0; i < ppet_size - 1; i++) 850 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3]; 851 852 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] & 853 (0xff >> (8 - (ppet_bits - 1) % 8)); 854 } 855 856 static int 857 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 858 struct ieee80211_sband_iftype_data *data) 859 { 860 struct mt7915_dev *dev = phy->dev; 861 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 862 u16 mcs_map = 0; 863 u16 mcs_map_160 = 0; 864 u8 nss_160; 865 866 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 867 if (is_mt7915(&dev->mt76) && !dev->dbdc_support) 868 nss_160 = nss / 2; 869 else 870 nss_160 = nss; 871 872 for (i = 0; i < 8; i++) { 873 if (i < nss) 874 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 875 else 876 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 877 878 if (i < nss_160) 879 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 880 else 881 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 882 } 883 884 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 885 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 886 struct ieee80211_he_cap_elem *he_cap_elem = 887 &he_cap->he_cap_elem; 888 struct ieee80211_he_mcs_nss_supp *he_mcs = 889 &he_cap->he_mcs_nss_supp; 890 891 switch (i) { 892 case NL80211_IFTYPE_STATION: 893 case NL80211_IFTYPE_AP: 894 #ifdef CONFIG_MAC80211_MESH 895 case NL80211_IFTYPE_MESH_POINT: 896 #endif 897 break; 898 default: 899 continue; 900 } 901 902 data[idx].types_mask = BIT(i); 903 he_cap->has_he = true; 904 905 he_cap_elem->mac_cap_info[0] = 906 IEEE80211_HE_MAC_CAP0_HTC_HE; 907 he_cap_elem->mac_cap_info[3] = 908 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 909 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 910 he_cap_elem->mac_cap_info[4] = 911 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 912 913 if (band == NL80211_BAND_2GHZ) 914 he_cap_elem->phy_cap_info[0] = 915 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 916 else 917 he_cap_elem->phy_cap_info[0] = 918 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 919 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G | 920 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; 921 922 he_cap_elem->phy_cap_info[1] = 923 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 924 he_cap_elem->phy_cap_info[2] = 925 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 926 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 927 928 switch (i) { 929 case NL80211_IFTYPE_AP: 930 he_cap_elem->mac_cap_info[0] |= 931 IEEE80211_HE_MAC_CAP0_TWT_RES; 932 he_cap_elem->mac_cap_info[2] |= 933 IEEE80211_HE_MAC_CAP2_BSR; 934 he_cap_elem->mac_cap_info[4] |= 935 IEEE80211_HE_MAC_CAP4_BQR; 936 he_cap_elem->mac_cap_info[5] |= 937 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 938 he_cap_elem->phy_cap_info[3] |= 939 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 940 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 941 he_cap_elem->phy_cap_info[6] |= 942 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 943 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 944 he_cap_elem->phy_cap_info[9] |= 945 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 946 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 947 break; 948 case NL80211_IFTYPE_STATION: 949 he_cap_elem->mac_cap_info[1] |= 950 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 951 952 if (band == NL80211_BAND_2GHZ) 953 he_cap_elem->phy_cap_info[0] |= 954 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 955 else 956 he_cap_elem->phy_cap_info[0] |= 957 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 958 959 he_cap_elem->phy_cap_info[1] |= 960 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 961 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 962 he_cap_elem->phy_cap_info[3] |= 963 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 964 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 965 he_cap_elem->phy_cap_info[6] |= 966 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 967 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 968 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 969 he_cap_elem->phy_cap_info[7] |= 970 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 971 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 972 he_cap_elem->phy_cap_info[8] |= 973 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 974 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 975 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 976 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 977 he_cap_elem->phy_cap_info[9] |= 978 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 979 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 980 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 981 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 982 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 983 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 984 break; 985 } 986 987 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 988 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 989 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 990 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 991 he_mcs->rx_mcs_80p80 = cpu_to_le16(mcs_map_160); 992 he_mcs->tx_mcs_80p80 = cpu_to_le16(mcs_map_160); 993 994 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 995 996 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 997 if (he_cap_elem->phy_cap_info[6] & 998 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 999 mt7915_gen_ppe_thresh(he_cap->ppe_thres, nss); 1000 } else { 1001 he_cap_elem->phy_cap_info[9] |= 1002 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1003 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1004 } 1005 1006 if (band == NL80211_BAND_6GHZ) { 1007 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1008 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1009 1010 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1011 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1012 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1013 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1014 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1015 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1016 1017 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1018 } 1019 1020 idx++; 1021 } 1022 1023 return idx; 1024 } 1025 1026 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1027 { 1028 struct ieee80211_sband_iftype_data *data; 1029 struct ieee80211_supported_band *band; 1030 int n; 1031 1032 if (phy->mt76->cap.has_2ghz) { 1033 data = phy->iftype[NL80211_BAND_2GHZ]; 1034 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1035 1036 band = &phy->mt76->sband_2g.sband; 1037 band->iftype_data = data; 1038 band->n_iftype_data = n; 1039 } 1040 1041 if (phy->mt76->cap.has_5ghz) { 1042 data = phy->iftype[NL80211_BAND_5GHZ]; 1043 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1044 1045 band = &phy->mt76->sband_5g.sband; 1046 band->iftype_data = data; 1047 band->n_iftype_data = n; 1048 } 1049 1050 if (phy->mt76->cap.has_6ghz) { 1051 data = phy->iftype[NL80211_BAND_6GHZ]; 1052 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1053 1054 band = &phy->mt76->sband_6g.sband; 1055 band->iftype_data = data; 1056 band->n_iftype_data = n; 1057 } 1058 } 1059 1060 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1061 { 1062 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1063 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1064 1065 if (!phy) 1066 return; 1067 1068 mt7915_unregister_thermal(phy); 1069 mt76_unregister_phy(mphy); 1070 ieee80211_free_hw(mphy->hw); 1071 } 1072 1073 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1074 { 1075 mt7915_mcu_exit(dev); 1076 mt7915_tx_token_put(dev); 1077 mt7915_dma_cleanup(dev); 1078 tasklet_disable(&dev->irq_tasklet); 1079 1080 if (is_mt7986(&dev->mt76)) 1081 mt7986_wmac_disable(dev); 1082 } 1083 1084 1085 int mt7915_register_device(struct mt7915_dev *dev) 1086 { 1087 struct ieee80211_hw *hw = mt76_hw(dev); 1088 struct mt7915_phy *phy2; 1089 int ret; 1090 1091 dev->phy.dev = dev; 1092 dev->phy.mt76 = &dev->mt76.phy; 1093 dev->mt76.phy.priv = &dev->phy; 1094 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1095 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1096 INIT_LIST_HEAD(&dev->sta_rc_list); 1097 INIT_LIST_HEAD(&dev->sta_poll_list); 1098 INIT_LIST_HEAD(&dev->twt_list); 1099 spin_lock_init(&dev->sta_poll_lock); 1100 1101 init_waitqueue_head(&dev->reset_wait); 1102 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1103 1104 dev->dbdc_support = mt7915_band_config(dev); 1105 1106 phy2 = mt7915_alloc_ext_phy(dev); 1107 if (IS_ERR(phy2)) 1108 return PTR_ERR(phy2); 1109 1110 ret = mt7915_init_hardware(dev, phy2); 1111 if (ret) 1112 goto free_phy2; 1113 1114 mt7915_init_wiphy(hw); 1115 1116 #ifdef CONFIG_NL80211_TESTMODE 1117 dev->mt76.test_ops = &mt7915_testmode_ops; 1118 #endif 1119 1120 /* init led callbacks */ 1121 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 1122 dev->mt76.led_cdev.brightness_set = mt7915_led_set_brightness; 1123 dev->mt76.led_cdev.blink_set = mt7915_led_set_blink; 1124 } 1125 1126 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1127 ARRAY_SIZE(mt76_rates)); 1128 if (ret) 1129 goto stop_hw; 1130 1131 ret = mt7915_thermal_init(&dev->phy); 1132 if (ret) 1133 goto unreg_dev; 1134 1135 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1136 1137 if (phy2) { 1138 ret = mt7915_register_ext_phy(dev, phy2); 1139 if (ret) 1140 goto unreg_thermal; 1141 } 1142 1143 dev->recovery.hw_init_done = true; 1144 1145 mt7915_init_debugfs(&dev->phy); 1146 1147 return 0; 1148 1149 unreg_thermal: 1150 mt7915_unregister_thermal(&dev->phy); 1151 unreg_dev: 1152 mt76_unregister_device(&dev->mt76); 1153 stop_hw: 1154 mt7915_stop_hardware(dev); 1155 free_phy2: 1156 if (phy2) 1157 ieee80211_free_hw(phy2->mt76->hw); 1158 return ret; 1159 } 1160 1161 void mt7915_unregister_device(struct mt7915_dev *dev) 1162 { 1163 mt7915_unregister_ext_phy(dev); 1164 mt7915_unregister_thermal(&dev->phy); 1165 mt76_unregister_device(&dev->mt76); 1166 mt7915_stop_hardware(dev); 1167 1168 mt76_free_device(&dev->mt76); 1169 } 1170