1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/of.h> 8 #include <linux/thermal.h> 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "mcu.h" 12 #include "coredump.h" 13 #include "eeprom.h" 14 15 static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }, { 26 .max = MT7915_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29 }; 30 31 static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7915_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 mutex_lock(&phy->dev->mt76.mutex); 57 temperature = mt7915_mcu_get_temperature(phy); 58 mutex_unlock(&phy->dev->mt76.mutex); 59 if (temperature < 0) 60 return temperature; 61 /* display in millidegree celcius */ 62 return sprintf(buf, "%u\n", temperature * 1000); 63 case 1: 64 case 2: 65 return sprintf(buf, "%u\n", 66 phy->throttle_temp[i - 1] * 1000); 67 case 3: 68 return sprintf(buf, "%hhu\n", phy->throttle_state); 69 default: 70 return -EINVAL; 71 } 72 } 73 74 static ssize_t mt7915_thermal_temp_store(struct device *dev, 75 struct device_attribute *attr, 76 const char *buf, size_t count) 77 { 78 struct mt7915_phy *phy = dev_get_drvdata(dev); 79 int ret, i = to_sensor_dev_attr(attr)->index; 80 long val; 81 82 ret = kstrtol(buf, 10, &val); 83 if (ret < 0) 84 return ret; 85 86 mutex_lock(&phy->dev->mt76.mutex); 87 val = DIV_ROUND_CLOSEST(clamp_val(val, 60 * 1000, 130 * 1000), 1000); 88 89 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 90 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 91 (i - 1 == MT7915_MAX_TEMP_IDX && 92 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 93 dev_err(phy->dev->mt76.dev, 94 "temp1_max shall be greater than temp1_crit."); 95 mutex_unlock(&phy->dev->mt76.mutex); 96 return -EINVAL; 97 } 98 99 phy->throttle_temp[i - 1] = val; 100 ret = mt7915_mcu_set_thermal_protect(phy); 101 mutex_unlock(&phy->dev->mt76.mutex); 102 if (ret) 103 return ret; 104 105 return count; 106 } 107 108 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 109 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 110 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 111 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 112 113 static struct attribute *mt7915_hwmon_attrs[] = { 114 &sensor_dev_attr_temp1_input.dev_attr.attr, 115 &sensor_dev_attr_temp1_crit.dev_attr.attr, 116 &sensor_dev_attr_temp1_max.dev_attr.attr, 117 &sensor_dev_attr_throttle1.dev_attr.attr, 118 NULL, 119 }; 120 ATTRIBUTE_GROUPS(mt7915_hwmon); 121 122 static int 123 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 124 unsigned long *state) 125 { 126 *state = MT7915_CDEV_THROTTLE_MAX; 127 128 return 0; 129 } 130 131 static int 132 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 133 unsigned long *state) 134 { 135 struct mt7915_phy *phy = cdev->devdata; 136 137 *state = phy->cdev_state; 138 139 return 0; 140 } 141 142 static int 143 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 144 unsigned long state) 145 { 146 struct mt7915_phy *phy = cdev->devdata; 147 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 148 int ret; 149 150 if (state > MT7915_CDEV_THROTTLE_MAX) { 151 dev_err(phy->dev->mt76.dev, 152 "please specify a valid throttling state\n"); 153 return -EINVAL; 154 } 155 156 if (state == phy->cdev_state) 157 return 0; 158 159 /* 160 * cooling_device convention: 0 = no cooling, more = more cooling 161 * mcu convention: 1 = max cooling, more = less cooling 162 */ 163 mutex_lock(&phy->dev->mt76.mutex); 164 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 165 mutex_unlock(&phy->dev->mt76.mutex); 166 if (ret) 167 return ret; 168 169 phy->cdev_state = state; 170 171 return 0; 172 } 173 174 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 175 .get_max_state = mt7915_thermal_get_max_throttle_state, 176 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 177 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 178 }; 179 180 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 181 { 182 struct wiphy *wiphy = phy->mt76->hw->wiphy; 183 184 if (!phy->cdev) 185 return; 186 187 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 188 thermal_cooling_device_unregister(phy->cdev); 189 } 190 191 static int mt7915_thermal_init(struct mt7915_phy *phy) 192 { 193 struct wiphy *wiphy = phy->mt76->hw->wiphy; 194 struct thermal_cooling_device *cdev; 195 struct device *hwmon; 196 const char *name; 197 198 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 199 wiphy_name(wiphy)); 200 if (!name) 201 return -ENOMEM; 202 203 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 204 if (!IS_ERR(cdev)) { 205 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 206 "cooling_device") < 0) 207 thermal_cooling_device_unregister(cdev); 208 else 209 phy->cdev = cdev; 210 } 211 212 /* initialize critical/maximum high temperature */ 213 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 214 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 215 216 if (!IS_REACHABLE(CONFIG_HWMON)) 217 return 0; 218 219 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 220 mt7915_hwmon_groups); 221 return PTR_ERR_OR_ZERO(hwmon); 222 } 223 224 static void mt7915_led_set_config(struct led_classdev *led_cdev, 225 u8 delay_on, u8 delay_off) 226 { 227 struct mt7915_dev *dev; 228 struct mt76_phy *mphy; 229 u32 val; 230 231 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 232 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 233 234 /* set PWM mode */ 235 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 236 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 237 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 238 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 239 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 240 241 /* enable LED */ 242 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 243 244 /* control LED */ 245 val = MT_LED_CTRL_KICK; 246 if (dev->mphy.leds.al) 247 val |= MT_LED_CTRL_POLARITY; 248 if (mphy->band_idx) 249 val |= MT_LED_CTRL_BAND; 250 251 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 252 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 253 } 254 255 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 256 unsigned long *delay_on, 257 unsigned long *delay_off) 258 { 259 u16 delta_on = 0, delta_off = 0; 260 261 #define HW_TICK 10 262 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 263 264 if (*delay_on) 265 delta_on = TO_HW_TICK(*delay_on); 266 if (*delay_off) 267 delta_off = TO_HW_TICK(*delay_off); 268 269 mt7915_led_set_config(led_cdev, delta_on, delta_off); 270 271 return 0; 272 } 273 274 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 275 enum led_brightness brightness) 276 { 277 if (!brightness) 278 mt7915_led_set_config(led_cdev, 0, 0xff); 279 else 280 mt7915_led_set_config(led_cdev, 0xff, 0); 281 } 282 283 static void __mt7915_init_txpower(struct mt7915_phy *phy, 284 struct ieee80211_supported_band *sband) 285 { 286 struct mt7915_dev *dev = phy->dev; 287 int i, n_chains = hweight16(phy->mt76->chainmask); 288 int path_delta = mt76_tx_power_path_delta(n_chains); 289 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 290 struct mt76_power_limits limits; 291 292 for (i = 0; i < sband->n_channels; i++) { 293 struct ieee80211_channel *chan = &sband->channels[i]; 294 u32 target_power = 0; 295 int j; 296 297 for (j = 0; j < n_chains; j++) { 298 u32 val; 299 300 val = mt7915_eeprom_get_target_power(dev, chan, j); 301 target_power = max(target_power, val); 302 } 303 304 target_power += pwr_delta; 305 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 306 &limits, 307 target_power); 308 target_power += path_delta; 309 target_power = DIV_ROUND_UP(target_power, 2); 310 chan->max_power = min_t(int, chan->max_reg_power, 311 target_power); 312 chan->orig_mpwr = target_power; 313 } 314 } 315 316 void mt7915_init_txpower(struct mt7915_phy *phy) 317 { 318 if (!phy) 319 return; 320 321 if (phy->mt76->cap.has_2ghz) 322 __mt7915_init_txpower(phy, &phy->mt76->sband_2g.sband); 323 if (phy->mt76->cap.has_5ghz) 324 __mt7915_init_txpower(phy, &phy->mt76->sband_5g.sband); 325 if (phy->mt76->cap.has_6ghz) 326 __mt7915_init_txpower(phy, &phy->mt76->sband_6g.sband); 327 } 328 329 static void 330 mt7915_regd_notifier(struct wiphy *wiphy, 331 struct regulatory_request *request) 332 { 333 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 334 struct mt7915_dev *dev = mt7915_hw_dev(hw); 335 struct mt76_phy *mphy = hw->priv; 336 struct mt7915_phy *phy = mphy->priv; 337 338 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 339 dev->mt76.region = request->dfs_region; 340 341 if (dev->mt76.region == NL80211_DFS_UNSET) 342 mt7915_mcu_rdd_background_enable(phy, NULL); 343 344 mt7915_init_txpower(phy); 345 346 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 347 mt7915_dfs_init_radar_detector(phy); 348 } 349 350 static void 351 mt7915_init_wiphy(struct mt7915_phy *phy) 352 { 353 struct mt76_phy *mphy = phy->mt76; 354 struct ieee80211_hw *hw = mphy->hw; 355 struct mt76_dev *mdev = &phy->dev->mt76; 356 struct wiphy *wiphy = hw->wiphy; 357 struct mt7915_dev *dev = phy->dev; 358 359 hw->queues = 4; 360 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 361 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 362 hw->netdev_features = NETIF_F_RXCSUM; 363 364 if (mtk_wed_device_active(&mdev->mmio.wed)) 365 hw->netdev_features |= NETIF_F_HW_TC; 366 367 hw->radiotap_timestamp.units_pos = 368 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 369 370 phy->slottime = 9; 371 372 hw->sta_data_size = sizeof(struct mt7915_sta); 373 hw->vif_data_size = sizeof(struct mt7915_vif); 374 375 wiphy->iface_combinations = if_comb; 376 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 377 wiphy->reg_notifier = mt7915_regd_notifier; 378 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 379 wiphy->mbssid_max_interfaces = 16; 380 381 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 382 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 383 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 384 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 385 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 386 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 387 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 388 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 389 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 390 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 391 392 if (!is_mt7915(&dev->mt76)) 393 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 394 395 if (mt7915_eeprom_has_background_radar(phy->dev) && 396 (!mdev->dev->of_node || 397 !of_property_read_bool(mdev->dev->of_node, 398 "mediatek,disable-radar-background"))) 399 wiphy_ext_feature_set(wiphy, 400 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 401 402 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 403 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 404 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 405 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 406 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 407 ieee80211_hw_set(hw, SUPPORTS_TX_FRAG); 408 409 hw->max_tx_fragments = 4; 410 411 if (phy->mt76->cap.has_2ghz) { 412 phy->mt76->sband_2g.sband.ht_cap.cap |= 413 IEEE80211_HT_CAP_LDPC_CODING | 414 IEEE80211_HT_CAP_MAX_AMSDU; 415 if (is_mt7915(&dev->mt76)) 416 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 417 IEEE80211_HT_MPDU_DENSITY_4; 418 else 419 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 420 IEEE80211_HT_MPDU_DENSITY_2; 421 } 422 423 if (phy->mt76->cap.has_5ghz) { 424 struct ieee80211_sta_vht_cap *vht_cap; 425 426 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 427 phy->mt76->sband_5g.sband.ht_cap.cap |= 428 IEEE80211_HT_CAP_LDPC_CODING | 429 IEEE80211_HT_CAP_MAX_AMSDU; 430 431 if (is_mt7915(&dev->mt76)) { 432 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 433 IEEE80211_HT_MPDU_DENSITY_4; 434 435 vht_cap->cap |= 436 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 437 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 438 439 if (!dev->dbdc_support) 440 vht_cap->cap |= 441 IEEE80211_VHT_CAP_SHORT_GI_160 | 442 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 443 } else { 444 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 445 IEEE80211_HT_MPDU_DENSITY_2; 446 447 vht_cap->cap |= 448 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 449 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 450 451 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 452 vht_cap->cap |= 453 IEEE80211_VHT_CAP_SHORT_GI_160 | 454 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 455 } 456 457 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 458 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 459 } 460 461 mt76_set_stream_caps(phy->mt76, true); 462 mt7915_set_stream_vht_txbf_caps(phy); 463 mt7915_set_stream_he_caps(phy); 464 mt7915_init_txpower(phy); 465 466 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 467 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 468 469 /* init led callbacks */ 470 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 471 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 472 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 473 } 474 } 475 476 static void 477 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 478 { 479 u32 mask, set; 480 481 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 482 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 483 mt76_set(dev, MT_TMAC_CTCR0(band), 484 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 485 MT_TMAC_CTCR0_INS_DDLMT_EN); 486 487 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 488 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 489 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 490 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 491 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 492 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 493 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 494 495 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 496 MT_MDP_RCFR1_RX_DROPPED_UCAST | 497 MT_MDP_RCFR1_RX_DROPPED_MCAST; 498 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 499 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 500 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 501 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 502 503 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 504 505 /* mt7915: disable rx rate report by default due to hw issues */ 506 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 507 508 /* clear estimated value of EIFS for Rx duration & OBSS time */ 509 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 510 511 /* clear backoff time for Rx duration */ 512 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 513 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 514 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 515 MT_WF_RMAC_MIB_QOS01_BACKOFF); 516 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 517 MT_WF_RMAC_MIB_QOS23_BACKOFF); 518 519 /* clear backoff time for Tx duration */ 520 mt76_clear(dev, MT_WTBLOFF_TOP_ACR(band), 521 MT_WTBLOFF_TOP_ADM_BACKOFFTIME); 522 523 /* exclude estimated backoff time for Tx duration on MT7915 */ 524 if (is_mt7915(&dev->mt76)) 525 mt76_set(dev, MT_AGG_ATCR0(band), 526 MT_AGG_ATCR_MAC_BFF_TIME_EN); 527 528 /* clear backoff time and set software compensation for OBSS time */ 529 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 530 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 531 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 532 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 533 534 /* filter out non-resp frames and get instanstaeous signal reporting */ 535 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 536 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 537 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 538 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 539 540 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 541 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 542 */ 543 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 544 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 545 } 546 547 static void 548 mt7915_init_led_mux(struct mt7915_dev *dev) 549 { 550 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 551 return; 552 553 if (dev->dbdc_support) { 554 switch (mt76_chip(&dev->mt76)) { 555 case 0x7915: 556 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 557 GENMASK(11, 8), 4); 558 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 559 GENMASK(11, 8), 4); 560 break; 561 case 0x7986: 562 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 563 GENMASK(7, 4), 1); 564 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 565 GENMASK(11, 8), 1); 566 break; 567 case 0x7916: 568 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 569 GENMASK(27, 24), 3); 570 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 571 GENMASK(31, 28), 3); 572 break; 573 default: 574 break; 575 } 576 } else if (dev->mphy.leds.pin) { 577 switch (mt76_chip(&dev->mt76)) { 578 case 0x7915: 579 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 580 GENMASK(11, 8), 4); 581 break; 582 case 0x7986: 583 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 584 GENMASK(11, 8), 1); 585 break; 586 case 0x7916: 587 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 588 GENMASK(31, 28), 3); 589 break; 590 default: 591 break; 592 } 593 } else { 594 switch (mt76_chip(&dev->mt76)) { 595 case 0x7915: 596 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 597 GENMASK(11, 8), 4); 598 break; 599 case 0x7986: 600 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 601 GENMASK(7, 4), 1); 602 break; 603 case 0x7916: 604 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 605 GENMASK(27, 24), 3); 606 break; 607 default: 608 break; 609 } 610 } 611 } 612 613 void mt7915_mac_init(struct mt7915_dev *dev) 614 { 615 int i; 616 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 617 618 /* config pse qid6 wfdma port selection */ 619 if (!is_mt7915(&dev->mt76) && dev->hif2) 620 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 621 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 622 623 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 624 625 if (!is_mt7915(&dev->mt76)) 626 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 627 else 628 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); 629 630 /* enable hardware de-agg */ 631 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 632 633 for (i = 0; i < mt7915_wtbl_size(dev); i++) 634 mt7915_mac_wtbl_update(dev, i, 635 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 636 for (i = 0; i < 2; i++) 637 mt7915_mac_init_band(dev, i); 638 639 mt7915_init_led_mux(dev); 640 } 641 642 int mt7915_txbf_init(struct mt7915_dev *dev) 643 { 644 int ret; 645 646 if (dev->dbdc_support) { 647 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 648 if (ret) 649 return ret; 650 } 651 652 /* trigger sounding packets */ 653 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 654 if (ret) 655 return ret; 656 657 /* enable eBF */ 658 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 659 } 660 661 static struct mt7915_phy * 662 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 663 { 664 struct mt7915_phy *phy; 665 struct mt76_phy *mphy; 666 667 if (!dev->dbdc_support) 668 return NULL; 669 670 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 671 if (!mphy) 672 return ERR_PTR(-ENOMEM); 673 674 phy = mphy->priv; 675 phy->dev = dev; 676 phy->mt76 = mphy; 677 678 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 679 phy->mt76->band_idx = 1; 680 681 return phy; 682 } 683 684 static int 685 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 686 { 687 struct mt76_phy *mphy = phy->mt76; 688 int ret; 689 690 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 691 692 mt7915_eeprom_parse_hw_cap(dev, phy); 693 694 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 695 ETH_ALEN); 696 /* Make the secondary PHY MAC address local without overlapping with 697 * the usual MAC address allocation scheme on multiple virtual interfaces 698 */ 699 if (!is_valid_ether_addr(mphy->macaddr)) { 700 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 701 ETH_ALEN); 702 mphy->macaddr[0] |= 2; 703 mphy->macaddr[0] ^= BIT(7); 704 } 705 ret = mt76_eeprom_override(mphy); 706 if (ret) 707 return ret; 708 709 /* init wiphy according to mphy and phy */ 710 mt7915_init_wiphy(phy); 711 712 ret = mt76_register_phy(mphy, true, mt76_rates, 713 ARRAY_SIZE(mt76_rates)); 714 if (ret) 715 return ret; 716 717 ret = mt7915_thermal_init(phy); 718 if (ret) 719 goto unreg; 720 721 mt7915_init_debugfs(phy); 722 723 return 0; 724 725 unreg: 726 mt76_unregister_phy(mphy); 727 return ret; 728 } 729 730 static void mt7915_init_work(struct work_struct *work) 731 { 732 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 733 init_work); 734 735 mt7915_mcu_set_eeprom(dev); 736 mt7915_mac_init(dev); 737 mt7915_txbf_init(dev); 738 } 739 740 void mt7915_wfsys_reset(struct mt7915_dev *dev) 741 { 742 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 743 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 744 745 if (is_mt7915(&dev->mt76)) { 746 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 747 748 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 749 750 /* change to software control */ 751 val |= MT_TOP_PWR_SW_RST; 752 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 753 754 /* reset wfsys */ 755 val &= ~MT_TOP_PWR_SW_RST; 756 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 757 758 /* release wfsys then mcu re-executes romcode */ 759 val |= MT_TOP_PWR_SW_RST; 760 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 761 762 /* switch to hw control */ 763 val &= ~MT_TOP_PWR_SW_RST; 764 val |= MT_TOP_PWR_HW_CTRL; 765 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 766 767 /* check whether mcu resets to default */ 768 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 769 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 770 1000)) { 771 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 772 return; 773 } 774 775 /* wfsys reset won't clear host registers */ 776 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 777 778 msleep(100); 779 } else if (is_mt798x(&dev->mt76)) { 780 mt7986_wmac_disable(dev); 781 msleep(20); 782 783 mt7986_wmac_enable(dev); 784 msleep(20); 785 } else { 786 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 787 msleep(20); 788 789 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 790 msleep(20); 791 } 792 } 793 794 static bool mt7915_band_config(struct mt7915_dev *dev) 795 { 796 bool ret = true; 797 798 dev->phy.mt76->band_idx = 0; 799 800 if (is_mt798x(&dev->mt76)) { 801 u32 sku = mt7915_check_adie(dev, true); 802 803 /* 804 * for mt7986, dbdc support is determined by the number 805 * of adie chips and the main phy is bound to band1 when 806 * dbdc is disabled. 807 */ 808 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 809 dev->phy.mt76->band_idx = 1; 810 ret = false; 811 } 812 } else { 813 ret = is_mt7915(&dev->mt76) ? 814 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 815 } 816 817 return ret; 818 } 819 820 static int 821 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 822 { 823 int ret, idx; 824 825 mt76_wr(dev, MT_INT_MASK_CSR, 0); 826 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 827 828 INIT_WORK(&dev->init_work, mt7915_init_work); 829 830 ret = mt7915_dma_init(dev, phy2); 831 if (ret) 832 return ret; 833 834 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 835 836 ret = mt7915_mcu_init(dev); 837 if (ret) 838 return ret; 839 840 ret = mt7915_eeprom_init(dev); 841 if (ret < 0) 842 return ret; 843 844 if (dev->cal) { 845 ret = mt7915_mcu_apply_group_cal(dev); 846 if (ret) 847 return ret; 848 } 849 850 /* Beacon and mgmt frames should occupy wcid 0 */ 851 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 852 if (idx) 853 return -ENOSPC; 854 855 dev->mt76.global_wcid.idx = idx; 856 dev->mt76.global_wcid.hw_key_idx = -1; 857 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 858 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 859 860 return 0; 861 } 862 863 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 864 { 865 int sts; 866 u32 *cap; 867 868 if (!phy->mt76->cap.has_5ghz) 869 return; 870 871 sts = hweight8(phy->mt76->chainmask); 872 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 873 874 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 875 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 876 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 877 sts - 1); 878 879 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 880 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 881 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 882 883 if (sts < 2) 884 return; 885 886 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 887 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 888 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 889 sts - 1); 890 } 891 892 static void 893 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 894 struct ieee80211_sta_he_cap *he_cap, int vif) 895 { 896 struct mt7915_dev *dev = phy->dev; 897 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 898 int sts = hweight8(phy->mt76->chainmask); 899 u8 c, sts_160 = sts; 900 901 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 902 if (is_mt7915(&dev->mt76)) { 903 if (!dev->dbdc_support) 904 sts_160 /= 2; 905 else 906 sts_160 = 0; 907 } 908 909 #ifdef CONFIG_MAC80211_MESH 910 if (vif == NL80211_IFTYPE_MESH_POINT) 911 return; 912 #endif 913 914 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 915 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 916 917 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 918 if (sts_160) 919 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 920 elem->phy_cap_info[5] &= ~c; 921 922 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 923 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 924 elem->phy_cap_info[6] &= ~c; 925 926 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 927 928 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 929 if (!is_mt7915(&dev->mt76)) 930 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 931 elem->phy_cap_info[2] |= c; 932 933 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 934 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 935 if (sts_160) 936 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 937 elem->phy_cap_info[4] |= c; 938 939 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 940 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 941 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 942 943 if (vif == NL80211_IFTYPE_STATION) 944 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 945 946 elem->phy_cap_info[6] |= c; 947 948 if (sts < 2) 949 return; 950 951 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 952 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 953 954 if (vif != NL80211_IFTYPE_AP && vif != NL80211_IFTYPE_STATION) 955 return; 956 957 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 958 959 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 960 sts - 1); 961 if (sts_160) 962 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 963 sts_160 - 1); 964 elem->phy_cap_info[5] |= c; 965 966 if (vif != NL80211_IFTYPE_AP) 967 return; 968 969 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 970 971 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 972 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 973 elem->phy_cap_info[6] |= c; 974 975 if (!is_mt7915(&dev->mt76)) { 976 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 977 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 978 elem->phy_cap_info[7] |= c; 979 } 980 } 981 982 static int 983 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 984 struct ieee80211_sband_iftype_data *data) 985 { 986 struct mt7915_dev *dev = phy->dev; 987 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 988 u16 mcs_map = 0; 989 u16 mcs_map_160 = 0; 990 u8 nss_160; 991 992 if (!is_mt7915(&dev->mt76)) 993 nss_160 = nss; 994 else if (!dev->dbdc_support) 995 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 996 nss_160 = nss / 2; 997 else 998 /* Can't do 160MHz with mt7915 dbdc */ 999 nss_160 = 0; 1000 1001 for (i = 0; i < 8; i++) { 1002 if (i < nss) 1003 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1004 else 1005 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1006 1007 if (i < nss_160) 1008 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1009 else 1010 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1011 } 1012 1013 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1014 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 1015 struct ieee80211_he_cap_elem *he_cap_elem = 1016 &he_cap->he_cap_elem; 1017 struct ieee80211_he_mcs_nss_supp *he_mcs = 1018 &he_cap->he_mcs_nss_supp; 1019 1020 switch (i) { 1021 case NL80211_IFTYPE_STATION: 1022 case NL80211_IFTYPE_AP: 1023 #ifdef CONFIG_MAC80211_MESH 1024 case NL80211_IFTYPE_MESH_POINT: 1025 #endif 1026 break; 1027 default: 1028 continue; 1029 } 1030 1031 data[idx].types_mask = BIT(i); 1032 he_cap->has_he = true; 1033 1034 he_cap_elem->mac_cap_info[0] = 1035 IEEE80211_HE_MAC_CAP0_HTC_HE; 1036 he_cap_elem->mac_cap_info[3] = 1037 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1038 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1039 he_cap_elem->mac_cap_info[4] = 1040 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1041 1042 if (band == NL80211_BAND_2GHZ) 1043 he_cap_elem->phy_cap_info[0] = 1044 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1045 else if (nss_160) 1046 he_cap_elem->phy_cap_info[0] = 1047 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1048 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1049 else 1050 he_cap_elem->phy_cap_info[0] = 1051 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1052 1053 he_cap_elem->phy_cap_info[1] = 1054 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1055 he_cap_elem->phy_cap_info[2] = 1056 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1057 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1058 1059 switch (i) { 1060 case NL80211_IFTYPE_AP: 1061 he_cap_elem->mac_cap_info[0] |= 1062 IEEE80211_HE_MAC_CAP0_TWT_RES; 1063 he_cap_elem->mac_cap_info[2] |= 1064 IEEE80211_HE_MAC_CAP2_BSR; 1065 he_cap_elem->mac_cap_info[4] |= 1066 IEEE80211_HE_MAC_CAP4_BQR; 1067 he_cap_elem->mac_cap_info[5] |= 1068 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1069 he_cap_elem->phy_cap_info[3] |= 1070 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1071 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1072 he_cap_elem->phy_cap_info[6] |= 1073 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1074 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1075 he_cap_elem->phy_cap_info[9] |= 1076 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1077 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1078 break; 1079 case NL80211_IFTYPE_STATION: 1080 he_cap_elem->mac_cap_info[1] |= 1081 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1082 1083 if (band == NL80211_BAND_2GHZ) 1084 he_cap_elem->phy_cap_info[0] |= 1085 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1086 else 1087 he_cap_elem->phy_cap_info[0] |= 1088 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1089 1090 he_cap_elem->phy_cap_info[1] |= 1091 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1092 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1093 he_cap_elem->phy_cap_info[3] |= 1094 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1095 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1096 he_cap_elem->phy_cap_info[6] |= 1097 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1098 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1099 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1100 he_cap_elem->phy_cap_info[7] |= 1101 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1102 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1103 he_cap_elem->phy_cap_info[8] |= 1104 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1105 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1106 if (nss_160) 1107 he_cap_elem->phy_cap_info[8] |= 1108 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1109 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1110 he_cap_elem->phy_cap_info[9] |= 1111 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1112 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1113 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1114 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1115 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1116 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1117 break; 1118 } 1119 1120 memset(he_mcs, 0, sizeof(*he_mcs)); 1121 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1122 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1123 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1124 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1125 1126 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1127 1128 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1129 if (he_cap_elem->phy_cap_info[6] & 1130 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1131 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1132 } else { 1133 he_cap_elem->phy_cap_info[9] |= 1134 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1135 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1136 } 1137 1138 if (band == NL80211_BAND_6GHZ) { 1139 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1140 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1141 1142 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1143 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1144 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1145 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1146 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1147 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1148 1149 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1150 } 1151 1152 idx++; 1153 } 1154 1155 return idx; 1156 } 1157 1158 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1159 { 1160 struct ieee80211_sband_iftype_data *data; 1161 struct ieee80211_supported_band *band; 1162 int n; 1163 1164 if (phy->mt76->cap.has_2ghz) { 1165 data = phy->iftype[NL80211_BAND_2GHZ]; 1166 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1167 1168 band = &phy->mt76->sband_2g.sband; 1169 _ieee80211_set_sband_iftype_data(band, data, n); 1170 } 1171 1172 if (phy->mt76->cap.has_5ghz) { 1173 data = phy->iftype[NL80211_BAND_5GHZ]; 1174 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1175 1176 band = &phy->mt76->sband_5g.sband; 1177 _ieee80211_set_sband_iftype_data(band, data, n); 1178 } 1179 1180 if (phy->mt76->cap.has_6ghz) { 1181 data = phy->iftype[NL80211_BAND_6GHZ]; 1182 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1183 1184 band = &phy->mt76->sband_6g.sband; 1185 _ieee80211_set_sband_iftype_data(band, data, n); 1186 } 1187 } 1188 1189 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1190 { 1191 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1192 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1193 1194 if (!phy) 1195 return; 1196 1197 mt7915_unregister_thermal(phy); 1198 mt76_unregister_phy(mphy); 1199 ieee80211_free_hw(mphy->hw); 1200 } 1201 1202 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1203 { 1204 mt7915_mcu_exit(dev); 1205 mt76_connac2_tx_token_put(&dev->mt76); 1206 mt7915_dma_cleanup(dev); 1207 tasklet_disable(&dev->mt76.irq_tasklet); 1208 1209 if (is_mt798x(&dev->mt76)) 1210 mt7986_wmac_disable(dev); 1211 } 1212 1213 int mt7915_register_device(struct mt7915_dev *dev) 1214 { 1215 struct mt7915_phy *phy2; 1216 int ret; 1217 1218 dev->phy.dev = dev; 1219 dev->phy.mt76 = &dev->mt76.phy; 1220 dev->mt76.phy.priv = &dev->phy; 1221 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1222 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1223 INIT_LIST_HEAD(&dev->sta_rc_list); 1224 INIT_LIST_HEAD(&dev->twt_list); 1225 1226 init_waitqueue_head(&dev->reset_wait); 1227 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1228 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1229 mutex_init(&dev->dump_mutex); 1230 1231 dev->dbdc_support = mt7915_band_config(dev); 1232 1233 phy2 = mt7915_alloc_ext_phy(dev); 1234 if (IS_ERR(phy2)) 1235 return PTR_ERR(phy2); 1236 1237 ret = mt7915_init_hardware(dev, phy2); 1238 if (ret) 1239 goto free_phy2; 1240 1241 mt7915_init_wiphy(&dev->phy); 1242 1243 #ifdef CONFIG_NL80211_TESTMODE 1244 dev->mt76.test_ops = &mt7915_testmode_ops; 1245 #endif 1246 1247 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1248 ARRAY_SIZE(mt76_rates)); 1249 if (ret) 1250 goto stop_hw; 1251 1252 ret = mt7915_thermal_init(&dev->phy); 1253 if (ret) 1254 goto unreg_dev; 1255 1256 if (phy2) { 1257 ret = mt7915_register_ext_phy(dev, phy2); 1258 if (ret) 1259 goto unreg_thermal; 1260 } 1261 1262 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1263 1264 dev->recovery.hw_init_done = true; 1265 1266 ret = mt7915_init_debugfs(&dev->phy); 1267 if (ret) 1268 goto unreg_thermal; 1269 1270 ret = mt7915_coredump_register(dev); 1271 if (ret) 1272 goto unreg_thermal; 1273 1274 return 0; 1275 1276 unreg_thermal: 1277 mt7915_unregister_thermal(&dev->phy); 1278 unreg_dev: 1279 mt76_unregister_device(&dev->mt76); 1280 stop_hw: 1281 mt7915_stop_hardware(dev); 1282 free_phy2: 1283 if (phy2) 1284 ieee80211_free_hw(phy2->mt76->hw); 1285 return ret; 1286 } 1287 1288 void mt7915_unregister_device(struct mt7915_dev *dev) 1289 { 1290 mt7915_unregister_ext_phy(dev); 1291 mt7915_coredump_unregister(dev); 1292 mt7915_unregister_thermal(&dev->phy); 1293 mt76_unregister_device(&dev->mt76); 1294 mt7915_stop_hardware(dev); 1295 1296 mt76_free_device(&dev->mt76); 1297 } 1298