1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/thermal.h> 8 #include "mt7915.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "coredump.h" 12 #include "eeprom.h" 13 14 static const struct ieee80211_iface_limit if_limits[] = { 15 { 16 .max = 1, 17 .types = BIT(NL80211_IFTYPE_ADHOC) 18 }, { 19 .max = 16, 20 .types = BIT(NL80211_IFTYPE_AP) 21 #ifdef CONFIG_MAC80211_MESH 22 | BIT(NL80211_IFTYPE_MESH_POINT) 23 #endif 24 }, { 25 .max = MT7915_MAX_INTERFACES, 26 .types = BIT(NL80211_IFTYPE_STATION) 27 } 28 }; 29 30 static const struct ieee80211_iface_combination if_comb[] = { 31 { 32 .limits = if_limits, 33 .n_limits = ARRAY_SIZE(if_limits), 34 .max_interfaces = MT7915_MAX_INTERFACES, 35 .num_different_channels = 1, 36 .beacon_int_infra_match = true, 37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 38 BIT(NL80211_CHAN_WIDTH_20) | 39 BIT(NL80211_CHAN_WIDTH_40) | 40 BIT(NL80211_CHAN_WIDTH_80) | 41 BIT(NL80211_CHAN_WIDTH_160) | 42 BIT(NL80211_CHAN_WIDTH_80P80), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 temperature = mt7915_mcu_get_temperature(phy); 57 if (temperature < 0) 58 return temperature; 59 /* display in millidegree celcius */ 60 return sprintf(buf, "%u\n", temperature * 1000); 61 case 1: 62 case 2: 63 return sprintf(buf, "%u\n", 64 phy->throttle_temp[i - 1] * 1000); 65 case 3: 66 return sprintf(buf, "%hhu\n", phy->throttle_state); 67 default: 68 return -EINVAL; 69 } 70 } 71 72 static ssize_t mt7915_thermal_temp_store(struct device *dev, 73 struct device_attribute *attr, 74 const char *buf, size_t count) 75 { 76 struct mt7915_phy *phy = dev_get_drvdata(dev); 77 int ret, i = to_sensor_dev_attr(attr)->index; 78 long val; 79 80 ret = kstrtol(buf, 10, &val); 81 if (ret < 0) 82 return ret; 83 84 mutex_lock(&phy->dev->mt76.mutex); 85 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 86 phy->throttle_temp[i - 1] = val; 87 mutex_unlock(&phy->dev->mt76.mutex); 88 89 return count; 90 } 91 92 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 93 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 94 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 95 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 96 97 static struct attribute *mt7915_hwmon_attrs[] = { 98 &sensor_dev_attr_temp1_input.dev_attr.attr, 99 &sensor_dev_attr_temp1_crit.dev_attr.attr, 100 &sensor_dev_attr_temp1_max.dev_attr.attr, 101 &sensor_dev_attr_throttle1.dev_attr.attr, 102 NULL, 103 }; 104 ATTRIBUTE_GROUPS(mt7915_hwmon); 105 106 static int 107 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 108 unsigned long *state) 109 { 110 *state = MT7915_CDEV_THROTTLE_MAX; 111 112 return 0; 113 } 114 115 static int 116 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 117 unsigned long *state) 118 { 119 struct mt7915_phy *phy = cdev->devdata; 120 121 *state = phy->cdev_state; 122 123 return 0; 124 } 125 126 static int 127 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 128 unsigned long state) 129 { 130 struct mt7915_phy *phy = cdev->devdata; 131 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 132 int ret; 133 134 if (state > MT7915_CDEV_THROTTLE_MAX) 135 return -EINVAL; 136 137 if (phy->throttle_temp[0] > phy->throttle_temp[1]) 138 return 0; 139 140 if (state == phy->cdev_state) 141 return 0; 142 143 /* 144 * cooling_device convention: 0 = no cooling, more = more cooling 145 * mcu convention: 1 = max cooling, more = less cooling 146 */ 147 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 148 if (ret) 149 return ret; 150 151 phy->cdev_state = state; 152 153 return 0; 154 } 155 156 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 157 .get_max_state = mt7915_thermal_get_max_throttle_state, 158 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 159 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 160 }; 161 162 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 163 { 164 struct wiphy *wiphy = phy->mt76->hw->wiphy; 165 166 if (!phy->cdev) 167 return; 168 169 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 170 thermal_cooling_device_unregister(phy->cdev); 171 } 172 173 static int mt7915_thermal_init(struct mt7915_phy *phy) 174 { 175 struct wiphy *wiphy = phy->mt76->hw->wiphy; 176 struct thermal_cooling_device *cdev; 177 struct device *hwmon; 178 const char *name; 179 180 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 181 wiphy_name(wiphy)); 182 183 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 184 if (!IS_ERR(cdev)) { 185 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 186 "cooling_device") < 0) 187 thermal_cooling_device_unregister(cdev); 188 else 189 phy->cdev = cdev; 190 } 191 192 if (!IS_REACHABLE(CONFIG_HWMON)) 193 return 0; 194 195 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 196 mt7915_hwmon_groups); 197 if (IS_ERR(hwmon)) 198 return PTR_ERR(hwmon); 199 200 /* initialize critical/maximum high temperature */ 201 phy->throttle_temp[0] = 110; 202 phy->throttle_temp[1] = 120; 203 204 return mt7915_mcu_set_thermal_throttling(phy, 205 MT7915_THERMAL_THROTTLE_MAX); 206 } 207 208 static void mt7915_led_set_config(struct led_classdev *led_cdev, 209 u8 delay_on, u8 delay_off) 210 { 211 struct mt7915_dev *dev; 212 struct mt76_dev *mt76; 213 u32 val; 214 215 mt76 = container_of(led_cdev, struct mt76_dev, led_cdev); 216 dev = container_of(mt76, struct mt7915_dev, mt76); 217 218 /* select TX blink mode, 2: only data frames */ 219 mt76_rmw_field(dev, MT_TMAC_TCR0(0), MT_TMAC_TCR0_TX_BLINK, 2); 220 221 /* enable LED */ 222 mt76_wr(dev, MT_LED_EN(0), 1); 223 224 /* set LED Tx blink on/off time */ 225 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 226 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 227 mt76_wr(dev, MT_LED_TX_BLINK(0), val); 228 229 /* control LED */ 230 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 231 if (dev->mt76.led_al) 232 val |= MT_LED_CTRL_POLARITY; 233 234 mt76_wr(dev, MT_LED_CTRL(0), val); 235 mt76_clear(dev, MT_LED_CTRL(0), MT_LED_CTRL_KICK); 236 } 237 238 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 239 unsigned long *delay_on, 240 unsigned long *delay_off) 241 { 242 u16 delta_on = 0, delta_off = 0; 243 244 #define HW_TICK 10 245 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 246 247 if (*delay_on) 248 delta_on = TO_HW_TICK(*delay_on); 249 if (*delay_off) 250 delta_off = TO_HW_TICK(*delay_off); 251 252 mt7915_led_set_config(led_cdev, delta_on, delta_off); 253 254 return 0; 255 } 256 257 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 258 enum led_brightness brightness) 259 { 260 if (!brightness) 261 mt7915_led_set_config(led_cdev, 0, 0xff); 262 else 263 mt7915_led_set_config(led_cdev, 0xff, 0); 264 } 265 266 void mt7915_init_txpower(struct mt7915_dev *dev, 267 struct ieee80211_supported_band *sband) 268 { 269 int i, n_chains = hweight8(dev->mphy.antenna_mask); 270 int nss_delta = mt76_tx_power_nss_delta(n_chains); 271 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 272 struct mt76_power_limits limits; 273 274 for (i = 0; i < sband->n_channels; i++) { 275 struct ieee80211_channel *chan = &sband->channels[i]; 276 u32 target_power = 0; 277 int j; 278 279 for (j = 0; j < n_chains; j++) { 280 u32 val; 281 282 val = mt7915_eeprom_get_target_power(dev, chan, j); 283 target_power = max(target_power, val); 284 } 285 286 target_power += pwr_delta; 287 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 288 &limits, 289 target_power); 290 target_power += nss_delta; 291 target_power = DIV_ROUND_UP(target_power, 2); 292 chan->max_power = min_t(int, chan->max_reg_power, 293 target_power); 294 chan->orig_mpwr = target_power; 295 } 296 } 297 298 static void 299 mt7915_regd_notifier(struct wiphy *wiphy, 300 struct regulatory_request *request) 301 { 302 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 303 struct mt7915_dev *dev = mt7915_hw_dev(hw); 304 struct mt76_phy *mphy = hw->priv; 305 struct mt7915_phy *phy = mphy->priv; 306 307 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 308 dev->mt76.region = request->dfs_region; 309 310 if (dev->mt76.region == NL80211_DFS_UNSET) 311 mt7915_mcu_rdd_background_enable(phy, NULL); 312 313 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 314 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 315 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 316 317 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 318 mt7915_dfs_init_radar_detector(phy); 319 } 320 321 static void 322 mt7915_init_wiphy(struct ieee80211_hw *hw) 323 { 324 struct mt7915_phy *phy = mt7915_hw_phy(hw); 325 struct mt76_dev *mdev = &phy->dev->mt76; 326 struct wiphy *wiphy = hw->wiphy; 327 struct mt7915_dev *dev = phy->dev; 328 329 hw->queues = 4; 330 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 331 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 332 hw->netdev_features = NETIF_F_RXCSUM; 333 334 hw->radiotap_timestamp.units_pos = 335 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 336 337 phy->slottime = 9; 338 339 hw->sta_data_size = sizeof(struct mt7915_sta); 340 hw->vif_data_size = sizeof(struct mt7915_vif); 341 342 wiphy->iface_combinations = if_comb; 343 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 344 wiphy->reg_notifier = mt7915_regd_notifier; 345 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 346 wiphy->mbssid_max_interfaces = 16; 347 348 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 349 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 350 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 351 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 352 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 353 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 354 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 355 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 356 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 357 358 if (!mdev->dev->of_node || 359 !of_property_read_bool(mdev->dev->of_node, 360 "mediatek,disable-radar-background")) 361 wiphy_ext_feature_set(wiphy, 362 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 363 364 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 365 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 366 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 367 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 368 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 369 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 370 371 hw->max_tx_fragments = 4; 372 373 if (phy->mt76->cap.has_2ghz) { 374 phy->mt76->sband_2g.sband.ht_cap.cap |= 375 IEEE80211_HT_CAP_LDPC_CODING | 376 IEEE80211_HT_CAP_MAX_AMSDU; 377 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 378 IEEE80211_HT_MPDU_DENSITY_4; 379 } 380 381 if (phy->mt76->cap.has_5ghz) { 382 phy->mt76->sband_5g.sband.ht_cap.cap |= 383 IEEE80211_HT_CAP_LDPC_CODING | 384 IEEE80211_HT_CAP_MAX_AMSDU; 385 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 386 IEEE80211_HT_MPDU_DENSITY_4; 387 388 if (is_mt7915(&dev->mt76)) { 389 phy->mt76->sband_5g.sband.vht_cap.cap |= 390 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 391 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 392 393 if (!dev->dbdc_support) 394 phy->mt76->sband_5g.sband.vht_cap.cap |= 395 IEEE80211_VHT_CAP_SHORT_GI_160 | 396 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ; 397 } else { 398 phy->mt76->sband_5g.sband.vht_cap.cap |= 399 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 400 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 401 402 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 403 phy->mt76->sband_5g.sband.vht_cap.cap |= 404 IEEE80211_VHT_CAP_SHORT_GI_160 | 405 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 406 } 407 } 408 409 mt76_set_stream_caps(phy->mt76, true); 410 mt7915_set_stream_vht_txbf_caps(phy); 411 mt7915_set_stream_he_caps(phy); 412 413 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 414 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 415 } 416 417 static void 418 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 419 { 420 u32 mask, set; 421 422 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 423 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 424 mt76_set(dev, MT_TMAC_CTCR0(band), 425 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 426 MT_TMAC_CTCR0_INS_DDLMT_EN); 427 428 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 429 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 430 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 431 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 432 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 433 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 434 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 435 436 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 437 MT_MDP_RCFR1_RX_DROPPED_UCAST | 438 MT_MDP_RCFR1_RX_DROPPED_MCAST; 439 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 440 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 441 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 442 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 443 444 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 445 446 /* mt7915: disable rx rate report by default due to hw issues */ 447 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 448 449 /* clear estimated value of EIFS for Rx duration & OBSS time */ 450 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 451 452 /* clear backoff time for Rx duration */ 453 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 454 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 455 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 456 MT_WF_RMAC_MIB_QOS01_BACKOFF); 457 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 458 MT_WF_RMAC_MIB_QOS23_BACKOFF); 459 460 /* clear backoff time and set software compensation for OBSS time */ 461 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 462 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 463 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 464 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 465 466 /* filter out non-resp frames and get instanstaeous signal reporting */ 467 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 468 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 469 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 470 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 471 } 472 473 void mt7915_mac_init(struct mt7915_dev *dev) 474 { 475 int i; 476 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 477 478 /* config pse qid6 wfdma port selection */ 479 if (!is_mt7915(&dev->mt76) && dev->hif2) 480 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 481 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 482 483 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 484 485 if (!is_mt7915(&dev->mt76)) 486 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 487 488 /* enable hardware de-agg */ 489 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 490 491 for (i = 0; i < mt7915_wtbl_size(dev); i++) 492 mt7915_mac_wtbl_update(dev, i, 493 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 494 for (i = 0; i < 2; i++) 495 mt7915_mac_init_band(dev, i); 496 497 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 498 i = dev->mt76.led_pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 499 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 500 } 501 } 502 503 int mt7915_txbf_init(struct mt7915_dev *dev) 504 { 505 int ret; 506 507 if (dev->dbdc_support) { 508 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 509 if (ret) 510 return ret; 511 } 512 513 /* trigger sounding packets */ 514 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 515 if (ret) 516 return ret; 517 518 /* enable eBF */ 519 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 520 } 521 522 static struct mt7915_phy * 523 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 524 { 525 struct mt7915_phy *phy; 526 struct mt76_phy *mphy; 527 528 if (!dev->dbdc_support) 529 return NULL; 530 531 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 532 if (!mphy) 533 return ERR_PTR(-ENOMEM); 534 535 phy = mphy->priv; 536 phy->dev = dev; 537 phy->mt76 = mphy; 538 539 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 540 phy->band_idx = 1; 541 542 return phy; 543 } 544 545 static int 546 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 547 { 548 struct mt76_phy *mphy = phy->mt76; 549 int ret; 550 551 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 552 553 mt7915_eeprom_parse_hw_cap(dev, phy); 554 555 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 556 ETH_ALEN); 557 /* Make the secondary PHY MAC address local without overlapping with 558 * the usual MAC address allocation scheme on multiple virtual interfaces 559 */ 560 if (!is_valid_ether_addr(mphy->macaddr)) { 561 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 562 ETH_ALEN); 563 mphy->macaddr[0] |= 2; 564 mphy->macaddr[0] ^= BIT(7); 565 } 566 mt76_eeprom_override(mphy); 567 568 /* init wiphy according to mphy and phy */ 569 mt7915_init_wiphy(mphy->hw); 570 571 ret = mt76_register_phy(mphy, true, mt76_rates, 572 ARRAY_SIZE(mt76_rates)); 573 if (ret) 574 return ret; 575 576 ret = mt7915_thermal_init(phy); 577 if (ret) 578 goto unreg; 579 580 mt7915_init_debugfs(phy); 581 582 return 0; 583 584 unreg: 585 mt76_unregister_phy(mphy); 586 return ret; 587 } 588 589 static void mt7915_init_work(struct work_struct *work) 590 { 591 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 592 init_work); 593 594 mt7915_mcu_set_eeprom(dev); 595 mt7915_mac_init(dev); 596 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 597 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 598 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 599 mt7915_txbf_init(dev); 600 } 601 602 void mt7915_wfsys_reset(struct mt7915_dev *dev) 603 { 604 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 605 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 606 607 if (is_mt7915(&dev->mt76)) { 608 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 609 610 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 611 612 /* change to software control */ 613 val |= MT_TOP_PWR_SW_RST; 614 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 615 616 /* reset wfsys */ 617 val &= ~MT_TOP_PWR_SW_RST; 618 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 619 620 /* release wfsys then mcu re-executes romcode */ 621 val |= MT_TOP_PWR_SW_RST; 622 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 623 624 /* switch to hw control */ 625 val &= ~MT_TOP_PWR_SW_RST; 626 val |= MT_TOP_PWR_HW_CTRL; 627 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 628 629 /* check whether mcu resets to default */ 630 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 631 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 632 1000)) { 633 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 634 return; 635 } 636 637 /* wfsys reset won't clear host registers */ 638 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 639 640 msleep(100); 641 } else if (is_mt7986(&dev->mt76)) { 642 mt7986_wmac_disable(dev); 643 msleep(20); 644 645 mt7986_wmac_enable(dev); 646 msleep(20); 647 } else { 648 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 649 msleep(20); 650 651 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 652 msleep(20); 653 } 654 } 655 656 static bool mt7915_band_config(struct mt7915_dev *dev) 657 { 658 bool ret = true; 659 660 dev->phy.band_idx = 0; 661 662 if (is_mt7986(&dev->mt76)) { 663 u32 sku = mt7915_check_adie(dev, true); 664 665 /* 666 * for mt7986, dbdc support is determined by the number 667 * of adie chips and the main phy is bound to band1 when 668 * dbdc is disabled. 669 */ 670 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 671 dev->phy.band_idx = 1; 672 ret = false; 673 } 674 } else { 675 ret = is_mt7915(&dev->mt76) ? 676 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 677 } 678 679 return ret; 680 } 681 682 static int 683 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 684 { 685 int ret, idx; 686 687 mt76_wr(dev, MT_INT_MASK_CSR, 0); 688 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 689 690 INIT_WORK(&dev->init_work, mt7915_init_work); 691 692 ret = mt7915_dma_init(dev, phy2); 693 if (ret) 694 return ret; 695 696 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 697 698 ret = mt7915_mcu_init(dev); 699 if (ret) 700 return ret; 701 702 ret = mt7915_eeprom_init(dev); 703 if (ret < 0) 704 return ret; 705 706 if (dev->flash_mode) { 707 ret = mt7915_mcu_apply_group_cal(dev); 708 if (ret) 709 return ret; 710 } 711 712 /* Beacon and mgmt frames should occupy wcid 0 */ 713 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 714 if (idx) 715 return -ENOSPC; 716 717 dev->mt76.global_wcid.idx = idx; 718 dev->mt76.global_wcid.hw_key_idx = -1; 719 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 720 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 721 722 return 0; 723 } 724 725 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 726 { 727 int sts; 728 u32 *cap; 729 730 if (!phy->mt76->cap.has_5ghz) 731 return; 732 733 sts = hweight8(phy->mt76->chainmask); 734 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 735 736 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 737 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 738 (3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 739 740 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 741 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 742 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 743 744 if (sts < 2) 745 return; 746 747 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 748 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 749 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 750 sts - 1); 751 } 752 753 static void 754 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 755 struct ieee80211_sta_he_cap *he_cap, int vif) 756 { 757 struct mt7915_dev *dev = phy->dev; 758 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 759 int sts = hweight8(phy->mt76->chainmask); 760 u8 c, sts_160 = sts; 761 762 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 763 if (is_mt7915(&dev->mt76) && !dev->dbdc_support) 764 sts_160 /= 2; 765 766 #ifdef CONFIG_MAC80211_MESH 767 if (vif == NL80211_IFTYPE_MESH_POINT) 768 return; 769 #endif 770 771 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 772 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 773 774 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 775 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 776 elem->phy_cap_info[5] &= ~c; 777 778 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 779 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 780 elem->phy_cap_info[6] &= ~c; 781 782 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 783 784 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 785 if (!is_mt7915(&dev->mt76)) 786 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 787 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 788 elem->phy_cap_info[2] |= c; 789 790 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 791 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 792 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 793 elem->phy_cap_info[4] |= c; 794 795 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 796 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 797 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 798 799 if (vif == NL80211_IFTYPE_STATION) 800 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 801 802 elem->phy_cap_info[6] |= c; 803 804 if (sts < 2) 805 return; 806 807 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 808 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 809 810 if (vif != NL80211_IFTYPE_AP) 811 return; 812 813 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 814 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 815 816 /* num_snd_dim 817 * for mt7915, max supported sts is 2 for bw > 80MHz 818 */ 819 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 820 sts - 1) | 821 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 822 sts_160 - 1); 823 elem->phy_cap_info[5] |= c; 824 825 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 826 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 827 elem->phy_cap_info[6] |= c; 828 829 if (!is_mt7915(&dev->mt76)) { 830 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 831 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 832 elem->phy_cap_info[7] |= c; 833 } 834 } 835 836 static void 837 mt7915_gen_ppe_thresh(u8 *he_ppet, int nss) 838 { 839 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */ 840 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71}; 841 842 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | 843 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, 844 ru_bit_mask); 845 846 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE * 847 nss * hweight8(ru_bit_mask) * 2; 848 ppet_size = DIV_ROUND_UP(ppet_bits, 8); 849 850 for (i = 0; i < ppet_size - 1; i++) 851 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3]; 852 853 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] & 854 (0xff >> (8 - (ppet_bits - 1) % 8)); 855 } 856 857 static int 858 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 859 struct ieee80211_sband_iftype_data *data) 860 { 861 struct mt7915_dev *dev = phy->dev; 862 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 863 u16 mcs_map = 0; 864 u16 mcs_map_160 = 0; 865 u8 nss_160; 866 867 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 868 if (is_mt7915(&dev->mt76) && !dev->dbdc_support) 869 nss_160 = nss / 2; 870 else 871 nss_160 = nss; 872 873 for (i = 0; i < 8; i++) { 874 if (i < nss) 875 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 876 else 877 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 878 879 if (i < nss_160) 880 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 881 else 882 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 883 } 884 885 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 886 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 887 struct ieee80211_he_cap_elem *he_cap_elem = 888 &he_cap->he_cap_elem; 889 struct ieee80211_he_mcs_nss_supp *he_mcs = 890 &he_cap->he_mcs_nss_supp; 891 892 switch (i) { 893 case NL80211_IFTYPE_STATION: 894 case NL80211_IFTYPE_AP: 895 #ifdef CONFIG_MAC80211_MESH 896 case NL80211_IFTYPE_MESH_POINT: 897 #endif 898 break; 899 default: 900 continue; 901 } 902 903 data[idx].types_mask = BIT(i); 904 he_cap->has_he = true; 905 906 he_cap_elem->mac_cap_info[0] = 907 IEEE80211_HE_MAC_CAP0_HTC_HE; 908 he_cap_elem->mac_cap_info[3] = 909 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 910 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 911 he_cap_elem->mac_cap_info[4] = 912 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 913 914 if (band == NL80211_BAND_2GHZ) 915 he_cap_elem->phy_cap_info[0] = 916 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 917 else 918 he_cap_elem->phy_cap_info[0] = 919 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 920 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G | 921 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; 922 923 he_cap_elem->phy_cap_info[1] = 924 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 925 he_cap_elem->phy_cap_info[2] = 926 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 927 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 928 929 switch (i) { 930 case NL80211_IFTYPE_AP: 931 he_cap_elem->mac_cap_info[0] |= 932 IEEE80211_HE_MAC_CAP0_TWT_RES; 933 he_cap_elem->mac_cap_info[2] |= 934 IEEE80211_HE_MAC_CAP2_BSR; 935 he_cap_elem->mac_cap_info[4] |= 936 IEEE80211_HE_MAC_CAP4_BQR; 937 he_cap_elem->mac_cap_info[5] |= 938 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 939 he_cap_elem->phy_cap_info[3] |= 940 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 941 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 942 he_cap_elem->phy_cap_info[6] |= 943 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 944 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 945 he_cap_elem->phy_cap_info[9] |= 946 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 947 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 948 break; 949 case NL80211_IFTYPE_STATION: 950 he_cap_elem->mac_cap_info[1] |= 951 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 952 953 if (band == NL80211_BAND_2GHZ) 954 he_cap_elem->phy_cap_info[0] |= 955 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 956 else 957 he_cap_elem->phy_cap_info[0] |= 958 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 959 960 he_cap_elem->phy_cap_info[1] |= 961 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 962 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 963 he_cap_elem->phy_cap_info[3] |= 964 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 965 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 966 he_cap_elem->phy_cap_info[6] |= 967 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 968 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 969 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 970 he_cap_elem->phy_cap_info[7] |= 971 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 972 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 973 he_cap_elem->phy_cap_info[8] |= 974 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 975 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 976 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 977 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 978 he_cap_elem->phy_cap_info[9] |= 979 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 980 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 981 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 982 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 983 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 984 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 985 break; 986 } 987 988 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 989 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 990 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 991 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 992 he_mcs->rx_mcs_80p80 = cpu_to_le16(mcs_map_160); 993 he_mcs->tx_mcs_80p80 = cpu_to_le16(mcs_map_160); 994 995 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 996 997 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 998 if (he_cap_elem->phy_cap_info[6] & 999 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1000 mt7915_gen_ppe_thresh(he_cap->ppe_thres, nss); 1001 } else { 1002 he_cap_elem->phy_cap_info[9] |= 1003 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1004 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1005 } 1006 1007 if (band == NL80211_BAND_6GHZ) { 1008 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1009 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1010 1011 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1012 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1013 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1014 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1015 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1016 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1017 1018 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1019 } 1020 1021 idx++; 1022 } 1023 1024 return idx; 1025 } 1026 1027 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1028 { 1029 struct ieee80211_sband_iftype_data *data; 1030 struct ieee80211_supported_band *band; 1031 int n; 1032 1033 if (phy->mt76->cap.has_2ghz) { 1034 data = phy->iftype[NL80211_BAND_2GHZ]; 1035 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1036 1037 band = &phy->mt76->sband_2g.sband; 1038 band->iftype_data = data; 1039 band->n_iftype_data = n; 1040 } 1041 1042 if (phy->mt76->cap.has_5ghz) { 1043 data = phy->iftype[NL80211_BAND_5GHZ]; 1044 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1045 1046 band = &phy->mt76->sband_5g.sband; 1047 band->iftype_data = data; 1048 band->n_iftype_data = n; 1049 } 1050 1051 if (phy->mt76->cap.has_6ghz) { 1052 data = phy->iftype[NL80211_BAND_6GHZ]; 1053 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1054 1055 band = &phy->mt76->sband_6g.sband; 1056 band->iftype_data = data; 1057 band->n_iftype_data = n; 1058 } 1059 } 1060 1061 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1062 { 1063 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1064 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1065 1066 if (!phy) 1067 return; 1068 1069 mt7915_unregister_thermal(phy); 1070 mt76_unregister_phy(mphy); 1071 ieee80211_free_hw(mphy->hw); 1072 } 1073 1074 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1075 { 1076 mt7915_mcu_exit(dev); 1077 mt7915_tx_token_put(dev); 1078 mt7915_dma_cleanup(dev); 1079 tasklet_disable(&dev->irq_tasklet); 1080 1081 if (is_mt7986(&dev->mt76)) 1082 mt7986_wmac_disable(dev); 1083 } 1084 1085 1086 int mt7915_register_device(struct mt7915_dev *dev) 1087 { 1088 struct ieee80211_hw *hw = mt76_hw(dev); 1089 struct mt7915_phy *phy2; 1090 int ret; 1091 1092 dev->phy.dev = dev; 1093 dev->phy.mt76 = &dev->mt76.phy; 1094 dev->mt76.phy.priv = &dev->phy; 1095 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1096 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1097 INIT_LIST_HEAD(&dev->sta_rc_list); 1098 INIT_LIST_HEAD(&dev->sta_poll_list); 1099 INIT_LIST_HEAD(&dev->twt_list); 1100 spin_lock_init(&dev->sta_poll_lock); 1101 1102 init_waitqueue_head(&dev->reset_wait); 1103 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1104 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1105 mutex_init(&dev->dump_mutex); 1106 1107 dev->dbdc_support = mt7915_band_config(dev); 1108 1109 phy2 = mt7915_alloc_ext_phy(dev); 1110 if (IS_ERR(phy2)) 1111 return PTR_ERR(phy2); 1112 1113 ret = mt7915_init_hardware(dev, phy2); 1114 if (ret) 1115 goto free_phy2; 1116 1117 mt7915_init_wiphy(hw); 1118 1119 #ifdef CONFIG_NL80211_TESTMODE 1120 dev->mt76.test_ops = &mt7915_testmode_ops; 1121 #endif 1122 1123 /* init led callbacks */ 1124 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 1125 dev->mt76.led_cdev.brightness_set = mt7915_led_set_brightness; 1126 dev->mt76.led_cdev.blink_set = mt7915_led_set_blink; 1127 } 1128 1129 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1130 ARRAY_SIZE(mt76_rates)); 1131 if (ret) 1132 goto stop_hw; 1133 1134 ret = mt7915_thermal_init(&dev->phy); 1135 if (ret) 1136 goto unreg_dev; 1137 1138 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1139 1140 if (phy2) { 1141 ret = mt7915_register_ext_phy(dev, phy2); 1142 if (ret) 1143 goto unreg_thermal; 1144 } 1145 1146 dev->recovery.hw_init_done = true; 1147 1148 ret = mt7915_init_debugfs(&dev->phy); 1149 if (ret) 1150 goto unreg_thermal; 1151 1152 ret = mt7915_coredump_register(dev); 1153 if (ret) 1154 goto unreg_thermal; 1155 1156 return 0; 1157 1158 unreg_thermal: 1159 mt7915_unregister_thermal(&dev->phy); 1160 unreg_dev: 1161 mt76_unregister_device(&dev->mt76); 1162 stop_hw: 1163 mt7915_stop_hardware(dev); 1164 free_phy2: 1165 if (phy2) 1166 ieee80211_free_hw(phy2->mt76->hw); 1167 return ret; 1168 } 1169 1170 void mt7915_unregister_device(struct mt7915_dev *dev) 1171 { 1172 mt7915_unregister_ext_phy(dev); 1173 mt7915_coredump_unregister(dev); 1174 mt7915_unregister_thermal(&dev->phy); 1175 mt76_unregister_device(&dev->mt76); 1176 mt7915_stop_hardware(dev); 1177 1178 mt76_free_device(&dev->mt76); 1179 } 1180