1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/relay.h> 5 #include "mt7915.h" 6 #include "eeprom.h" 7 #include "mcu.h" 8 #include "mac.h" 9 10 #define FW_BIN_LOG_MAGIC 0x44e98caf 11 12 /** global debugfs **/ 13 14 struct hw_queue_map { 15 const char *name; 16 u8 index; 17 u8 pid; 18 u8 qid; 19 }; 20 21 static int 22 mt7915_implicit_txbf_set(void *data, u64 val) 23 { 24 struct mt7915_dev *dev = data; 25 26 /* The existing connected stations shall reconnect to apply 27 * new implicit txbf configuration. 28 */ 29 dev->ibf = !!val; 30 31 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 32 } 33 34 static int 35 mt7915_implicit_txbf_get(void *data, u64 *val) 36 { 37 struct mt7915_dev *dev = data; 38 39 *val = dev->ibf; 40 41 return 0; 42 } 43 44 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get, 45 mt7915_implicit_txbf_set, "%lld\n"); 46 47 /* test knob of system error recovery */ 48 static ssize_t 49 mt7915_sys_recovery_set(struct file *file, const char __user *user_buf, 50 size_t count, loff_t *ppos) 51 { 52 struct mt7915_phy *phy = file->private_data; 53 struct mt7915_dev *dev = phy->dev; 54 bool band = phy->mt76->band_idx; 55 char buf[16]; 56 int ret = 0; 57 u16 val; 58 59 if (count >= sizeof(buf)) 60 return -EINVAL; 61 62 if (copy_from_user(buf, user_buf, count)) 63 return -EFAULT; 64 65 if (count && buf[count - 1] == '\n') 66 buf[count - 1] = '\0'; 67 else 68 buf[count] = '\0'; 69 70 if (kstrtou16(buf, 0, &val)) 71 return -EINVAL; 72 73 switch (val) { 74 /* 75 * 0: grab firmware current SER state. 76 * 1: trigger & enable system error L1 recovery. 77 * 2: trigger & enable system error L2 recovery. 78 * 3: trigger & enable system error L3 rx abort. 79 * 4: trigger & enable system error L3 tx abort 80 * 5: trigger & enable system error L3 tx disable. 81 * 6: trigger & enable system error L3 bf recovery. 82 * 7: trigger & enable system error full recovery. 83 * 8: trigger firmware crash. 84 */ 85 case SER_QUERY: 86 ret = mt7915_mcu_set_ser(dev, 0, 0, band); 87 break; 88 case SER_SET_RECOVER_L1: 89 case SER_SET_RECOVER_L2: 90 case SER_SET_RECOVER_L3_RX_ABORT: 91 case SER_SET_RECOVER_L3_TX_ABORT: 92 case SER_SET_RECOVER_L3_TX_DISABLE: 93 case SER_SET_RECOVER_L3_BF: 94 ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), band); 95 if (ret) 96 return ret; 97 98 ret = mt7915_mcu_set_ser(dev, SER_RECOVER, val, band); 99 break; 100 101 /* enable full chip reset */ 102 case SER_SET_RECOVER_FULL: 103 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 104 ret = mt7915_mcu_set_ser(dev, 1, 3, band); 105 if (ret) 106 return ret; 107 108 dev->recovery.state |= MT_MCU_CMD_WDT_MASK; 109 mt7915_reset(dev); 110 break; 111 112 /* WARNING: trigger firmware crash */ 113 case SER_SET_SYSTEM_ASSERT: 114 mt76_wr(dev, MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR, BIT(18)); 115 mt76_wr(dev, MT_MCU_WM_CIRQ_EINT_SOFT_ADDR, BIT(18)); 116 break; 117 default: 118 break; 119 } 120 121 return ret ? ret : count; 122 } 123 124 static ssize_t 125 mt7915_sys_recovery_get(struct file *file, char __user *user_buf, 126 size_t count, loff_t *ppos) 127 { 128 struct mt7915_phy *phy = file->private_data; 129 struct mt7915_dev *dev = phy->dev; 130 char *buff; 131 int desc = 0; 132 ssize_t ret; 133 static const size_t bufsz = 1024; 134 135 buff = kmalloc(bufsz, GFP_KERNEL); 136 if (!buff) 137 return -ENOMEM; 138 139 /* HELP */ 140 desc += scnprintf(buff + desc, bufsz - desc, 141 "Please echo the correct value ...\n"); 142 desc += scnprintf(buff + desc, bufsz - desc, 143 "0: grab firmware transient SER state\n"); 144 desc += scnprintf(buff + desc, bufsz - desc, 145 "1: trigger system error L1 recovery\n"); 146 desc += scnprintf(buff + desc, bufsz - desc, 147 "2: trigger system error L2 recovery\n"); 148 desc += scnprintf(buff + desc, bufsz - desc, 149 "3: trigger system error L3 rx abort\n"); 150 desc += scnprintf(buff + desc, bufsz - desc, 151 "4: trigger system error L3 tx abort\n"); 152 desc += scnprintf(buff + desc, bufsz - desc, 153 "5: trigger system error L3 tx disable\n"); 154 desc += scnprintf(buff + desc, bufsz - desc, 155 "6: trigger system error L3 bf recovery\n"); 156 desc += scnprintf(buff + desc, bufsz - desc, 157 "7: trigger system error full recovery\n"); 158 desc += scnprintf(buff + desc, bufsz - desc, 159 "8: trigger firmware crash\n"); 160 161 /* SER statistics */ 162 desc += scnprintf(buff + desc, bufsz - desc, 163 "\nlet's dump firmware SER statistics...\n"); 164 desc += scnprintf(buff + desc, bufsz - desc, 165 "::E R , SER_STATUS = 0x%08x\n", 166 mt76_rr(dev, MT_SWDEF_SER_STATS)); 167 desc += scnprintf(buff + desc, bufsz - desc, 168 "::E R , SER_PLE_ERR = 0x%08x\n", 169 mt76_rr(dev, MT_SWDEF_PLE_STATS)); 170 desc += scnprintf(buff + desc, bufsz - desc, 171 "::E R , SER_PLE_ERR_1 = 0x%08x\n", 172 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); 173 desc += scnprintf(buff + desc, bufsz - desc, 174 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n", 175 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); 176 desc += scnprintf(buff + desc, bufsz - desc, 177 "::E R , SER_PSE_ERR = 0x%08x\n", 178 mt76_rr(dev, MT_SWDEF_PSE_STATS)); 179 desc += scnprintf(buff + desc, bufsz - desc, 180 "::E R , SER_PSE_ERR_1 = 0x%08x\n", 181 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); 182 desc += scnprintf(buff + desc, bufsz - desc, 183 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n", 184 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); 185 desc += scnprintf(buff + desc, bufsz - desc, 186 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n", 187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); 188 desc += scnprintf(buff + desc, bufsz - desc, 189 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n", 190 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); 191 desc += scnprintf(buff + desc, bufsz - desc, 192 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n", 193 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); 194 desc += scnprintf(buff + desc, bufsz - desc, 195 "\nSYS_RESET_COUNT: WM %d, WA %d\n", 196 dev->recovery.wm_reset_count, 197 dev->recovery.wa_reset_count); 198 199 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); 200 kfree(buff); 201 return ret; 202 } 203 204 static const struct file_operations mt7915_sys_recovery_ops = { 205 .write = mt7915_sys_recovery_set, 206 .read = mt7915_sys_recovery_get, 207 .open = simple_open, 208 .llseek = default_llseek, 209 }; 210 211 static int 212 mt7915_radar_trigger(void *data, u64 val) 213 { 214 struct mt7915_dev *dev = data; 215 216 if (val > MT_RX_SEL2) 217 return -EINVAL; 218 219 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_RADAR_EMULATE, 220 val, 0, 0); 221 } 222 223 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, 224 mt7915_radar_trigger, "%lld\n"); 225 226 static int 227 mt7915_muru_debug_set(void *data, u64 val) 228 { 229 struct mt7915_dev *dev = data; 230 231 dev->muru_debug = val; 232 mt7915_mcu_muru_debug_set(dev, dev->muru_debug); 233 234 return 0; 235 } 236 237 static int 238 mt7915_muru_debug_get(void *data, u64 *val) 239 { 240 struct mt7915_dev *dev = data; 241 242 *val = dev->muru_debug; 243 244 return 0; 245 } 246 247 DEFINE_DEBUGFS_ATTRIBUTE(fops_muru_debug, mt7915_muru_debug_get, 248 mt7915_muru_debug_set, "%lld\n"); 249 250 static int mt7915_muru_stats_show(struct seq_file *file, void *data) 251 { 252 struct mt7915_phy *phy = file->private; 253 struct mt7915_dev *dev = phy->dev; 254 static const char * const dl_non_he_type[] = { 255 "CCK", "OFDM", "HT MIX", "HT GF", 256 "VHT SU", "VHT 2MU", "VHT 3MU", "VHT 4MU" 257 }; 258 static const char * const dl_he_type[] = { 259 "HE SU", "HE EXT", "HE 2MU", "HE 3MU", "HE 4MU", 260 "HE 2RU", "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", 261 "HE >16RU" 262 }; 263 static const char * const ul_he_type[] = { 264 "HE 2MU", "HE 3MU", "HE 4MU", "HE SU", "HE 2RU", 265 "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", "HE >16RU" 266 }; 267 int ret, i; 268 u64 total_ppdu_cnt, sub_total_cnt; 269 270 if (!dev->muru_debug) { 271 seq_puts(file, "Please enable muru_debug first.\n"); 272 return 0; 273 } 274 275 mutex_lock(&dev->mt76.mutex); 276 277 ret = mt7915_mcu_muru_debug_get(phy); 278 if (ret) 279 goto exit; 280 281 /* Non-HE Downlink*/ 282 seq_puts(file, "[Non-HE]\nDownlink\nData Type: "); 283 284 for (i = 0; i < 5; i++) 285 seq_printf(file, "%8s | ", dl_non_he_type[i]); 286 287 seq_puts(file, "\nTotal Count:"); 288 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | ", 289 phy->mib.dl_cck_cnt, 290 phy->mib.dl_ofdm_cnt, 291 phy->mib.dl_htmix_cnt, 292 phy->mib.dl_htgf_cnt, 293 phy->mib.dl_vht_su_cnt); 294 295 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); 296 297 for (i = 5; i < 8; i++) 298 seq_printf(file, "%8s | ", dl_non_he_type[i]); 299 300 seq_puts(file, "\nTotal Count:"); 301 seq_printf(file, "%8u | %8u | %8u | ", 302 phy->mib.dl_vht_2mu_cnt, 303 phy->mib.dl_vht_3mu_cnt, 304 phy->mib.dl_vht_4mu_cnt); 305 306 sub_total_cnt = (u64)phy->mib.dl_vht_2mu_cnt + 307 phy->mib.dl_vht_3mu_cnt + 308 phy->mib.dl_vht_4mu_cnt; 309 310 seq_printf(file, "\nTotal non-HE MU-MIMO DL PPDU count: %lld", 311 sub_total_cnt); 312 313 total_ppdu_cnt = sub_total_cnt + 314 phy->mib.dl_cck_cnt + 315 phy->mib.dl_ofdm_cnt + 316 phy->mib.dl_htmix_cnt + 317 phy->mib.dl_htgf_cnt + 318 phy->mib.dl_vht_su_cnt; 319 320 seq_printf(file, "\nAll non-HE DL PPDU count: %lld", total_ppdu_cnt); 321 322 /* HE Downlink */ 323 seq_puts(file, "\n\n[HE]\nDownlink\nData Type: "); 324 325 for (i = 0; i < 2; i++) 326 seq_printf(file, "%8s | ", dl_he_type[i]); 327 328 seq_puts(file, "\nTotal Count:"); 329 seq_printf(file, "%8u | %8u | ", 330 phy->mib.dl_he_su_cnt, phy->mib.dl_he_ext_su_cnt); 331 332 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); 333 334 for (i = 2; i < 5; i++) 335 seq_printf(file, "%8s | ", dl_he_type[i]); 336 337 seq_puts(file, "\nTotal Count:"); 338 seq_printf(file, "%8u | %8u | %8u | ", 339 phy->mib.dl_he_2mu_cnt, phy->mib.dl_he_3mu_cnt, 340 phy->mib.dl_he_4mu_cnt); 341 342 seq_puts(file, "\nDownlink OFDMA\nData Type: "); 343 344 for (i = 5; i < 11; i++) 345 seq_printf(file, "%8s | ", dl_he_type[i]); 346 347 seq_puts(file, "\nTotal Count:"); 348 seq_printf(file, "%8u | %8u | %8u | %8u | %9u | %8u | ", 349 phy->mib.dl_he_2ru_cnt, 350 phy->mib.dl_he_3ru_cnt, 351 phy->mib.dl_he_4ru_cnt, 352 phy->mib.dl_he_5to8ru_cnt, 353 phy->mib.dl_he_9to16ru_cnt, 354 phy->mib.dl_he_gtr16ru_cnt); 355 356 sub_total_cnt = (u64)phy->mib.dl_he_2mu_cnt + 357 phy->mib.dl_he_3mu_cnt + 358 phy->mib.dl_he_4mu_cnt; 359 total_ppdu_cnt = sub_total_cnt; 360 361 seq_printf(file, "\nTotal HE MU-MIMO DL PPDU count: %lld", 362 sub_total_cnt); 363 364 sub_total_cnt = (u64)phy->mib.dl_he_2ru_cnt + 365 phy->mib.dl_he_3ru_cnt + 366 phy->mib.dl_he_4ru_cnt + 367 phy->mib.dl_he_5to8ru_cnt + 368 phy->mib.dl_he_9to16ru_cnt + 369 phy->mib.dl_he_gtr16ru_cnt; 370 total_ppdu_cnt += sub_total_cnt; 371 372 seq_printf(file, "\nTotal HE OFDMA DL PPDU count: %lld", 373 sub_total_cnt); 374 375 total_ppdu_cnt += (u64)phy->mib.dl_he_su_cnt + 376 phy->mib.dl_he_ext_su_cnt; 377 378 seq_printf(file, "\nAll HE DL PPDU count: %lld", total_ppdu_cnt); 379 380 /* HE Uplink */ 381 seq_puts(file, "\n\nUplink"); 382 seq_puts(file, "\nTrigger-based Uplink MU-MIMO\nData Type: "); 383 384 for (i = 0; i < 3; i++) 385 seq_printf(file, "%8s | ", ul_he_type[i]); 386 387 seq_puts(file, "\nTotal Count:"); 388 seq_printf(file, "%8u | %8u | %8u | ", 389 phy->mib.ul_hetrig_2mu_cnt, 390 phy->mib.ul_hetrig_3mu_cnt, 391 phy->mib.ul_hetrig_4mu_cnt); 392 393 seq_puts(file, "\nTrigger-based Uplink OFDMA\nData Type: "); 394 395 for (i = 3; i < 10; i++) 396 seq_printf(file, "%8s | ", ul_he_type[i]); 397 398 seq_puts(file, "\nTotal Count:"); 399 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | %9u | %7u | ", 400 phy->mib.ul_hetrig_su_cnt, 401 phy->mib.ul_hetrig_2ru_cnt, 402 phy->mib.ul_hetrig_3ru_cnt, 403 phy->mib.ul_hetrig_4ru_cnt, 404 phy->mib.ul_hetrig_5to8ru_cnt, 405 phy->mib.ul_hetrig_9to16ru_cnt, 406 phy->mib.ul_hetrig_gtr16ru_cnt); 407 408 sub_total_cnt = (u64)phy->mib.ul_hetrig_2mu_cnt + 409 phy->mib.ul_hetrig_3mu_cnt + 410 phy->mib.ul_hetrig_4mu_cnt; 411 total_ppdu_cnt = sub_total_cnt; 412 413 seq_printf(file, "\nTotal HE MU-MIMO UL TB PPDU count: %lld", 414 sub_total_cnt); 415 416 sub_total_cnt = (u64)phy->mib.ul_hetrig_2ru_cnt + 417 phy->mib.ul_hetrig_3ru_cnt + 418 phy->mib.ul_hetrig_4ru_cnt + 419 phy->mib.ul_hetrig_5to8ru_cnt + 420 phy->mib.ul_hetrig_9to16ru_cnt + 421 phy->mib.ul_hetrig_gtr16ru_cnt; 422 total_ppdu_cnt += sub_total_cnt; 423 424 seq_printf(file, "\nTotal HE OFDMA UL TB PPDU count: %lld", 425 sub_total_cnt); 426 427 total_ppdu_cnt += phy->mib.ul_hetrig_su_cnt; 428 429 seq_printf(file, "\nAll HE UL TB PPDU count: %lld\n", total_ppdu_cnt); 430 431 exit: 432 mutex_unlock(&dev->mt76.mutex); 433 434 return ret; 435 } 436 DEFINE_SHOW_ATTRIBUTE(mt7915_muru_stats); 437 438 static int 439 mt7915_rdd_monitor(struct seq_file *s, void *data) 440 { 441 struct mt7915_dev *dev = dev_get_drvdata(s->private); 442 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; 443 const char *bw; 444 int ret = 0; 445 446 mutex_lock(&dev->mt76.mutex); 447 448 if (!cfg80211_chandef_valid(chandef)) { 449 ret = -EINVAL; 450 goto out; 451 } 452 453 if (!dev->rdd2_phy) { 454 seq_puts(s, "not running\n"); 455 goto out; 456 } 457 458 switch (chandef->width) { 459 case NL80211_CHAN_WIDTH_40: 460 bw = "40"; 461 break; 462 case NL80211_CHAN_WIDTH_80: 463 bw = "80"; 464 break; 465 case NL80211_CHAN_WIDTH_160: 466 bw = "160"; 467 break; 468 case NL80211_CHAN_WIDTH_80P80: 469 bw = "80P80"; 470 break; 471 default: 472 bw = "20"; 473 break; 474 } 475 476 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", 477 chandef->chan->hw_value, chandef->chan->center_freq, 478 bw, chandef->center_freq1); 479 out: 480 mutex_unlock(&dev->mt76.mutex); 481 482 return ret; 483 } 484 485 static int 486 mt7915_fw_debug_wm_set(void *data, u64 val) 487 { 488 struct mt7915_dev *dev = data; 489 enum { 490 DEBUG_TXCMD = 62, 491 DEBUG_CMD_RPT_TX, 492 DEBUG_CMD_RPT_TRIG, 493 DEBUG_SPL, 494 DEBUG_RPT_RX, 495 } debug; 496 bool tx, rx, en; 497 int ret; 498 499 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; 500 501 if (dev->fw.debug_bin) 502 val = 16; 503 else 504 val = dev->fw.debug_wm; 505 506 tx = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(1)); 507 rx = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(2)); 508 en = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(0)); 509 510 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); 511 if (ret) 512 goto out; 513 514 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RX; debug++) { 515 if (debug == DEBUG_RPT_RX) 516 val = en && rx; 517 else 518 val = en && tx; 519 520 ret = mt7915_mcu_fw_dbg_ctrl(dev, debug, val); 521 if (ret) 522 goto out; 523 } 524 525 /* WM CPU info record control */ 526 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0)); 527 mt76_wr(dev, MT_DIC_CMD_REG_CMD, BIT(2) | BIT(13) | 528 (dev->fw.debug_wm ? 0 : BIT(0))); 529 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5)); 530 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5)); 531 532 out: 533 if (ret) 534 dev->fw.debug_wm = 0; 535 536 return ret; 537 } 538 539 static int 540 mt7915_fw_debug_wm_get(void *data, u64 *val) 541 { 542 struct mt7915_dev *dev = data; 543 544 *val = dev->fw.debug_wm; 545 546 return 0; 547 } 548 549 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7915_fw_debug_wm_get, 550 mt7915_fw_debug_wm_set, "%lld\n"); 551 552 static int 553 mt7915_fw_debug_wa_set(void *data, u64 val) 554 { 555 struct mt7915_dev *dev = data; 556 int ret; 557 558 dev->fw.debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; 559 560 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw.debug_wa); 561 if (ret) 562 goto out; 563 564 ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 565 MCU_WA_PARAM_PDMA_RX, !!dev->fw.debug_wa, 0); 566 out: 567 if (ret) 568 dev->fw.debug_wa = 0; 569 570 return ret; 571 } 572 573 static int 574 mt7915_fw_debug_wa_get(void *data, u64 *val) 575 { 576 struct mt7915_dev *dev = data; 577 578 *val = dev->fw.debug_wa; 579 580 return 0; 581 } 582 583 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7915_fw_debug_wa_get, 584 mt7915_fw_debug_wa_set, "%lld\n"); 585 586 static struct dentry * 587 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, 588 struct rchan_buf *buf, int *is_global) 589 { 590 struct dentry *f; 591 592 f = debugfs_create_file("fwlog_data", mode, parent, buf, 593 &relay_file_operations); 594 if (IS_ERR(f)) 595 return NULL; 596 597 *is_global = 1; 598 599 return f; 600 } 601 602 static int 603 remove_buf_file_cb(struct dentry *f) 604 { 605 debugfs_remove(f); 606 607 return 0; 608 } 609 610 static int 611 mt7915_fw_debug_bin_set(void *data, u64 val) 612 { 613 static struct rchan_callbacks relay_cb = { 614 .create_buf_file = create_buf_file_cb, 615 .remove_buf_file = remove_buf_file_cb, 616 }; 617 struct mt7915_dev *dev = data; 618 619 if (!dev->relay_fwlog) 620 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, 621 1500, 512, &relay_cb, NULL); 622 if (!dev->relay_fwlog) 623 return -ENOMEM; 624 625 dev->fw.debug_bin = val; 626 627 relay_reset(dev->relay_fwlog); 628 629 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm); 630 } 631 632 static int 633 mt7915_fw_debug_bin_get(void *data, u64 *val) 634 { 635 struct mt7915_dev *dev = data; 636 637 *val = dev->fw.debug_bin; 638 639 return 0; 640 } 641 642 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7915_fw_debug_bin_get, 643 mt7915_fw_debug_bin_set, "%lld\n"); 644 645 static int 646 mt7915_fw_util_wm_show(struct seq_file *file, void *data) 647 { 648 struct mt7915_dev *dev = file->private; 649 650 seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WM_MCU_PC)); 651 652 if (dev->fw.debug_wm) { 653 seq_printf(file, "Busy: %u%% Peak busy: %u%%\n", 654 mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT), 655 mt76_rr(dev, MT_CPU_UTIL_PEAK_BUSY_PCT)); 656 seq_printf(file, "Idle count: %u Peak idle count: %u\n", 657 mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT), 658 mt76_rr(dev, MT_CPU_UTIL_PEAK_IDLE_CNT)); 659 } 660 661 return 0; 662 } 663 664 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wm); 665 666 static int 667 mt7915_fw_util_wa_show(struct seq_file *file, void *data) 668 { 669 struct mt7915_dev *dev = file->private; 670 671 seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WA_MCU_PC)); 672 673 if (dev->fw.debug_wa) 674 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), 675 MCU_WA_PARAM_CPU_UTIL, 0, 0); 676 677 return 0; 678 } 679 680 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wa); 681 682 static void 683 mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy, 684 struct seq_file *file) 685 { 686 struct mt7915_dev *dev = phy->dev; 687 bool ext_phy = phy != &dev->phy; 688 int bound[15], range[4], i; 689 u8 band = phy->mt76->band_idx; 690 691 /* Tx ampdu stat */ 692 for (i = 0; i < ARRAY_SIZE(range); i++) 693 range[i] = mt76_rr(dev, MT_MIB_ARNG(band, i)); 694 695 for (i = 0; i < ARRAY_SIZE(bound); i++) 696 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1; 697 698 seq_printf(file, "\nPhy %d, Phy band %d\n", ext_phy, band); 699 700 seq_printf(file, "Length: %8d | ", bound[0]); 701 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) 702 seq_printf(file, "%3d -%3d | ", 703 bound[i] + 1, bound[i + 1]); 704 705 seq_puts(file, "\nCount: "); 706 for (i = 0; i < ARRAY_SIZE(bound); i++) 707 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]); 708 seq_puts(file, "\n"); 709 710 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); 711 } 712 713 static void 714 mt7915_txbf_stat_read_phy(struct mt7915_phy *phy, struct seq_file *s) 715 { 716 struct mt76_mib_stats *mib = &phy->mib; 717 static const char * const bw[] = { 718 "BW20", "BW40", "BW80", "BW160" 719 }; 720 721 /* Tx Beamformer monitor */ 722 seq_puts(s, "\nTx Beamformer applied PPDU counts: "); 723 724 seq_printf(s, "iBF: %d, eBF: %d\n", 725 mib->tx_bf_ibf_ppdu_cnt, 726 mib->tx_bf_ebf_ppdu_cnt); 727 728 /* Tx Beamformer Rx feedback monitor */ 729 seq_puts(s, "Tx Beamformer Rx feedback statistics: "); 730 731 seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ", 732 mib->tx_bf_rx_fb_all_cnt, 733 mib->tx_bf_rx_fb_he_cnt, 734 mib->tx_bf_rx_fb_vht_cnt, 735 mib->tx_bf_rx_fb_ht_cnt); 736 737 seq_printf(s, "%s, NC: %d, NR: %d\n", 738 bw[mib->tx_bf_rx_fb_bw], 739 mib->tx_bf_rx_fb_nc_cnt, 740 mib->tx_bf_rx_fb_nr_cnt); 741 742 /* Tx Beamformee Rx NDPA & Tx feedback report */ 743 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", 744 mib->tx_bf_fb_cpl_cnt); 745 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", 746 mib->tx_bf_fb_trig_cnt); 747 748 /* Tx SU & MU counters */ 749 seq_printf(s, "Tx multi-user Beamforming counts: %d\n", 750 mib->tx_bf_cnt); 751 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); 752 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", 753 mib->tx_mu_acked_mpdu_cnt); 754 seq_printf(s, "Tx single-user successful MPDU counts: %d\n", 755 mib->tx_su_acked_mpdu_cnt); 756 757 seq_puts(s, "\n"); 758 } 759 760 static int 761 mt7915_tx_stats_show(struct seq_file *file, void *data) 762 { 763 struct mt7915_phy *phy = file->private; 764 struct mt7915_dev *dev = phy->dev; 765 struct mt76_mib_stats *mib = &phy->mib; 766 int i; 767 768 mutex_lock(&dev->mt76.mutex); 769 770 mt7915_ampdu_stat_read_phy(phy, file); 771 mt7915_mac_update_stats(phy); 772 mt7915_txbf_stat_read_phy(phy, file); 773 774 /* Tx amsdu info */ 775 seq_puts(file, "Tx MSDU statistics:\n"); 776 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 777 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", 778 i + 1, mib->tx_amsdu[i]); 779 if (mib->tx_amsdu_cnt) 780 seq_printf(file, "(%3d%%)\n", 781 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); 782 else 783 seq_puts(file, "\n"); 784 } 785 786 mutex_unlock(&dev->mt76.mutex); 787 788 return 0; 789 } 790 791 DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats); 792 793 static void 794 mt7915_hw_queue_read(struct seq_file *s, u32 size, 795 const struct hw_queue_map *map) 796 { 797 struct mt7915_phy *phy = s->private; 798 struct mt7915_dev *dev = phy->dev; 799 u32 i, val; 800 801 val = mt76_rr(dev, MT_FL_Q_EMPTY); 802 for (i = 0; i < size; i++) { 803 u32 ctrl, head, tail, queued; 804 805 if (val & BIT(map[i].index)) 806 continue; 807 808 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24); 809 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); 810 811 head = mt76_get_field(dev, MT_FL_Q2_CTRL, 812 GENMASK(11, 0)); 813 tail = mt76_get_field(dev, MT_FL_Q2_CTRL, 814 GENMASK(27, 16)); 815 queued = mt76_get_field(dev, MT_FL_Q3_CTRL, 816 GENMASK(11, 0)); 817 818 seq_printf(s, "\t%s: ", map[i].name); 819 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", 820 queued, head, tail); 821 } 822 } 823 824 static void 825 mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) 826 { 827 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 828 struct mt7915_dev *dev = msta->vif->phy->dev; 829 struct seq_file *s = data; 830 u8 ac; 831 832 for (ac = 0; ac < 4; ac++) { 833 u32 qlen, ctrl, val; 834 u32 idx = msta->wcid.idx >> 5; 835 u8 offs = msta->wcid.idx & GENMASK(4, 0); 836 837 ctrl = BIT(31) | BIT(11) | (ac << 24); 838 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); 839 840 if (val & BIT(offs)) 841 continue; 842 843 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx); 844 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, 845 GENMASK(11, 0)); 846 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", 847 sta->addr, msta->wcid.idx, 848 msta->vif->mt76.wmm_idx, ac, qlen); 849 } 850 } 851 852 static int 853 mt7915_hw_queues_show(struct seq_file *file, void *data) 854 { 855 struct mt7915_phy *phy = file->private; 856 struct mt7915_dev *dev = phy->dev; 857 static const struct hw_queue_map ple_queue_map[] = { 858 { "CPU_Q0", 0, 1, MT_CTX0 }, 859 { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, 860 { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, 861 { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, 862 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, 863 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, 864 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, 865 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, 866 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, 867 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, 868 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, 869 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, 870 }; 871 static const struct hw_queue_map pse_queue_map[] = { 872 { "CPU Q0", 0, 1, MT_CTX0 }, 873 { "CPU Q1", 1, 1, MT_CTX0 + 1 }, 874 { "CPU Q2", 2, 1, MT_CTX0 + 2 }, 875 { "CPU Q3", 3, 1, MT_CTX0 + 3 }, 876 { "HIF_Q0", 8, 0, MT_HIF0 }, 877 { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, 878 { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, 879 { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, 880 { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, 881 { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, 882 { "LMAC_Q", 16, 2, 0 }, 883 { "MDP_TXQ", 17, 2, 1 }, 884 { "MDP_RXQ", 18, 2, 2 }, 885 { "SEC_TXQ", 19, 2, 3 }, 886 { "SEC_RXQ", 20, 2, 4 }, 887 }; 888 u32 val, head, tail; 889 890 /* ple queue */ 891 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); 892 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); 893 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); 894 seq_puts(file, "PLE page info:\n"); 895 seq_printf(file, 896 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", 897 val, head, tail); 898 899 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); 900 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); 901 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); 902 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", 903 val, head, tail); 904 905 seq_puts(file, "PLE non-empty queue info:\n"); 906 mt7915_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), 907 &ple_queue_map[0]); 908 909 /* iterate per-sta ple queue */ 910 ieee80211_iterate_stations_atomic(phy->mt76->hw, 911 mt7915_sta_hw_queue_read, file); 912 /* pse queue */ 913 seq_puts(file, "PSE non-empty queue info:\n"); 914 mt7915_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), 915 &pse_queue_map[0]); 916 917 return 0; 918 } 919 920 DEFINE_SHOW_ATTRIBUTE(mt7915_hw_queues); 921 922 static int 923 mt7915_xmit_queues_show(struct seq_file *file, void *data) 924 { 925 struct mt7915_phy *phy = file->private; 926 struct mt7915_dev *dev = phy->dev; 927 struct { 928 struct mt76_queue *q; 929 char *queue; 930 } queue_map[] = { 931 { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" }, 932 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, 933 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, 934 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, 935 }; 936 int i; 937 938 seq_puts(file, " queue | hw-queued | head | tail |\n"); 939 for (i = 0; i < ARRAY_SIZE(queue_map); i++) { 940 struct mt76_queue *q = queue_map[i].q; 941 942 if (!q) 943 continue; 944 945 seq_printf(file, " %s | %9d | %9d | %9d |\n", 946 queue_map[i].queue, q->queued, q->head, 947 q->tail); 948 } 949 950 return 0; 951 } 952 953 DEFINE_SHOW_ATTRIBUTE(mt7915_xmit_queues); 954 955 #define mt7915_txpower_puts(rate) \ 956 ({ \ 957 len += scnprintf(buf + len, sz - len, "%-16s:", #rate " (TMAC)"); \ 958 for (i = 0; i < mt7915_sku_group_len[SKU_##rate]; i++, offs++) \ 959 len += scnprintf(buf + len, sz - len, " %6d", txpwr[offs]); \ 960 len += scnprintf(buf + len, sz - len, "\n"); \ 961 }) 962 963 #define mt7915_txpower_sets(rate, pwr, flag) \ 964 ({ \ 965 offs += len; \ 966 len = mt7915_sku_group_len[rate]; \ 967 if (mode == flag) { \ 968 for (i = 0; i < len; i++) \ 969 req.txpower_sku[offs + i] = pwr; \ 970 } \ 971 }) 972 973 static ssize_t 974 mt7915_rate_txpower_get(struct file *file, char __user *user_buf, 975 size_t count, loff_t *ppos) 976 { 977 struct mt7915_phy *phy = file->private_data; 978 struct mt7915_dev *dev = phy->dev; 979 s8 txpwr[MT7915_SKU_RATE_NUM]; 980 static const size_t sz = 2048; 981 u8 band = phy->mt76->band_idx; 982 int i, offs = 0, len = 0; 983 ssize_t ret; 984 char *buf; 985 u32 reg; 986 987 buf = kzalloc(sz, GFP_KERNEL); 988 if (!buf) 989 return -ENOMEM; 990 991 ret = mt7915_mcu_get_txpower_sku(phy, txpwr, sizeof(txpwr)); 992 if (ret) 993 goto out; 994 995 /* Txpower propagation path: TMAC -> TXV -> BBP */ 996 len += scnprintf(buf + len, sz - len, 997 "\nPhy%d Tx power table (channel %d)\n", 998 phy != &dev->phy, phy->mt76->chandef.chan->hw_value); 999 len += scnprintf(buf + len, sz - len, "%-16s %6s %6s %6s %6s\n", 1000 " ", "1m", "2m", "5m", "11m"); 1001 mt7915_txpower_puts(CCK); 1002 1003 len += scnprintf(buf + len, sz - len, 1004 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1005 " ", "6m", "9m", "12m", "18m", "24m", "36m", "48m", 1006 "54m"); 1007 mt7915_txpower_puts(OFDM); 1008 1009 len += scnprintf(buf + len, sz - len, 1010 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1011 " ", "mcs0", "mcs1", "mcs2", "mcs3", "mcs4", 1012 "mcs5", "mcs6", "mcs7"); 1013 mt7915_txpower_puts(HT_BW20); 1014 1015 len += scnprintf(buf + len, sz - len, 1016 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1017 " ", "mcs0", "mcs1", "mcs2", "mcs3", "mcs4", "mcs5", 1018 "mcs6", "mcs7", "mcs32"); 1019 mt7915_txpower_puts(HT_BW40); 1020 1021 len += scnprintf(buf + len, sz - len, 1022 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1023 " ", "mcs0", "mcs1", "mcs2", "mcs3", "mcs4", "mcs5", 1024 "mcs6", "mcs7", "mcs8", "mcs9", "mcs10", "mcs11"); 1025 mt7915_txpower_puts(VHT_BW20); 1026 mt7915_txpower_puts(VHT_BW40); 1027 mt7915_txpower_puts(VHT_BW80); 1028 mt7915_txpower_puts(VHT_BW160); 1029 mt7915_txpower_puts(HE_RU26); 1030 mt7915_txpower_puts(HE_RU52); 1031 mt7915_txpower_puts(HE_RU106); 1032 mt7915_txpower_puts(HE_RU242); 1033 mt7915_txpower_puts(HE_RU484); 1034 mt7915_txpower_puts(HE_RU996); 1035 mt7915_txpower_puts(HE_RU2x996); 1036 1037 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_TPC_CTRL_STAT(band) : 1038 MT_WF_PHY_TPC_CTRL_STAT_MT7916(band); 1039 1040 len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld\n", 1041 mt76_get_field(dev, reg, MT_WF_PHY_TPC_POWER)); 1042 1043 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 1044 1045 out: 1046 kfree(buf); 1047 return ret; 1048 } 1049 1050 static ssize_t 1051 mt7915_rate_txpower_set(struct file *file, const char __user *user_buf, 1052 size_t count, loff_t *ppos) 1053 { 1054 int i, ret, pwr, pwr160 = 0, pwr80 = 0, pwr40 = 0, pwr20 = 0; 1055 struct mt7915_phy *phy = file->private_data; 1056 struct mt7915_dev *dev = phy->dev; 1057 struct mt76_phy *mphy = phy->mt76; 1058 struct mt7915_mcu_txpower_sku req = { 1059 .format_id = TX_POWER_LIMIT_TABLE, 1060 .band_idx = phy->mt76->band_idx, 1061 }; 1062 char buf[100]; 1063 enum mac80211_rx_encoding mode; 1064 u32 offs = 0, len = 0; 1065 1066 if (count >= sizeof(buf)) 1067 return -EINVAL; 1068 1069 if (copy_from_user(buf, user_buf, count)) 1070 return -EFAULT; 1071 1072 if (count && buf[count - 1] == '\n') 1073 buf[count - 1] = '\0'; 1074 else 1075 buf[count] = '\0'; 1076 1077 if (sscanf(buf, "%u %u %u %u %u", 1078 &mode, &pwr160, &pwr80, &pwr40, &pwr20) != 5) { 1079 dev_warn(dev->mt76.dev, 1080 "per bandwidth power limit: Mode BW160 BW80 BW40 BW20"); 1081 return -EINVAL; 1082 } 1083 1084 if (mode > RX_ENC_HE) 1085 return -EINVAL; 1086 1087 if (pwr160) 1088 pwr160 = mt76_get_power_bound(mphy, pwr160); 1089 if (pwr80) 1090 pwr80 = mt76_get_power_bound(mphy, pwr80); 1091 if (pwr40) 1092 pwr40 = mt76_get_power_bound(mphy, pwr40); 1093 if (pwr20) 1094 pwr20 = mt76_get_power_bound(mphy, pwr20); 1095 1096 if (pwr160 < 0 || pwr80 < 0 || pwr40 < 0 || pwr20 < 0) 1097 return -EINVAL; 1098 1099 mutex_lock(&dev->mt76.mutex); 1100 ret = mt7915_mcu_get_txpower_sku(phy, req.txpower_sku, 1101 sizeof(req.txpower_sku)); 1102 if (ret) 1103 goto out; 1104 1105 mt7915_txpower_sets(SKU_CCK, pwr20, RX_ENC_LEGACY); 1106 mt7915_txpower_sets(SKU_OFDM, pwr20, RX_ENC_LEGACY); 1107 if (mode == RX_ENC_LEGACY) 1108 goto skip; 1109 1110 mt7915_txpower_sets(SKU_HT_BW20, pwr20, RX_ENC_HT); 1111 mt7915_txpower_sets(SKU_HT_BW40, pwr40, RX_ENC_HT); 1112 if (mode == RX_ENC_HT) 1113 goto skip; 1114 1115 mt7915_txpower_sets(SKU_VHT_BW20, pwr20, RX_ENC_VHT); 1116 mt7915_txpower_sets(SKU_VHT_BW40, pwr40, RX_ENC_VHT); 1117 mt7915_txpower_sets(SKU_VHT_BW80, pwr80, RX_ENC_VHT); 1118 mt7915_txpower_sets(SKU_VHT_BW160, pwr160, RX_ENC_VHT); 1119 if (mode == RX_ENC_VHT) 1120 goto skip; 1121 1122 mt7915_txpower_sets(SKU_HE_RU26, pwr20, RX_ENC_HE + 1); 1123 mt7915_txpower_sets(SKU_HE_RU52, pwr20, RX_ENC_HE + 1); 1124 mt7915_txpower_sets(SKU_HE_RU106, pwr20, RX_ENC_HE + 1); 1125 mt7915_txpower_sets(SKU_HE_RU242, pwr20, RX_ENC_HE); 1126 mt7915_txpower_sets(SKU_HE_RU484, pwr40, RX_ENC_HE); 1127 mt7915_txpower_sets(SKU_HE_RU996, pwr80, RX_ENC_HE); 1128 mt7915_txpower_sets(SKU_HE_RU2x996, pwr160, RX_ENC_HE); 1129 skip: 1130 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 1131 &req, sizeof(req), true); 1132 if (ret) 1133 goto out; 1134 1135 pwr = max3(pwr80, pwr40, pwr20); 1136 mphy->txpower_cur = max3(mphy->txpower_cur, pwr160, pwr); 1137 out: 1138 mutex_unlock(&dev->mt76.mutex); 1139 1140 return ret ? ret : count; 1141 } 1142 1143 static const struct file_operations mt7915_rate_txpower_fops = { 1144 .write = mt7915_rate_txpower_set, 1145 .read = mt7915_rate_txpower_get, 1146 .open = simple_open, 1147 .owner = THIS_MODULE, 1148 .llseek = default_llseek, 1149 }; 1150 1151 static int 1152 mt7915_twt_stats(struct seq_file *s, void *data) 1153 { 1154 struct mt7915_dev *dev = dev_get_drvdata(s->private); 1155 struct mt7915_twt_flow *iter; 1156 1157 rcu_read_lock(); 1158 1159 seq_puts(s, " wcid | id | flags | exp | mantissa"); 1160 seq_puts(s, " | duration | tsf |\n"); 1161 list_for_each_entry_rcu(iter, &dev->twt_list, list) 1162 seq_printf(s, 1163 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", 1164 iter->wcid, iter->id, 1165 iter->sched ? 's' : 'u', 1166 iter->protection ? 'p' : '-', 1167 iter->trigger ? 't' : '-', 1168 iter->flowtype ? '-' : 'a', 1169 iter->exp, iter->mantissa, 1170 iter->duration, iter->tsf); 1171 1172 rcu_read_unlock(); 1173 1174 return 0; 1175 } 1176 1177 /* The index of RF registers use the generic regidx, combined with two parts: 1178 * WF selection [31:24] and offset [23:0]. 1179 */ 1180 static int 1181 mt7915_rf_regval_get(void *data, u64 *val) 1182 { 1183 struct mt7915_dev *dev = data; 1184 u32 regval; 1185 int ret; 1186 1187 ret = mt7915_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false); 1188 if (ret) 1189 return ret; 1190 1191 *val = regval; 1192 1193 return 0; 1194 } 1195 1196 static int 1197 mt7915_rf_regval_set(void *data, u64 val) 1198 { 1199 struct mt7915_dev *dev = data; 1200 u32 val32 = val; 1201 1202 return mt7915_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true); 1203 } 1204 1205 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7915_rf_regval_get, 1206 mt7915_rf_regval_set, "0x%08llx\n"); 1207 1208 int mt7915_init_debugfs(struct mt7915_phy *phy) 1209 { 1210 struct mt7915_dev *dev = phy->dev; 1211 bool ext_phy = phy != &dev->phy; 1212 struct dentry *dir; 1213 1214 dir = mt76_register_debugfs_fops(phy->mt76, NULL); 1215 if (!dir) 1216 return -ENOMEM; 1217 debugfs_create_file("muru_debug", 0600, dir, dev, &fops_muru_debug); 1218 debugfs_create_file("muru_stats", 0400, dir, phy, 1219 &mt7915_muru_stats_fops); 1220 debugfs_create_file("hw-queues", 0400, dir, phy, 1221 &mt7915_hw_queues_fops); 1222 debugfs_create_file("xmit-queues", 0400, dir, phy, 1223 &mt7915_xmit_queues_fops); 1224 debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops); 1225 debugfs_create_file("sys_recovery", 0600, dir, phy, 1226 &mt7915_sys_recovery_ops); 1227 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); 1228 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); 1229 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); 1230 debugfs_create_file("fw_util_wm", 0400, dir, dev, 1231 &mt7915_fw_util_wm_fops); 1232 debugfs_create_file("fw_util_wa", 0400, dir, dev, 1233 &mt7915_fw_util_wa_fops); 1234 debugfs_create_file("implicit_txbf", 0600, dir, dev, 1235 &fops_implicit_txbf); 1236 debugfs_create_file("txpower_sku", 0400, dir, phy, 1237 &mt7915_rate_txpower_fops); 1238 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, 1239 mt7915_twt_stats); 1240 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); 1241 1242 if (!dev->dbdc_support || phy->mt76->band_idx) { 1243 debugfs_create_u32("dfs_hw_pattern", 0400, dir, 1244 &dev->hw_pattern); 1245 debugfs_create_file("radar_trigger", 0200, dir, dev, 1246 &fops_radar_trigger); 1247 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, 1248 mt7915_rdd_monitor); 1249 } 1250 1251 if (!ext_phy) 1252 dev->debugfs_dir = dir; 1253 1254 return 0; 1255 } 1256 1257 static void 1258 mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen, 1259 const void *data, int len) 1260 { 1261 static DEFINE_SPINLOCK(lock); 1262 unsigned long flags; 1263 void *dest; 1264 1265 spin_lock_irqsave(&lock, flags); 1266 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); 1267 if (dest) { 1268 *(u32 *)dest = hdrlen + len; 1269 dest += 4; 1270 1271 if (hdrlen) { 1272 memcpy(dest, hdr, hdrlen); 1273 dest += hdrlen; 1274 } 1275 1276 memcpy(dest, data, len); 1277 relay_flush(dev->relay_fwlog); 1278 } 1279 spin_unlock_irqrestore(&lock, flags); 1280 } 1281 1282 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len) 1283 { 1284 struct { 1285 __le32 magic; 1286 __le32 timestamp; 1287 __le16 msg_type; 1288 __le16 len; 1289 } hdr = { 1290 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), 1291 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), 1292 }; 1293 1294 if (!dev->relay_fwlog) 1295 return; 1296 1297 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); 1298 hdr.len = *(__le16 *)data; 1299 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); 1300 } 1301 1302 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len) 1303 { 1304 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) 1305 return false; 1306 1307 if (dev->relay_fwlog) 1308 mt7915_debugfs_write_fwlog(dev, NULL, 0, data, len); 1309 1310 return true; 1311 } 1312 1313 #ifdef CONFIG_MAC80211_DEBUGFS 1314 /** per-station debugfs **/ 1315 1316 static ssize_t mt7915_sta_fixed_rate_set(struct file *file, 1317 const char __user *user_buf, 1318 size_t count, loff_t *ppos) 1319 { 1320 struct ieee80211_sta *sta = file->private_data; 1321 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 1322 struct mt7915_dev *dev = msta->vif->phy->dev; 1323 struct ieee80211_vif *vif; 1324 struct sta_phy phy = {}; 1325 char buf[100]; 1326 int ret; 1327 u32 field; 1328 u8 i, gi, he_ltf; 1329 1330 if (count >= sizeof(buf)) 1331 return -EINVAL; 1332 1333 if (copy_from_user(buf, user_buf, count)) 1334 return -EFAULT; 1335 1336 if (count && buf[count - 1] == '\n') 1337 buf[count - 1] = '\0'; 1338 else 1339 buf[count] = '\0'; 1340 1341 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 1342 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3 1343 * nss - vht: 1~4, he: 1~4, others: ignore 1344 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2 1345 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 1346 * ldpc - off: 0, on: 1 1347 * stbc - off: 0, on: 1 1348 * he_ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 1349 */ 1350 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hhu %hhu %hhu %hhu", 1351 &phy.type, &phy.bw, &phy.nss, &phy.mcs, &gi, 1352 &phy.ldpc, &phy.stbc, &he_ltf) != 8) { 1353 dev_warn(dev->mt76.dev, 1354 "format: Mode BW NSS MCS (HE)GI LDPC STBC HE_LTF\n"); 1355 field = RATE_PARAM_AUTO; 1356 goto out; 1357 } 1358 1359 phy.ldpc = (phy.bw || phy.ldpc) * GENMASK(2, 0); 1360 for (i = 0; i <= phy.bw; i++) { 1361 phy.sgi |= gi << (i << sta->deflink.he_cap.has_he); 1362 phy.he_ltf |= he_ltf << (i << sta->deflink.he_cap.has_he); 1363 } 1364 field = RATE_PARAM_FIXED; 1365 1366 out: 1367 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1368 ret = mt7915_mcu_set_fixed_rate_ctrl(dev, vif, sta, &phy, field); 1369 if (ret) 1370 return -EFAULT; 1371 1372 return count; 1373 } 1374 1375 static const struct file_operations fops_fixed_rate = { 1376 .write = mt7915_sta_fixed_rate_set, 1377 .open = simple_open, 1378 .owner = THIS_MODULE, 1379 .llseek = default_llseek, 1380 }; 1381 1382 static int 1383 mt7915_queues_show(struct seq_file *s, void *data) 1384 { 1385 struct ieee80211_sta *sta = s->private; 1386 1387 mt7915_sta_hw_queue_read(s, sta); 1388 1389 return 0; 1390 } 1391 1392 DEFINE_SHOW_ATTRIBUTE(mt7915_queues); 1393 1394 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1395 struct ieee80211_sta *sta, struct dentry *dir) 1396 { 1397 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate); 1398 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7915_queues_fops); 1399 } 1400 1401 #endif 1402