1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/relay.h> 5 #include "mt7915.h" 6 #include "eeprom.h" 7 #include "mcu.h" 8 #include "mac.h" 9 10 #define FW_BIN_LOG_MAGIC 0x44e98caf 11 12 /** global debugfs **/ 13 14 struct hw_queue_map { 15 const char *name; 16 u8 index; 17 u8 pid; 18 u8 qid; 19 }; 20 21 static int 22 mt7915_implicit_txbf_set(void *data, u64 val) 23 { 24 struct mt7915_dev *dev = data; 25 26 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) 27 return -EBUSY; 28 29 dev->ibf = !!val; 30 31 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 32 } 33 34 static int 35 mt7915_implicit_txbf_get(void *data, u64 *val) 36 { 37 struct mt7915_dev *dev = data; 38 39 *val = dev->ibf; 40 41 return 0; 42 } 43 44 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get, 45 mt7915_implicit_txbf_set, "%lld\n"); 46 47 /* test knob of system layer 1/2 error recovery */ 48 static int mt7915_ser_trigger_set(void *data, u64 val) 49 { 50 enum { 51 SER_SET_RECOVER_L1 = 1, 52 SER_SET_RECOVER_L2, 53 SER_ENABLE = 2, 54 SER_RECOVER 55 }; 56 struct mt7915_dev *dev = data; 57 int ret = 0; 58 59 switch (val) { 60 case SER_SET_RECOVER_L1: 61 case SER_SET_RECOVER_L2: 62 ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), 0); 63 if (ret) 64 return ret; 65 66 return mt7915_mcu_set_ser(dev, SER_RECOVER, val, 0); 67 default: 68 break; 69 } 70 71 return ret; 72 } 73 74 DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL, 75 mt7915_ser_trigger_set, "%lld\n"); 76 77 static int 78 mt7915_radar_trigger(void *data, u64 val) 79 { 80 struct mt7915_dev *dev = data; 81 82 if (val > MT_RX_SEL2) 83 return -EINVAL; 84 85 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_RADAR_EMULATE, 86 val, 0, 0); 87 } 88 89 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, 90 mt7915_radar_trigger, "%lld\n"); 91 92 static int 93 mt7915_muru_debug_set(void *data, u64 val) 94 { 95 struct mt7915_dev *dev = data; 96 97 dev->muru_debug = val; 98 mt7915_mcu_muru_debug_set(dev, data); 99 100 return 0; 101 } 102 103 static int 104 mt7915_muru_debug_get(void *data, u64 *val) 105 { 106 struct mt7915_dev *dev = data; 107 108 *val = dev->muru_debug; 109 110 return 0; 111 } 112 113 DEFINE_DEBUGFS_ATTRIBUTE(fops_muru_debug, mt7915_muru_debug_get, 114 mt7915_muru_debug_set, "%lld\n"); 115 116 static int mt7915_muru_stats_show(struct seq_file *file, void *data) 117 { 118 struct mt7915_phy *phy = file->private; 119 struct mt7915_dev *dev = phy->dev; 120 struct mt7915_mcu_muru_stats mu_stats = {}; 121 static const char * const dl_non_he_type[] = { 122 "CCK", "OFDM", "HT MIX", "HT GF", 123 "VHT SU", "VHT 2MU", "VHT 3MU", "VHT 4MU" 124 }; 125 static const char * const dl_he_type[] = { 126 "HE SU", "HE EXT", "HE 2MU", "HE 3MU", "HE 4MU", 127 "HE 2RU", "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", 128 "HE >16RU" 129 }; 130 static const char * const ul_he_type[] = { 131 "HE 2MU", "HE 3MU", "HE 4MU", "HE SU", "HE 2RU", 132 "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", "HE >16RU" 133 }; 134 int ret, i; 135 u64 total_ppdu_cnt, sub_total_cnt; 136 137 if (!dev->muru_debug) { 138 seq_puts(file, "Please enable muru_debug first.\n"); 139 return 0; 140 } 141 142 mutex_lock(&dev->mt76.mutex); 143 144 ret = mt7915_mcu_muru_debug_get(phy, &mu_stats); 145 if (ret) 146 goto exit; 147 148 /* Non-HE Downlink*/ 149 seq_puts(file, "[Non-HE]\nDownlink\nData Type: "); 150 151 for (i = 0; i < 5; i++) 152 seq_printf(file, "%8s | ", dl_non_he_type[i]); 153 154 #define __dl_u32(s) le32_to_cpu(mu_stats.dl.s) 155 seq_puts(file, "\nTotal Count:"); 156 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | ", 157 __dl_u32(cck_cnt), 158 __dl_u32(ofdm_cnt), 159 __dl_u32(htmix_cnt), 160 __dl_u32(htgf_cnt), 161 __dl_u32(vht_su_cnt)); 162 163 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); 164 165 for (i = 5; i < 8; i++) 166 seq_printf(file, "%8s | ", dl_non_he_type[i]); 167 168 seq_puts(file, "\nTotal Count:"); 169 seq_printf(file, "%8u | %8u | %8u | ", 170 __dl_u32(vht_2mu_cnt), 171 __dl_u32(vht_3mu_cnt), 172 __dl_u32(vht_4mu_cnt)); 173 174 sub_total_cnt = __dl_u32(vht_2mu_cnt) + 175 __dl_u32(vht_3mu_cnt) + 176 __dl_u32(vht_4mu_cnt); 177 178 seq_printf(file, "\nTotal non-HE MU-MIMO DL PPDU count: %lld", 179 sub_total_cnt); 180 181 total_ppdu_cnt = sub_total_cnt + 182 __dl_u32(cck_cnt) + 183 __dl_u32(ofdm_cnt) + 184 __dl_u32(htmix_cnt) + 185 __dl_u32(htgf_cnt) + 186 __dl_u32(vht_su_cnt); 187 188 seq_printf(file, "\nAll non-HE DL PPDU count: %lld", total_ppdu_cnt); 189 190 /* HE Downlink */ 191 seq_puts(file, "\n\n[HE]\nDownlink\nData Type: "); 192 193 for (i = 0; i < 2; i++) 194 seq_printf(file, "%8s | ", dl_he_type[i]); 195 196 seq_puts(file, "\nTotal Count:"); 197 seq_printf(file, "%8u | %8u | ", 198 __dl_u32(he_su_cnt), 199 __dl_u32(he_ext_su_cnt)); 200 201 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); 202 203 for (i = 2; i < 5; i++) 204 seq_printf(file, "%8s | ", dl_he_type[i]); 205 206 seq_puts(file, "\nTotal Count:"); 207 seq_printf(file, "%8u | %8u | %8u | ", 208 __dl_u32(he_2mu_cnt), 209 __dl_u32(he_3mu_cnt), 210 __dl_u32(he_4mu_cnt)); 211 212 seq_puts(file, "\nDownlink OFDMA\nData Type: "); 213 214 for (i = 5; i < 11; i++) 215 seq_printf(file, "%8s | ", dl_he_type[i]); 216 217 seq_puts(file, "\nTotal Count:"); 218 seq_printf(file, "%8u | %8u | %8u | %8u | %9u | %8u | ", 219 __dl_u32(he_2ru_cnt), 220 __dl_u32(he_3ru_cnt), 221 __dl_u32(he_4ru_cnt), 222 __dl_u32(he_5to8ru_cnt), 223 __dl_u32(he_9to16ru_cnt), 224 __dl_u32(he_gtr16ru_cnt)); 225 226 sub_total_cnt = __dl_u32(he_2mu_cnt) + 227 __dl_u32(he_3mu_cnt) + 228 __dl_u32(he_4mu_cnt); 229 total_ppdu_cnt = sub_total_cnt; 230 231 seq_printf(file, "\nTotal HE MU-MIMO DL PPDU count: %lld", 232 sub_total_cnt); 233 234 sub_total_cnt = __dl_u32(he_2ru_cnt) + 235 __dl_u32(he_3ru_cnt) + 236 __dl_u32(he_4ru_cnt) + 237 __dl_u32(he_5to8ru_cnt) + 238 __dl_u32(he_9to16ru_cnt) + 239 __dl_u32(he_gtr16ru_cnt); 240 total_ppdu_cnt += sub_total_cnt; 241 242 seq_printf(file, "\nTotal HE OFDMA DL PPDU count: %lld", 243 sub_total_cnt); 244 245 total_ppdu_cnt += __dl_u32(he_su_cnt) + 246 __dl_u32(he_ext_su_cnt); 247 248 seq_printf(file, "\nAll HE DL PPDU count: %lld", total_ppdu_cnt); 249 #undef __dl_u32 250 251 /* HE Uplink */ 252 seq_puts(file, "\n\nUplink"); 253 seq_puts(file, "\nTrigger-based Uplink MU-MIMO\nData Type: "); 254 255 for (i = 0; i < 3; i++) 256 seq_printf(file, "%8s | ", ul_he_type[i]); 257 258 #define __ul_u32(s) le32_to_cpu(mu_stats.ul.s) 259 seq_puts(file, "\nTotal Count:"); 260 seq_printf(file, "%8u | %8u | %8u | ", 261 __ul_u32(hetrig_2mu_cnt), 262 __ul_u32(hetrig_3mu_cnt), 263 __ul_u32(hetrig_4mu_cnt)); 264 265 seq_puts(file, "\nTrigger-based Uplink OFDMA\nData Type: "); 266 267 for (i = 3; i < 10; i++) 268 seq_printf(file, "%8s | ", ul_he_type[i]); 269 270 seq_puts(file, "\nTotal Count:"); 271 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | %9u | %7u | ", 272 __ul_u32(hetrig_su_cnt), 273 __ul_u32(hetrig_2ru_cnt), 274 __ul_u32(hetrig_3ru_cnt), 275 __ul_u32(hetrig_4ru_cnt), 276 __ul_u32(hetrig_5to8ru_cnt), 277 __ul_u32(hetrig_9to16ru_cnt), 278 __ul_u32(hetrig_gtr16ru_cnt)); 279 280 sub_total_cnt = __ul_u32(hetrig_2mu_cnt) + 281 __ul_u32(hetrig_3mu_cnt) + 282 __ul_u32(hetrig_4mu_cnt); 283 total_ppdu_cnt = sub_total_cnt; 284 285 seq_printf(file, "\nTotal HE MU-MIMO UL TB PPDU count: %lld", 286 sub_total_cnt); 287 288 sub_total_cnt = __ul_u32(hetrig_2ru_cnt) + 289 __ul_u32(hetrig_3ru_cnt) + 290 __ul_u32(hetrig_4ru_cnt) + 291 __ul_u32(hetrig_5to8ru_cnt) + 292 __ul_u32(hetrig_9to16ru_cnt) + 293 __ul_u32(hetrig_gtr16ru_cnt); 294 total_ppdu_cnt += sub_total_cnt; 295 296 seq_printf(file, "\nTotal HE OFDMA UL TB PPDU count: %lld", 297 sub_total_cnt); 298 299 total_ppdu_cnt += __ul_u32(hetrig_su_cnt); 300 301 seq_printf(file, "\nAll HE UL TB PPDU count: %lld\n", total_ppdu_cnt); 302 #undef __ul_u32 303 304 exit: 305 mutex_unlock(&dev->mt76.mutex); 306 307 return ret; 308 } 309 DEFINE_SHOW_ATTRIBUTE(mt7915_muru_stats); 310 311 static int 312 mt7915_rdd_monitor(struct seq_file *s, void *data) 313 { 314 struct mt7915_dev *dev = dev_get_drvdata(s->private); 315 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; 316 const char *bw; 317 int ret = 0; 318 319 mutex_lock(&dev->mt76.mutex); 320 321 if (!cfg80211_chandef_valid(chandef)) { 322 ret = -EINVAL; 323 goto out; 324 } 325 326 if (!dev->rdd2_phy) { 327 seq_puts(s, "not running\n"); 328 goto out; 329 } 330 331 switch (chandef->width) { 332 case NL80211_CHAN_WIDTH_40: 333 bw = "40"; 334 break; 335 case NL80211_CHAN_WIDTH_80: 336 bw = "80"; 337 break; 338 case NL80211_CHAN_WIDTH_160: 339 bw = "160"; 340 break; 341 case NL80211_CHAN_WIDTH_80P80: 342 bw = "80P80"; 343 break; 344 default: 345 bw = "20"; 346 break; 347 } 348 349 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", 350 chandef->chan->hw_value, chandef->chan->center_freq, 351 bw, chandef->center_freq1); 352 out: 353 mutex_unlock(&dev->mt76.mutex); 354 355 return ret; 356 } 357 358 static int 359 mt7915_fw_debug_wm_set(void *data, u64 val) 360 { 361 struct mt7915_dev *dev = data; 362 enum { 363 DEBUG_TXCMD = 62, 364 DEBUG_CMD_RPT_TX, 365 DEBUG_CMD_RPT_TRIG, 366 DEBUG_SPL, 367 DEBUG_RPT_RX, 368 } debug; 369 bool tx, rx, en; 370 int ret; 371 372 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; 373 374 if (dev->fw_debug_bin) 375 val = 16; 376 else 377 val = dev->fw_debug_wm; 378 379 tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1)); 380 rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2)); 381 en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0)); 382 383 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); 384 if (ret) 385 return ret; 386 387 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RX; debug++) { 388 if (debug == DEBUG_RPT_RX) 389 val = en && rx; 390 else 391 val = en && tx; 392 393 ret = mt7915_mcu_fw_dbg_ctrl(dev, debug, val); 394 if (ret) 395 return ret; 396 } 397 398 /* WM CPU info record control */ 399 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0)); 400 mt76_wr(dev, MT_DIC_CMD_REG_CMD, BIT(2) | BIT(13) | !dev->fw_debug_wm); 401 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5)); 402 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5)); 403 404 return 0; 405 } 406 407 static int 408 mt7915_fw_debug_wm_get(void *data, u64 *val) 409 { 410 struct mt7915_dev *dev = data; 411 412 *val = dev->fw_debug_wm; 413 414 return 0; 415 } 416 417 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7915_fw_debug_wm_get, 418 mt7915_fw_debug_wm_set, "%lld\n"); 419 420 static int 421 mt7915_fw_debug_wa_set(void *data, u64 val) 422 { 423 struct mt7915_dev *dev = data; 424 int ret; 425 426 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; 427 428 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa); 429 if (ret) 430 return ret; 431 432 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX, 433 !!dev->fw_debug_wa, 0); 434 } 435 436 static int 437 mt7915_fw_debug_wa_get(void *data, u64 *val) 438 { 439 struct mt7915_dev *dev = data; 440 441 *val = dev->fw_debug_wa; 442 443 return 0; 444 } 445 446 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7915_fw_debug_wa_get, 447 mt7915_fw_debug_wa_set, "%lld\n"); 448 449 static struct dentry * 450 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, 451 struct rchan_buf *buf, int *is_global) 452 { 453 struct dentry *f; 454 455 f = debugfs_create_file("fwlog_data", mode, parent, buf, 456 &relay_file_operations); 457 if (IS_ERR(f)) 458 return NULL; 459 460 *is_global = 1; 461 462 return f; 463 } 464 465 static int 466 remove_buf_file_cb(struct dentry *f) 467 { 468 debugfs_remove(f); 469 470 return 0; 471 } 472 473 static int 474 mt7915_fw_debug_bin_set(void *data, u64 val) 475 { 476 static struct rchan_callbacks relay_cb = { 477 .create_buf_file = create_buf_file_cb, 478 .remove_buf_file = remove_buf_file_cb, 479 }; 480 struct mt7915_dev *dev = data; 481 482 if (!dev->relay_fwlog) 483 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, 484 1500, 512, &relay_cb, NULL); 485 if (!dev->relay_fwlog) 486 return -ENOMEM; 487 488 dev->fw_debug_bin = val; 489 490 relay_reset(dev->relay_fwlog); 491 492 return mt7915_fw_debug_wm_set(dev, dev->fw_debug_wm); 493 } 494 495 static int 496 mt7915_fw_debug_bin_get(void *data, u64 *val) 497 { 498 struct mt7915_dev *dev = data; 499 500 *val = dev->fw_debug_bin; 501 502 return 0; 503 } 504 505 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7915_fw_debug_bin_get, 506 mt7915_fw_debug_bin_set, "%lld\n"); 507 508 static int 509 mt7915_fw_util_wm_show(struct seq_file *file, void *data) 510 { 511 struct mt7915_dev *dev = file->private; 512 513 if (dev->fw_debug_wm) { 514 seq_printf(file, "Busy: %u%% Peak busy: %u%%\n", 515 mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT), 516 mt76_rr(dev, MT_CPU_UTIL_PEAK_BUSY_PCT)); 517 seq_printf(file, "Idle count: %u Peak idle count: %u\n", 518 mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT), 519 mt76_rr(dev, MT_CPU_UTIL_PEAK_IDLE_CNT)); 520 } 521 522 return 0; 523 } 524 525 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wm); 526 527 static int 528 mt7915_fw_util_wa_show(struct seq_file *file, void *data) 529 { 530 struct mt7915_dev *dev = file->private; 531 532 if (dev->fw_debug_wa) 533 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), 534 MCU_WA_PARAM_CPU_UTIL, 0, 0); 535 536 return 0; 537 } 538 539 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wa); 540 541 static void 542 mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy, 543 struct seq_file *file) 544 { 545 struct mt7915_dev *dev = phy->dev; 546 bool ext_phy = phy != &dev->phy; 547 int bound[15], range[4], i, n; 548 549 /* Tx ampdu stat */ 550 for (i = 0; i < ARRAY_SIZE(range); i++) 551 range[i] = mt76_rr(dev, MT_MIB_ARNG(phy->band_idx, i)); 552 553 for (i = 0; i < ARRAY_SIZE(bound); i++) 554 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1; 555 556 seq_printf(file, "\nPhy %d, Phy band %d\n", ext_phy, phy->band_idx); 557 558 seq_printf(file, "Length: %8d | ", bound[0]); 559 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) 560 seq_printf(file, "%3d -%3d | ", 561 bound[i] + 1, bound[i + 1]); 562 563 seq_puts(file, "\nCount: "); 564 n = phy->band_idx ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 565 for (i = 0; i < ARRAY_SIZE(bound); i++) 566 seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i + n]); 567 seq_puts(file, "\n"); 568 569 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); 570 } 571 572 static void 573 mt7915_txbf_stat_read_phy(struct mt7915_phy *phy, struct seq_file *s) 574 { 575 static const char * const bw[] = { 576 "BW20", "BW40", "BW80", "BW160" 577 }; 578 struct mib_stats *mib = &phy->mib; 579 580 /* Tx Beamformer monitor */ 581 seq_puts(s, "\nTx Beamformer applied PPDU counts: "); 582 583 seq_printf(s, "iBF: %d, eBF: %d\n", 584 mib->tx_bf_ibf_ppdu_cnt, 585 mib->tx_bf_ebf_ppdu_cnt); 586 587 /* Tx Beamformer Rx feedback monitor */ 588 seq_puts(s, "Tx Beamformer Rx feedback statistics: "); 589 590 seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ", 591 mib->tx_bf_rx_fb_all_cnt, 592 mib->tx_bf_rx_fb_he_cnt, 593 mib->tx_bf_rx_fb_vht_cnt, 594 mib->tx_bf_rx_fb_ht_cnt); 595 596 seq_printf(s, "%s, NC: %d, NR: %d\n", 597 bw[mib->tx_bf_rx_fb_bw], 598 mib->tx_bf_rx_fb_nc_cnt, 599 mib->tx_bf_rx_fb_nr_cnt); 600 601 /* Tx Beamformee Rx NDPA & Tx feedback report */ 602 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", 603 mib->tx_bf_fb_cpl_cnt); 604 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", 605 mib->tx_bf_fb_trig_cnt); 606 607 /* Tx SU & MU counters */ 608 seq_printf(s, "Tx multi-user Beamforming counts: %d\n", 609 mib->tx_bf_cnt); 610 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); 611 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", 612 mib->tx_mu_acked_mpdu_cnt); 613 seq_printf(s, "Tx single-user successful MPDU counts: %d\n", 614 mib->tx_su_acked_mpdu_cnt); 615 616 seq_puts(s, "\n"); 617 } 618 619 static int 620 mt7915_tx_stats_show(struct seq_file *file, void *data) 621 { 622 struct mt7915_phy *phy = file->private; 623 struct mt7915_dev *dev = phy->dev; 624 struct mib_stats *mib = &phy->mib; 625 int i; 626 627 mutex_lock(&dev->mt76.mutex); 628 629 mt7915_ampdu_stat_read_phy(phy, file); 630 mt7915_mac_update_stats(phy); 631 mt7915_txbf_stat_read_phy(phy, file); 632 633 /* Tx amsdu info */ 634 seq_puts(file, "Tx MSDU statistics:\n"); 635 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 636 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", 637 i + 1, mib->tx_amsdu[i]); 638 if (mib->tx_amsdu_cnt) 639 seq_printf(file, "(%3d%%)\n", 640 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); 641 else 642 seq_puts(file, "\n"); 643 } 644 645 mutex_unlock(&dev->mt76.mutex); 646 647 return 0; 648 } 649 650 DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats); 651 652 static void 653 mt7915_hw_queue_read(struct seq_file *s, u32 size, 654 const struct hw_queue_map *map) 655 { 656 struct mt7915_phy *phy = s->private; 657 struct mt7915_dev *dev = phy->dev; 658 u32 i, val; 659 660 val = mt76_rr(dev, MT_FL_Q_EMPTY); 661 for (i = 0; i < size; i++) { 662 u32 ctrl, head, tail, queued; 663 664 if (val & BIT(map[i].index)) 665 continue; 666 667 ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24); 668 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); 669 670 head = mt76_get_field(dev, MT_FL_Q2_CTRL, 671 GENMASK(11, 0)); 672 tail = mt76_get_field(dev, MT_FL_Q2_CTRL, 673 GENMASK(27, 16)); 674 queued = mt76_get_field(dev, MT_FL_Q3_CTRL, 675 GENMASK(11, 0)); 676 677 seq_printf(s, "\t%s: ", map[i].name); 678 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", 679 queued, head, tail); 680 } 681 } 682 683 static void 684 mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) 685 { 686 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 687 struct mt7915_dev *dev = msta->vif->phy->dev; 688 struct seq_file *s = data; 689 u8 ac; 690 691 for (ac = 0; ac < 4; ac++) { 692 u32 qlen, ctrl, val; 693 u32 idx = msta->wcid.idx >> 5; 694 u8 offs = msta->wcid.idx & GENMASK(4, 0); 695 696 ctrl = BIT(31) | BIT(11) | (ac << 24); 697 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); 698 699 if (val & BIT(offs)) 700 continue; 701 702 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx); 703 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, 704 GENMASK(11, 0)); 705 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", 706 sta->addr, msta->wcid.idx, 707 msta->vif->mt76.wmm_idx, ac, qlen); 708 } 709 } 710 711 static int 712 mt7915_hw_queues_show(struct seq_file *file, void *data) 713 { 714 struct mt7915_phy *phy = file->private; 715 struct mt7915_dev *dev = phy->dev; 716 static const struct hw_queue_map ple_queue_map[] = { 717 { "CPU_Q0", 0, 1, MT_CTX0 }, 718 { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, 719 { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, 720 { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, 721 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, 722 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, 723 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, 724 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, 725 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, 726 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, 727 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, 728 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, 729 }; 730 static const struct hw_queue_map pse_queue_map[] = { 731 { "CPU Q0", 0, 1, MT_CTX0 }, 732 { "CPU Q1", 1, 1, MT_CTX0 + 1 }, 733 { "CPU Q2", 2, 1, MT_CTX0 + 2 }, 734 { "CPU Q3", 3, 1, MT_CTX0 + 3 }, 735 { "HIF_Q0", 8, 0, MT_HIF0 }, 736 { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, 737 { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, 738 { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, 739 { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, 740 { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, 741 { "LMAC_Q", 16, 2, 0 }, 742 { "MDP_TXQ", 17, 2, 1 }, 743 { "MDP_RXQ", 18, 2, 2 }, 744 { "SEC_TXQ", 19, 2, 3 }, 745 { "SEC_RXQ", 20, 2, 4 }, 746 }; 747 u32 val, head, tail; 748 749 /* ple queue */ 750 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); 751 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); 752 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); 753 seq_puts(file, "PLE page info:\n"); 754 seq_printf(file, 755 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", 756 val, head, tail); 757 758 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); 759 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); 760 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); 761 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", 762 val, head, tail); 763 764 seq_puts(file, "PLE non-empty queue info:\n"); 765 mt7915_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), 766 &ple_queue_map[0]); 767 768 /* iterate per-sta ple queue */ 769 ieee80211_iterate_stations_atomic(phy->mt76->hw, 770 mt7915_sta_hw_queue_read, file); 771 /* pse queue */ 772 seq_puts(file, "PSE non-empty queue info:\n"); 773 mt7915_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), 774 &pse_queue_map[0]); 775 776 return 0; 777 } 778 779 DEFINE_SHOW_ATTRIBUTE(mt7915_hw_queues); 780 781 static int 782 mt7915_xmit_queues_show(struct seq_file *file, void *data) 783 { 784 struct mt7915_phy *phy = file->private; 785 struct mt7915_dev *dev = phy->dev; 786 struct { 787 struct mt76_queue *q; 788 char *queue; 789 } queue_map[] = { 790 { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" }, 791 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, 792 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, 793 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, 794 }; 795 int i; 796 797 seq_puts(file, " queue | hw-queued | head | tail |\n"); 798 for (i = 0; i < ARRAY_SIZE(queue_map); i++) { 799 struct mt76_queue *q = queue_map[i].q; 800 801 if (!q) 802 continue; 803 804 seq_printf(file, " %s | %9d | %9d | %9d |\n", 805 queue_map[i].queue, q->queued, q->head, 806 q->tail); 807 } 808 809 return 0; 810 } 811 812 DEFINE_SHOW_ATTRIBUTE(mt7915_xmit_queues); 813 814 static int 815 mt7915_rate_txpower_show(struct seq_file *file, void *data) 816 { 817 static const char * const sku_group_name[] = { 818 "CCK", "OFDM", "HT20", "HT40", 819 "VHT20", "VHT40", "VHT80", "VHT160", 820 "RU26", "RU52", "RU106", "RU242/SU20", 821 "RU484/SU40", "RU996/SU80", "RU2x996/SU160" 822 }; 823 struct mt7915_phy *phy = file->private; 824 s8 txpower[MT7915_SKU_RATE_NUM], *buf; 825 int i; 826 827 seq_printf(file, "\nBand %d\n", phy != &phy->dev->phy); 828 mt7915_mcu_get_txpower_sku(phy, txpower, sizeof(txpower)); 829 for (i = 0, buf = txpower; i < ARRAY_SIZE(mt7915_sku_group_len); i++) { 830 u8 mcs_num = mt7915_sku_group_len[i]; 831 832 if (i >= SKU_VHT_BW20 && i <= SKU_VHT_BW160) 833 mcs_num = 10; 834 835 mt76_seq_puts_array(file, sku_group_name[i], buf, mcs_num); 836 buf += mt7915_sku_group_len[i]; 837 } 838 839 return 0; 840 } 841 842 DEFINE_SHOW_ATTRIBUTE(mt7915_rate_txpower); 843 844 static int 845 mt7915_twt_stats(struct seq_file *s, void *data) 846 { 847 struct mt7915_dev *dev = dev_get_drvdata(s->private); 848 struct mt7915_twt_flow *iter; 849 850 rcu_read_lock(); 851 852 seq_puts(s, " wcid | id | flags | exp | mantissa"); 853 seq_puts(s, " | duration | tsf |\n"); 854 list_for_each_entry_rcu(iter, &dev->twt_list, list) 855 seq_printf(s, 856 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", 857 iter->wcid, iter->id, 858 iter->sched ? 's' : 'u', 859 iter->protection ? 'p' : '-', 860 iter->trigger ? 't' : '-', 861 iter->flowtype ? '-' : 'a', 862 iter->exp, iter->mantissa, 863 iter->duration, iter->tsf); 864 865 rcu_read_unlock(); 866 867 return 0; 868 } 869 870 int mt7915_init_debugfs(struct mt7915_phy *phy) 871 { 872 struct mt7915_dev *dev = phy->dev; 873 bool ext_phy = phy != &dev->phy; 874 struct dentry *dir; 875 876 dir = mt76_register_debugfs_fops(phy->mt76, NULL); 877 if (!dir) 878 return -ENOMEM; 879 debugfs_create_file("muru_debug", 0600, dir, dev, &fops_muru_debug); 880 debugfs_create_file("muru_stats", 0400, dir, phy, 881 &mt7915_muru_stats_fops); 882 debugfs_create_file("hw-queues", 0400, dir, phy, 883 &mt7915_hw_queues_fops); 884 debugfs_create_file("xmit-queues", 0400, dir, phy, 885 &mt7915_xmit_queues_fops); 886 debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops); 887 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); 888 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); 889 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); 890 debugfs_create_file("fw_util_wm", 0400, dir, dev, 891 &mt7915_fw_util_wm_fops); 892 debugfs_create_file("fw_util_wa", 0400, dir, dev, 893 &mt7915_fw_util_wa_fops); 894 debugfs_create_file("implicit_txbf", 0600, dir, dev, 895 &fops_implicit_txbf); 896 debugfs_create_file("txpower_sku", 0400, dir, phy, 897 &mt7915_rate_txpower_fops); 898 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, 899 mt7915_twt_stats); 900 debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger); 901 if (!dev->dbdc_support || phy->band_idx) { 902 debugfs_create_u32("dfs_hw_pattern", 0400, dir, 903 &dev->hw_pattern); 904 debugfs_create_file("radar_trigger", 0200, dir, dev, 905 &fops_radar_trigger); 906 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, 907 mt7915_rdd_monitor); 908 } 909 910 if (!ext_phy) 911 dev->debugfs_dir = dir; 912 913 return 0; 914 } 915 916 static void 917 mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen, 918 const void *data, int len) 919 { 920 static DEFINE_SPINLOCK(lock); 921 unsigned long flags; 922 void *dest; 923 924 spin_lock_irqsave(&lock, flags); 925 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); 926 if (dest) { 927 *(u32 *)dest = hdrlen + len; 928 dest += 4; 929 930 if (hdrlen) { 931 memcpy(dest, hdr, hdrlen); 932 dest += hdrlen; 933 } 934 935 memcpy(dest, data, len); 936 relay_flush(dev->relay_fwlog); 937 } 938 spin_unlock_irqrestore(&lock, flags); 939 } 940 941 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len) 942 { 943 struct { 944 __le32 magic; 945 __le32 timestamp; 946 __le16 msg_type; 947 __le16 len; 948 } hdr = { 949 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), 950 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), 951 }; 952 953 if (!dev->relay_fwlog) 954 return; 955 956 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); 957 hdr.len = *(__le16 *)data; 958 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); 959 } 960 961 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len) 962 { 963 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) 964 return false; 965 966 if (dev->relay_fwlog) 967 mt7915_debugfs_write_fwlog(dev, NULL, 0, data, len); 968 969 return true; 970 } 971 972 #ifdef CONFIG_MAC80211_DEBUGFS 973 /** per-station debugfs **/ 974 975 static ssize_t mt7915_sta_fixed_rate_set(struct file *file, 976 const char __user *user_buf, 977 size_t count, loff_t *ppos) 978 { 979 struct ieee80211_sta *sta = file->private_data; 980 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 981 struct mt7915_dev *dev = msta->vif->phy->dev; 982 struct ieee80211_vif *vif; 983 struct sta_phy phy = {}; 984 char buf[100]; 985 int ret; 986 u32 field; 987 u8 i, gi, he_ltf; 988 989 if (count >= sizeof(buf)) 990 return -EINVAL; 991 992 if (copy_from_user(buf, user_buf, count)) 993 return -EFAULT; 994 995 if (count && buf[count - 1] == '\n') 996 buf[count - 1] = '\0'; 997 else 998 buf[count] = '\0'; 999 1000 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 1001 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3 1002 * nss - vht: 1~4, he: 1~4, others: ignore 1003 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2 1004 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 1005 * ldpc - off: 0, on: 1 1006 * stbc - off: 0, on: 1 1007 * he_ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 1008 */ 1009 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hhu %hhu %hhu %hhu", 1010 &phy.type, &phy.bw, &phy.nss, &phy.mcs, &gi, 1011 &phy.ldpc, &phy.stbc, &he_ltf) != 8) { 1012 dev_warn(dev->mt76.dev, 1013 "format: Mode BW NSS MCS (HE)GI LDPC STBC HE_LTF\n"); 1014 field = RATE_PARAM_AUTO; 1015 goto out; 1016 } 1017 1018 phy.ldpc = (phy.bw || phy.ldpc) * GENMASK(2, 0); 1019 for (i = 0; i <= phy.bw; i++) { 1020 phy.sgi |= gi << (i << sta->he_cap.has_he); 1021 phy.he_ltf |= he_ltf << (i << sta->he_cap.has_he); 1022 } 1023 field = RATE_PARAM_FIXED; 1024 1025 out: 1026 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1027 ret = mt7915_mcu_set_fixed_rate_ctrl(dev, vif, sta, &phy, field); 1028 if (ret) 1029 return -EFAULT; 1030 1031 return count; 1032 } 1033 1034 static const struct file_operations fops_fixed_rate = { 1035 .write = mt7915_sta_fixed_rate_set, 1036 .open = simple_open, 1037 .owner = THIS_MODULE, 1038 .llseek = default_llseek, 1039 }; 1040 1041 static int 1042 mt7915_queues_show(struct seq_file *s, void *data) 1043 { 1044 struct ieee80211_sta *sta = s->private; 1045 1046 mt7915_sta_hw_queue_read(s, sta); 1047 1048 return 0; 1049 } 1050 1051 DEFINE_SHOW_ATTRIBUTE(mt7915_queues); 1052 1053 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1054 struct ieee80211_sta *sta, struct dentry *dir) 1055 { 1056 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate); 1057 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7915_queues_fops); 1058 } 1059 1060 #endif 1061