1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/delay.h> 18 #include "mt76x2.h" 19 #include "eeprom.h" 20 #include "mcu.h" 21 22 static void 23 mt76x2_mac_pbf_init(struct mt76x02_dev *dev) 24 { 25 u32 val; 26 27 val = MT_PBF_SYS_CTRL_MCU_RESET | 28 MT_PBF_SYS_CTRL_DMA_RESET | 29 MT_PBF_SYS_CTRL_MAC_RESET | 30 MT_PBF_SYS_CTRL_PBF_RESET | 31 MT_PBF_SYS_CTRL_ASY_RESET; 32 33 mt76_set(dev, MT_PBF_SYS_CTRL, val); 34 mt76_clear(dev, MT_PBF_SYS_CTRL, val); 35 36 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); 37 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); 38 } 39 40 static void 41 mt76x2_fixup_xtal(struct mt76x02_dev *dev) 42 { 43 u16 eep_val; 44 s8 offset = 0; 45 46 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); 47 48 offset = eep_val & 0x7f; 49 if ((eep_val & 0xff) == 0xff) 50 offset = 0; 51 else if (eep_val & 0x80) 52 offset = 0 - offset; 53 54 eep_val >>= 8; 55 if (eep_val == 0x00 || eep_val == 0xff) { 56 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); 57 eep_val &= 0xff; 58 59 if (eep_val == 0x00 || eep_val == 0xff) 60 eep_val = 0x14; 61 } 62 63 eep_val &= 0x7f; 64 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset); 65 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); 66 67 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); 68 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 69 case 0: 70 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 71 break; 72 case 1: 73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); 74 break; 75 default: 76 break; 77 } 78 } 79 80 static int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard) 81 { 82 const u8 *macaddr = dev->mt76.macaddr; 83 u32 val; 84 int i, k; 85 86 if (!mt76x02_wait_for_mac(&dev->mt76)) 87 return -ETIMEDOUT; 88 89 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); 90 91 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | 92 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 93 MT_WPDMA_GLO_CFG_RX_DMA_EN | 94 MT_WPDMA_GLO_CFG_RX_DMA_BUSY | 95 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE); 96 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); 97 98 mt76_wr(dev, MT_WPDMA_GLO_CFG, val); 99 100 mt76x2_mac_pbf_init(dev); 101 mt76_write_mac_initvals(dev); 102 mt76x2_fixup_xtal(dev); 103 104 mt76_clear(dev, MT_MAC_SYS_CTRL, 105 MT_MAC_SYS_CTRL_RESET_CSR | 106 MT_MAC_SYS_CTRL_RESET_BBP); 107 108 if (is_mt7612(dev)) 109 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); 110 111 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); 112 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); 113 114 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); 115 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); 116 usleep_range(5000, 10000); 117 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); 118 119 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); 120 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 121 122 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr)); 123 mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4)); 124 125 mt76x02_init_beacon_config(dev); 126 if (!hard) 127 return 0; 128 129 for (i = 0; i < 256 / 32; i++) 130 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); 131 132 for (i = 0; i < 256; i++) { 133 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 134 mt76_wr(dev, MT_WCID_TX_RATE(i), 0); 135 mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0); 136 } 137 138 for (i = 0; i < MT_MAX_VIFS; i++) 139 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL); 140 141 for (i = 0; i < 16; i++) 142 for (k = 0; k < 4; k++) 143 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 144 145 for (i = 0; i < 16; i++) 146 mt76_rr(dev, MT_TX_STAT_FIFO); 147 148 mt76_wr(dev, MT_CH_TIME_CFG, 149 MT_CH_TIME_CFG_TIMER_EN | 150 MT_CH_TIME_CFG_TX_AS_BUSY | 151 MT_CH_TIME_CFG_RX_AS_BUSY | 152 MT_CH_TIME_CFG_NAV_AS_BUSY | 153 MT_CH_TIME_CFG_EIFS_AS_BUSY | 154 MT_CH_CCA_RC_EN | 155 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1)); 156 157 mt76x02_set_tx_ackto(dev); 158 159 return 0; 160 } 161 162 int mt76x2_mac_start(struct mt76x02_dev *dev) 163 { 164 int i; 165 166 for (i = 0; i < 16; i++) 167 mt76_rr(dev, MT_TX_AGG_CNT(i)); 168 169 for (i = 0; i < 16; i++) 170 mt76_rr(dev, MT_TX_STAT_FIFO); 171 172 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats)); 173 mt76x02_mac_start(dev); 174 175 return 0; 176 } 177 178 void mt76x2_mac_resume(struct mt76x02_dev *dev) 179 { 180 mt76_wr(dev, MT_MAC_SYS_CTRL, 181 MT_MAC_SYS_CTRL_ENABLE_TX | 182 MT_MAC_SYS_CTRL_ENABLE_RX); 183 } 184 185 static void 186 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev) 187 { 188 mt76_set(dev, 0x10130, BIT(0) | BIT(16)); 189 udelay(1); 190 191 mt76_clear(dev, 0x1001c, 0xff); 192 mt76_set(dev, 0x1001c, 0x30); 193 194 mt76_wr(dev, 0x10014, 0x484f); 195 udelay(1); 196 197 mt76_set(dev, 0x10130, BIT(17)); 198 udelay(125); 199 200 mt76_clear(dev, 0x10130, BIT(16)); 201 udelay(50); 202 203 mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); 204 } 205 206 static void 207 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit) 208 { 209 int shift = unit ? 8 : 0; 210 211 /* Enable RF BG */ 212 mt76_set(dev, 0x10130, BIT(0) << shift); 213 udelay(10); 214 215 /* Enable RFDIG LDO/AFE/ABB/ADDA */ 216 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift); 217 udelay(10); 218 219 /* Switch RFDIG power to internal LDO */ 220 mt76_clear(dev, 0x10130, BIT(2) << shift); 221 udelay(10); 222 223 mt76x2_power_on_rf_patch(dev); 224 225 mt76_set(dev, 0x530, 0xf); 226 } 227 228 static void 229 mt76x2_power_on(struct mt76x02_dev *dev) 230 { 231 u32 val; 232 233 /* Turn on WL MTCMOS */ 234 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP); 235 236 val = MT_WLAN_MTC_CTRL_STATE_UP | 237 MT_WLAN_MTC_CTRL_PWR_ACK | 238 MT_WLAN_MTC_CTRL_PWR_ACK_S; 239 240 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000); 241 242 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16); 243 udelay(10); 244 245 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 246 udelay(10); 247 248 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 249 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff); 250 251 /* Turn on AD/DA power down */ 252 mt76_clear(dev, 0x11204, BIT(3)); 253 254 /* WLAN function enable */ 255 mt76_set(dev, 0x10080, BIT(0)); 256 257 /* Release BBP software reset */ 258 mt76_clear(dev, 0x10064, BIT(18)); 259 260 mt76x2_power_on_rf(dev, 0); 261 mt76x2_power_on_rf(dev, 1); 262 } 263 264 static int mt76x2_init_hardware(struct mt76x02_dev *dev) 265 { 266 int ret; 267 268 mt76x02_dma_disable(dev); 269 mt76x2_reset_wlan(dev, true); 270 mt76x2_power_on(dev); 271 272 ret = mt76x2_eeprom_init(dev); 273 if (ret) 274 return ret; 275 276 ret = mt76x2_mac_reset(dev, true); 277 if (ret) 278 return ret; 279 280 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 281 282 ret = mt76x02_dma_init(dev); 283 if (ret) 284 return ret; 285 286 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); 287 ret = mt76x2_mac_start(dev); 288 if (ret) 289 return ret; 290 291 ret = mt76x2_mcu_init(dev); 292 if (ret) 293 return ret; 294 295 mt76x2_mac_stop(dev, false); 296 297 return 0; 298 } 299 300 void mt76x2_stop_hardware(struct mt76x02_dev *dev) 301 { 302 cancel_delayed_work_sync(&dev->cal_work); 303 cancel_delayed_work_sync(&dev->mac_work); 304 cancel_delayed_work_sync(&dev->wdt_work); 305 mt76x02_mcu_set_radio_state(dev, false); 306 mt76x2_mac_stop(dev, false); 307 } 308 309 void mt76x2_cleanup(struct mt76x02_dev *dev) 310 { 311 tasklet_disable(&dev->dfs_pd.dfs_tasklet); 312 tasklet_disable(&dev->pre_tbtt_tasklet); 313 mt76x2_stop_hardware(dev); 314 mt76x02_dma_cleanup(dev); 315 mt76x02_mcu_cleanup(dev); 316 } 317 318 struct mt76x02_dev *mt76x2_alloc_device(struct device *pdev) 319 { 320 static const struct mt76_driver_ops drv_ops = { 321 .txwi_size = sizeof(struct mt76x02_txwi), 322 .update_survey = mt76x02_update_channel, 323 .tx_prepare_skb = mt76x02_tx_prepare_skb, 324 .tx_complete_skb = mt76x02_tx_complete_skb, 325 .rx_skb = mt76x02_queue_rx_skb, 326 .rx_poll_complete = mt76x02_rx_poll_complete, 327 .sta_ps = mt76x02_sta_ps, 328 .sta_add = mt76x02_sta_add, 329 .sta_remove = mt76x02_sta_remove, 330 }; 331 struct mt76x02_dev *dev; 332 struct mt76_dev *mdev; 333 334 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2_ops); 335 if (!mdev) 336 return NULL; 337 338 dev = container_of(mdev, struct mt76x02_dev, mt76); 339 mdev->dev = pdev; 340 mdev->drv = &drv_ops; 341 342 return dev; 343 } 344 345 int mt76x2_register_device(struct mt76x02_dev *dev) 346 { 347 int ret; 348 349 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate); 350 351 mt76x02_init_device(dev); 352 353 ret = mt76x2_init_hardware(dev); 354 if (ret) 355 return ret; 356 357 mt76x02_config_mac_addr_list(dev); 358 359 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 360 ARRAY_SIZE(mt76x02_rates)); 361 if (ret) 362 goto fail; 363 364 mt76x02_init_debugfs(dev); 365 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband); 366 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband); 367 368 return 0; 369 370 fail: 371 mt76x2_stop_hardware(dev); 372 return ret; 373 } 374 375 376