1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "mt76x02.h" 19 #include "mt76x02_trace.h" 20 21 enum mt76x02_cipher_type 22 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 23 { 24 memset(key_data, 0, 32); 25 if (!key) 26 return MT_CIPHER_NONE; 27 28 if (key->keylen > 32) 29 return MT_CIPHER_NONE; 30 31 memcpy(key_data, key->key, key->keylen); 32 33 switch (key->cipher) { 34 case WLAN_CIPHER_SUITE_WEP40: 35 return MT_CIPHER_WEP40; 36 case WLAN_CIPHER_SUITE_WEP104: 37 return MT_CIPHER_WEP104; 38 case WLAN_CIPHER_SUITE_TKIP: 39 return MT_CIPHER_TKIP; 40 case WLAN_CIPHER_SUITE_CCMP: 41 return MT_CIPHER_AES_CCMP; 42 default: 43 return MT_CIPHER_NONE; 44 } 45 } 46 EXPORT_SYMBOL_GPL(mt76x02_mac_get_key_info); 47 48 int mt76x02_mac_shared_key_setup(struct mt76_dev *dev, u8 vif_idx, u8 key_idx, 49 struct ieee80211_key_conf *key) 50 { 51 enum mt76x02_cipher_type cipher; 52 u8 key_data[32]; 53 u32 val; 54 55 cipher = mt76x02_mac_get_key_info(key, key_data); 56 if (cipher == MT_CIPHER_NONE && key) 57 return -EOPNOTSUPP; 58 59 val = __mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 60 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 61 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 62 __mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 63 64 __mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 65 sizeof(key_data)); 66 67 return 0; 68 } 69 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 70 71 int mt76x02_mac_wcid_set_key(struct mt76_dev *dev, u8 idx, 72 struct ieee80211_key_conf *key) 73 { 74 enum mt76x02_cipher_type cipher; 75 u8 key_data[32]; 76 u8 iv_data[8]; 77 78 cipher = mt76x02_mac_get_key_info(key, key_data); 79 if (cipher == MT_CIPHER_NONE && key) 80 return -EOPNOTSUPP; 81 82 __mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 83 __mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 84 85 memset(iv_data, 0, sizeof(iv_data)); 86 if (key) { 87 __mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 88 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 89 iv_data[3] = key->keyidx << 6; 90 if (cipher >= MT_CIPHER_TKIP) 91 iv_data[3] |= 0x20; 92 } 93 94 __mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 95 96 return 0; 97 } 98 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_key); 99 100 void mt76x02_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac) 101 { 102 struct mt76_wcid_addr addr = {}; 103 u32 attr; 104 105 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 106 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 107 108 __mt76_wr(dev, MT_WCID_ATTR(idx), attr); 109 110 __mt76_wr(dev, MT_WCID_TX_RATE(idx), 0); 111 __mt76_wr(dev, MT_WCID_TX_RATE(idx) + 4, 0); 112 113 if (idx >= 128) 114 return; 115 116 if (mac) 117 memcpy(addr.macaddr, mac, ETH_ALEN); 118 119 __mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 120 } 121 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 122 123 void mt76x02_mac_wcid_set_drop(struct mt76_dev *dev, u8 idx, bool drop) 124 { 125 u32 val = __mt76_rr(dev, MT_WCID_DROP(idx)); 126 u32 bit = MT_WCID_DROP_MASK(idx); 127 128 /* prevent unnecessary writes */ 129 if ((val & bit) != (bit * drop)) 130 __mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 131 } 132 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_drop); 133 134 void mt76x02_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq) 135 { 136 struct mt76_txq *mtxq; 137 138 if (!txq) 139 return; 140 141 mtxq = (struct mt76_txq *) txq->drv_priv; 142 if (txq->sta) { 143 struct mt76x02_sta *sta; 144 145 sta = (struct mt76x02_sta *) txq->sta->drv_priv; 146 mtxq->wcid = &sta->wcid; 147 } else { 148 struct mt76x02_vif *mvif; 149 150 mvif = (struct mt76x02_vif *) txq->vif->drv_priv; 151 mtxq->wcid = &mvif->group_wcid; 152 } 153 154 mt76_txq_init(dev, txq); 155 } 156 EXPORT_SYMBOL_GPL(mt76x02_txq_init); 157 158 static void 159 mt76x02_mac_fill_txwi(struct mt76x02_txwi *txwi, struct sk_buff *skb, 160 struct ieee80211_sta *sta, int len, u8 nss) 161 { 162 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 163 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 164 u16 txwi_flags = 0; 165 166 if (info->flags & IEEE80211_TX_CTL_LDPC) 167 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 168 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 169 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 170 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC) 171 txwi_flags |= MT_TXWI_FLAGS_MMPS; 172 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 173 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 174 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 175 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 176 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 177 txwi->pktid |= MT_TXWI_PKTID_PROBE; 178 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 179 u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 180 181 ba_size <<= sta->ht_cap.ampdu_factor; 182 ba_size = min_t(int, 63, ba_size - 1); 183 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 184 ba_size = 0; 185 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 186 187 txwi_flags |= MT_TXWI_FLAGS_AMPDU | 188 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, 189 sta->ht_cap.ampdu_density); 190 } 191 192 if (ieee80211_is_probe_resp(hdr->frame_control) || 193 ieee80211_is_beacon(hdr->frame_control)) 194 txwi_flags |= MT_TXWI_FLAGS_TS; 195 196 txwi->flags |= cpu_to_le16(txwi_flags); 197 txwi->len_ctl = cpu_to_le16(len); 198 } 199 200 static __le16 201 mt76x02_mac_tx_rate_val(struct mt76_dev *dev, 202 const struct ieee80211_tx_rate *rate, u8 *nss_val) 203 { 204 u16 rateval; 205 u8 phy, rate_idx; 206 u8 nss = 1; 207 u8 bw = 0; 208 209 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 210 rate_idx = rate->idx; 211 nss = 1 + (rate->idx >> 4); 212 phy = MT_PHY_TYPE_VHT; 213 if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 214 bw = 2; 215 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 216 bw = 1; 217 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 218 rate_idx = rate->idx; 219 nss = 1 + (rate->idx >> 3); 220 phy = MT_PHY_TYPE_HT; 221 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 222 phy = MT_PHY_TYPE_HT_GF; 223 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 224 bw = 1; 225 } else { 226 const struct ieee80211_rate *r; 227 int band = dev->chandef.chan->band; 228 u16 val; 229 230 r = &dev->hw->wiphy->bands[band]->bitrates[rate->idx]; 231 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 232 val = r->hw_value_short; 233 else 234 val = r->hw_value; 235 236 phy = val >> 8; 237 rate_idx = val & 0xff; 238 bw = 0; 239 } 240 241 rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 242 rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 243 rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 244 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 245 rateval |= MT_RXWI_RATE_SGI; 246 247 *nss_val = nss; 248 return cpu_to_le16(rateval); 249 } 250 251 void mt76x02_mac_wcid_set_rate(struct mt76_dev *dev, struct mt76_wcid *wcid, 252 const struct ieee80211_tx_rate *rate) 253 { 254 spin_lock_bh(&dev->lock); 255 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 256 wcid->tx_rate_set = true; 257 spin_unlock_bh(&dev->lock); 258 } 259 260 bool mt76x02_mac_load_tx_status(struct mt76_dev *dev, 261 struct mt76x02_tx_status *stat) 262 { 263 u32 stat1, stat2; 264 265 stat2 = __mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 266 stat1 = __mt76_rr(dev, MT_TX_STAT_FIFO); 267 268 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 269 if (!stat->valid) 270 return false; 271 272 stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 273 stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 274 stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 275 stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 276 stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 277 278 stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 279 stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 280 281 return true; 282 } 283 EXPORT_SYMBOL_GPL(mt76x02_mac_load_tx_status); 284 285 static int 286 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 287 enum nl80211_band band) 288 { 289 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 290 291 txrate->idx = 0; 292 txrate->flags = 0; 293 txrate->count = 1; 294 295 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 296 case MT_PHY_TYPE_OFDM: 297 if (band == NL80211_BAND_2GHZ) 298 idx += 4; 299 300 txrate->idx = idx; 301 return 0; 302 case MT_PHY_TYPE_CCK: 303 if (idx >= 8) 304 idx -= 8; 305 306 txrate->idx = idx; 307 return 0; 308 case MT_PHY_TYPE_HT_GF: 309 txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 310 /* fall through */ 311 case MT_PHY_TYPE_HT: 312 txrate->flags |= IEEE80211_TX_RC_MCS; 313 txrate->idx = idx; 314 break; 315 case MT_PHY_TYPE_VHT: 316 txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 317 txrate->idx = idx; 318 break; 319 default: 320 return -EINVAL; 321 } 322 323 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 324 case MT_PHY_BW_20: 325 break; 326 case MT_PHY_BW_40: 327 txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 328 break; 329 case MT_PHY_BW_80: 330 txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 331 break; 332 default: 333 return -EINVAL; 334 } 335 336 if (rate & MT_RXWI_RATE_SGI) 337 txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 338 339 return 0; 340 } 341 342 void mt76x02_mac_write_txwi(struct mt76_dev *dev, struct mt76x02_txwi *txwi, 343 struct sk_buff *skb, struct mt76_wcid *wcid, 344 struct ieee80211_sta *sta, int len) 345 { 346 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 347 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 348 struct ieee80211_key_conf *key = info->control.hw_key; 349 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 350 u8 nss; 351 s8 txpwr_adj, max_txpwr_adj; 352 u8 ccmp_pn[8], nstreams = dev->chainmask & 0xf; 353 354 memset(txwi, 0, sizeof(*txwi)); 355 356 if (wcid) 357 txwi->wcid = wcid->idx; 358 else 359 txwi->wcid = 0xff; 360 361 txwi->pktid = 1; 362 363 if (wcid && wcid->sw_iv && key) { 364 u64 pn = atomic64_inc_return(&key->tx_pn); 365 ccmp_pn[0] = pn; 366 ccmp_pn[1] = pn >> 8; 367 ccmp_pn[2] = 0; 368 ccmp_pn[3] = 0x20 | (key->keyidx << 6); 369 ccmp_pn[4] = pn >> 16; 370 ccmp_pn[5] = pn >> 24; 371 ccmp_pn[6] = pn >> 32; 372 ccmp_pn[7] = pn >> 40; 373 txwi->iv = *((__le32 *)&ccmp_pn[0]); 374 txwi->eiv = *((__le32 *)&ccmp_pn[1]); 375 } 376 377 spin_lock_bh(&dev->lock); 378 if (wcid && (rate->idx < 0 || !rate->count)) { 379 txwi->rate = wcid->tx_rate; 380 max_txpwr_adj = wcid->max_txpwr_adj; 381 nss = wcid->tx_rate_nss; 382 } else { 383 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 384 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 385 } 386 spin_unlock_bh(&dev->lock); 387 388 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->txpower_conf, 389 max_txpwr_adj); 390 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 391 392 if (nstreams > 1 && mt76_rev(dev) >= MT76XX_REV_E4) 393 txwi->txstream = 0x13; 394 else if (nstreams > 1 && mt76_rev(dev) >= MT76XX_REV_E3 && 395 !(txwi->rate & cpu_to_le16(rate_ht_mask))) 396 txwi->txstream = 0x93; 397 398 mt76x02_mac_fill_txwi(txwi, skb, sta, len, nss); 399 } 400 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 401 402 static void 403 mt76x02_mac_fill_tx_status(struct mt76_dev *dev, 404 struct ieee80211_tx_info *info, 405 struct mt76x02_tx_status *st, int n_frames) 406 { 407 struct ieee80211_tx_rate *rate = info->status.rates; 408 int cur_idx, last_rate; 409 int i; 410 411 if (!n_frames) 412 return; 413 414 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 415 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 416 dev->chandef.chan->band); 417 if (last_rate < IEEE80211_TX_MAX_RATES - 1) 418 rate[last_rate + 1].idx = -1; 419 420 cur_idx = rate[last_rate].idx + last_rate; 421 for (i = 0; i <= last_rate; i++) { 422 rate[i].flags = rate[last_rate].flags; 423 rate[i].idx = max_t(int, 0, cur_idx - i); 424 rate[i].count = 1; 425 } 426 rate[last_rate].count = st->retry + 1 - last_rate; 427 428 info->status.ampdu_len = n_frames; 429 info->status.ampdu_ack_len = st->success ? n_frames : 0; 430 431 if (st->pktid & MT_TXWI_PKTID_PROBE) 432 info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE; 433 434 if (st->aggr) 435 info->flags |= IEEE80211_TX_CTL_AMPDU | 436 IEEE80211_TX_STAT_AMPDU; 437 438 if (!st->ack_req) 439 info->flags |= IEEE80211_TX_CTL_NO_ACK; 440 else if (st->success) 441 info->flags |= IEEE80211_TX_STAT_ACK; 442 } 443 444 void mt76x02_send_tx_status(struct mt76_dev *dev, 445 struct mt76x02_tx_status *stat, u8 *update) 446 { 447 struct ieee80211_tx_info info = {}; 448 struct ieee80211_sta *sta = NULL; 449 struct mt76_wcid *wcid = NULL; 450 struct mt76x02_sta *msta = NULL; 451 452 rcu_read_lock(); 453 if (stat->wcid < ARRAY_SIZE(dev->wcid)) 454 wcid = rcu_dereference(dev->wcid[stat->wcid]); 455 456 if (wcid) { 457 void *priv; 458 459 priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 460 sta = container_of(priv, struct ieee80211_sta, 461 drv_priv); 462 } 463 464 if (msta && stat->aggr) { 465 u32 stat_val, stat_cache; 466 467 stat_val = stat->rate; 468 stat_val |= ((u32) stat->retry) << 16; 469 stat_cache = msta->status.rate; 470 stat_cache |= ((u32) msta->status.retry) << 16; 471 472 if (*update == 0 && stat_val == stat_cache && 473 stat->wcid == msta->status.wcid && msta->n_frames < 32) { 474 msta->n_frames++; 475 goto out; 476 } 477 478 mt76x02_mac_fill_tx_status(dev, &info, &msta->status, 479 msta->n_frames); 480 481 msta->status = *stat; 482 msta->n_frames = 1; 483 *update = 0; 484 } else { 485 mt76x02_mac_fill_tx_status(dev, &info, stat, 1); 486 *update = 1; 487 } 488 489 ieee80211_tx_status_noskb(dev->hw, sta, &info); 490 491 out: 492 rcu_read_unlock(); 493 } 494 EXPORT_SYMBOL_GPL(mt76x02_send_tx_status); 495 496 int 497 mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate) 498 { 499 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 500 501 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 502 case MT_PHY_TYPE_OFDM: 503 if (idx >= 8) 504 idx = 0; 505 506 if (status->band == NL80211_BAND_2GHZ) 507 idx += 4; 508 509 status->rate_idx = idx; 510 return 0; 511 case MT_PHY_TYPE_CCK: 512 if (idx >= 8) { 513 idx -= 8; 514 status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 515 } 516 517 if (idx >= 4) 518 idx = 0; 519 520 status->rate_idx = idx; 521 return 0; 522 case MT_PHY_TYPE_HT_GF: 523 status->enc_flags |= RX_ENC_FLAG_HT_GF; 524 /* fall through */ 525 case MT_PHY_TYPE_HT: 526 status->encoding = RX_ENC_HT; 527 status->rate_idx = idx; 528 break; 529 case MT_PHY_TYPE_VHT: 530 status->encoding = RX_ENC_VHT; 531 status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 532 status->nss = FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1; 533 break; 534 default: 535 return -EINVAL; 536 } 537 538 if (rate & MT_RXWI_RATE_LDPC) 539 status->enc_flags |= RX_ENC_FLAG_LDPC; 540 541 if (rate & MT_RXWI_RATE_SGI) 542 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 543 544 if (rate & MT_RXWI_RATE_STBC) 545 status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 546 547 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 548 case MT_PHY_BW_20: 549 break; 550 case MT_PHY_BW_40: 551 status->bw = RATE_INFO_BW_40; 552 break; 553 case MT_PHY_BW_80: 554 status->bw = RATE_INFO_BW_80; 555 break; 556 default: 557 break; 558 } 559 560 return 0; 561 } 562 EXPORT_SYMBOL_GPL(mt76x02_mac_process_rate); 563 564 void mt76x02_mac_setaddr(struct mt76_dev *dev, u8 *addr) 565 { 566 ether_addr_copy(dev->macaddr, addr); 567 568 if (!is_valid_ether_addr(dev->macaddr)) { 569 eth_random_addr(dev->macaddr); 570 dev_info(dev->dev, 571 "Invalid MAC address, using random address %pM\n", 572 dev->macaddr); 573 } 574 575 __mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr)); 576 __mt76_wr(dev, MT_MAC_ADDR_DW1, 577 get_unaligned_le16(dev->macaddr + 4) | 578 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 579 } 580 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 581 582 static int 583 mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 584 { 585 struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 586 587 rssi += cal->rssi_offset[chain]; 588 rssi -= cal->lna_gain; 589 590 return rssi; 591 } 592 593 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 594 void *rxi) 595 { 596 struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb; 597 struct mt76x02_rxwi *rxwi = rxi; 598 struct mt76x02_sta *sta; 599 u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 600 u32 ctl = le32_to_cpu(rxwi->ctl); 601 u16 rate = le16_to_cpu(rxwi->rate); 602 u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 603 bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 604 int i, pad_len = 0, nstreams = dev->mt76.chainmask & 0xf; 605 s8 signal; 606 u8 pn_len; 607 u8 wcid; 608 int len; 609 610 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 611 return -EINVAL; 612 613 if (rxinfo & MT_RXINFO_L2PAD) 614 pad_len += 2; 615 616 if (rxinfo & MT_RXINFO_DECRYPT) { 617 status->flag |= RX_FLAG_DECRYPTED; 618 status->flag |= RX_FLAG_MMIC_STRIPPED; 619 status->flag |= RX_FLAG_MIC_STRIPPED; 620 status->flag |= RX_FLAG_IV_STRIPPED; 621 } 622 623 wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 624 sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 625 status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 626 627 len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 628 pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 629 if (pn_len) { 630 int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 631 u8 *data = skb->data + offset; 632 633 status->iv[0] = data[7]; 634 status->iv[1] = data[6]; 635 status->iv[2] = data[5]; 636 status->iv[3] = data[4]; 637 status->iv[4] = data[1]; 638 status->iv[5] = data[0]; 639 640 /* 641 * Driver CCMP validation can't deal with fragments. 642 * Let mac80211 take care of it. 643 */ 644 if (rxinfo & MT_RXINFO_FRAG) { 645 status->flag &= ~RX_FLAG_IV_STRIPPED; 646 } else { 647 pad_len += pn_len << 2; 648 len -= pn_len << 2; 649 } 650 } 651 652 mt76x02_remove_hdr_pad(skb, pad_len); 653 654 if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 655 status->aggr = true; 656 657 if (WARN_ON_ONCE(len > skb->len)) 658 return -EINVAL; 659 660 pskb_trim(skb, len); 661 662 status->chains = BIT(0); 663 signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 664 for (i = 1; i < nstreams; i++) { 665 status->chains |= BIT(i); 666 status->chain_signal[i] = mt76x02_mac_get_rssi(dev, 667 rxwi->rssi[i], 668 i); 669 signal = max_t(s8, signal, status->chain_signal[i]); 670 } 671 status->signal = signal; 672 status->freq = dev->mt76.chandef.chan->center_freq; 673 status->band = dev->mt76.chandef.chan->band; 674 675 status->tid = FIELD_GET(MT_RXWI_TID, tid_sn); 676 status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 677 678 if (sta) { 679 ewma_signal_add(&sta->rssi, status->signal); 680 sta->inactive_count = 0; 681 } 682 683 return mt76x02_mac_process_rate(status, rate); 684 } 685 686 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 687 { 688 struct mt76x02_tx_status stat = {}; 689 unsigned long flags; 690 u8 update = 1; 691 bool ret; 692 693 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 694 return; 695 696 trace_mac_txstat_poll(dev); 697 698 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 699 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 700 ret = mt76x02_mac_load_tx_status(&dev->mt76, &stat); 701 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 702 703 if (!ret) 704 break; 705 706 trace_mac_txstat_fetch(dev, &stat); 707 708 if (!irq) { 709 mt76x02_send_tx_status(&dev->mt76, &stat, &update); 710 continue; 711 } 712 713 kfifo_put(&dev->txstatus_fifo, stat); 714 } 715 } 716 EXPORT_SYMBOL_GPL(mt76x02_mac_poll_tx_status); 717 718 static void 719 mt76x02_mac_queue_txdone(struct mt76x02_dev *dev, struct sk_buff *skb, 720 void *txwi_ptr) 721 { 722 struct mt76x02_tx_info *txi = mt76x02_skb_tx_info(skb); 723 struct mt76x02_txwi *txwi = txwi_ptr; 724 725 mt76x02_mac_poll_tx_status(dev, false); 726 727 txi->tries = 0; 728 txi->jiffies = jiffies; 729 txi->wcid = txwi->wcid; 730 txi->pktid = txwi->pktid; 731 trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid); 732 mt76x02_tx_complete(&dev->mt76, skb); 733 } 734 735 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 736 struct mt76_queue_entry *e, bool flush) 737 { 738 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 739 740 if (e->txwi) 741 mt76x02_mac_queue_txdone(dev, e->skb, &e->txwi->txwi); 742 else 743 dev_kfree_skb_any(e->skb); 744 } 745 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 746