1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "mt76x02.h" 19 #include "mt76x02_trace.h" 20 21 static enum mt76x02_cipher_type 22 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 23 { 24 memset(key_data, 0, 32); 25 if (!key) 26 return MT_CIPHER_NONE; 27 28 if (key->keylen > 32) 29 return MT_CIPHER_NONE; 30 31 memcpy(key_data, key->key, key->keylen); 32 33 switch (key->cipher) { 34 case WLAN_CIPHER_SUITE_WEP40: 35 return MT_CIPHER_WEP40; 36 case WLAN_CIPHER_SUITE_WEP104: 37 return MT_CIPHER_WEP104; 38 case WLAN_CIPHER_SUITE_TKIP: 39 return MT_CIPHER_TKIP; 40 case WLAN_CIPHER_SUITE_CCMP: 41 return MT_CIPHER_AES_CCMP; 42 default: 43 return MT_CIPHER_NONE; 44 } 45 } 46 47 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 48 u8 key_idx, struct ieee80211_key_conf *key) 49 { 50 enum mt76x02_cipher_type cipher; 51 u8 key_data[32]; 52 u32 val; 53 54 cipher = mt76x02_mac_get_key_info(key, key_data); 55 if (cipher == MT_CIPHER_NONE && key) 56 return -EOPNOTSUPP; 57 58 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 59 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 60 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 61 mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 62 63 mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 64 sizeof(key_data)); 65 66 return 0; 67 } 68 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 69 70 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 71 struct ieee80211_key_conf *key) 72 { 73 enum mt76x02_cipher_type cipher; 74 u8 key_data[32]; 75 u8 iv_data[8]; 76 77 cipher = mt76x02_mac_get_key_info(key, key_data); 78 if (cipher == MT_CIPHER_NONE && key) 79 return -EOPNOTSUPP; 80 81 mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 82 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 83 84 memset(iv_data, 0, sizeof(iv_data)); 85 if (key) { 86 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 87 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 88 iv_data[3] = key->keyidx << 6; 89 if (cipher >= MT_CIPHER_TKIP) 90 iv_data[3] |= 0x20; 91 } 92 93 mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 94 95 return 0; 96 } 97 98 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, 99 u8 vif_idx, u8 *mac) 100 { 101 struct mt76_wcid_addr addr = {}; 102 u32 attr; 103 104 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 105 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 106 107 mt76_wr(dev, MT_WCID_ATTR(idx), attr); 108 109 if (idx >= 128) 110 return; 111 112 if (mac) 113 memcpy(addr.macaddr, mac, ETH_ALEN); 114 115 mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 116 } 117 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 118 119 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop) 120 { 121 u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); 122 u32 bit = MT_WCID_DROP_MASK(idx); 123 124 /* prevent unnecessary writes */ 125 if ((val & bit) != (bit * drop)) 126 mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 127 } 128 129 static __le16 130 mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev, 131 const struct ieee80211_tx_rate *rate, u8 *nss_val) 132 { 133 u8 phy, rate_idx, nss, bw = 0; 134 u16 rateval; 135 136 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 137 rate_idx = rate->idx; 138 nss = 1 + (rate->idx >> 4); 139 phy = MT_PHY_TYPE_VHT; 140 if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 141 bw = 2; 142 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 143 bw = 1; 144 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 145 rate_idx = rate->idx; 146 nss = 1 + (rate->idx >> 3); 147 phy = MT_PHY_TYPE_HT; 148 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 149 phy = MT_PHY_TYPE_HT_GF; 150 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 151 bw = 1; 152 } else { 153 const struct ieee80211_rate *r; 154 int band = dev->mt76.chandef.chan->band; 155 u16 val; 156 157 r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx]; 158 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 159 val = r->hw_value_short; 160 else 161 val = r->hw_value; 162 163 phy = val >> 8; 164 rate_idx = val & 0xff; 165 nss = 1; 166 } 167 168 rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 169 rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 170 rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 171 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 172 rateval |= MT_RXWI_RATE_SGI; 173 174 *nss_val = nss; 175 return cpu_to_le16(rateval); 176 } 177 178 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 179 const struct ieee80211_tx_rate *rate) 180 { 181 spin_lock_bh(&dev->mt76.lock); 182 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 183 wcid->tx_rate_set = true; 184 spin_unlock_bh(&dev->mt76.lock); 185 } 186 187 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable) 188 { 189 if (enable) 190 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 191 else 192 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 193 } 194 195 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 196 struct mt76x02_tx_status *stat) 197 { 198 u32 stat1, stat2; 199 200 stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 201 stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); 202 203 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 204 if (!stat->valid) 205 return false; 206 207 stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 208 stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 209 stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 210 stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 211 stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 212 213 stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 214 stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 215 216 trace_mac_txstat_fetch(dev, stat); 217 218 return true; 219 } 220 221 static int 222 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 223 enum nl80211_band band) 224 { 225 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 226 227 txrate->idx = 0; 228 txrate->flags = 0; 229 txrate->count = 1; 230 231 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 232 case MT_PHY_TYPE_OFDM: 233 if (band == NL80211_BAND_2GHZ) 234 idx += 4; 235 236 txrate->idx = idx; 237 return 0; 238 case MT_PHY_TYPE_CCK: 239 if (idx >= 8) 240 idx -= 8; 241 242 txrate->idx = idx; 243 return 0; 244 case MT_PHY_TYPE_HT_GF: 245 txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 246 /* fall through */ 247 case MT_PHY_TYPE_HT: 248 txrate->flags |= IEEE80211_TX_RC_MCS; 249 txrate->idx = idx; 250 break; 251 case MT_PHY_TYPE_VHT: 252 txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 253 txrate->idx = idx; 254 break; 255 default: 256 return -EINVAL; 257 } 258 259 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 260 case MT_PHY_BW_20: 261 break; 262 case MT_PHY_BW_40: 263 txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 264 break; 265 case MT_PHY_BW_80: 266 txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 267 break; 268 default: 269 return -EINVAL; 270 } 271 272 if (rate & MT_RXWI_RATE_SGI) 273 txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 274 275 return 0; 276 } 277 278 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 279 struct sk_buff *skb, struct mt76_wcid *wcid, 280 struct ieee80211_sta *sta, int len) 281 { 282 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 283 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 284 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 285 struct ieee80211_key_conf *key = info->control.hw_key; 286 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 287 u16 txwi_flags = 0; 288 u8 nss; 289 s8 txpwr_adj, max_txpwr_adj; 290 u8 ccmp_pn[8], nstreams = dev->mt76.chainmask & 0xf; 291 292 memset(txwi, 0, sizeof(*txwi)); 293 294 if (wcid) 295 txwi->wcid = wcid->idx; 296 else 297 txwi->wcid = 0xff; 298 299 if (wcid && wcid->sw_iv && key) { 300 u64 pn = atomic64_inc_return(&key->tx_pn); 301 ccmp_pn[0] = pn; 302 ccmp_pn[1] = pn >> 8; 303 ccmp_pn[2] = 0; 304 ccmp_pn[3] = 0x20 | (key->keyidx << 6); 305 ccmp_pn[4] = pn >> 16; 306 ccmp_pn[5] = pn >> 24; 307 ccmp_pn[6] = pn >> 32; 308 ccmp_pn[7] = pn >> 40; 309 txwi->iv = *((__le32 *)&ccmp_pn[0]); 310 txwi->eiv = *((__le32 *)&ccmp_pn[1]); 311 } 312 313 spin_lock_bh(&dev->mt76.lock); 314 if (wcid && (rate->idx < 0 || !rate->count)) { 315 txwi->rate = wcid->tx_rate; 316 max_txpwr_adj = wcid->max_txpwr_adj; 317 nss = wcid->tx_rate_nss; 318 } else { 319 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 320 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 321 } 322 spin_unlock_bh(&dev->mt76.lock); 323 324 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->mt76.txpower_conf, 325 max_txpwr_adj); 326 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 327 328 if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4) 329 txwi->txstream = 0x13; 330 else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 && 331 !(txwi->rate & cpu_to_le16(rate_ht_mask))) 332 txwi->txstream = 0x93; 333 334 if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC)) 335 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 336 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 337 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 338 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC) 339 txwi_flags |= MT_TXWI_FLAGS_MMPS; 340 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 341 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 342 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 343 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 344 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 345 u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 346 347 ba_size <<= sta->ht_cap.ampdu_factor; 348 ba_size = min_t(int, 63, ba_size - 1); 349 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 350 ba_size = 0; 351 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 352 353 txwi_flags |= MT_TXWI_FLAGS_AMPDU | 354 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, 355 sta->ht_cap.ampdu_density); 356 } 357 358 if (ieee80211_is_probe_resp(hdr->frame_control) || 359 ieee80211_is_beacon(hdr->frame_control)) 360 txwi_flags |= MT_TXWI_FLAGS_TS; 361 362 txwi->flags |= cpu_to_le16(txwi_flags); 363 txwi->len_ctl = cpu_to_le16(len); 364 } 365 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 366 367 static void 368 mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, 369 struct ieee80211_tx_info *info, 370 struct mt76x02_tx_status *st, int n_frames) 371 { 372 struct ieee80211_tx_rate *rate = info->status.rates; 373 int cur_idx, last_rate; 374 int i; 375 376 if (!n_frames) 377 return; 378 379 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 380 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 381 dev->mt76.chandef.chan->band); 382 if (last_rate < IEEE80211_TX_MAX_RATES - 1) 383 rate[last_rate + 1].idx = -1; 384 385 cur_idx = rate[last_rate].idx + last_rate; 386 for (i = 0; i <= last_rate; i++) { 387 rate[i].flags = rate[last_rate].flags; 388 rate[i].idx = max_t(int, 0, cur_idx - i); 389 rate[i].count = 1; 390 } 391 rate[last_rate].count = st->retry + 1 - last_rate; 392 393 info->status.ampdu_len = n_frames; 394 info->status.ampdu_ack_len = st->success ? n_frames : 0; 395 396 if (st->aggr) 397 info->flags |= IEEE80211_TX_CTL_AMPDU | 398 IEEE80211_TX_STAT_AMPDU; 399 400 if (!st->ack_req) 401 info->flags |= IEEE80211_TX_CTL_NO_ACK; 402 else if (st->success) 403 info->flags |= IEEE80211_TX_STAT_ACK; 404 } 405 406 void mt76x02_send_tx_status(struct mt76x02_dev *dev, 407 struct mt76x02_tx_status *stat, u8 *update) 408 { 409 struct ieee80211_tx_info info = {}; 410 struct ieee80211_tx_status status = { 411 .info = &info 412 }; 413 struct mt76_wcid *wcid = NULL; 414 struct mt76x02_sta *msta = NULL; 415 struct mt76_dev *mdev = &dev->mt76; 416 struct sk_buff_head list; 417 418 if (stat->pktid == MT_PACKET_ID_NO_ACK) 419 return; 420 421 rcu_read_lock(); 422 mt76_tx_status_lock(mdev, &list); 423 424 if (stat->wcid < ARRAY_SIZE(dev->mt76.wcid)) 425 wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]); 426 427 if (wcid && wcid->sta) { 428 void *priv; 429 430 priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 431 status.sta = container_of(priv, struct ieee80211_sta, 432 drv_priv); 433 } 434 435 if (wcid) { 436 if (stat->pktid >= MT_PACKET_ID_FIRST) 437 status.skb = mt76_tx_status_skb_get(mdev, wcid, 438 stat->pktid, &list); 439 if (status.skb) 440 status.info = IEEE80211_SKB_CB(status.skb); 441 } 442 443 if (msta && stat->aggr && !status.skb) { 444 u32 stat_val, stat_cache; 445 446 stat_val = stat->rate; 447 stat_val |= ((u32) stat->retry) << 16; 448 stat_cache = msta->status.rate; 449 stat_cache |= ((u32) msta->status.retry) << 16; 450 451 if (*update == 0 && stat_val == stat_cache && 452 stat->wcid == msta->status.wcid && msta->n_frames < 32) { 453 msta->n_frames++; 454 goto out; 455 } 456 457 mt76x02_mac_fill_tx_status(dev, status.info, &msta->status, 458 msta->n_frames); 459 460 msta->status = *stat; 461 msta->n_frames = 1; 462 *update = 0; 463 } else { 464 mt76x02_mac_fill_tx_status(dev, status.info, stat, 1); 465 *update = 1; 466 } 467 468 if (status.skb) 469 mt76_tx_status_skb_done(mdev, status.skb, &list); 470 else 471 ieee80211_tx_status_ext(mt76_hw(dev), &status); 472 473 out: 474 mt76_tx_status_unlock(mdev, &list); 475 rcu_read_unlock(); 476 } 477 478 static int 479 mt76x02_mac_process_rate(struct mt76x02_dev *dev, 480 struct mt76_rx_status *status, 481 u16 rate) 482 { 483 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 484 485 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 486 case MT_PHY_TYPE_OFDM: 487 if (idx >= 8) 488 idx = 0; 489 490 if (status->band == NL80211_BAND_2GHZ) 491 idx += 4; 492 493 status->rate_idx = idx; 494 return 0; 495 case MT_PHY_TYPE_CCK: 496 if (idx >= 8) { 497 idx -= 8; 498 status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 499 } 500 501 if (idx >= 4) 502 idx = 0; 503 504 status->rate_idx = idx; 505 return 0; 506 case MT_PHY_TYPE_HT_GF: 507 status->enc_flags |= RX_ENC_FLAG_HT_GF; 508 /* fall through */ 509 case MT_PHY_TYPE_HT: 510 status->encoding = RX_ENC_HT; 511 status->rate_idx = idx; 512 break; 513 case MT_PHY_TYPE_VHT: { 514 u8 n_rxstream = dev->mt76.chainmask & 0xf; 515 516 status->encoding = RX_ENC_VHT; 517 status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 518 status->nss = min_t(u8, n_rxstream, 519 FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1); 520 break; 521 } 522 default: 523 return -EINVAL; 524 } 525 526 if (rate & MT_RXWI_RATE_LDPC) 527 status->enc_flags |= RX_ENC_FLAG_LDPC; 528 529 if (rate & MT_RXWI_RATE_SGI) 530 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 531 532 if (rate & MT_RXWI_RATE_STBC) 533 status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 534 535 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 536 case MT_PHY_BW_20: 537 break; 538 case MT_PHY_BW_40: 539 status->bw = RATE_INFO_BW_40; 540 break; 541 case MT_PHY_BW_80: 542 status->bw = RATE_INFO_BW_80; 543 break; 544 default: 545 break; 546 } 547 548 return 0; 549 } 550 551 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, u8 *addr) 552 { 553 ether_addr_copy(dev->mt76.macaddr, addr); 554 555 if (!is_valid_ether_addr(dev->mt76.macaddr)) { 556 eth_random_addr(dev->mt76.macaddr); 557 dev_info(dev->mt76.dev, 558 "Invalid MAC address, using random address %pM\n", 559 dev->mt76.macaddr); 560 } 561 562 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr)); 563 mt76_wr(dev, MT_MAC_ADDR_DW1, 564 get_unaligned_le16(dev->mt76.macaddr + 4) | 565 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 566 } 567 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 568 569 static int 570 mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 571 { 572 struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 573 574 rssi += cal->rssi_offset[chain]; 575 rssi -= cal->lna_gain; 576 577 return rssi; 578 } 579 580 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 581 void *rxi) 582 { 583 struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb; 584 struct mt76x02_rxwi *rxwi = rxi; 585 struct mt76x02_sta *sta; 586 u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 587 u32 ctl = le32_to_cpu(rxwi->ctl); 588 u16 rate = le16_to_cpu(rxwi->rate); 589 u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 590 bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 591 int i, pad_len = 0, nstreams = dev->mt76.chainmask & 0xf; 592 s8 signal; 593 u8 pn_len; 594 u8 wcid; 595 int len; 596 597 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 598 return -EINVAL; 599 600 if (rxinfo & MT_RXINFO_L2PAD) 601 pad_len += 2; 602 603 if (rxinfo & MT_RXINFO_DECRYPT) { 604 status->flag |= RX_FLAG_DECRYPTED; 605 status->flag |= RX_FLAG_MMIC_STRIPPED; 606 status->flag |= RX_FLAG_MIC_STRIPPED; 607 status->flag |= RX_FLAG_IV_STRIPPED; 608 } 609 610 wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 611 sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 612 status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 613 614 len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 615 pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 616 if (pn_len) { 617 int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 618 u8 *data = skb->data + offset; 619 620 status->iv[0] = data[7]; 621 status->iv[1] = data[6]; 622 status->iv[2] = data[5]; 623 status->iv[3] = data[4]; 624 status->iv[4] = data[1]; 625 status->iv[5] = data[0]; 626 627 /* 628 * Driver CCMP validation can't deal with fragments. 629 * Let mac80211 take care of it. 630 */ 631 if (rxinfo & MT_RXINFO_FRAG) { 632 status->flag &= ~RX_FLAG_IV_STRIPPED; 633 } else { 634 pad_len += pn_len << 2; 635 len -= pn_len << 2; 636 } 637 } 638 639 mt76x02_remove_hdr_pad(skb, pad_len); 640 641 if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 642 status->aggr = true; 643 644 if (WARN_ON_ONCE(len > skb->len)) 645 return -EINVAL; 646 647 pskb_trim(skb, len); 648 649 status->chains = BIT(0); 650 signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 651 for (i = 0; i < nstreams; i++) { 652 status->chains |= BIT(i); 653 status->chain_signal[i] = mt76x02_mac_get_rssi(dev, 654 rxwi->rssi[i], 655 i); 656 signal = max_t(s8, signal, status->chain_signal[i]); 657 } 658 status->signal = signal; 659 status->freq = dev->mt76.chandef.chan->center_freq; 660 status->band = dev->mt76.chandef.chan->band; 661 662 status->tid = FIELD_GET(MT_RXWI_TID, tid_sn); 663 status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 664 665 return mt76x02_mac_process_rate(dev, status, rate); 666 } 667 668 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 669 { 670 struct mt76x02_tx_status stat = {}; 671 unsigned long flags; 672 u8 update = 1; 673 bool ret; 674 675 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 676 return; 677 678 trace_mac_txstat_poll(dev); 679 680 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 681 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 682 ret = mt76x02_mac_load_tx_status(dev, &stat); 683 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 684 685 if (!ret) 686 break; 687 688 if (!irq) { 689 mt76x02_send_tx_status(dev, &stat, &update); 690 continue; 691 } 692 693 kfifo_put(&dev->txstatus_fifo, stat); 694 } 695 } 696 697 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 698 struct mt76_queue_entry *e, bool flush) 699 { 700 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 701 struct mt76x02_txwi *txwi; 702 703 if (!e->txwi) { 704 dev_kfree_skb_any(e->skb); 705 return; 706 } 707 708 mt76x02_mac_poll_tx_status(dev, false); 709 710 txwi = (struct mt76x02_txwi *) &e->txwi->txwi; 711 trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid); 712 713 mt76_tx_complete_skb(mdev, e->skb); 714 } 715 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 716 717 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val) 718 { 719 u32 data = 0; 720 721 if (val != ~0) 722 data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) | 723 MT_PROT_CFG_RTS_THRESH; 724 725 mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); 726 727 mt76_rmw(dev, MT_CCK_PROT_CFG, 728 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 729 mt76_rmw(dev, MT_OFDM_PROT_CFG, 730 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 731 } 732 733 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot, 734 int ht_mode) 735 { 736 int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION; 737 bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 738 u32 prot[6]; 739 u32 vht_prot[3]; 740 int i; 741 u16 rts_thr; 742 743 for (i = 0; i < ARRAY_SIZE(prot); i++) { 744 prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4); 745 prot[i] &= ~MT_PROT_CFG_CTRL; 746 if (i >= 2) 747 prot[i] &= ~MT_PROT_CFG_RATE; 748 } 749 750 for (i = 0; i < ARRAY_SIZE(vht_prot); i++) { 751 vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4); 752 vht_prot[i] &= ~(MT_PROT_CFG_CTRL | MT_PROT_CFG_RATE); 753 } 754 755 rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH); 756 757 if (rts_thr != 0xffff) 758 prot[0] |= MT_PROT_CTRL_RTS_CTS; 759 760 if (legacy_prot) { 761 prot[1] |= MT_PROT_CTRL_CTS2SELF; 762 763 prot[2] |= MT_PROT_RATE_CCK_11; 764 prot[3] |= MT_PROT_RATE_CCK_11; 765 prot[4] |= MT_PROT_RATE_CCK_11; 766 prot[5] |= MT_PROT_RATE_CCK_11; 767 768 vht_prot[0] |= MT_PROT_RATE_CCK_11; 769 vht_prot[1] |= MT_PROT_RATE_CCK_11; 770 vht_prot[2] |= MT_PROT_RATE_CCK_11; 771 } else { 772 if (rts_thr != 0xffff) 773 prot[1] |= MT_PROT_CTRL_RTS_CTS; 774 775 prot[2] |= MT_PROT_RATE_OFDM_24; 776 prot[3] |= MT_PROT_RATE_DUP_OFDM_24; 777 prot[4] |= MT_PROT_RATE_OFDM_24; 778 prot[5] |= MT_PROT_RATE_DUP_OFDM_24; 779 780 vht_prot[0] |= MT_PROT_RATE_OFDM_24; 781 vht_prot[1] |= MT_PROT_RATE_DUP_OFDM_24; 782 vht_prot[2] |= MT_PROT_RATE_SGI_OFDM_24; 783 } 784 785 switch (mode) { 786 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 787 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 788 prot[2] |= MT_PROT_CTRL_RTS_CTS; 789 prot[3] |= MT_PROT_CTRL_RTS_CTS; 790 prot[4] |= MT_PROT_CTRL_RTS_CTS; 791 prot[5] |= MT_PROT_CTRL_RTS_CTS; 792 vht_prot[0] |= MT_PROT_CTRL_RTS_CTS; 793 vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 794 vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 795 break; 796 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 797 prot[3] |= MT_PROT_CTRL_RTS_CTS; 798 prot[5] |= MT_PROT_CTRL_RTS_CTS; 799 vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 800 vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 801 break; 802 } 803 804 if (non_gf) { 805 prot[4] |= MT_PROT_CTRL_RTS_CTS; 806 prot[5] |= MT_PROT_CTRL_RTS_CTS; 807 } 808 809 for (i = 0; i < ARRAY_SIZE(prot); i++) 810 mt76_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]); 811 812 for (i = 0; i < ARRAY_SIZE(vht_prot); i++) 813 mt76_wr(dev, MT_TX_PROT_CFG6 + i * 4, vht_prot[i]); 814 } 815 816 void mt76x02_update_channel(struct mt76_dev *mdev) 817 { 818 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 819 struct mt76_channel_state *state; 820 u32 active, busy; 821 822 state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan); 823 824 busy = mt76_rr(dev, MT_CH_BUSY); 825 active = busy + mt76_rr(dev, MT_CH_IDLE); 826 827 spin_lock_bh(&dev->mt76.cc_lock); 828 state->cc_busy += busy; 829 state->cc_active += active; 830 spin_unlock_bh(&dev->mt76.cc_lock); 831 } 832 EXPORT_SYMBOL_GPL(mt76x02_update_channel); 833 834 static void mt76x02_check_mac_err(struct mt76x02_dev *dev) 835 { 836 u32 val = mt76_rr(dev, 0x10f4); 837 838 if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) 839 return; 840 841 dev_err(dev->mt76.dev, "mac specific condition occurred\n"); 842 843 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); 844 udelay(10); 845 mt76_wr(dev, MT_MAC_SYS_CTRL, 846 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 847 } 848 849 static void 850 mt76x02_edcca_tx_enable(struct mt76x02_dev *dev, bool enable) 851 { 852 if (enable) { 853 u32 data; 854 855 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 856 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 857 /* enable pa-lna */ 858 data = mt76_rr(dev, MT_TX_PIN_CFG); 859 data |= MT_TX_PIN_CFG_TXANT | 860 MT_TX_PIN_CFG_RXANT | 861 MT_TX_PIN_RFTR_EN | 862 MT_TX_PIN_TRSW_EN; 863 mt76_wr(dev, MT_TX_PIN_CFG, data); 864 } else { 865 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 866 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 867 /* disable pa-lna */ 868 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT); 869 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT); 870 } 871 dev->ed_tx_blocked = !enable; 872 } 873 874 void mt76x02_edcca_init(struct mt76x02_dev *dev) 875 { 876 dev->ed_trigger = 0; 877 dev->ed_silent = 0; 878 879 if (dev->ed_monitor) { 880 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 881 u8 ed_th = chan->band == NL80211_BAND_5GHZ ? 0x0e : 0x20; 882 883 mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 884 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 885 mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0), 886 ed_th << 8 | ed_th); 887 if (!is_mt76x2(dev)) 888 mt76_set(dev, MT_TXOP_HLDR_ET, 889 MT_TXOP_HLDR_TX40M_BLK_EN); 890 } else { 891 mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 892 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 893 if (is_mt76x2(dev)) { 894 mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); 895 } else { 896 mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464); 897 mt76_clear(dev, MT_TXOP_HLDR_ET, 898 MT_TXOP_HLDR_TX40M_BLK_EN); 899 } 900 } 901 mt76x02_edcca_tx_enable(dev, true); 902 } 903 EXPORT_SYMBOL_GPL(mt76x02_edcca_init); 904 905 #define MT_EDCCA_TH 90 906 #define MT_EDCCA_BLOCK_TH 2 907 static void mt76x02_edcca_check(struct mt76x02_dev *dev) 908 { 909 u32 val, busy; 910 911 val = mt76_rr(dev, MT_ED_CCA_TIMER); 912 busy = (val * 100) / jiffies_to_usecs(MT_CALIBRATE_INTERVAL); 913 busy = min_t(u32, busy, 100); 914 915 if (busy > MT_EDCCA_TH) { 916 dev->ed_trigger++; 917 dev->ed_silent = 0; 918 } else { 919 dev->ed_silent++; 920 dev->ed_trigger = 0; 921 } 922 923 if (dev->ed_trigger > MT_EDCCA_BLOCK_TH && 924 !dev->ed_tx_blocked) 925 mt76x02_edcca_tx_enable(dev, false); 926 else if (dev->ed_silent > MT_EDCCA_BLOCK_TH && 927 dev->ed_tx_blocked) 928 mt76x02_edcca_tx_enable(dev, true); 929 } 930 931 void mt76x02_mac_work(struct work_struct *work) 932 { 933 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 934 mac_work.work); 935 int i, idx; 936 937 mutex_lock(&dev->mt76.mutex); 938 939 mt76x02_update_channel(&dev->mt76); 940 for (i = 0, idx = 0; i < 16; i++) { 941 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 942 943 dev->aggr_stats[idx++] += val & 0xffff; 944 dev->aggr_stats[idx++] += val >> 16; 945 } 946 947 if (!dev->beacon_mask) 948 mt76x02_check_mac_err(dev); 949 950 if (dev->ed_monitor) 951 mt76x02_edcca_check(dev); 952 953 mutex_unlock(&dev->mt76.mutex); 954 955 mt76_tx_status_check(&dev->mt76, NULL, false); 956 957 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work, 958 MT_CALIBRATE_INTERVAL); 959 } 960 961 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr) 962 { 963 idx &= 7; 964 mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr)); 965 mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR, 966 get_unaligned_le16(addr + 4)); 967 } 968 969 static int 970 mt76x02_write_beacon(struct mt76x02_dev *dev, int offset, struct sk_buff *skb) 971 { 972 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 973 struct mt76x02_txwi txwi; 974 975 if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi))) 976 return -ENOSPC; 977 978 mt76x02_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len); 979 980 mt76_wr_copy(dev, offset, &txwi, sizeof(txwi)); 981 offset += sizeof(txwi); 982 983 mt76_wr_copy(dev, offset, skb->data, skb->len); 984 return 0; 985 } 986 987 static int 988 __mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 bcn_idx, 989 struct sk_buff *skb) 990 { 991 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 992 int beacon_addr = mt76x02_beacon_offsets[bcn_idx]; 993 int ret = 0; 994 int i; 995 996 /* Prevent corrupt transmissions during update */ 997 mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx)); 998 999 if (skb) { 1000 ret = mt76x02_write_beacon(dev, beacon_addr, skb); 1001 if (!ret) 1002 dev->beacon_data_mask |= BIT(bcn_idx); 1003 } else { 1004 dev->beacon_data_mask &= ~BIT(bcn_idx); 1005 for (i = 0; i < beacon_len; i += 4) 1006 mt76_wr(dev, beacon_addr + i, 0); 1007 } 1008 1009 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask); 1010 1011 return ret; 1012 } 1013 1014 int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx, 1015 struct sk_buff *skb) 1016 { 1017 bool force_update = false; 1018 int bcn_idx = 0; 1019 int i; 1020 1021 for (i = 0; i < ARRAY_SIZE(dev->beacons); i++) { 1022 if (vif_idx == i) { 1023 force_update = !!dev->beacons[i] ^ !!skb; 1024 1025 if (dev->beacons[i]) 1026 dev_kfree_skb(dev->beacons[i]); 1027 1028 dev->beacons[i] = skb; 1029 __mt76x02_mac_set_beacon(dev, bcn_idx, skb); 1030 } else if (force_update && dev->beacons[i]) { 1031 __mt76x02_mac_set_beacon(dev, bcn_idx, 1032 dev->beacons[i]); 1033 } 1034 1035 bcn_idx += !!dev->beacons[i]; 1036 } 1037 1038 for (i = bcn_idx; i < ARRAY_SIZE(dev->beacons); i++) { 1039 if (!(dev->beacon_data_mask & BIT(i))) 1040 break; 1041 1042 __mt76x02_mac_set_beacon(dev, i, NULL); 1043 } 1044 1045 mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 1046 bcn_idx - 1); 1047 return 0; 1048 } 1049 1050 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, 1051 u8 vif_idx, bool val) 1052 { 1053 u8 old_mask = dev->beacon_mask; 1054 bool en; 1055 u32 reg; 1056 1057 if (val) { 1058 dev->beacon_mask |= BIT(vif_idx); 1059 } else { 1060 dev->beacon_mask &= ~BIT(vif_idx); 1061 mt76x02_mac_set_beacon(dev, vif_idx, NULL); 1062 } 1063 1064 if (!!old_mask == !!dev->beacon_mask) 1065 return; 1066 1067 en = dev->beacon_mask; 1068 1069 mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); 1070 reg = MT_BEACON_TIME_CFG_BEACON_TX | 1071 MT_BEACON_TIME_CFG_TBTT_EN | 1072 MT_BEACON_TIME_CFG_TIMER_EN; 1073 mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en); 1074 1075 if (en) 1076 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1077 else 1078 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1079 } 1080