1c378f247SStanislaw Gruszka /* 2c378f247SStanislaw Gruszka * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3c378f247SStanislaw Gruszka * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4c378f247SStanislaw Gruszka * 5c378f247SStanislaw Gruszka * Permission to use, copy, modify, and/or distribute this software for any 6c378f247SStanislaw Gruszka * purpose with or without fee is hereby granted, provided that the above 7c378f247SStanislaw Gruszka * copyright notice and this permission notice appear in all copies. 8c378f247SStanislaw Gruszka * 9c378f247SStanislaw Gruszka * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10c378f247SStanislaw Gruszka * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11c378f247SStanislaw Gruszka * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12c378f247SStanislaw Gruszka * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13c378f247SStanislaw Gruszka * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14c378f247SStanislaw Gruszka * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15c378f247SStanislaw Gruszka * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16c378f247SStanislaw Gruszka */ 17c378f247SStanislaw Gruszka 187a07adcdSLorenzo Bianconi #include "mt76x02.h" 193e2342edSLorenzo Bianconi #include "mt76x02_trace.h" 20c378f247SStanislaw Gruszka 215567b373SFelix Fietkau static enum mt76x02_cipher_type 22c378f247SStanislaw Gruszka mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 23c378f247SStanislaw Gruszka { 24c378f247SStanislaw Gruszka memset(key_data, 0, 32); 25c378f247SStanislaw Gruszka if (!key) 26c378f247SStanislaw Gruszka return MT_CIPHER_NONE; 27c378f247SStanislaw Gruszka 28c378f247SStanislaw Gruszka if (key->keylen > 32) 29c378f247SStanislaw Gruszka return MT_CIPHER_NONE; 30c378f247SStanislaw Gruszka 31c378f247SStanislaw Gruszka memcpy(key_data, key->key, key->keylen); 32c378f247SStanislaw Gruszka 33c378f247SStanislaw Gruszka switch (key->cipher) { 34c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_WEP40: 35c378f247SStanislaw Gruszka return MT_CIPHER_WEP40; 36c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_WEP104: 37c378f247SStanislaw Gruszka return MT_CIPHER_WEP104; 38c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_TKIP: 39c378f247SStanislaw Gruszka return MT_CIPHER_TKIP; 40c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_CCMP: 41c378f247SStanislaw Gruszka return MT_CIPHER_AES_CCMP; 42c378f247SStanislaw Gruszka default: 43c378f247SStanislaw Gruszka return MT_CIPHER_NONE; 44c378f247SStanislaw Gruszka } 45c378f247SStanislaw Gruszka } 46047aed1cSStanislaw Gruszka 478d66af49SLorenzo Bianconi int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 488d66af49SLorenzo Bianconi u8 key_idx, struct ieee80211_key_conf *key) 49047aed1cSStanislaw Gruszka { 50047aed1cSStanislaw Gruszka enum mt76x02_cipher_type cipher; 51047aed1cSStanislaw Gruszka u8 key_data[32]; 52047aed1cSStanislaw Gruszka u32 val; 53047aed1cSStanislaw Gruszka 54047aed1cSStanislaw Gruszka cipher = mt76x02_mac_get_key_info(key, key_data); 55047aed1cSStanislaw Gruszka if (cipher == MT_CIPHER_NONE && key) 56047aed1cSStanislaw Gruszka return -EOPNOTSUPP; 57047aed1cSStanislaw Gruszka 588d66af49SLorenzo Bianconi val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 59047aed1cSStanislaw Gruszka val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 60047aed1cSStanislaw Gruszka val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 618d66af49SLorenzo Bianconi mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 62047aed1cSStanislaw Gruszka 638d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 64047aed1cSStanislaw Gruszka sizeof(key_data)); 65047aed1cSStanislaw Gruszka 66047aed1cSStanislaw Gruszka return 0; 67047aed1cSStanislaw Gruszka } 68047aed1cSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 6946436b5eSStanislaw Gruszka 708d66af49SLorenzo Bianconi int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 7146436b5eSStanislaw Gruszka struct ieee80211_key_conf *key) 7246436b5eSStanislaw Gruszka { 7346436b5eSStanislaw Gruszka enum mt76x02_cipher_type cipher; 7446436b5eSStanislaw Gruszka u8 key_data[32]; 7546436b5eSStanislaw Gruszka u8 iv_data[8]; 7646436b5eSStanislaw Gruszka 7746436b5eSStanislaw Gruszka cipher = mt76x02_mac_get_key_info(key, key_data); 7846436b5eSStanislaw Gruszka if (cipher == MT_CIPHER_NONE && key) 7946436b5eSStanislaw Gruszka return -EOPNOTSUPP; 8046436b5eSStanislaw Gruszka 818d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 828d66af49SLorenzo Bianconi mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 8346436b5eSStanislaw Gruszka 8446436b5eSStanislaw Gruszka memset(iv_data, 0, sizeof(iv_data)); 8546436b5eSStanislaw Gruszka if (key) { 868d66af49SLorenzo Bianconi mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 8746436b5eSStanislaw Gruszka !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 8846436b5eSStanislaw Gruszka iv_data[3] = key->keyidx << 6; 8946436b5eSStanislaw Gruszka if (cipher >= MT_CIPHER_TKIP) 9046436b5eSStanislaw Gruszka iv_data[3] |= 0x20; 9146436b5eSStanislaw Gruszka } 9246436b5eSStanislaw Gruszka 938d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 9446436b5eSStanislaw Gruszka 9546436b5eSStanislaw Gruszka return 0; 9646436b5eSStanislaw Gruszka } 9732bb405fSStanislaw Gruszka 988d66af49SLorenzo Bianconi void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, 998d66af49SLorenzo Bianconi u8 vif_idx, u8 *mac) 10032bb405fSStanislaw Gruszka { 10132bb405fSStanislaw Gruszka struct mt76_wcid_addr addr = {}; 10232bb405fSStanislaw Gruszka u32 attr; 10332bb405fSStanislaw Gruszka 10432bb405fSStanislaw Gruszka attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 10532bb405fSStanislaw Gruszka FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 10632bb405fSStanislaw Gruszka 1078d66af49SLorenzo Bianconi mt76_wr(dev, MT_WCID_ATTR(idx), attr); 10832bb405fSStanislaw Gruszka 10932bb405fSStanislaw Gruszka if (idx >= 128) 11032bb405fSStanislaw Gruszka return; 11132bb405fSStanislaw Gruszka 11232bb405fSStanislaw Gruszka if (mac) 11332bb405fSStanislaw Gruszka memcpy(addr.macaddr, mac, ETH_ALEN); 11432bb405fSStanislaw Gruszka 1158d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 11632bb405fSStanislaw Gruszka } 11732bb405fSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 118516ea2a2SStanislaw Gruszka 1198d66af49SLorenzo Bianconi void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop) 120516ea2a2SStanislaw Gruszka { 1218d66af49SLorenzo Bianconi u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); 122516ea2a2SStanislaw Gruszka u32 bit = MT_WCID_DROP_MASK(idx); 123516ea2a2SStanislaw Gruszka 124516ea2a2SStanislaw Gruszka /* prevent unnecessary writes */ 125516ea2a2SStanislaw Gruszka if ((val & bit) != (bit * drop)) 1268d66af49SLorenzo Bianconi mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 127516ea2a2SStanislaw Gruszka } 128f5a7f126SStanislaw Gruszka 129c4ed5088SLorenzo Bianconi static __le16 1308d66af49SLorenzo Bianconi mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev, 1315327b5eaSStanislaw Gruszka const struct ieee80211_tx_rate *rate, u8 *nss_val) 1325327b5eaSStanislaw Gruszka { 133c09f4d0aSLorenzo Bianconi u8 phy, rate_idx, nss, bw = 0; 1345327b5eaSStanislaw Gruszka u16 rateval; 1355327b5eaSStanislaw Gruszka 1365327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 1375327b5eaSStanislaw Gruszka rate_idx = rate->idx; 1385327b5eaSStanislaw Gruszka nss = 1 + (rate->idx >> 4); 1395327b5eaSStanislaw Gruszka phy = MT_PHY_TYPE_VHT; 1405327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 1415327b5eaSStanislaw Gruszka bw = 2; 1425327b5eaSStanislaw Gruszka else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1435327b5eaSStanislaw Gruszka bw = 1; 1445327b5eaSStanislaw Gruszka } else if (rate->flags & IEEE80211_TX_RC_MCS) { 1455327b5eaSStanislaw Gruszka rate_idx = rate->idx; 1465327b5eaSStanislaw Gruszka nss = 1 + (rate->idx >> 3); 1475327b5eaSStanislaw Gruszka phy = MT_PHY_TYPE_HT; 1485327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 1495327b5eaSStanislaw Gruszka phy = MT_PHY_TYPE_HT_GF; 1505327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1515327b5eaSStanislaw Gruszka bw = 1; 1525327b5eaSStanislaw Gruszka } else { 1535327b5eaSStanislaw Gruszka const struct ieee80211_rate *r; 1548d66af49SLorenzo Bianconi int band = dev->mt76.chandef.chan->band; 1555327b5eaSStanislaw Gruszka u16 val; 1565327b5eaSStanislaw Gruszka 1578d66af49SLorenzo Bianconi r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx]; 1585327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1595327b5eaSStanislaw Gruszka val = r->hw_value_short; 1605327b5eaSStanislaw Gruszka else 1615327b5eaSStanislaw Gruszka val = r->hw_value; 1625327b5eaSStanislaw Gruszka 1635327b5eaSStanislaw Gruszka phy = val >> 8; 1645327b5eaSStanislaw Gruszka rate_idx = val & 0xff; 165c09f4d0aSLorenzo Bianconi nss = 1; 1665327b5eaSStanislaw Gruszka } 1675327b5eaSStanislaw Gruszka 1685327b5eaSStanislaw Gruszka rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 1695327b5eaSStanislaw Gruszka rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 1705327b5eaSStanislaw Gruszka rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 1715327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 1725327b5eaSStanislaw Gruszka rateval |= MT_RXWI_RATE_SGI; 1735327b5eaSStanislaw Gruszka 1745327b5eaSStanislaw Gruszka *nss_val = nss; 1755327b5eaSStanislaw Gruszka return cpu_to_le16(rateval); 1765327b5eaSStanislaw Gruszka } 1775327b5eaSStanislaw Gruszka 1788d66af49SLorenzo Bianconi void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 1795327b5eaSStanislaw Gruszka const struct ieee80211_tx_rate *rate) 1805327b5eaSStanislaw Gruszka { 1818d66af49SLorenzo Bianconi spin_lock_bh(&dev->mt76.lock); 1825327b5eaSStanislaw Gruszka wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 1835327b5eaSStanislaw Gruszka wcid->tx_rate_set = true; 1848d66af49SLorenzo Bianconi spin_unlock_bh(&dev->mt76.lock); 1855327b5eaSStanislaw Gruszka } 186b490b1dfSStanislaw Gruszka 187dd61100dSLorenzo Bianconi void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable) 188dd61100dSLorenzo Bianconi { 189dd61100dSLorenzo Bianconi if (enable) 190dd61100dSLorenzo Bianconi mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 191dd61100dSLorenzo Bianconi else 192dd61100dSLorenzo Bianconi mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 193dd61100dSLorenzo Bianconi } 194dd61100dSLorenzo Bianconi 1958d66af49SLorenzo Bianconi bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 196b490b1dfSStanislaw Gruszka struct mt76x02_tx_status *stat) 197b490b1dfSStanislaw Gruszka { 198b490b1dfSStanislaw Gruszka u32 stat1, stat2; 199b490b1dfSStanislaw Gruszka 2008d66af49SLorenzo Bianconi stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 2018d66af49SLorenzo Bianconi stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); 202b490b1dfSStanislaw Gruszka 203b490b1dfSStanislaw Gruszka stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 204b490b1dfSStanislaw Gruszka if (!stat->valid) 205b490b1dfSStanislaw Gruszka return false; 206b490b1dfSStanislaw Gruszka 207b490b1dfSStanislaw Gruszka stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 208b490b1dfSStanislaw Gruszka stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 209b490b1dfSStanislaw Gruszka stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 210b490b1dfSStanislaw Gruszka stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 211b490b1dfSStanislaw Gruszka stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 212b490b1dfSStanislaw Gruszka 213b490b1dfSStanislaw Gruszka stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 214b490b1dfSStanislaw Gruszka stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 215b490b1dfSStanislaw Gruszka 216e0168dc6SLorenzo Bianconi trace_mac_txstat_fetch(dev, stat); 217e0168dc6SLorenzo Bianconi 218b490b1dfSStanislaw Gruszka return true; 219b490b1dfSStanislaw Gruszka } 2207c1f8881SStanislaw Gruszka 2217c1f8881SStanislaw Gruszka static int 2227c1f8881SStanislaw Gruszka mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 2237c1f8881SStanislaw Gruszka enum nl80211_band band) 2247c1f8881SStanislaw Gruszka { 2257c1f8881SStanislaw Gruszka u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 2267c1f8881SStanislaw Gruszka 2277c1f8881SStanislaw Gruszka txrate->idx = 0; 2287c1f8881SStanislaw Gruszka txrate->flags = 0; 2297c1f8881SStanislaw Gruszka txrate->count = 1; 2307c1f8881SStanislaw Gruszka 2317c1f8881SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 2327c1f8881SStanislaw Gruszka case MT_PHY_TYPE_OFDM: 2337c1f8881SStanislaw Gruszka if (band == NL80211_BAND_2GHZ) 2347c1f8881SStanislaw Gruszka idx += 4; 2357c1f8881SStanislaw Gruszka 2367c1f8881SStanislaw Gruszka txrate->idx = idx; 2377c1f8881SStanislaw Gruszka return 0; 2387c1f8881SStanislaw Gruszka case MT_PHY_TYPE_CCK: 2397c1f8881SStanislaw Gruszka if (idx >= 8) 2407c1f8881SStanislaw Gruszka idx -= 8; 2417c1f8881SStanislaw Gruszka 2427c1f8881SStanislaw Gruszka txrate->idx = idx; 2437c1f8881SStanislaw Gruszka return 0; 2447c1f8881SStanislaw Gruszka case MT_PHY_TYPE_HT_GF: 2457c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 2467c1f8881SStanislaw Gruszka /* fall through */ 2477c1f8881SStanislaw Gruszka case MT_PHY_TYPE_HT: 2487c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_MCS; 2497c1f8881SStanislaw Gruszka txrate->idx = idx; 2507c1f8881SStanislaw Gruszka break; 2517c1f8881SStanislaw Gruszka case MT_PHY_TYPE_VHT: 2527c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 2537c1f8881SStanislaw Gruszka txrate->idx = idx; 2547c1f8881SStanislaw Gruszka break; 2557c1f8881SStanislaw Gruszka default: 2567c1f8881SStanislaw Gruszka return -EINVAL; 2577c1f8881SStanislaw Gruszka } 2587c1f8881SStanislaw Gruszka 2597c1f8881SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 2607c1f8881SStanislaw Gruszka case MT_PHY_BW_20: 2617c1f8881SStanislaw Gruszka break; 2627c1f8881SStanislaw Gruszka case MT_PHY_BW_40: 2637c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 2647c1f8881SStanislaw Gruszka break; 2657c1f8881SStanislaw Gruszka case MT_PHY_BW_80: 2667c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 2677c1f8881SStanislaw Gruszka break; 2687c1f8881SStanislaw Gruszka default: 2697c1f8881SStanislaw Gruszka return -EINVAL; 2707c1f8881SStanislaw Gruszka } 2717c1f8881SStanislaw Gruszka 2727c1f8881SStanislaw Gruszka if (rate & MT_RXWI_RATE_SGI) 2737c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 2747c1f8881SStanislaw Gruszka 2757c1f8881SStanislaw Gruszka return 0; 2767c1f8881SStanislaw Gruszka } 2777c1f8881SStanislaw Gruszka 2788d66af49SLorenzo Bianconi void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 279427f9ebeSLorenzo Bianconi struct sk_buff *skb, struct mt76_wcid *wcid, 280427f9ebeSLorenzo Bianconi struct ieee80211_sta *sta, int len) 281427f9ebeSLorenzo Bianconi { 282320c85e6SLorenzo Bianconi struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 283427f9ebeSLorenzo Bianconi struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 284427f9ebeSLorenzo Bianconi struct ieee80211_tx_rate *rate = &info->control.rates[0]; 285427f9ebeSLorenzo Bianconi struct ieee80211_key_conf *key = info->control.hw_key; 286427f9ebeSLorenzo Bianconi u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 287320c85e6SLorenzo Bianconi u16 txwi_flags = 0; 288427f9ebeSLorenzo Bianconi u8 nss; 289427f9ebeSLorenzo Bianconi s8 txpwr_adj, max_txpwr_adj; 2908d66af49SLorenzo Bianconi u8 ccmp_pn[8], nstreams = dev->mt76.chainmask & 0xf; 291427f9ebeSLorenzo Bianconi 292427f9ebeSLorenzo Bianconi memset(txwi, 0, sizeof(*txwi)); 293427f9ebeSLorenzo Bianconi 294128b75bfSFelix Fietkau if (!info->control.hw_key && wcid && wcid->hw_key_idx != 0xff && 295128b75bfSFelix Fietkau ieee80211_has_protected(hdr->frame_control)) { 296128b75bfSFelix Fietkau wcid = NULL; 297128b75bfSFelix Fietkau ieee80211_get_tx_rates(info->control.vif, sta, skb, 298128b75bfSFelix Fietkau info->control.rates, 1); 299128b75bfSFelix Fietkau } 300128b75bfSFelix Fietkau 301427f9ebeSLorenzo Bianconi if (wcid) 302427f9ebeSLorenzo Bianconi txwi->wcid = wcid->idx; 303427f9ebeSLorenzo Bianconi else 304427f9ebeSLorenzo Bianconi txwi->wcid = 0xff; 305427f9ebeSLorenzo Bianconi 306427f9ebeSLorenzo Bianconi if (wcid && wcid->sw_iv && key) { 307427f9ebeSLorenzo Bianconi u64 pn = atomic64_inc_return(&key->tx_pn); 308427f9ebeSLorenzo Bianconi ccmp_pn[0] = pn; 309427f9ebeSLorenzo Bianconi ccmp_pn[1] = pn >> 8; 310427f9ebeSLorenzo Bianconi ccmp_pn[2] = 0; 311427f9ebeSLorenzo Bianconi ccmp_pn[3] = 0x20 | (key->keyidx << 6); 312427f9ebeSLorenzo Bianconi ccmp_pn[4] = pn >> 16; 313427f9ebeSLorenzo Bianconi ccmp_pn[5] = pn >> 24; 314427f9ebeSLorenzo Bianconi ccmp_pn[6] = pn >> 32; 315427f9ebeSLorenzo Bianconi ccmp_pn[7] = pn >> 40; 316427f9ebeSLorenzo Bianconi txwi->iv = *((__le32 *)&ccmp_pn[0]); 317427f9ebeSLorenzo Bianconi txwi->eiv = *((__le32 *)&ccmp_pn[1]); 318427f9ebeSLorenzo Bianconi } 319427f9ebeSLorenzo Bianconi 3208d66af49SLorenzo Bianconi spin_lock_bh(&dev->mt76.lock); 321427f9ebeSLorenzo Bianconi if (wcid && (rate->idx < 0 || !rate->count)) { 322427f9ebeSLorenzo Bianconi txwi->rate = wcid->tx_rate; 323427f9ebeSLorenzo Bianconi max_txpwr_adj = wcid->max_txpwr_adj; 324427f9ebeSLorenzo Bianconi nss = wcid->tx_rate_nss; 325427f9ebeSLorenzo Bianconi } else { 326427f9ebeSLorenzo Bianconi txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 32791be8e8aSLorenzo Bianconi max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 328427f9ebeSLorenzo Bianconi } 3298d66af49SLorenzo Bianconi spin_unlock_bh(&dev->mt76.lock); 330427f9ebeSLorenzo Bianconi 33191be8e8aSLorenzo Bianconi txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->mt76.txpower_conf, 332427f9ebeSLorenzo Bianconi max_txpwr_adj); 333427f9ebeSLorenzo Bianconi txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 334427f9ebeSLorenzo Bianconi 3358d66af49SLorenzo Bianconi if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4) 336427f9ebeSLorenzo Bianconi txwi->txstream = 0x13; 3378d66af49SLorenzo Bianconi else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 && 338427f9ebeSLorenzo Bianconi !(txwi->rate & cpu_to_le16(rate_ht_mask))) 339427f9ebeSLorenzo Bianconi txwi->txstream = 0x93; 340427f9ebeSLorenzo Bianconi 341320c85e6SLorenzo Bianconi if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC)) 342320c85e6SLorenzo Bianconi txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 343320c85e6SLorenzo Bianconi if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 344320c85e6SLorenzo Bianconi txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 345320c85e6SLorenzo Bianconi if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC) 346320c85e6SLorenzo Bianconi txwi_flags |= MT_TXWI_FLAGS_MMPS; 347320c85e6SLorenzo Bianconi if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 348320c85e6SLorenzo Bianconi txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 349320c85e6SLorenzo Bianconi if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 350320c85e6SLorenzo Bianconi txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 351320c85e6SLorenzo Bianconi if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 352320c85e6SLorenzo Bianconi u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 353320c85e6SLorenzo Bianconi 354320c85e6SLorenzo Bianconi ba_size <<= sta->ht_cap.ampdu_factor; 355320c85e6SLorenzo Bianconi ba_size = min_t(int, 63, ba_size - 1); 356320c85e6SLorenzo Bianconi if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 357320c85e6SLorenzo Bianconi ba_size = 0; 358320c85e6SLorenzo Bianconi txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 359320c85e6SLorenzo Bianconi 360320c85e6SLorenzo Bianconi txwi_flags |= MT_TXWI_FLAGS_AMPDU | 361320c85e6SLorenzo Bianconi FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, 362320c85e6SLorenzo Bianconi sta->ht_cap.ampdu_density); 363320c85e6SLorenzo Bianconi } 364320c85e6SLorenzo Bianconi 365320c85e6SLorenzo Bianconi if (ieee80211_is_probe_resp(hdr->frame_control) || 366320c85e6SLorenzo Bianconi ieee80211_is_beacon(hdr->frame_control)) 367320c85e6SLorenzo Bianconi txwi_flags |= MT_TXWI_FLAGS_TS; 368320c85e6SLorenzo Bianconi 369320c85e6SLorenzo Bianconi txwi->flags |= cpu_to_le16(txwi_flags); 370320c85e6SLorenzo Bianconi txwi->len_ctl = cpu_to_le16(len); 371427f9ebeSLorenzo Bianconi } 372427f9ebeSLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 373427f9ebeSLorenzo Bianconi 3747c1f8881SStanislaw Gruszka static void 3758d66af49SLorenzo Bianconi mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, 3767c1f8881SStanislaw Gruszka struct ieee80211_tx_info *info, 3777c1f8881SStanislaw Gruszka struct mt76x02_tx_status *st, int n_frames) 3787c1f8881SStanislaw Gruszka { 3797c1f8881SStanislaw Gruszka struct ieee80211_tx_rate *rate = info->status.rates; 3807c1f8881SStanislaw Gruszka int cur_idx, last_rate; 3817c1f8881SStanislaw Gruszka int i; 3827c1f8881SStanislaw Gruszka 3837c1f8881SStanislaw Gruszka if (!n_frames) 3847c1f8881SStanislaw Gruszka return; 3857c1f8881SStanislaw Gruszka 3867c1f8881SStanislaw Gruszka last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 3877c1f8881SStanislaw Gruszka mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 3888d66af49SLorenzo Bianconi dev->mt76.chandef.chan->band); 3897c1f8881SStanislaw Gruszka if (last_rate < IEEE80211_TX_MAX_RATES - 1) 3907c1f8881SStanislaw Gruszka rate[last_rate + 1].idx = -1; 3917c1f8881SStanislaw Gruszka 3927c1f8881SStanislaw Gruszka cur_idx = rate[last_rate].idx + last_rate; 3937c1f8881SStanislaw Gruszka for (i = 0; i <= last_rate; i++) { 3947c1f8881SStanislaw Gruszka rate[i].flags = rate[last_rate].flags; 3957c1f8881SStanislaw Gruszka rate[i].idx = max_t(int, 0, cur_idx - i); 3967c1f8881SStanislaw Gruszka rate[i].count = 1; 3977c1f8881SStanislaw Gruszka } 3987c1f8881SStanislaw Gruszka rate[last_rate].count = st->retry + 1 - last_rate; 3997c1f8881SStanislaw Gruszka 4007c1f8881SStanislaw Gruszka info->status.ampdu_len = n_frames; 4017c1f8881SStanislaw Gruszka info->status.ampdu_ack_len = st->success ? n_frames : 0; 4027c1f8881SStanislaw Gruszka 4037c1f8881SStanislaw Gruszka if (st->aggr) 4047c1f8881SStanislaw Gruszka info->flags |= IEEE80211_TX_CTL_AMPDU | 4057c1f8881SStanislaw Gruszka IEEE80211_TX_STAT_AMPDU; 4067c1f8881SStanislaw Gruszka 4077c1f8881SStanislaw Gruszka if (!st->ack_req) 4087c1f8881SStanislaw Gruszka info->flags |= IEEE80211_TX_CTL_NO_ACK; 4097c1f8881SStanislaw Gruszka else if (st->success) 4107c1f8881SStanislaw Gruszka info->flags |= IEEE80211_TX_STAT_ACK; 4117c1f8881SStanislaw Gruszka } 4127c1f8881SStanislaw Gruszka 4138d66af49SLorenzo Bianconi void mt76x02_send_tx_status(struct mt76x02_dev *dev, 4147c1f8881SStanislaw Gruszka struct mt76x02_tx_status *stat, u8 *update) 4157c1f8881SStanislaw Gruszka { 4167c1f8881SStanislaw Gruszka struct ieee80211_tx_info info = {}; 41788046b2cSFelix Fietkau struct ieee80211_tx_status status = { 41888046b2cSFelix Fietkau .info = &info 41988046b2cSFelix Fietkau }; 4207c1f8881SStanislaw Gruszka struct mt76_wcid *wcid = NULL; 4217c1f8881SStanislaw Gruszka struct mt76x02_sta *msta = NULL; 42288046b2cSFelix Fietkau struct mt76_dev *mdev = &dev->mt76; 42379d1c94cSFelix Fietkau struct sk_buff_head list; 42488046b2cSFelix Fietkau 42588046b2cSFelix Fietkau if (stat->pktid == MT_PACKET_ID_NO_ACK) 42688046b2cSFelix Fietkau return; 4277c1f8881SStanislaw Gruszka 4287c1f8881SStanislaw Gruszka rcu_read_lock(); 42979d1c94cSFelix Fietkau mt76_tx_status_lock(mdev, &list); 43088046b2cSFelix Fietkau 4318d66af49SLorenzo Bianconi if (stat->wcid < ARRAY_SIZE(dev->mt76.wcid)) 4328d66af49SLorenzo Bianconi wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]); 4337c1f8881SStanislaw Gruszka 43465b526a1SFelix Fietkau if (wcid && wcid->sta) { 4357c1f8881SStanislaw Gruszka void *priv; 4367c1f8881SStanislaw Gruszka 4377c1f8881SStanislaw Gruszka priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 43888046b2cSFelix Fietkau status.sta = container_of(priv, struct ieee80211_sta, 4397c1f8881SStanislaw Gruszka drv_priv); 4407c1f8881SStanislaw Gruszka } 4417c1f8881SStanislaw Gruszka 44288046b2cSFelix Fietkau if (wcid) { 443013b2dffSFelix Fietkau if (stat->pktid >= MT_PACKET_ID_FIRST) 44488046b2cSFelix Fietkau status.skb = mt76_tx_status_skb_get(mdev, wcid, 44579d1c94cSFelix Fietkau stat->pktid, &list); 44688046b2cSFelix Fietkau if (status.skb) 44788046b2cSFelix Fietkau status.info = IEEE80211_SKB_CB(status.skb); 44888046b2cSFelix Fietkau } 44988046b2cSFelix Fietkau 45088046b2cSFelix Fietkau if (msta && stat->aggr && !status.skb) { 4517c1f8881SStanislaw Gruszka u32 stat_val, stat_cache; 4527c1f8881SStanislaw Gruszka 4537c1f8881SStanislaw Gruszka stat_val = stat->rate; 4547c1f8881SStanislaw Gruszka stat_val |= ((u32) stat->retry) << 16; 4557c1f8881SStanislaw Gruszka stat_cache = msta->status.rate; 4567c1f8881SStanislaw Gruszka stat_cache |= ((u32) msta->status.retry) << 16; 4577c1f8881SStanislaw Gruszka 4587c1f8881SStanislaw Gruszka if (*update == 0 && stat_val == stat_cache && 4597c1f8881SStanislaw Gruszka stat->wcid == msta->status.wcid && msta->n_frames < 32) { 4607c1f8881SStanislaw Gruszka msta->n_frames++; 4617c1f8881SStanislaw Gruszka goto out; 4627c1f8881SStanislaw Gruszka } 4637c1f8881SStanislaw Gruszka 46488046b2cSFelix Fietkau mt76x02_mac_fill_tx_status(dev, status.info, &msta->status, 4657c1f8881SStanislaw Gruszka msta->n_frames); 4667c1f8881SStanislaw Gruszka 4677c1f8881SStanislaw Gruszka msta->status = *stat; 4687c1f8881SStanislaw Gruszka msta->n_frames = 1; 4697c1f8881SStanislaw Gruszka *update = 0; 4707c1f8881SStanislaw Gruszka } else { 47188046b2cSFelix Fietkau mt76x02_mac_fill_tx_status(dev, status.info, stat, 1); 4727c1f8881SStanislaw Gruszka *update = 1; 4737c1f8881SStanislaw Gruszka } 4747c1f8881SStanislaw Gruszka 47588046b2cSFelix Fietkau if (status.skb) 47679d1c94cSFelix Fietkau mt76_tx_status_skb_done(mdev, status.skb, &list); 47788046b2cSFelix Fietkau else 47888046b2cSFelix Fietkau ieee80211_tx_status_ext(mt76_hw(dev), &status); 4797c1f8881SStanislaw Gruszka 4807c1f8881SStanislaw Gruszka out: 48179d1c94cSFelix Fietkau mt76_tx_status_unlock(mdev, &list); 4827c1f8881SStanislaw Gruszka rcu_read_unlock(); 4837c1f8881SStanislaw Gruszka } 48474ff4539SStanislaw Gruszka 4851a4846fcSFelix Fietkau static int 486f832898dSLorenzo Bianconi mt76x02_mac_process_rate(struct mt76x02_dev *dev, 487f832898dSLorenzo Bianconi struct mt76_rx_status *status, 488f832898dSLorenzo Bianconi u16 rate) 48974ff4539SStanislaw Gruszka { 49074ff4539SStanislaw Gruszka u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 49174ff4539SStanislaw Gruszka 49274ff4539SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 49374ff4539SStanislaw Gruszka case MT_PHY_TYPE_OFDM: 49474ff4539SStanislaw Gruszka if (idx >= 8) 49574ff4539SStanislaw Gruszka idx = 0; 49674ff4539SStanislaw Gruszka 49774ff4539SStanislaw Gruszka if (status->band == NL80211_BAND_2GHZ) 49874ff4539SStanislaw Gruszka idx += 4; 49974ff4539SStanislaw Gruszka 50074ff4539SStanislaw Gruszka status->rate_idx = idx; 50174ff4539SStanislaw Gruszka return 0; 50274ff4539SStanislaw Gruszka case MT_PHY_TYPE_CCK: 50374ff4539SStanislaw Gruszka if (idx >= 8) { 50474ff4539SStanislaw Gruszka idx -= 8; 50574ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 50674ff4539SStanislaw Gruszka } 50774ff4539SStanislaw Gruszka 50874ff4539SStanislaw Gruszka if (idx >= 4) 50974ff4539SStanislaw Gruszka idx = 0; 51074ff4539SStanislaw Gruszka 51174ff4539SStanislaw Gruszka status->rate_idx = idx; 51274ff4539SStanislaw Gruszka return 0; 51374ff4539SStanislaw Gruszka case MT_PHY_TYPE_HT_GF: 51474ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_HT_GF; 51574ff4539SStanislaw Gruszka /* fall through */ 51674ff4539SStanislaw Gruszka case MT_PHY_TYPE_HT: 51774ff4539SStanislaw Gruszka status->encoding = RX_ENC_HT; 51874ff4539SStanislaw Gruszka status->rate_idx = idx; 51974ff4539SStanislaw Gruszka break; 520f832898dSLorenzo Bianconi case MT_PHY_TYPE_VHT: { 521f832898dSLorenzo Bianconi u8 n_rxstream = dev->mt76.chainmask & 0xf; 522f832898dSLorenzo Bianconi 52374ff4539SStanislaw Gruszka status->encoding = RX_ENC_VHT; 52474ff4539SStanislaw Gruszka status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 525f832898dSLorenzo Bianconi status->nss = min_t(u8, n_rxstream, 526f832898dSLorenzo Bianconi FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1); 52774ff4539SStanislaw Gruszka break; 528f832898dSLorenzo Bianconi } 52974ff4539SStanislaw Gruszka default: 53074ff4539SStanislaw Gruszka return -EINVAL; 53174ff4539SStanislaw Gruszka } 53274ff4539SStanislaw Gruszka 53374ff4539SStanislaw Gruszka if (rate & MT_RXWI_RATE_LDPC) 53474ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_LDPC; 53574ff4539SStanislaw Gruszka 53674ff4539SStanislaw Gruszka if (rate & MT_RXWI_RATE_SGI) 53774ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 53874ff4539SStanislaw Gruszka 53974ff4539SStanislaw Gruszka if (rate & MT_RXWI_RATE_STBC) 54074ff4539SStanislaw Gruszka status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 54174ff4539SStanislaw Gruszka 54274ff4539SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 54374ff4539SStanislaw Gruszka case MT_PHY_BW_20: 54474ff4539SStanislaw Gruszka break; 54574ff4539SStanislaw Gruszka case MT_PHY_BW_40: 54674ff4539SStanislaw Gruszka status->bw = RATE_INFO_BW_40; 54774ff4539SStanislaw Gruszka break; 54874ff4539SStanislaw Gruszka case MT_PHY_BW_80: 54974ff4539SStanislaw Gruszka status->bw = RATE_INFO_BW_80; 55074ff4539SStanislaw Gruszka break; 55174ff4539SStanislaw Gruszka default: 55274ff4539SStanislaw Gruszka break; 55374ff4539SStanislaw Gruszka } 55474ff4539SStanislaw Gruszka 55574ff4539SStanislaw Gruszka return 0; 55674ff4539SStanislaw Gruszka } 55789a8607cSLorenzo Bianconi 5580b2d27e5SStanislaw Gruszka void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr) 55989a8607cSLorenzo Bianconi { 5600b2d27e5SStanislaw Gruszka static const u8 null_addr[ETH_ALEN] = {}; 5610b2d27e5SStanislaw Gruszka int i; 5620b2d27e5SStanislaw Gruszka 5638d66af49SLorenzo Bianconi ether_addr_copy(dev->mt76.macaddr, addr); 56489a8607cSLorenzo Bianconi 5658d66af49SLorenzo Bianconi if (!is_valid_ether_addr(dev->mt76.macaddr)) { 5668d66af49SLorenzo Bianconi eth_random_addr(dev->mt76.macaddr); 5678d66af49SLorenzo Bianconi dev_info(dev->mt76.dev, 56889a8607cSLorenzo Bianconi "Invalid MAC address, using random address %pM\n", 5698d66af49SLorenzo Bianconi dev->mt76.macaddr); 57089a8607cSLorenzo Bianconi } 57189a8607cSLorenzo Bianconi 5728d66af49SLorenzo Bianconi mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr)); 5738d66af49SLorenzo Bianconi mt76_wr(dev, MT_MAC_ADDR_DW1, 5748d66af49SLorenzo Bianconi get_unaligned_le16(dev->mt76.macaddr + 4) | 57589a8607cSLorenzo Bianconi FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 5760b2d27e5SStanislaw Gruszka 5770b2d27e5SStanislaw Gruszka mt76_wr(dev, MT_MAC_BSSID_DW0, 5780b2d27e5SStanislaw Gruszka get_unaligned_le32(dev->mt76.macaddr)); 5790b2d27e5SStanislaw Gruszka mt76_wr(dev, MT_MAC_BSSID_DW1, 5800b2d27e5SStanislaw Gruszka get_unaligned_le16(dev->mt76.macaddr + 4) | 5810b2d27e5SStanislaw Gruszka FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 APs + 8 STAs */ 5820b2d27e5SStanislaw Gruszka MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT); 5830b2d27e5SStanislaw Gruszka 5840b2d27e5SStanislaw Gruszka for (i = 0; i < 16; i++) 5850b2d27e5SStanislaw Gruszka mt76x02_mac_set_bssid(dev, i, null_addr); 58689a8607cSLorenzo Bianconi } 58789a8607cSLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 588d9f8934eSLorenzo Bianconi 589d9f8934eSLorenzo Bianconi static int 590d9f8934eSLorenzo Bianconi mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 591d9f8934eSLorenzo Bianconi { 592d9f8934eSLorenzo Bianconi struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 593d9f8934eSLorenzo Bianconi 594d9f8934eSLorenzo Bianconi rssi += cal->rssi_offset[chain]; 595d9f8934eSLorenzo Bianconi rssi -= cal->lna_gain; 596d9f8934eSLorenzo Bianconi 597d9f8934eSLorenzo Bianconi return rssi; 598d9f8934eSLorenzo Bianconi } 599d9f8934eSLorenzo Bianconi 600d9f8934eSLorenzo Bianconi int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 601d9f8934eSLorenzo Bianconi void *rxi) 602d9f8934eSLorenzo Bianconi { 603d9f8934eSLorenzo Bianconi struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb; 604d9f8934eSLorenzo Bianconi struct mt76x02_rxwi *rxwi = rxi; 605d9f8934eSLorenzo Bianconi struct mt76x02_sta *sta; 606d9f8934eSLorenzo Bianconi u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 607d9f8934eSLorenzo Bianconi u32 ctl = le32_to_cpu(rxwi->ctl); 608d9f8934eSLorenzo Bianconi u16 rate = le16_to_cpu(rxwi->rate); 609d9f8934eSLorenzo Bianconi u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 610d9f8934eSLorenzo Bianconi bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 611d9f8934eSLorenzo Bianconi int i, pad_len = 0, nstreams = dev->mt76.chainmask & 0xf; 612d9f8934eSLorenzo Bianconi s8 signal; 613d9f8934eSLorenzo Bianconi u8 pn_len; 614d9f8934eSLorenzo Bianconi u8 wcid; 615d9f8934eSLorenzo Bianconi int len; 616d9f8934eSLorenzo Bianconi 617d9f8934eSLorenzo Bianconi if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 618d9f8934eSLorenzo Bianconi return -EINVAL; 619d9f8934eSLorenzo Bianconi 620d9f8934eSLorenzo Bianconi if (rxinfo & MT_RXINFO_L2PAD) 621d9f8934eSLorenzo Bianconi pad_len += 2; 622d9f8934eSLorenzo Bianconi 623d9f8934eSLorenzo Bianconi if (rxinfo & MT_RXINFO_DECRYPT) { 624d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_DECRYPTED; 625d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_MMIC_STRIPPED; 626d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_MIC_STRIPPED; 627d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_IV_STRIPPED; 628d9f8934eSLorenzo Bianconi } 629d9f8934eSLorenzo Bianconi 630d9f8934eSLorenzo Bianconi wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 631d9f8934eSLorenzo Bianconi sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 632d9f8934eSLorenzo Bianconi status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 633d9f8934eSLorenzo Bianconi 634d9f8934eSLorenzo Bianconi len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 635d9f8934eSLorenzo Bianconi pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 636d9f8934eSLorenzo Bianconi if (pn_len) { 637d9f8934eSLorenzo Bianconi int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 638d9f8934eSLorenzo Bianconi u8 *data = skb->data + offset; 639d9f8934eSLorenzo Bianconi 640d9f8934eSLorenzo Bianconi status->iv[0] = data[7]; 641d9f8934eSLorenzo Bianconi status->iv[1] = data[6]; 642d9f8934eSLorenzo Bianconi status->iv[2] = data[5]; 643d9f8934eSLorenzo Bianconi status->iv[3] = data[4]; 644d9f8934eSLorenzo Bianconi status->iv[4] = data[1]; 645d9f8934eSLorenzo Bianconi status->iv[5] = data[0]; 646d9f8934eSLorenzo Bianconi 647d9f8934eSLorenzo Bianconi /* 648d9f8934eSLorenzo Bianconi * Driver CCMP validation can't deal with fragments. 649d9f8934eSLorenzo Bianconi * Let mac80211 take care of it. 650d9f8934eSLorenzo Bianconi */ 651d9f8934eSLorenzo Bianconi if (rxinfo & MT_RXINFO_FRAG) { 652d9f8934eSLorenzo Bianconi status->flag &= ~RX_FLAG_IV_STRIPPED; 653d9f8934eSLorenzo Bianconi } else { 654d9f8934eSLorenzo Bianconi pad_len += pn_len << 2; 655d9f8934eSLorenzo Bianconi len -= pn_len << 2; 656d9f8934eSLorenzo Bianconi } 657d9f8934eSLorenzo Bianconi } 658d9f8934eSLorenzo Bianconi 659d9f8934eSLorenzo Bianconi mt76x02_remove_hdr_pad(skb, pad_len); 660d9f8934eSLorenzo Bianconi 661d9f8934eSLorenzo Bianconi if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 662d9f8934eSLorenzo Bianconi status->aggr = true; 663d9f8934eSLorenzo Bianconi 664d9f8934eSLorenzo Bianconi if (WARN_ON_ONCE(len > skb->len)) 665d9f8934eSLorenzo Bianconi return -EINVAL; 666d9f8934eSLorenzo Bianconi 667d9f8934eSLorenzo Bianconi pskb_trim(skb, len); 668d9f8934eSLorenzo Bianconi 669d9f8934eSLorenzo Bianconi status->chains = BIT(0); 670d9f8934eSLorenzo Bianconi signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 67168f7030fSFelix Fietkau for (i = 0; i < nstreams; i++) { 672d9f8934eSLorenzo Bianconi status->chains |= BIT(i); 673d9f8934eSLorenzo Bianconi status->chain_signal[i] = mt76x02_mac_get_rssi(dev, 674d9f8934eSLorenzo Bianconi rxwi->rssi[i], 675d9f8934eSLorenzo Bianconi i); 676d9f8934eSLorenzo Bianconi signal = max_t(s8, signal, status->chain_signal[i]); 677d9f8934eSLorenzo Bianconi } 678d9f8934eSLorenzo Bianconi status->signal = signal; 679d9f8934eSLorenzo Bianconi status->freq = dev->mt76.chandef.chan->center_freq; 680d9f8934eSLorenzo Bianconi status->band = dev->mt76.chandef.chan->band; 681d9f8934eSLorenzo Bianconi 682d9f8934eSLorenzo Bianconi status->tid = FIELD_GET(MT_RXWI_TID, tid_sn); 683d9f8934eSLorenzo Bianconi status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 684d9f8934eSLorenzo Bianconi 685f832898dSLorenzo Bianconi return mt76x02_mac_process_rate(dev, status, rate); 686d9f8934eSLorenzo Bianconi } 6873e2342edSLorenzo Bianconi 6883e2342edSLorenzo Bianconi void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 6893e2342edSLorenzo Bianconi { 6903e2342edSLorenzo Bianconi struct mt76x02_tx_status stat = {}; 6913e2342edSLorenzo Bianconi unsigned long flags; 6923e2342edSLorenzo Bianconi u8 update = 1; 6933e2342edSLorenzo Bianconi bool ret; 6943e2342edSLorenzo Bianconi 6953e2342edSLorenzo Bianconi if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 6963e2342edSLorenzo Bianconi return; 6973e2342edSLorenzo Bianconi 6983e2342edSLorenzo Bianconi trace_mac_txstat_poll(dev); 6993e2342edSLorenzo Bianconi 7003e2342edSLorenzo Bianconi while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 7013e2342edSLorenzo Bianconi spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 7028d66af49SLorenzo Bianconi ret = mt76x02_mac_load_tx_status(dev, &stat); 7033e2342edSLorenzo Bianconi spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 7043e2342edSLorenzo Bianconi 7053e2342edSLorenzo Bianconi if (!ret) 7063e2342edSLorenzo Bianconi break; 7073e2342edSLorenzo Bianconi 7083e2342edSLorenzo Bianconi if (!irq) { 7098d66af49SLorenzo Bianconi mt76x02_send_tx_status(dev, &stat, &update); 7103e2342edSLorenzo Bianconi continue; 7113e2342edSLorenzo Bianconi } 7123e2342edSLorenzo Bianconi 7133e2342edSLorenzo Bianconi kfifo_put(&dev->txstatus_fifo, stat); 7143e2342edSLorenzo Bianconi } 7153e2342edSLorenzo Bianconi } 716466495b1SLorenzo Bianconi 717466495b1SLorenzo Bianconi void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 718466495b1SLorenzo Bianconi struct mt76_queue_entry *e, bool flush) 719466495b1SLorenzo Bianconi { 720466495b1SLorenzo Bianconi struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 72188046b2cSFelix Fietkau struct mt76x02_txwi *txwi; 722466495b1SLorenzo Bianconi 72388046b2cSFelix Fietkau if (!e->txwi) { 724466495b1SLorenzo Bianconi dev_kfree_skb_any(e->skb); 72588046b2cSFelix Fietkau return; 72688046b2cSFelix Fietkau } 72788046b2cSFelix Fietkau 72888046b2cSFelix Fietkau mt76x02_mac_poll_tx_status(dev, false); 72988046b2cSFelix Fietkau 73088046b2cSFelix Fietkau txwi = (struct mt76x02_txwi *) &e->txwi->txwi; 73188046b2cSFelix Fietkau trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid); 73288046b2cSFelix Fietkau 73388046b2cSFelix Fietkau mt76_tx_complete_skb(mdev, e->skb); 734466495b1SLorenzo Bianconi } 735466495b1SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 73662503186SLorenzo Bianconi 73720ce270eSStanislaw Gruszka void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val) 738317ed42bSLorenzo Bianconi { 739317ed42bSLorenzo Bianconi u32 data = 0; 740317ed42bSLorenzo Bianconi 741317ed42bSLorenzo Bianconi if (val != ~0) 742317ed42bSLorenzo Bianconi data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) | 743317ed42bSLorenzo Bianconi MT_PROT_CFG_RTS_THRESH; 744317ed42bSLorenzo Bianconi 745317ed42bSLorenzo Bianconi mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); 746317ed42bSLorenzo Bianconi 747317ed42bSLorenzo Bianconi mt76_rmw(dev, MT_CCK_PROT_CFG, 748317ed42bSLorenzo Bianconi MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 749317ed42bSLorenzo Bianconi mt76_rmw(dev, MT_OFDM_PROT_CFG, 750317ed42bSLorenzo Bianconi MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 751317ed42bSLorenzo Bianconi } 752317ed42bSLorenzo Bianconi 75326a7b547SStanislaw Gruszka void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot, 75426a7b547SStanislaw Gruszka int ht_mode) 75526a7b547SStanislaw Gruszka { 75626a7b547SStanislaw Gruszka int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION; 75726a7b547SStanislaw Gruszka bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 75826a7b547SStanislaw Gruszka u32 prot[6]; 75926a7b547SStanislaw Gruszka u32 vht_prot[3]; 76026a7b547SStanislaw Gruszka int i; 76126a7b547SStanislaw Gruszka u16 rts_thr; 76226a7b547SStanislaw Gruszka 76326a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(prot); i++) { 76426a7b547SStanislaw Gruszka prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4); 76526a7b547SStanislaw Gruszka prot[i] &= ~MT_PROT_CFG_CTRL; 76626a7b547SStanislaw Gruszka if (i >= 2) 76726a7b547SStanislaw Gruszka prot[i] &= ~MT_PROT_CFG_RATE; 76826a7b547SStanislaw Gruszka } 76926a7b547SStanislaw Gruszka 77026a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(vht_prot); i++) { 77126a7b547SStanislaw Gruszka vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4); 77226a7b547SStanislaw Gruszka vht_prot[i] &= ~(MT_PROT_CFG_CTRL | MT_PROT_CFG_RATE); 77326a7b547SStanislaw Gruszka } 77426a7b547SStanislaw Gruszka 77526a7b547SStanislaw Gruszka rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH); 77626a7b547SStanislaw Gruszka 77726a7b547SStanislaw Gruszka if (rts_thr != 0xffff) 77826a7b547SStanislaw Gruszka prot[0] |= MT_PROT_CTRL_RTS_CTS; 77926a7b547SStanislaw Gruszka 78026a7b547SStanislaw Gruszka if (legacy_prot) { 78126a7b547SStanislaw Gruszka prot[1] |= MT_PROT_CTRL_CTS2SELF; 78226a7b547SStanislaw Gruszka 78326a7b547SStanislaw Gruszka prot[2] |= MT_PROT_RATE_CCK_11; 78426a7b547SStanislaw Gruszka prot[3] |= MT_PROT_RATE_CCK_11; 78526a7b547SStanislaw Gruszka prot[4] |= MT_PROT_RATE_CCK_11; 78626a7b547SStanislaw Gruszka prot[5] |= MT_PROT_RATE_CCK_11; 78726a7b547SStanislaw Gruszka 78826a7b547SStanislaw Gruszka vht_prot[0] |= MT_PROT_RATE_CCK_11; 78926a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_RATE_CCK_11; 79026a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_RATE_CCK_11; 79126a7b547SStanislaw Gruszka } else { 79226a7b547SStanislaw Gruszka if (rts_thr != 0xffff) 79326a7b547SStanislaw Gruszka prot[1] |= MT_PROT_CTRL_RTS_CTS; 79426a7b547SStanislaw Gruszka 79526a7b547SStanislaw Gruszka prot[2] |= MT_PROT_RATE_OFDM_24; 79626a7b547SStanislaw Gruszka prot[3] |= MT_PROT_RATE_DUP_OFDM_24; 79726a7b547SStanislaw Gruszka prot[4] |= MT_PROT_RATE_OFDM_24; 79826a7b547SStanislaw Gruszka prot[5] |= MT_PROT_RATE_DUP_OFDM_24; 79926a7b547SStanislaw Gruszka 80026a7b547SStanislaw Gruszka vht_prot[0] |= MT_PROT_RATE_OFDM_24; 80126a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_RATE_DUP_OFDM_24; 80226a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_RATE_SGI_OFDM_24; 80326a7b547SStanislaw Gruszka } 80426a7b547SStanislaw Gruszka 80526a7b547SStanislaw Gruszka switch (mode) { 80626a7b547SStanislaw Gruszka case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 80726a7b547SStanislaw Gruszka case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 80826a7b547SStanislaw Gruszka prot[2] |= MT_PROT_CTRL_RTS_CTS; 80926a7b547SStanislaw Gruszka prot[3] |= MT_PROT_CTRL_RTS_CTS; 81026a7b547SStanislaw Gruszka prot[4] |= MT_PROT_CTRL_RTS_CTS; 81126a7b547SStanislaw Gruszka prot[5] |= MT_PROT_CTRL_RTS_CTS; 81226a7b547SStanislaw Gruszka vht_prot[0] |= MT_PROT_CTRL_RTS_CTS; 81326a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 81426a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 81526a7b547SStanislaw Gruszka break; 81626a7b547SStanislaw Gruszka case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 81726a7b547SStanislaw Gruszka prot[3] |= MT_PROT_CTRL_RTS_CTS; 81826a7b547SStanislaw Gruszka prot[5] |= MT_PROT_CTRL_RTS_CTS; 81926a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 82026a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 82126a7b547SStanislaw Gruszka break; 82226a7b547SStanislaw Gruszka } 82326a7b547SStanislaw Gruszka 82426a7b547SStanislaw Gruszka if (non_gf) { 82526a7b547SStanislaw Gruszka prot[4] |= MT_PROT_CTRL_RTS_CTS; 82626a7b547SStanislaw Gruszka prot[5] |= MT_PROT_CTRL_RTS_CTS; 82726a7b547SStanislaw Gruszka } 82826a7b547SStanislaw Gruszka 82926a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(prot); i++) 83026a7b547SStanislaw Gruszka mt76_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]); 83126a7b547SStanislaw Gruszka 83226a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(vht_prot); i++) 83326a7b547SStanislaw Gruszka mt76_wr(dev, MT_TX_PROT_CFG6 + i * 4, vht_prot[i]); 83426a7b547SStanislaw Gruszka } 83526a7b547SStanislaw Gruszka 83662503186SLorenzo Bianconi void mt76x02_update_channel(struct mt76_dev *mdev) 83762503186SLorenzo Bianconi { 83862503186SLorenzo Bianconi struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 83962503186SLorenzo Bianconi struct mt76_channel_state *state; 84062503186SLorenzo Bianconi u32 active, busy; 84162503186SLorenzo Bianconi 84262503186SLorenzo Bianconi state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan); 84362503186SLorenzo Bianconi 84462503186SLorenzo Bianconi busy = mt76_rr(dev, MT_CH_BUSY); 84562503186SLorenzo Bianconi active = busy + mt76_rr(dev, MT_CH_IDLE); 84662503186SLorenzo Bianconi 84762503186SLorenzo Bianconi spin_lock_bh(&dev->mt76.cc_lock); 84862503186SLorenzo Bianconi state->cc_busy += busy; 84962503186SLorenzo Bianconi state->cc_active += active; 85062503186SLorenzo Bianconi spin_unlock_bh(&dev->mt76.cc_lock); 85162503186SLorenzo Bianconi } 85262503186SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_update_channel); 8537dd73588SLorenzo Bianconi 85473556561SLorenzo Bianconi static void mt76x02_check_mac_err(struct mt76x02_dev *dev) 85573556561SLorenzo Bianconi { 85673556561SLorenzo Bianconi u32 val = mt76_rr(dev, 0x10f4); 85773556561SLorenzo Bianconi 85873556561SLorenzo Bianconi if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) 85973556561SLorenzo Bianconi return; 86073556561SLorenzo Bianconi 86173556561SLorenzo Bianconi dev_err(dev->mt76.dev, "mac specific condition occurred\n"); 86273556561SLorenzo Bianconi 86373556561SLorenzo Bianconi mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); 86473556561SLorenzo Bianconi udelay(10); 865374eb1b5SLorenzo Bianconi mt76_wr(dev, MT_MAC_SYS_CTRL, 86673556561SLorenzo Bianconi MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 86773556561SLorenzo Bianconi } 86873556561SLorenzo Bianconi 869f82ce8d9SLorenzo Bianconi static void 870f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(struct mt76x02_dev *dev, bool enable) 871f82ce8d9SLorenzo Bianconi { 872f82ce8d9SLorenzo Bianconi if (enable) { 873f82ce8d9SLorenzo Bianconi u32 data; 874f82ce8d9SLorenzo Bianconi 875f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 876f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 877f82ce8d9SLorenzo Bianconi /* enable pa-lna */ 878f82ce8d9SLorenzo Bianconi data = mt76_rr(dev, MT_TX_PIN_CFG); 879f82ce8d9SLorenzo Bianconi data |= MT_TX_PIN_CFG_TXANT | 880f82ce8d9SLorenzo Bianconi MT_TX_PIN_CFG_RXANT | 881f82ce8d9SLorenzo Bianconi MT_TX_PIN_RFTR_EN | 882f82ce8d9SLorenzo Bianconi MT_TX_PIN_TRSW_EN; 883f82ce8d9SLorenzo Bianconi mt76_wr(dev, MT_TX_PIN_CFG, data); 884f82ce8d9SLorenzo Bianconi } else { 885f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 886f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 887f82ce8d9SLorenzo Bianconi /* disable pa-lna */ 888f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT); 889f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT); 890f82ce8d9SLorenzo Bianconi } 891f82ce8d9SLorenzo Bianconi dev->ed_tx_blocked = !enable; 892f82ce8d9SLorenzo Bianconi } 893f82ce8d9SLorenzo Bianconi 89420c06572SFelix Fietkau void mt76x02_edcca_init(struct mt76x02_dev *dev, bool enable) 895f82ce8d9SLorenzo Bianconi { 896f82ce8d9SLorenzo Bianconi dev->ed_trigger = 0; 897f82ce8d9SLorenzo Bianconi dev->ed_silent = 0; 898f82ce8d9SLorenzo Bianconi 89920c06572SFelix Fietkau if (dev->ed_monitor && enable) { 900f82ce8d9SLorenzo Bianconi struct ieee80211_channel *chan = dev->mt76.chandef.chan; 901f82ce8d9SLorenzo Bianconi u8 ed_th = chan->band == NL80211_BAND_5GHZ ? 0x0e : 0x20; 902f82ce8d9SLorenzo Bianconi 903f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 904f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 905f82ce8d9SLorenzo Bianconi mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0), 906f82ce8d9SLorenzo Bianconi ed_th << 8 | ed_th); 907f82ce8d9SLorenzo Bianconi if (!is_mt76x2(dev)) 908f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_TXOP_HLDR_ET, 909f82ce8d9SLorenzo Bianconi MT_TXOP_HLDR_TX40M_BLK_EN); 910f82ce8d9SLorenzo Bianconi } else { 911f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 912f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 913f82ce8d9SLorenzo Bianconi if (is_mt76x2(dev)) { 914f82ce8d9SLorenzo Bianconi mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); 915f82ce8d9SLorenzo Bianconi } else { 916f82ce8d9SLorenzo Bianconi mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464); 917f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TXOP_HLDR_ET, 918f82ce8d9SLorenzo Bianconi MT_TXOP_HLDR_TX40M_BLK_EN); 919f82ce8d9SLorenzo Bianconi } 920f82ce8d9SLorenzo Bianconi } 921f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(dev, true); 922c15b7cefSFelix Fietkau 923c15b7cefSFelix Fietkau /* clear previous CCA timer value */ 924c15b7cefSFelix Fietkau mt76_rr(dev, MT_ED_CCA_TIMER); 925ccdaf7b4SFelix Fietkau dev->ed_time = ktime_get_boottime(); 926f82ce8d9SLorenzo Bianconi } 927f82ce8d9SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_edcca_init); 928f82ce8d9SLorenzo Bianconi 929*f1906fb2SFelix Fietkau #define MT_EDCCA_TH 92 930f82ce8d9SLorenzo Bianconi #define MT_EDCCA_BLOCK_TH 2 931f82ce8d9SLorenzo Bianconi static void mt76x02_edcca_check(struct mt76x02_dev *dev) 932f82ce8d9SLorenzo Bianconi { 933ccdaf7b4SFelix Fietkau ktime_t cur_time; 934ccdaf7b4SFelix Fietkau u32 active, val, busy; 935f82ce8d9SLorenzo Bianconi 936ccdaf7b4SFelix Fietkau cur_time = ktime_get_boottime(); 937f82ce8d9SLorenzo Bianconi val = mt76_rr(dev, MT_ED_CCA_TIMER); 938ccdaf7b4SFelix Fietkau 939ccdaf7b4SFelix Fietkau active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 940ccdaf7b4SFelix Fietkau dev->ed_time = cur_time; 941ccdaf7b4SFelix Fietkau 942ccdaf7b4SFelix Fietkau busy = (val * 100) / active; 943f82ce8d9SLorenzo Bianconi busy = min_t(u32, busy, 100); 944f82ce8d9SLorenzo Bianconi 945f82ce8d9SLorenzo Bianconi if (busy > MT_EDCCA_TH) { 946f82ce8d9SLorenzo Bianconi dev->ed_trigger++; 947f82ce8d9SLorenzo Bianconi dev->ed_silent = 0; 948f82ce8d9SLorenzo Bianconi } else { 949f82ce8d9SLorenzo Bianconi dev->ed_silent++; 950f82ce8d9SLorenzo Bianconi dev->ed_trigger = 0; 951f82ce8d9SLorenzo Bianconi } 952f82ce8d9SLorenzo Bianconi 953f82ce8d9SLorenzo Bianconi if (dev->ed_trigger > MT_EDCCA_BLOCK_TH && 954f82ce8d9SLorenzo Bianconi !dev->ed_tx_blocked) 955f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(dev, false); 956f82ce8d9SLorenzo Bianconi else if (dev->ed_silent > MT_EDCCA_BLOCK_TH && 957f82ce8d9SLorenzo Bianconi dev->ed_tx_blocked) 958f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(dev, true); 959f82ce8d9SLorenzo Bianconi } 960f82ce8d9SLorenzo Bianconi 9617dd73588SLorenzo Bianconi void mt76x02_mac_work(struct work_struct *work) 9627dd73588SLorenzo Bianconi { 9637dd73588SLorenzo Bianconi struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 9647dd73588SLorenzo Bianconi mac_work.work); 9657dd73588SLorenzo Bianconi int i, idx; 9667dd73588SLorenzo Bianconi 9674989338eSLorenzo Bianconi mutex_lock(&dev->mt76.mutex); 9684989338eSLorenzo Bianconi 9697dd73588SLorenzo Bianconi mt76x02_update_channel(&dev->mt76); 9707dd73588SLorenzo Bianconi for (i = 0, idx = 0; i < 16; i++) { 9717dd73588SLorenzo Bianconi u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 9727dd73588SLorenzo Bianconi 9737dd73588SLorenzo Bianconi dev->aggr_stats[idx++] += val & 0xffff; 9747dd73588SLorenzo Bianconi dev->aggr_stats[idx++] += val >> 16; 9757dd73588SLorenzo Bianconi } 9767dd73588SLorenzo Bianconi 97773556561SLorenzo Bianconi if (!dev->beacon_mask) 97873556561SLorenzo Bianconi mt76x02_check_mac_err(dev); 97973556561SLorenzo Bianconi 980f82ce8d9SLorenzo Bianconi if (dev->ed_monitor) 981f82ce8d9SLorenzo Bianconi mt76x02_edcca_check(dev); 982f82ce8d9SLorenzo Bianconi 9834989338eSLorenzo Bianconi mutex_unlock(&dev->mt76.mutex); 9844989338eSLorenzo Bianconi 98579d1c94cSFelix Fietkau mt76_tx_status_check(&dev->mt76, NULL, false); 98688046b2cSFelix Fietkau 9877dd73588SLorenzo Bianconi ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work, 9882e405024SFelix Fietkau MT_MAC_WORK_INTERVAL); 9897dd73588SLorenzo Bianconi } 990dc33b251SLorenzo Bianconi 991dc33b251SLorenzo Bianconi void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr) 992dc33b251SLorenzo Bianconi { 993dc33b251SLorenzo Bianconi idx &= 7; 994dc33b251SLorenzo Bianconi mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr)); 995dc33b251SLorenzo Bianconi mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR, 996dc33b251SLorenzo Bianconi get_unaligned_le16(addr + 4)); 997dc33b251SLorenzo Bianconi } 998dc33b251SLorenzo Bianconi 999dc33b251SLorenzo Bianconi static int 1000dc33b251SLorenzo Bianconi mt76x02_write_beacon(struct mt76x02_dev *dev, int offset, struct sk_buff *skb) 1001dc33b251SLorenzo Bianconi { 1002dc33b251SLorenzo Bianconi int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 1003dc33b251SLorenzo Bianconi struct mt76x02_txwi txwi; 1004dc33b251SLorenzo Bianconi 1005dc33b251SLorenzo Bianconi if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi))) 1006dc33b251SLorenzo Bianconi return -ENOSPC; 1007dc33b251SLorenzo Bianconi 1008dc33b251SLorenzo Bianconi mt76x02_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len); 1009dc33b251SLorenzo Bianconi 1010dc33b251SLorenzo Bianconi mt76_wr_copy(dev, offset, &txwi, sizeof(txwi)); 1011dc33b251SLorenzo Bianconi offset += sizeof(txwi); 1012dc33b251SLorenzo Bianconi 1013dc33b251SLorenzo Bianconi mt76_wr_copy(dev, offset, skb->data, skb->len); 1014dc33b251SLorenzo Bianconi return 0; 1015dc33b251SLorenzo Bianconi } 1016dc33b251SLorenzo Bianconi 1017dc33b251SLorenzo Bianconi static int 1018dc33b251SLorenzo Bianconi __mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 bcn_idx, 1019dc33b251SLorenzo Bianconi struct sk_buff *skb) 1020dc33b251SLorenzo Bianconi { 1021dc33b251SLorenzo Bianconi int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 1022dc33b251SLorenzo Bianconi int beacon_addr = mt76x02_beacon_offsets[bcn_idx]; 1023dc33b251SLorenzo Bianconi int ret = 0; 1024dc33b251SLorenzo Bianconi int i; 1025dc33b251SLorenzo Bianconi 1026dc33b251SLorenzo Bianconi /* Prevent corrupt transmissions during update */ 1027dc33b251SLorenzo Bianconi mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx)); 1028dc33b251SLorenzo Bianconi 1029dc33b251SLorenzo Bianconi if (skb) { 1030dc33b251SLorenzo Bianconi ret = mt76x02_write_beacon(dev, beacon_addr, skb); 1031dc33b251SLorenzo Bianconi if (!ret) 1032dc33b251SLorenzo Bianconi dev->beacon_data_mask |= BIT(bcn_idx); 1033dc33b251SLorenzo Bianconi } else { 1034dc33b251SLorenzo Bianconi dev->beacon_data_mask &= ~BIT(bcn_idx); 1035dc33b251SLorenzo Bianconi for (i = 0; i < beacon_len; i += 4) 1036dc33b251SLorenzo Bianconi mt76_wr(dev, beacon_addr + i, 0); 1037dc33b251SLorenzo Bianconi } 1038dc33b251SLorenzo Bianconi 1039dc33b251SLorenzo Bianconi mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask); 1040dc33b251SLorenzo Bianconi 1041dc33b251SLorenzo Bianconi return ret; 1042dc33b251SLorenzo Bianconi } 1043dc33b251SLorenzo Bianconi 1044dc33b251SLorenzo Bianconi int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx, 1045dc33b251SLorenzo Bianconi struct sk_buff *skb) 1046dc33b251SLorenzo Bianconi { 1047dc33b251SLorenzo Bianconi bool force_update = false; 1048dc33b251SLorenzo Bianconi int bcn_idx = 0; 1049dc33b251SLorenzo Bianconi int i; 1050dc33b251SLorenzo Bianconi 1051dc33b251SLorenzo Bianconi for (i = 0; i < ARRAY_SIZE(dev->beacons); i++) { 1052dc33b251SLorenzo Bianconi if (vif_idx == i) { 1053dc33b251SLorenzo Bianconi force_update = !!dev->beacons[i] ^ !!skb; 1054dc33b251SLorenzo Bianconi 1055dc33b251SLorenzo Bianconi if (dev->beacons[i]) 1056dc33b251SLorenzo Bianconi dev_kfree_skb(dev->beacons[i]); 1057dc33b251SLorenzo Bianconi 1058dc33b251SLorenzo Bianconi dev->beacons[i] = skb; 1059dc33b251SLorenzo Bianconi __mt76x02_mac_set_beacon(dev, bcn_idx, skb); 1060dc33b251SLorenzo Bianconi } else if (force_update && dev->beacons[i]) { 1061dc33b251SLorenzo Bianconi __mt76x02_mac_set_beacon(dev, bcn_idx, 1062dc33b251SLorenzo Bianconi dev->beacons[i]); 1063dc33b251SLorenzo Bianconi } 1064dc33b251SLorenzo Bianconi 1065dc33b251SLorenzo Bianconi bcn_idx += !!dev->beacons[i]; 1066dc33b251SLorenzo Bianconi } 1067dc33b251SLorenzo Bianconi 1068dc33b251SLorenzo Bianconi for (i = bcn_idx; i < ARRAY_SIZE(dev->beacons); i++) { 1069dc33b251SLorenzo Bianconi if (!(dev->beacon_data_mask & BIT(i))) 1070dc33b251SLorenzo Bianconi break; 1071dc33b251SLorenzo Bianconi 1072dc33b251SLorenzo Bianconi __mt76x02_mac_set_beacon(dev, i, NULL); 1073dc33b251SLorenzo Bianconi } 1074dc33b251SLorenzo Bianconi 1075dc33b251SLorenzo Bianconi mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 1076dc33b251SLorenzo Bianconi bcn_idx - 1); 1077dc33b251SLorenzo Bianconi return 0; 1078dc33b251SLorenzo Bianconi } 1079dc33b251SLorenzo Bianconi 1080dbb2b22bSStanislaw Gruszka static void 1081dbb2b22bSStanislaw Gruszka __mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, u8 vif_idx, 1082dbb2b22bSStanislaw Gruszka bool val, struct sk_buff *skb) 1083dc33b251SLorenzo Bianconi { 1084dc33b251SLorenzo Bianconi u8 old_mask = dev->beacon_mask; 1085dc33b251SLorenzo Bianconi bool en; 1086dc33b251SLorenzo Bianconi u32 reg; 1087dc33b251SLorenzo Bianconi 1088dc33b251SLorenzo Bianconi if (val) { 1089dc33b251SLorenzo Bianconi dev->beacon_mask |= BIT(vif_idx); 1090dbb2b22bSStanislaw Gruszka if (skb) 1091dbb2b22bSStanislaw Gruszka mt76x02_mac_set_beacon(dev, vif_idx, skb); 1092dc33b251SLorenzo Bianconi } else { 1093dc33b251SLorenzo Bianconi dev->beacon_mask &= ~BIT(vif_idx); 1094dc33b251SLorenzo Bianconi mt76x02_mac_set_beacon(dev, vif_idx, NULL); 1095dc33b251SLorenzo Bianconi } 1096dc33b251SLorenzo Bianconi 1097dc33b251SLorenzo Bianconi if (!!old_mask == !!dev->beacon_mask) 1098dc33b251SLorenzo Bianconi return; 1099dc33b251SLorenzo Bianconi 1100dc33b251SLorenzo Bianconi en = dev->beacon_mask; 1101dc33b251SLorenzo Bianconi 1102dc33b251SLorenzo Bianconi reg = MT_BEACON_TIME_CFG_BEACON_TX | 1103dc33b251SLorenzo Bianconi MT_BEACON_TIME_CFG_TBTT_EN | 1104dc33b251SLorenzo Bianconi MT_BEACON_TIME_CFG_TIMER_EN; 1105dc33b251SLorenzo Bianconi mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en); 1106dc33b251SLorenzo Bianconi 1107dbb2b22bSStanislaw Gruszka if (mt76_is_usb(dev)) 1108dbb2b22bSStanislaw Gruszka return; 1109dbb2b22bSStanislaw Gruszka 1110dbb2b22bSStanislaw Gruszka mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); 1111dc33b251SLorenzo Bianconi if (en) 1112dc33b251SLorenzo Bianconi mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1113dc33b251SLorenzo Bianconi else 1114dc33b251SLorenzo Bianconi mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1115dc33b251SLorenzo Bianconi } 1116dbb2b22bSStanislaw Gruszka 1117dbb2b22bSStanislaw Gruszka void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, 1118dbb2b22bSStanislaw Gruszka struct ieee80211_vif *vif, bool val) 1119dbb2b22bSStanislaw Gruszka { 1120dbb2b22bSStanislaw Gruszka u8 vif_idx = ((struct mt76x02_vif *)vif->drv_priv)->idx; 1121dbb2b22bSStanislaw Gruszka struct sk_buff *skb = NULL; 1122dbb2b22bSStanislaw Gruszka 1123dbb2b22bSStanislaw Gruszka if (mt76_is_mmio(dev)) 1124dbb2b22bSStanislaw Gruszka tasklet_disable(&dev->pre_tbtt_tasklet); 1125dbb2b22bSStanislaw Gruszka else if (val) 1126dbb2b22bSStanislaw Gruszka skb = ieee80211_beacon_get(mt76_hw(dev), vif); 1127dbb2b22bSStanislaw Gruszka 1128dbb2b22bSStanislaw Gruszka __mt76x02_mac_set_beacon_enable(dev, vif_idx, val, skb); 1129dbb2b22bSStanislaw Gruszka 1130dbb2b22bSStanislaw Gruszka if (mt76_is_mmio(dev)) 1131dbb2b22bSStanislaw Gruszka tasklet_enable(&dev->pre_tbtt_tasklet); 1132dbb2b22bSStanislaw Gruszka } 1133