10e3d6777SRyder Lee // SPDX-License-Identifier: ISC 2c378f247SStanislaw Gruszka /* 3c378f247SStanislaw Gruszka * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4c378f247SStanislaw Gruszka * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 5c378f247SStanislaw Gruszka */ 6c378f247SStanislaw Gruszka 77a07adcdSLorenzo Bianconi #include "mt76x02.h" 83e2342edSLorenzo Bianconi #include "mt76x02_trace.h" 95498974bSLorenzo Bianconi #include "trace.h" 10c378f247SStanislaw Gruszka 117b37cce0SLorenzo Bianconi void mt76x02_mac_reset_counters(struct mt76x02_dev *dev) 127b37cce0SLorenzo Bianconi { 137b37cce0SLorenzo Bianconi int i; 147b37cce0SLorenzo Bianconi 157b37cce0SLorenzo Bianconi mt76_rr(dev, MT_RX_STAT_0); 167b37cce0SLorenzo Bianconi mt76_rr(dev, MT_RX_STAT_1); 177b37cce0SLorenzo Bianconi mt76_rr(dev, MT_RX_STAT_2); 187b37cce0SLorenzo Bianconi mt76_rr(dev, MT_TX_STA_0); 197b37cce0SLorenzo Bianconi mt76_rr(dev, MT_TX_STA_1); 207b37cce0SLorenzo Bianconi mt76_rr(dev, MT_TX_STA_2); 217b37cce0SLorenzo Bianconi 227b37cce0SLorenzo Bianconi for (i = 0; i < 16; i++) 237b37cce0SLorenzo Bianconi mt76_rr(dev, MT_TX_AGG_CNT(i)); 247b37cce0SLorenzo Bianconi 257b37cce0SLorenzo Bianconi for (i = 0; i < 16; i++) 267b37cce0SLorenzo Bianconi mt76_rr(dev, MT_TX_STAT_FIFO); 277b37cce0SLorenzo Bianconi 28d107501aSLorenzo Bianconi memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats)); 297b37cce0SLorenzo Bianconi } 307b37cce0SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_mac_reset_counters); 317b37cce0SLorenzo Bianconi 325567b373SFelix Fietkau static enum mt76x02_cipher_type 33c378f247SStanislaw Gruszka mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 34c378f247SStanislaw Gruszka { 35c378f247SStanislaw Gruszka memset(key_data, 0, 32); 36c378f247SStanislaw Gruszka if (!key) 37c368362cSRyder Lee return MT76X02_CIPHER_NONE; 38c378f247SStanislaw Gruszka 39c378f247SStanislaw Gruszka if (key->keylen > 32) 40c368362cSRyder Lee return MT76X02_CIPHER_NONE; 41c378f247SStanislaw Gruszka 42c378f247SStanislaw Gruszka memcpy(key_data, key->key, key->keylen); 43c378f247SStanislaw Gruszka 44c378f247SStanislaw Gruszka switch (key->cipher) { 45c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_WEP40: 46c368362cSRyder Lee return MT76X02_CIPHER_WEP40; 47c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_WEP104: 48c368362cSRyder Lee return MT76X02_CIPHER_WEP104; 49c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_TKIP: 50c368362cSRyder Lee return MT76X02_CIPHER_TKIP; 51c378f247SStanislaw Gruszka case WLAN_CIPHER_SUITE_CCMP: 52c368362cSRyder Lee return MT76X02_CIPHER_AES_CCMP; 53c378f247SStanislaw Gruszka default: 54c368362cSRyder Lee return MT76X02_CIPHER_NONE; 55c378f247SStanislaw Gruszka } 56c378f247SStanislaw Gruszka } 57047aed1cSStanislaw Gruszka 588d66af49SLorenzo Bianconi int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 598d66af49SLorenzo Bianconi u8 key_idx, struct ieee80211_key_conf *key) 60047aed1cSStanislaw Gruszka { 61047aed1cSStanislaw Gruszka enum mt76x02_cipher_type cipher; 62047aed1cSStanislaw Gruszka u8 key_data[32]; 63047aed1cSStanislaw Gruszka u32 val; 64047aed1cSStanislaw Gruszka 65047aed1cSStanislaw Gruszka cipher = mt76x02_mac_get_key_info(key, key_data); 66c368362cSRyder Lee if (cipher == MT76X02_CIPHER_NONE && key) 67047aed1cSStanislaw Gruszka return -EOPNOTSUPP; 68047aed1cSStanislaw Gruszka 698d66af49SLorenzo Bianconi val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 70047aed1cSStanislaw Gruszka val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 71047aed1cSStanislaw Gruszka val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 728d66af49SLorenzo Bianconi mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 73047aed1cSStanislaw Gruszka 748d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 75047aed1cSStanislaw Gruszka sizeof(key_data)); 76047aed1cSStanislaw Gruszka 77047aed1cSStanislaw Gruszka return 0; 78047aed1cSStanislaw Gruszka } 79047aed1cSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 8046436b5eSStanislaw Gruszka 8100496042SFelix Fietkau void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx, 8200496042SFelix Fietkau struct ieee80211_key_conf *key) 8300496042SFelix Fietkau { 8400496042SFelix Fietkau enum mt76x02_cipher_type cipher; 8500496042SFelix Fietkau u8 key_data[32]; 8600496042SFelix Fietkau u32 iv, eiv; 8700496042SFelix Fietkau u64 pn; 8800496042SFelix Fietkau 8900496042SFelix Fietkau cipher = mt76x02_mac_get_key_info(key, key_data); 9000496042SFelix Fietkau iv = mt76_rr(dev, MT_WCID_IV(idx)); 9100496042SFelix Fietkau eiv = mt76_rr(dev, MT_WCID_IV(idx) + 4); 9200496042SFelix Fietkau 9300496042SFelix Fietkau pn = (u64)eiv << 16; 94c368362cSRyder Lee if (cipher == MT76X02_CIPHER_TKIP) { 9500496042SFelix Fietkau pn |= (iv >> 16) & 0xff; 9600496042SFelix Fietkau pn |= (iv & 0xff) << 8; 97c368362cSRyder Lee } else if (cipher >= MT76X02_CIPHER_AES_CCMP) { 9800496042SFelix Fietkau pn |= iv & 0xffff; 9900496042SFelix Fietkau } else { 10000496042SFelix Fietkau return; 10100496042SFelix Fietkau } 10200496042SFelix Fietkau 10300496042SFelix Fietkau atomic64_set(&key->tx_pn, pn); 10400496042SFelix Fietkau } 10500496042SFelix Fietkau 1068d66af49SLorenzo Bianconi int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 10746436b5eSStanislaw Gruszka struct ieee80211_key_conf *key) 10846436b5eSStanislaw Gruszka { 10946436b5eSStanislaw Gruszka enum mt76x02_cipher_type cipher; 11046436b5eSStanislaw Gruszka u8 key_data[32]; 11146436b5eSStanislaw Gruszka u8 iv_data[8]; 112de3c2af1SFelix Fietkau u64 pn; 11346436b5eSStanislaw Gruszka 11446436b5eSStanislaw Gruszka cipher = mt76x02_mac_get_key_info(key, key_data); 115c368362cSRyder Lee if (cipher == MT76X02_CIPHER_NONE && key) 11646436b5eSStanislaw Gruszka return -EOPNOTSUPP; 11746436b5eSStanislaw Gruszka 1188d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 1198d66af49SLorenzo Bianconi mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 12046436b5eSStanislaw Gruszka 12146436b5eSStanislaw Gruszka memset(iv_data, 0, sizeof(iv_data)); 12246436b5eSStanislaw Gruszka if (key) { 1238d66af49SLorenzo Bianconi mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 12446436b5eSStanislaw Gruszka !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 125de3c2af1SFelix Fietkau 126de3c2af1SFelix Fietkau pn = atomic64_read(&key->tx_pn); 127de3c2af1SFelix Fietkau 12846436b5eSStanislaw Gruszka iv_data[3] = key->keyidx << 6; 129c368362cSRyder Lee if (cipher >= MT76X02_CIPHER_TKIP) { 13046436b5eSStanislaw Gruszka iv_data[3] |= 0x20; 131de3c2af1SFelix Fietkau put_unaligned_le32(pn >> 16, &iv_data[4]); 132de3c2af1SFelix Fietkau } 133de3c2af1SFelix Fietkau 134c368362cSRyder Lee if (cipher == MT76X02_CIPHER_TKIP) { 135de3c2af1SFelix Fietkau iv_data[0] = (pn >> 8) & 0xff; 136de3c2af1SFelix Fietkau iv_data[1] = (iv_data[0] | 0x20) & 0x7f; 137de3c2af1SFelix Fietkau iv_data[2] = pn & 0xff; 138c368362cSRyder Lee } else if (cipher >= MT76X02_CIPHER_AES_CCMP) { 139de3c2af1SFelix Fietkau put_unaligned_le16((pn & 0xffff), &iv_data[0]); 140de3c2af1SFelix Fietkau } 14146436b5eSStanislaw Gruszka } 14246436b5eSStanislaw Gruszka 1438d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 14446436b5eSStanislaw Gruszka 14546436b5eSStanislaw Gruszka return 0; 14646436b5eSStanislaw Gruszka } 14732bb405fSStanislaw Gruszka 1488d66af49SLorenzo Bianconi void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, 1498d66af49SLorenzo Bianconi u8 vif_idx, u8 *mac) 15032bb405fSStanislaw Gruszka { 15132bb405fSStanislaw Gruszka struct mt76_wcid_addr addr = {}; 15232bb405fSStanislaw Gruszka u32 attr; 15332bb405fSStanislaw Gruszka 15432bb405fSStanislaw Gruszka attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 15532bb405fSStanislaw Gruszka FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 15632bb405fSStanislaw Gruszka 1578d66af49SLorenzo Bianconi mt76_wr(dev, MT_WCID_ATTR(idx), attr); 15832bb405fSStanislaw Gruszka 15932bb405fSStanislaw Gruszka if (idx >= 128) 16032bb405fSStanislaw Gruszka return; 16132bb405fSStanislaw Gruszka 16232bb405fSStanislaw Gruszka if (mac) 16332bb405fSStanislaw Gruszka memcpy(addr.macaddr, mac, ETH_ALEN); 16432bb405fSStanislaw Gruszka 1658d66af49SLorenzo Bianconi mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 16632bb405fSStanislaw Gruszka } 16732bb405fSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 168516ea2a2SStanislaw Gruszka 1698d66af49SLorenzo Bianconi void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop) 170516ea2a2SStanislaw Gruszka { 1718d66af49SLorenzo Bianconi u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); 172516ea2a2SStanislaw Gruszka u32 bit = MT_WCID_DROP_MASK(idx); 173516ea2a2SStanislaw Gruszka 174516ea2a2SStanislaw Gruszka /* prevent unnecessary writes */ 175516ea2a2SStanislaw Gruszka if ((val & bit) != (bit * drop)) 1768d66af49SLorenzo Bianconi mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 177516ea2a2SStanislaw Gruszka } 178f5a7f126SStanislaw Gruszka 179c33edef5SLorenzo Bianconi static u16 1808d66af49SLorenzo Bianconi mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev, 1815327b5eaSStanislaw Gruszka const struct ieee80211_tx_rate *rate, u8 *nss_val) 1825327b5eaSStanislaw Gruszka { 183c09f4d0aSLorenzo Bianconi u8 phy, rate_idx, nss, bw = 0; 1845327b5eaSStanislaw Gruszka u16 rateval; 1855327b5eaSStanislaw Gruszka 1865327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 1875327b5eaSStanislaw Gruszka rate_idx = rate->idx; 1885327b5eaSStanislaw Gruszka nss = 1 + (rate->idx >> 4); 1895327b5eaSStanislaw Gruszka phy = MT_PHY_TYPE_VHT; 1905327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 1915327b5eaSStanislaw Gruszka bw = 2; 1925327b5eaSStanislaw Gruszka else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1935327b5eaSStanislaw Gruszka bw = 1; 1945327b5eaSStanislaw Gruszka } else if (rate->flags & IEEE80211_TX_RC_MCS) { 1955327b5eaSStanislaw Gruszka rate_idx = rate->idx; 1965327b5eaSStanislaw Gruszka nss = 1 + (rate->idx >> 3); 1975327b5eaSStanislaw Gruszka phy = MT_PHY_TYPE_HT; 1985327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 1995327b5eaSStanislaw Gruszka phy = MT_PHY_TYPE_HT_GF; 2005327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 2015327b5eaSStanislaw Gruszka bw = 1; 2025327b5eaSStanislaw Gruszka } else { 2035327b5eaSStanislaw Gruszka const struct ieee80211_rate *r; 20496747a51SFelix Fietkau int band = dev->mphy.chandef.chan->band; 2055327b5eaSStanislaw Gruszka u16 val; 2065327b5eaSStanislaw Gruszka 2078d66af49SLorenzo Bianconi r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx]; 2085327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 2095327b5eaSStanislaw Gruszka val = r->hw_value_short; 2105327b5eaSStanislaw Gruszka else 2115327b5eaSStanislaw Gruszka val = r->hw_value; 2125327b5eaSStanislaw Gruszka 2135327b5eaSStanislaw Gruszka phy = val >> 8; 2145327b5eaSStanislaw Gruszka rate_idx = val & 0xff; 215c09f4d0aSLorenzo Bianconi nss = 1; 2165327b5eaSStanislaw Gruszka } 2175327b5eaSStanislaw Gruszka 2185327b5eaSStanislaw Gruszka rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 2195327b5eaSStanislaw Gruszka rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 2205327b5eaSStanislaw Gruszka rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 2215327b5eaSStanislaw Gruszka if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 2225327b5eaSStanislaw Gruszka rateval |= MT_RXWI_RATE_SGI; 2235327b5eaSStanislaw Gruszka 2245327b5eaSStanislaw Gruszka *nss_val = nss; 225c33edef5SLorenzo Bianconi return rateval; 2265327b5eaSStanislaw Gruszka } 2275327b5eaSStanislaw Gruszka 2288d66af49SLorenzo Bianconi void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 2295327b5eaSStanislaw Gruszka const struct ieee80211_tx_rate *rate) 2305327b5eaSStanislaw Gruszka { 231db9f11d3SFelix Fietkau s8 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 232c33edef5SLorenzo Bianconi u16 rateval; 233db9f11d3SFelix Fietkau u32 tx_info; 234db9f11d3SFelix Fietkau s8 nss; 235db9f11d3SFelix Fietkau 236db9f11d3SFelix Fietkau rateval = mt76x02_mac_tx_rate_val(dev, rate, &nss); 237db9f11d3SFelix Fietkau tx_info = FIELD_PREP(MT_WCID_TX_INFO_RATE, rateval) | 238db9f11d3SFelix Fietkau FIELD_PREP(MT_WCID_TX_INFO_NSS, nss) | 239db9f11d3SFelix Fietkau FIELD_PREP(MT_WCID_TX_INFO_TXPWR_ADJ, max_txpwr_adj) | 240db9f11d3SFelix Fietkau MT_WCID_TX_INFO_SET; 241db9f11d3SFelix Fietkau wcid->tx_info = tx_info; 2425327b5eaSStanislaw Gruszka } 243b490b1dfSStanislaw Gruszka 244dd61100dSLorenzo Bianconi void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable) 245dd61100dSLorenzo Bianconi { 246dd61100dSLorenzo Bianconi if (enable) 247dd61100dSLorenzo Bianconi mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 248dd61100dSLorenzo Bianconi else 249dd61100dSLorenzo Bianconi mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 250dd61100dSLorenzo Bianconi } 251dd61100dSLorenzo Bianconi 2528d66af49SLorenzo Bianconi bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 253b490b1dfSStanislaw Gruszka struct mt76x02_tx_status *stat) 254b490b1dfSStanislaw Gruszka { 255b490b1dfSStanislaw Gruszka u32 stat1, stat2; 256b490b1dfSStanislaw Gruszka 2578d66af49SLorenzo Bianconi stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 2588d66af49SLorenzo Bianconi stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); 259b490b1dfSStanislaw Gruszka 260b490b1dfSStanislaw Gruszka stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 261b490b1dfSStanislaw Gruszka if (!stat->valid) 262b490b1dfSStanislaw Gruszka return false; 263b490b1dfSStanislaw Gruszka 264b490b1dfSStanislaw Gruszka stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 265b490b1dfSStanislaw Gruszka stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 266b490b1dfSStanislaw Gruszka stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 267b490b1dfSStanislaw Gruszka stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 268b490b1dfSStanislaw Gruszka stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 269b490b1dfSStanislaw Gruszka 270b490b1dfSStanislaw Gruszka stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 271b490b1dfSStanislaw Gruszka stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 272b490b1dfSStanislaw Gruszka 273e0168dc6SLorenzo Bianconi trace_mac_txstat_fetch(dev, stat); 274e0168dc6SLorenzo Bianconi 275b490b1dfSStanislaw Gruszka return true; 276b490b1dfSStanislaw Gruszka } 2777c1f8881SStanislaw Gruszka 2787c1f8881SStanislaw Gruszka static int 2797c1f8881SStanislaw Gruszka mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 2807c1f8881SStanislaw Gruszka enum nl80211_band band) 2817c1f8881SStanislaw Gruszka { 2827c1f8881SStanislaw Gruszka u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 2837c1f8881SStanislaw Gruszka 2847c1f8881SStanislaw Gruszka txrate->idx = 0; 2857c1f8881SStanislaw Gruszka txrate->flags = 0; 2867c1f8881SStanislaw Gruszka txrate->count = 1; 2877c1f8881SStanislaw Gruszka 2887c1f8881SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 2897c1f8881SStanislaw Gruszka case MT_PHY_TYPE_OFDM: 2907c1f8881SStanislaw Gruszka if (band == NL80211_BAND_2GHZ) 2917c1f8881SStanislaw Gruszka idx += 4; 2927c1f8881SStanislaw Gruszka 2937c1f8881SStanislaw Gruszka txrate->idx = idx; 2947c1f8881SStanislaw Gruszka return 0; 2957c1f8881SStanislaw Gruszka case MT_PHY_TYPE_CCK: 2967c1f8881SStanislaw Gruszka if (idx >= 8) 2977c1f8881SStanislaw Gruszka idx -= 8; 2987c1f8881SStanislaw Gruszka 2997c1f8881SStanislaw Gruszka txrate->idx = idx; 3007c1f8881SStanislaw Gruszka return 0; 3017c1f8881SStanislaw Gruszka case MT_PHY_TYPE_HT_GF: 3027c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 303aab662ccSGustavo A. R. Silva fallthrough; 3047c1f8881SStanislaw Gruszka case MT_PHY_TYPE_HT: 3057c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_MCS; 3067c1f8881SStanislaw Gruszka txrate->idx = idx; 3077c1f8881SStanislaw Gruszka break; 3087c1f8881SStanislaw Gruszka case MT_PHY_TYPE_VHT: 3097c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 3107c1f8881SStanislaw Gruszka txrate->idx = idx; 3117c1f8881SStanislaw Gruszka break; 3127c1f8881SStanislaw Gruszka default: 3137c1f8881SStanislaw Gruszka return -EINVAL; 3147c1f8881SStanislaw Gruszka } 3157c1f8881SStanislaw Gruszka 3167c1f8881SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 3177c1f8881SStanislaw Gruszka case MT_PHY_BW_20: 3187c1f8881SStanislaw Gruszka break; 3197c1f8881SStanislaw Gruszka case MT_PHY_BW_40: 3207c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 3217c1f8881SStanislaw Gruszka break; 3227c1f8881SStanislaw Gruszka case MT_PHY_BW_80: 3237c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 3247c1f8881SStanislaw Gruszka break; 3257c1f8881SStanislaw Gruszka default: 3267c1f8881SStanislaw Gruszka return -EINVAL; 3277c1f8881SStanislaw Gruszka } 3287c1f8881SStanislaw Gruszka 3297c1f8881SStanislaw Gruszka if (rate & MT_RXWI_RATE_SGI) 3307c1f8881SStanislaw Gruszka txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 3317c1f8881SStanislaw Gruszka 3327c1f8881SStanislaw Gruszka return 0; 3337c1f8881SStanislaw Gruszka } 3347c1f8881SStanislaw Gruszka 3358d66af49SLorenzo Bianconi void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 336427f9ebeSLorenzo Bianconi struct sk_buff *skb, struct mt76_wcid *wcid, 337427f9ebeSLorenzo Bianconi struct ieee80211_sta *sta, int len) 338427f9ebeSLorenzo Bianconi { 339320c85e6SLorenzo Bianconi struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 340427f9ebeSLorenzo Bianconi struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 341427f9ebeSLorenzo Bianconi struct ieee80211_tx_rate *rate = &info->control.rates[0]; 342427f9ebeSLorenzo Bianconi struct ieee80211_key_conf *key = info->control.hw_key; 343db9f11d3SFelix Fietkau u32 wcid_tx_info; 344427f9ebeSLorenzo Bianconi u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 345c33edef5SLorenzo Bianconi u16 txwi_flags = 0, rateval; 346427f9ebeSLorenzo Bianconi u8 nss; 347427f9ebeSLorenzo Bianconi s8 txpwr_adj, max_txpwr_adj; 348b9027e08SLorenzo Bianconi u8 ccmp_pn[8], nstreams = dev->mphy.chainmask & 0xf; 349427f9ebeSLorenzo Bianconi 350427f9ebeSLorenzo Bianconi memset(txwi, 0, sizeof(*txwi)); 351427f9ebeSLorenzo Bianconi 352c50d105aSFelix Fietkau mt76_tx_check_agg_ssn(sta, skb); 353c50d105aSFelix Fietkau 354128b75bfSFelix Fietkau if (!info->control.hw_key && wcid && wcid->hw_key_idx != 0xff && 355128b75bfSFelix Fietkau ieee80211_has_protected(hdr->frame_control)) { 356128b75bfSFelix Fietkau wcid = NULL; 357128b75bfSFelix Fietkau ieee80211_get_tx_rates(info->control.vif, sta, skb, 358128b75bfSFelix Fietkau info->control.rates, 1); 359128b75bfSFelix Fietkau } 360128b75bfSFelix Fietkau 361427f9ebeSLorenzo Bianconi if (wcid) 362427f9ebeSLorenzo Bianconi txwi->wcid = wcid->idx; 363427f9ebeSLorenzo Bianconi else 364427f9ebeSLorenzo Bianconi txwi->wcid = 0xff; 365427f9ebeSLorenzo Bianconi 366427f9ebeSLorenzo Bianconi if (wcid && wcid->sw_iv && key) { 367427f9ebeSLorenzo Bianconi u64 pn = atomic64_inc_return(&key->tx_pn); 368ff97c52aSRyder Lee 369427f9ebeSLorenzo Bianconi ccmp_pn[0] = pn; 370427f9ebeSLorenzo Bianconi ccmp_pn[1] = pn >> 8; 371427f9ebeSLorenzo Bianconi ccmp_pn[2] = 0; 372427f9ebeSLorenzo Bianconi ccmp_pn[3] = 0x20 | (key->keyidx << 6); 373427f9ebeSLorenzo Bianconi ccmp_pn[4] = pn >> 16; 374427f9ebeSLorenzo Bianconi ccmp_pn[5] = pn >> 24; 375427f9ebeSLorenzo Bianconi ccmp_pn[6] = pn >> 32; 376427f9ebeSLorenzo Bianconi ccmp_pn[7] = pn >> 40; 377427f9ebeSLorenzo Bianconi txwi->iv = *((__le32 *)&ccmp_pn[0]); 378906d2d3fSFelix Fietkau txwi->eiv = *((__le32 *)&ccmp_pn[4]); 379427f9ebeSLorenzo Bianconi } 380427f9ebeSLorenzo Bianconi 381427f9ebeSLorenzo Bianconi if (wcid && (rate->idx < 0 || !rate->count)) { 382db9f11d3SFelix Fietkau wcid_tx_info = wcid->tx_info; 383c33edef5SLorenzo Bianconi rateval = FIELD_GET(MT_WCID_TX_INFO_RATE, wcid_tx_info); 384db9f11d3SFelix Fietkau max_txpwr_adj = FIELD_GET(MT_WCID_TX_INFO_TXPWR_ADJ, 385db9f11d3SFelix Fietkau wcid_tx_info); 386db9f11d3SFelix Fietkau nss = FIELD_GET(MT_WCID_TX_INFO_NSS, wcid_tx_info); 387427f9ebeSLorenzo Bianconi } else { 388c33edef5SLorenzo Bianconi rateval = mt76x02_mac_tx_rate_val(dev, rate, &nss); 38991be8e8aSLorenzo Bianconi max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 390427f9ebeSLorenzo Bianconi } 391c33edef5SLorenzo Bianconi txwi->rate = cpu_to_le16(rateval); 392427f9ebeSLorenzo Bianconi 3939e5f6dd7SFelix Fietkau txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->txpower_conf, 394427f9ebeSLorenzo Bianconi max_txpwr_adj); 395427f9ebeSLorenzo Bianconi txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 396427f9ebeSLorenzo Bianconi 3978d66af49SLorenzo Bianconi if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4) 398427f9ebeSLorenzo Bianconi txwi->txstream = 0x13; 3998d66af49SLorenzo Bianconi else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 && 400427f9ebeSLorenzo Bianconi !(txwi->rate & cpu_to_le16(rate_ht_mask))) 401427f9ebeSLorenzo Bianconi txwi->txstream = 0x93; 402427f9ebeSLorenzo Bianconi 403320c85e6SLorenzo Bianconi if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC)) 404320c85e6SLorenzo Bianconi txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 405320c85e6SLorenzo Bianconi if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 406320c85e6SLorenzo Bianconi txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 407261ce887SBenjamin Berg if (nss > 1 && sta && sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC) 408320c85e6SLorenzo Bianconi txwi_flags |= MT_TXWI_FLAGS_MMPS; 409320c85e6SLorenzo Bianconi if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 410320c85e6SLorenzo Bianconi txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 411320c85e6SLorenzo Bianconi if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 412320c85e6SLorenzo Bianconi txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 413320c85e6SLorenzo Bianconi if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 414320c85e6SLorenzo Bianconi u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 415046d2e7cSSriram R u8 ampdu_density = sta->deflink.ht_cap.ampdu_density; 416320c85e6SLorenzo Bianconi 417046d2e7cSSriram R ba_size <<= sta->deflink.ht_cap.ampdu_factor; 418320c85e6SLorenzo Bianconi ba_size = min_t(int, 63, ba_size - 1); 419320c85e6SLorenzo Bianconi if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 420320c85e6SLorenzo Bianconi ba_size = 0; 421320c85e6SLorenzo Bianconi txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 422320c85e6SLorenzo Bianconi 42355961d8bSFelix Fietkau if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4) 42455961d8bSFelix Fietkau ampdu_density = IEEE80211_HT_MPDU_DENSITY_4; 42555961d8bSFelix Fietkau 426320c85e6SLorenzo Bianconi txwi_flags |= MT_TXWI_FLAGS_AMPDU | 42755961d8bSFelix Fietkau FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, ampdu_density); 428320c85e6SLorenzo Bianconi } 429320c85e6SLorenzo Bianconi 430320c85e6SLorenzo Bianconi if (ieee80211_is_probe_resp(hdr->frame_control) || 431320c85e6SLorenzo Bianconi ieee80211_is_beacon(hdr->frame_control)) 432320c85e6SLorenzo Bianconi txwi_flags |= MT_TXWI_FLAGS_TS; 433320c85e6SLorenzo Bianconi 434320c85e6SLorenzo Bianconi txwi->flags |= cpu_to_le16(txwi_flags); 435320c85e6SLorenzo Bianconi txwi->len_ctl = cpu_to_le16(len); 436427f9ebeSLorenzo Bianconi } 437427f9ebeSLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 438427f9ebeSLorenzo Bianconi 4397c1f8881SStanislaw Gruszka static void 4408548c6ebSFelix Fietkau mt76x02_tx_rate_fallback(struct ieee80211_tx_rate *rates, int idx, int phy) 4418548c6ebSFelix Fietkau { 4428548c6ebSFelix Fietkau u8 mcs, nss; 4438548c6ebSFelix Fietkau 4448548c6ebSFelix Fietkau if (!idx) 4458548c6ebSFelix Fietkau return; 4468548c6ebSFelix Fietkau 4478548c6ebSFelix Fietkau rates += idx - 1; 4488548c6ebSFelix Fietkau rates[1] = rates[0]; 4498548c6ebSFelix Fietkau switch (phy) { 4508548c6ebSFelix Fietkau case MT_PHY_TYPE_VHT: 4518548c6ebSFelix Fietkau mcs = ieee80211_rate_get_vht_mcs(rates); 4528548c6ebSFelix Fietkau nss = ieee80211_rate_get_vht_nss(rates); 4538548c6ebSFelix Fietkau 4548548c6ebSFelix Fietkau if (mcs == 0) 4558548c6ebSFelix Fietkau nss = max_t(int, nss - 1, 1); 4568548c6ebSFelix Fietkau else 4578548c6ebSFelix Fietkau mcs--; 4588548c6ebSFelix Fietkau 4598548c6ebSFelix Fietkau ieee80211_rate_set_vht(rates + 1, mcs, nss); 4608548c6ebSFelix Fietkau break; 4618548c6ebSFelix Fietkau case MT_PHY_TYPE_HT_GF: 4628548c6ebSFelix Fietkau case MT_PHY_TYPE_HT: 4638548c6ebSFelix Fietkau /* MCS 8 falls back to MCS 0 */ 4648548c6ebSFelix Fietkau if (rates[0].idx == 8) { 4658548c6ebSFelix Fietkau rates[1].idx = 0; 4668548c6ebSFelix Fietkau break; 4678548c6ebSFelix Fietkau } 468aab662ccSGustavo A. R. Silva fallthrough; 4698548c6ebSFelix Fietkau default: 4708548c6ebSFelix Fietkau rates[1].idx = max_t(int, rates[0].idx - 1, 0); 4718548c6ebSFelix Fietkau break; 4728548c6ebSFelix Fietkau } 4738548c6ebSFelix Fietkau } 4748548c6ebSFelix Fietkau 4758548c6ebSFelix Fietkau static void 4768548c6ebSFelix Fietkau mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, struct mt76x02_sta *msta, 4777c1f8881SStanislaw Gruszka struct ieee80211_tx_info *info, 4787c1f8881SStanislaw Gruszka struct mt76x02_tx_status *st, int n_frames) 4797c1f8881SStanislaw Gruszka { 4807c1f8881SStanislaw Gruszka struct ieee80211_tx_rate *rate = info->status.rates; 4818548c6ebSFelix Fietkau struct ieee80211_tx_rate last_rate; 4828548c6ebSFelix Fietkau u16 first_rate; 4838548c6ebSFelix Fietkau int retry = st->retry; 4848548c6ebSFelix Fietkau int phy; 4857c1f8881SStanislaw Gruszka int i; 4867c1f8881SStanislaw Gruszka 4877c1f8881SStanislaw Gruszka if (!n_frames) 4887c1f8881SStanislaw Gruszka return; 4897c1f8881SStanislaw Gruszka 4908548c6ebSFelix Fietkau phy = FIELD_GET(MT_RXWI_RATE_PHY, st->rate); 4917c1f8881SStanislaw Gruszka 4928548c6ebSFelix Fietkau if (st->pktid & MT_PACKET_ID_HAS_RATE) { 493355f8d00SFelix Fietkau first_rate = st->rate & ~MT_PKTID_RATE; 494355f8d00SFelix Fietkau first_rate |= st->pktid & MT_PKTID_RATE; 4958548c6ebSFelix Fietkau 4968548c6ebSFelix Fietkau mt76x02_mac_process_tx_rate(&rate[0], first_rate, 49796747a51SFelix Fietkau dev->mphy.chandef.chan->band); 4988548c6ebSFelix Fietkau } else if (rate[0].idx < 0) { 4998548c6ebSFelix Fietkau if (!msta) 5008548c6ebSFelix Fietkau return; 5018548c6ebSFelix Fietkau 5028548c6ebSFelix Fietkau mt76x02_mac_process_tx_rate(&rate[0], msta->wcid.tx_info, 50396747a51SFelix Fietkau dev->mphy.chandef.chan->band); 5047c1f8881SStanislaw Gruszka } 5058548c6ebSFelix Fietkau 5068548c6ebSFelix Fietkau mt76x02_mac_process_tx_rate(&last_rate, st->rate, 50796747a51SFelix Fietkau dev->mphy.chandef.chan->band); 5088548c6ebSFelix Fietkau 5098548c6ebSFelix Fietkau for (i = 0; i < ARRAY_SIZE(info->status.rates); i++) { 5108548c6ebSFelix Fietkau retry--; 5118548c6ebSFelix Fietkau if (i + 1 == ARRAY_SIZE(info->status.rates)) { 5128548c6ebSFelix Fietkau info->status.rates[i] = last_rate; 5138548c6ebSFelix Fietkau info->status.rates[i].count = max_t(int, retry, 1); 5148548c6ebSFelix Fietkau break; 5158548c6ebSFelix Fietkau } 5168548c6ebSFelix Fietkau 5178548c6ebSFelix Fietkau mt76x02_tx_rate_fallback(info->status.rates, i, phy); 5188548c6ebSFelix Fietkau if (info->status.rates[i].idx == last_rate.idx) 5198548c6ebSFelix Fietkau break; 5208548c6ebSFelix Fietkau } 5218548c6ebSFelix Fietkau 5228548c6ebSFelix Fietkau if (i + 1 < ARRAY_SIZE(info->status.rates)) { 5238548c6ebSFelix Fietkau info->status.rates[i + 1].idx = -1; 5248548c6ebSFelix Fietkau info->status.rates[i + 1].count = 0; 5258548c6ebSFelix Fietkau } 5267c1f8881SStanislaw Gruszka 5277c1f8881SStanislaw Gruszka info->status.ampdu_len = n_frames; 5287c1f8881SStanislaw Gruszka info->status.ampdu_ack_len = st->success ? n_frames : 0; 5297c1f8881SStanislaw Gruszka 5307c1f8881SStanislaw Gruszka if (st->aggr) 5317c1f8881SStanislaw Gruszka info->flags |= IEEE80211_TX_CTL_AMPDU | 5327c1f8881SStanislaw Gruszka IEEE80211_TX_STAT_AMPDU; 5337c1f8881SStanislaw Gruszka 5347c1f8881SStanislaw Gruszka if (!st->ack_req) 5357c1f8881SStanislaw Gruszka info->flags |= IEEE80211_TX_CTL_NO_ACK; 5367c1f8881SStanislaw Gruszka else if (st->success) 5377c1f8881SStanislaw Gruszka info->flags |= IEEE80211_TX_STAT_ACK; 5387c1f8881SStanislaw Gruszka } 5397c1f8881SStanislaw Gruszka 5408d66af49SLorenzo Bianconi void mt76x02_send_tx_status(struct mt76x02_dev *dev, 5417c1f8881SStanislaw Gruszka struct mt76x02_tx_status *stat, u8 *update) 5427c1f8881SStanislaw Gruszka { 5437c1f8881SStanislaw Gruszka struct ieee80211_tx_info info = {}; 54488046b2cSFelix Fietkau struct ieee80211_tx_status status = { 54588046b2cSFelix Fietkau .info = &info 54688046b2cSFelix Fietkau }; 547355f8d00SFelix Fietkau static const u8 ac_to_tid[4] = { 548355f8d00SFelix Fietkau [IEEE80211_AC_BE] = 0, 549355f8d00SFelix Fietkau [IEEE80211_AC_BK] = 1, 550355f8d00SFelix Fietkau [IEEE80211_AC_VI] = 4, 551355f8d00SFelix Fietkau [IEEE80211_AC_VO] = 6 552355f8d00SFelix Fietkau }; 5537c1f8881SStanislaw Gruszka struct mt76_wcid *wcid = NULL; 5547c1f8881SStanislaw Gruszka struct mt76x02_sta *msta = NULL; 55588046b2cSFelix Fietkau struct mt76_dev *mdev = &dev->mt76; 55679d1c94cSFelix Fietkau struct sk_buff_head list; 557355f8d00SFelix Fietkau u32 duration = 0; 558355f8d00SFelix Fietkau u8 cur_pktid; 559355f8d00SFelix Fietkau u32 ac = 0; 560355f8d00SFelix Fietkau int len = 0; 56188046b2cSFelix Fietkau 56288046b2cSFelix Fietkau if (stat->pktid == MT_PACKET_ID_NO_ACK) 56388046b2cSFelix Fietkau return; 5647c1f8881SStanislaw Gruszka 5657c1f8881SStanislaw Gruszka rcu_read_lock(); 56688046b2cSFelix Fietkau 567238f5d6fSFelix Fietkau if (stat->wcid < MT76x02_N_WCIDS) 5688d66af49SLorenzo Bianconi wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]); 5697c1f8881SStanislaw Gruszka 57065b526a1SFelix Fietkau if (wcid && wcid->sta) { 5717c1f8881SStanislaw Gruszka void *priv; 5727c1f8881SStanislaw Gruszka 5737c1f8881SStanislaw Gruszka priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 57488046b2cSFelix Fietkau status.sta = container_of(priv, struct ieee80211_sta, 5757c1f8881SStanislaw Gruszka drv_priv); 5767c1f8881SStanislaw Gruszka } 5777c1f8881SStanislaw Gruszka 578bafdf85dSStanislaw Gruszka mt76_tx_status_lock(mdev, &list); 579bafdf85dSStanislaw Gruszka 58088046b2cSFelix Fietkau if (wcid) { 5818548c6ebSFelix Fietkau if (mt76_is_skb_pktid(stat->pktid)) 58288046b2cSFelix Fietkau status.skb = mt76_tx_status_skb_get(mdev, wcid, 58379d1c94cSFelix Fietkau stat->pktid, &list); 58488046b2cSFelix Fietkau if (status.skb) 58588046b2cSFelix Fietkau status.info = IEEE80211_SKB_CB(status.skb); 58688046b2cSFelix Fietkau } 58788046b2cSFelix Fietkau 5888548c6ebSFelix Fietkau if (!status.skb && !(stat->pktid & MT_PACKET_ID_HAS_RATE)) { 5898548c6ebSFelix Fietkau mt76_tx_status_unlock(mdev, &list); 590355f8d00SFelix Fietkau goto out; 5918548c6ebSFelix Fietkau } 5928548c6ebSFelix Fietkau 593355f8d00SFelix Fietkau 59488046b2cSFelix Fietkau if (msta && stat->aggr && !status.skb) { 5957c1f8881SStanislaw Gruszka u32 stat_val, stat_cache; 5967c1f8881SStanislaw Gruszka 5977c1f8881SStanislaw Gruszka stat_val = stat->rate; 5987c1f8881SStanislaw Gruszka stat_val |= ((u32)stat->retry) << 16; 5997c1f8881SStanislaw Gruszka stat_cache = msta->status.rate; 6007c1f8881SStanislaw Gruszka stat_cache |= ((u32)msta->status.retry) << 16; 6017c1f8881SStanislaw Gruszka 6027c1f8881SStanislaw Gruszka if (*update == 0 && stat_val == stat_cache && 6037c1f8881SStanislaw Gruszka stat->wcid == msta->status.wcid && msta->n_frames < 32) { 6047c1f8881SStanislaw Gruszka msta->n_frames++; 605bafdf85dSStanislaw Gruszka mt76_tx_status_unlock(mdev, &list); 606355f8d00SFelix Fietkau goto out; 6077c1f8881SStanislaw Gruszka } 6087c1f8881SStanislaw Gruszka 609355f8d00SFelix Fietkau cur_pktid = msta->status.pktid; 6108548c6ebSFelix Fietkau mt76x02_mac_fill_tx_status(dev, msta, status.info, 6118548c6ebSFelix Fietkau &msta->status, msta->n_frames); 6127c1f8881SStanislaw Gruszka 6137c1f8881SStanislaw Gruszka msta->status = *stat; 6147c1f8881SStanislaw Gruszka msta->n_frames = 1; 6157c1f8881SStanislaw Gruszka *update = 0; 6167c1f8881SStanislaw Gruszka } else { 617355f8d00SFelix Fietkau cur_pktid = stat->pktid; 6188548c6ebSFelix Fietkau mt76x02_mac_fill_tx_status(dev, msta, status.info, stat, 1); 6197c1f8881SStanislaw Gruszka *update = 1; 6207c1f8881SStanislaw Gruszka } 6217c1f8881SStanislaw Gruszka 622355f8d00SFelix Fietkau if (status.skb) { 623355f8d00SFelix Fietkau info = *status.info; 624355f8d00SFelix Fietkau len = status.skb->len; 625355f8d00SFelix Fietkau ac = skb_get_queue_mapping(status.skb); 62679d1c94cSFelix Fietkau mt76_tx_status_skb_done(mdev, status.skb, &list); 627355f8d00SFelix Fietkau } else if (msta) { 628355f8d00SFelix Fietkau len = status.info->status.ampdu_len * ewma_pktlen_read(&msta->pktlen); 629355f8d00SFelix Fietkau ac = FIELD_GET(MT_PKTID_AC, cur_pktid); 630355f8d00SFelix Fietkau } 631355f8d00SFelix Fietkau 63279d1c94cSFelix Fietkau mt76_tx_status_unlock(mdev, &list); 633bafdf85dSStanislaw Gruszka 634*5b8ccdfbSFelix Fietkau if (!status.skb) { 635*5b8ccdfbSFelix Fietkau spin_lock_bh(&dev->mt76.rx_lock); 636bafdf85dSStanislaw Gruszka ieee80211_tx_status_ext(mt76_hw(dev), &status); 637*5b8ccdfbSFelix Fietkau spin_unlock_bh(&dev->mt76.rx_lock); 638*5b8ccdfbSFelix Fietkau } 639355f8d00SFelix Fietkau 640355f8d00SFelix Fietkau if (!len) 641355f8d00SFelix Fietkau goto out; 642355f8d00SFelix Fietkau 64385b7a5d0SLorenzo Bianconi duration = ieee80211_calc_tx_airtime(mt76_hw(dev), &info, len); 644355f8d00SFelix Fietkau 645355f8d00SFelix Fietkau spin_lock_bh(&dev->mt76.cc_lock); 646355f8d00SFelix Fietkau dev->tx_airtime += duration; 647355f8d00SFelix Fietkau spin_unlock_bh(&dev->mt76.cc_lock); 648355f8d00SFelix Fietkau 649355f8d00SFelix Fietkau if (msta) 650355f8d00SFelix Fietkau ieee80211_sta_register_airtime(status.sta, ac_to_tid[ac], duration, 0); 651355f8d00SFelix Fietkau 652355f8d00SFelix Fietkau out: 6537c1f8881SStanislaw Gruszka rcu_read_unlock(); 6547c1f8881SStanislaw Gruszka } 65574ff4539SStanislaw Gruszka 6561a4846fcSFelix Fietkau static int 657f832898dSLorenzo Bianconi mt76x02_mac_process_rate(struct mt76x02_dev *dev, 658f832898dSLorenzo Bianconi struct mt76_rx_status *status, 659f832898dSLorenzo Bianconi u16 rate) 66074ff4539SStanislaw Gruszka { 66174ff4539SStanislaw Gruszka u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 66274ff4539SStanislaw Gruszka 66374ff4539SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 66474ff4539SStanislaw Gruszka case MT_PHY_TYPE_OFDM: 66574ff4539SStanislaw Gruszka if (idx >= 8) 66674ff4539SStanislaw Gruszka idx = 0; 66774ff4539SStanislaw Gruszka 66874ff4539SStanislaw Gruszka if (status->band == NL80211_BAND_2GHZ) 66974ff4539SStanislaw Gruszka idx += 4; 67074ff4539SStanislaw Gruszka 67174ff4539SStanislaw Gruszka status->rate_idx = idx; 67274ff4539SStanislaw Gruszka return 0; 67374ff4539SStanislaw Gruszka case MT_PHY_TYPE_CCK: 67474ff4539SStanislaw Gruszka if (idx >= 8) { 67574ff4539SStanislaw Gruszka idx -= 8; 67674ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 67774ff4539SStanislaw Gruszka } 67874ff4539SStanislaw Gruszka 67974ff4539SStanislaw Gruszka if (idx >= 4) 68074ff4539SStanislaw Gruszka idx = 0; 68174ff4539SStanislaw Gruszka 68274ff4539SStanislaw Gruszka status->rate_idx = idx; 68374ff4539SStanislaw Gruszka return 0; 68474ff4539SStanislaw Gruszka case MT_PHY_TYPE_HT_GF: 68574ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_HT_GF; 686aab662ccSGustavo A. R. Silva fallthrough; 68774ff4539SStanislaw Gruszka case MT_PHY_TYPE_HT: 68874ff4539SStanislaw Gruszka status->encoding = RX_ENC_HT; 68974ff4539SStanislaw Gruszka status->rate_idx = idx; 69074ff4539SStanislaw Gruszka break; 691f832898dSLorenzo Bianconi case MT_PHY_TYPE_VHT: { 692b9027e08SLorenzo Bianconi u8 n_rxstream = dev->mphy.chainmask & 0xf; 693f832898dSLorenzo Bianconi 69474ff4539SStanislaw Gruszka status->encoding = RX_ENC_VHT; 69574ff4539SStanislaw Gruszka status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 696f832898dSLorenzo Bianconi status->nss = min_t(u8, n_rxstream, 697f832898dSLorenzo Bianconi FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1); 69874ff4539SStanislaw Gruszka break; 699f832898dSLorenzo Bianconi } 70074ff4539SStanislaw Gruszka default: 70174ff4539SStanislaw Gruszka return -EINVAL; 70274ff4539SStanislaw Gruszka } 70374ff4539SStanislaw Gruszka 70474ff4539SStanislaw Gruszka if (rate & MT_RXWI_RATE_LDPC) 70574ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_LDPC; 70674ff4539SStanislaw Gruszka 70774ff4539SStanislaw Gruszka if (rate & MT_RXWI_RATE_SGI) 70874ff4539SStanislaw Gruszka status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 70974ff4539SStanislaw Gruszka 71074ff4539SStanislaw Gruszka if (rate & MT_RXWI_RATE_STBC) 71174ff4539SStanislaw Gruszka status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 71274ff4539SStanislaw Gruszka 71374ff4539SStanislaw Gruszka switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 71474ff4539SStanislaw Gruszka case MT_PHY_BW_20: 71574ff4539SStanislaw Gruszka break; 71674ff4539SStanislaw Gruszka case MT_PHY_BW_40: 71774ff4539SStanislaw Gruszka status->bw = RATE_INFO_BW_40; 71874ff4539SStanislaw Gruszka break; 71974ff4539SStanislaw Gruszka case MT_PHY_BW_80: 72074ff4539SStanislaw Gruszka status->bw = RATE_INFO_BW_80; 72174ff4539SStanislaw Gruszka break; 72274ff4539SStanislaw Gruszka default: 72374ff4539SStanislaw Gruszka break; 72474ff4539SStanislaw Gruszka } 72574ff4539SStanislaw Gruszka 72674ff4539SStanislaw Gruszka return 0; 72774ff4539SStanislaw Gruszka } 72889a8607cSLorenzo Bianconi 7290b2d27e5SStanislaw Gruszka void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr) 73089a8607cSLorenzo Bianconi { 7310b2d27e5SStanislaw Gruszka static const u8 null_addr[ETH_ALEN] = {}; 7320b2d27e5SStanislaw Gruszka int i; 7330b2d27e5SStanislaw Gruszka 73498df2baeSLorenzo Bianconi ether_addr_copy(dev->mphy.macaddr, addr); 73589a8607cSLorenzo Bianconi 73698df2baeSLorenzo Bianconi if (!is_valid_ether_addr(dev->mphy.macaddr)) { 73798df2baeSLorenzo Bianconi eth_random_addr(dev->mphy.macaddr); 7388d66af49SLorenzo Bianconi dev_info(dev->mt76.dev, 73989a8607cSLorenzo Bianconi "Invalid MAC address, using random address %pM\n", 74098df2baeSLorenzo Bianconi dev->mphy.macaddr); 74189a8607cSLorenzo Bianconi } 74289a8607cSLorenzo Bianconi 74398df2baeSLorenzo Bianconi mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mphy.macaddr)); 7448d66af49SLorenzo Bianconi mt76_wr(dev, MT_MAC_ADDR_DW1, 74598df2baeSLorenzo Bianconi get_unaligned_le16(dev->mphy.macaddr + 4) | 74689a8607cSLorenzo Bianconi FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 7470b2d27e5SStanislaw Gruszka 7480b2d27e5SStanislaw Gruszka mt76_wr(dev, MT_MAC_BSSID_DW0, 74998df2baeSLorenzo Bianconi get_unaligned_le32(dev->mphy.macaddr)); 7500b2d27e5SStanislaw Gruszka mt76_wr(dev, MT_MAC_BSSID_DW1, 75198df2baeSLorenzo Bianconi get_unaligned_le16(dev->mphy.macaddr + 4) | 7520b2d27e5SStanislaw Gruszka FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 APs + 8 STAs */ 7530b2d27e5SStanislaw Gruszka MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT); 754f27469a9SMarkus Theil /* enable 7 additional beacon slots and control them with bypass mask */ 755f27469a9SMarkus Theil mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 7); 7560b2d27e5SStanislaw Gruszka 7570b2d27e5SStanislaw Gruszka for (i = 0; i < 16; i++) 7580b2d27e5SStanislaw Gruszka mt76x02_mac_set_bssid(dev, i, null_addr); 75989a8607cSLorenzo Bianconi } 76089a8607cSLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 761d9f8934eSLorenzo Bianconi 762d9f8934eSLorenzo Bianconi static int 763d9f8934eSLorenzo Bianconi mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 764d9f8934eSLorenzo Bianconi { 765d9f8934eSLorenzo Bianconi struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 766d9f8934eSLorenzo Bianconi 767d9f8934eSLorenzo Bianconi rssi += cal->rssi_offset[chain]; 768d9f8934eSLorenzo Bianconi rssi -= cal->lna_gain; 769d9f8934eSLorenzo Bianconi 770d9f8934eSLorenzo Bianconi return rssi; 771d9f8934eSLorenzo Bianconi } 772d9f8934eSLorenzo Bianconi 773d9f8934eSLorenzo Bianconi int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 774d9f8934eSLorenzo Bianconi void *rxi) 775d9f8934eSLorenzo Bianconi { 776d9f8934eSLorenzo Bianconi struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 777e195dad1SFelix Fietkau struct ieee80211_hdr *hdr; 778d9f8934eSLorenzo Bianconi struct mt76x02_rxwi *rxwi = rxi; 779d9f8934eSLorenzo Bianconi struct mt76x02_sta *sta; 780d9f8934eSLorenzo Bianconi u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 781d9f8934eSLorenzo Bianconi u32 ctl = le32_to_cpu(rxwi->ctl); 782d9f8934eSLorenzo Bianconi u16 rate = le16_to_cpu(rxwi->rate); 783d9f8934eSLorenzo Bianconi u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 784d9f8934eSLorenzo Bianconi bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 785b9027e08SLorenzo Bianconi int pad_len = 0, nstreams = dev->mphy.chainmask & 0xf; 786d9f8934eSLorenzo Bianconi s8 signal; 787d9f8934eSLorenzo Bianconi u8 pn_len; 788d9f8934eSLorenzo Bianconi u8 wcid; 789d9f8934eSLorenzo Bianconi int len; 790d9f8934eSLorenzo Bianconi 791011849e0SFelix Fietkau if (!test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) 792d9f8934eSLorenzo Bianconi return -EINVAL; 793d9f8934eSLorenzo Bianconi 794d9f8934eSLorenzo Bianconi if (rxinfo & MT_RXINFO_L2PAD) 795d9f8934eSLorenzo Bianconi pad_len += 2; 796d9f8934eSLorenzo Bianconi 797d9f8934eSLorenzo Bianconi if (rxinfo & MT_RXINFO_DECRYPT) { 798d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_DECRYPTED; 799d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_MMIC_STRIPPED; 800d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_MIC_STRIPPED; 801d9f8934eSLorenzo Bianconi status->flag |= RX_FLAG_IV_STRIPPED; 802d9f8934eSLorenzo Bianconi } 803d9f8934eSLorenzo Bianconi 804d9f8934eSLorenzo Bianconi wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 805d9f8934eSLorenzo Bianconi sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 806d9f8934eSLorenzo Bianconi status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 807d9f8934eSLorenzo Bianconi 808d9f8934eSLorenzo Bianconi len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 809d9f8934eSLorenzo Bianconi pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 810d9f8934eSLorenzo Bianconi if (pn_len) { 811d9f8934eSLorenzo Bianconi int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 812d9f8934eSLorenzo Bianconi u8 *data = skb->data + offset; 813d9f8934eSLorenzo Bianconi 814d9f8934eSLorenzo Bianconi status->iv[0] = data[7]; 815d9f8934eSLorenzo Bianconi status->iv[1] = data[6]; 816d9f8934eSLorenzo Bianconi status->iv[2] = data[5]; 817d9f8934eSLorenzo Bianconi status->iv[3] = data[4]; 818d9f8934eSLorenzo Bianconi status->iv[4] = data[1]; 819d9f8934eSLorenzo Bianconi status->iv[5] = data[0]; 820d9f8934eSLorenzo Bianconi 821d9f8934eSLorenzo Bianconi /* 822d9f8934eSLorenzo Bianconi * Driver CCMP validation can't deal with fragments. 823d9f8934eSLorenzo Bianconi * Let mac80211 take care of it. 824d9f8934eSLorenzo Bianconi */ 825d9f8934eSLorenzo Bianconi if (rxinfo & MT_RXINFO_FRAG) { 826d9f8934eSLorenzo Bianconi status->flag &= ~RX_FLAG_IV_STRIPPED; 827d9f8934eSLorenzo Bianconi } else { 828d9f8934eSLorenzo Bianconi pad_len += pn_len << 2; 829d9f8934eSLorenzo Bianconi len -= pn_len << 2; 830d9f8934eSLorenzo Bianconi } 831d9f8934eSLorenzo Bianconi } 832d9f8934eSLorenzo Bianconi 833d9f8934eSLorenzo Bianconi mt76x02_remove_hdr_pad(skb, pad_len); 834d9f8934eSLorenzo Bianconi 835d9f8934eSLorenzo Bianconi if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 836d9f8934eSLorenzo Bianconi status->aggr = true; 837d9f8934eSLorenzo Bianconi 838d515fdcaSFelix Fietkau if (rxinfo & MT_RXINFO_AMPDU) { 839d515fdcaSFelix Fietkau status->flag |= RX_FLAG_AMPDU_DETAILS; 84030684481SFelix Fietkau status->ampdu_ref = dev->ampdu_ref; 841d515fdcaSFelix Fietkau 842d515fdcaSFelix Fietkau /* 843d515fdcaSFelix Fietkau * When receiving an A-MPDU subframe and RSSI info is not valid, 844d515fdcaSFelix Fietkau * we can assume that more subframes belonging to the same A-MPDU 845d515fdcaSFelix Fietkau * are coming. The last one will have valid RSSI info 846d515fdcaSFelix Fietkau */ 8475ce09c1aSFelix Fietkau if (rxinfo & MT_RXINFO_RSSI) { 84830684481SFelix Fietkau if (!++dev->ampdu_ref) 84930684481SFelix Fietkau dev->ampdu_ref++; 850d515fdcaSFelix Fietkau } 851d515fdcaSFelix Fietkau } 852d515fdcaSFelix Fietkau 853d9f8934eSLorenzo Bianconi if (WARN_ON_ONCE(len > skb->len)) 854d9f8934eSLorenzo Bianconi return -EINVAL; 855d9f8934eSLorenzo Bianconi 856d9f8934eSLorenzo Bianconi pskb_trim(skb, len); 857d9f8934eSLorenzo Bianconi 858d9f8934eSLorenzo Bianconi status->chains = BIT(0); 859d9f8934eSLorenzo Bianconi signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 8609f688473SFelix Fietkau status->chain_signal[0] = signal; 8619f688473SFelix Fietkau if (nstreams > 1) { 8629f688473SFelix Fietkau status->chains |= BIT(1); 8639f688473SFelix Fietkau status->chain_signal[1] = mt76x02_mac_get_rssi(dev, 8649f688473SFelix Fietkau rxwi->rssi[1], 8659f688473SFelix Fietkau 1); 866d9f8934eSLorenzo Bianconi } 86796747a51SFelix Fietkau status->freq = dev->mphy.chandef.chan->center_freq; 86896747a51SFelix Fietkau status->band = dev->mphy.chandef.chan->band; 869d9f8934eSLorenzo Bianconi 870e195dad1SFelix Fietkau hdr = (struct ieee80211_hdr *)skb->data; 871e195dad1SFelix Fietkau status->qos_ctl = *ieee80211_get_qos_ctl(hdr); 872d9f8934eSLorenzo Bianconi status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 873d9f8934eSLorenzo Bianconi 874f832898dSLorenzo Bianconi return mt76x02_mac_process_rate(dev, status, rate); 875d9f8934eSLorenzo Bianconi } 8763e2342edSLorenzo Bianconi 8773e2342edSLorenzo Bianconi void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 8783e2342edSLorenzo Bianconi { 8793e2342edSLorenzo Bianconi struct mt76x02_tx_status stat = {}; 8803e2342edSLorenzo Bianconi u8 update = 1; 8813e2342edSLorenzo Bianconi bool ret; 8823e2342edSLorenzo Bianconi 883011849e0SFelix Fietkau if (!test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) 8843e2342edSLorenzo Bianconi return; 8853e2342edSLorenzo Bianconi 8863e2342edSLorenzo Bianconi trace_mac_txstat_poll(dev); 8873e2342edSLorenzo Bianconi 8883e2342edSLorenzo Bianconi while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 8896fe53337SFelix Fietkau if (!spin_trylock(&dev->txstatus_fifo_lock)) 8906fe53337SFelix Fietkau break; 8916fe53337SFelix Fietkau 8928d66af49SLorenzo Bianconi ret = mt76x02_mac_load_tx_status(dev, &stat); 8936fe53337SFelix Fietkau spin_unlock(&dev->txstatus_fifo_lock); 8943e2342edSLorenzo Bianconi 8953e2342edSLorenzo Bianconi if (!ret) 8963e2342edSLorenzo Bianconi break; 8973e2342edSLorenzo Bianconi 8983e2342edSLorenzo Bianconi if (!irq) { 8998d66af49SLorenzo Bianconi mt76x02_send_tx_status(dev, &stat, &update); 9003e2342edSLorenzo Bianconi continue; 9013e2342edSLorenzo Bianconi } 9023e2342edSLorenzo Bianconi 9033e2342edSLorenzo Bianconi kfifo_put(&dev->txstatus_fifo, stat); 9043e2342edSLorenzo Bianconi } 9053e2342edSLorenzo Bianconi } 906466495b1SLorenzo Bianconi 907d80e52c7SFelix Fietkau void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 908466495b1SLorenzo Bianconi { 909466495b1SLorenzo Bianconi struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 91088046b2cSFelix Fietkau struct mt76x02_txwi *txwi; 911f3950a41SLorenzo Bianconi u8 *txwi_ptr; 912466495b1SLorenzo Bianconi 91388046b2cSFelix Fietkau if (!e->txwi) { 914466495b1SLorenzo Bianconi dev_kfree_skb_any(e->skb); 91588046b2cSFelix Fietkau return; 91688046b2cSFelix Fietkau } 91788046b2cSFelix Fietkau 91888046b2cSFelix Fietkau mt76x02_mac_poll_tx_status(dev, false); 91988046b2cSFelix Fietkau 920f3950a41SLorenzo Bianconi txwi_ptr = mt76_get_txwi_ptr(mdev, e->txwi); 921f3950a41SLorenzo Bianconi txwi = (struct mt76x02_txwi *)txwi_ptr; 9225498974bSLorenzo Bianconi trace_mac_txdone(mdev, txwi->wcid, txwi->pktid); 92388046b2cSFelix Fietkau 924e1378e52SFelix Fietkau mt76_tx_complete_skb(mdev, e->wcid, e->skb); 925466495b1SLorenzo Bianconi } 926466495b1SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 92762503186SLorenzo Bianconi 92820ce270eSStanislaw Gruszka void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val) 929317ed42bSLorenzo Bianconi { 930317ed42bSLorenzo Bianconi u32 data = 0; 931317ed42bSLorenzo Bianconi 932317ed42bSLorenzo Bianconi if (val != ~0) 933317ed42bSLorenzo Bianconi data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) | 934317ed42bSLorenzo Bianconi MT_PROT_CFG_RTS_THRESH; 935317ed42bSLorenzo Bianconi 936317ed42bSLorenzo Bianconi mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); 937317ed42bSLorenzo Bianconi 938317ed42bSLorenzo Bianconi mt76_rmw(dev, MT_CCK_PROT_CFG, 939317ed42bSLorenzo Bianconi MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 940317ed42bSLorenzo Bianconi mt76_rmw(dev, MT_OFDM_PROT_CFG, 941317ed42bSLorenzo Bianconi MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 942317ed42bSLorenzo Bianconi } 943317ed42bSLorenzo Bianconi 94426a7b547SStanislaw Gruszka void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot, 94526a7b547SStanislaw Gruszka int ht_mode) 94626a7b547SStanislaw Gruszka { 94726a7b547SStanislaw Gruszka int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION; 94826a7b547SStanislaw Gruszka bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 94926a7b547SStanislaw Gruszka u32 prot[6]; 95026a7b547SStanislaw Gruszka u32 vht_prot[3]; 95126a7b547SStanislaw Gruszka int i; 95226a7b547SStanislaw Gruszka u16 rts_thr; 95326a7b547SStanislaw Gruszka 95426a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(prot); i++) { 95526a7b547SStanislaw Gruszka prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4); 95626a7b547SStanislaw Gruszka prot[i] &= ~MT_PROT_CFG_CTRL; 95726a7b547SStanislaw Gruszka if (i >= 2) 95826a7b547SStanislaw Gruszka prot[i] &= ~MT_PROT_CFG_RATE; 95926a7b547SStanislaw Gruszka } 96026a7b547SStanislaw Gruszka 96126a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(vht_prot); i++) { 96226a7b547SStanislaw Gruszka vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4); 96326a7b547SStanislaw Gruszka vht_prot[i] &= ~(MT_PROT_CFG_CTRL | MT_PROT_CFG_RATE); 96426a7b547SStanislaw Gruszka } 96526a7b547SStanislaw Gruszka 96626a7b547SStanislaw Gruszka rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH); 96726a7b547SStanislaw Gruszka 96826a7b547SStanislaw Gruszka if (rts_thr != 0xffff) 96926a7b547SStanislaw Gruszka prot[0] |= MT_PROT_CTRL_RTS_CTS; 97026a7b547SStanislaw Gruszka 97126a7b547SStanislaw Gruszka if (legacy_prot) { 97226a7b547SStanislaw Gruszka prot[1] |= MT_PROT_CTRL_CTS2SELF; 97326a7b547SStanislaw Gruszka 97426a7b547SStanislaw Gruszka prot[2] |= MT_PROT_RATE_CCK_11; 97526a7b547SStanislaw Gruszka prot[3] |= MT_PROT_RATE_CCK_11; 97626a7b547SStanislaw Gruszka prot[4] |= MT_PROT_RATE_CCK_11; 97726a7b547SStanislaw Gruszka prot[5] |= MT_PROT_RATE_CCK_11; 97826a7b547SStanislaw Gruszka 97926a7b547SStanislaw Gruszka vht_prot[0] |= MT_PROT_RATE_CCK_11; 98026a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_RATE_CCK_11; 98126a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_RATE_CCK_11; 98226a7b547SStanislaw Gruszka } else { 98326a7b547SStanislaw Gruszka if (rts_thr != 0xffff) 98426a7b547SStanislaw Gruszka prot[1] |= MT_PROT_CTRL_RTS_CTS; 98526a7b547SStanislaw Gruszka 98626a7b547SStanislaw Gruszka prot[2] |= MT_PROT_RATE_OFDM_24; 98726a7b547SStanislaw Gruszka prot[3] |= MT_PROT_RATE_DUP_OFDM_24; 98826a7b547SStanislaw Gruszka prot[4] |= MT_PROT_RATE_OFDM_24; 98926a7b547SStanislaw Gruszka prot[5] |= MT_PROT_RATE_DUP_OFDM_24; 99026a7b547SStanislaw Gruszka 99126a7b547SStanislaw Gruszka vht_prot[0] |= MT_PROT_RATE_OFDM_24; 99226a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_RATE_DUP_OFDM_24; 99326a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_RATE_SGI_OFDM_24; 99426a7b547SStanislaw Gruszka } 99526a7b547SStanislaw Gruszka 99626a7b547SStanislaw Gruszka switch (mode) { 99726a7b547SStanislaw Gruszka case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 99826a7b547SStanislaw Gruszka case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 99926a7b547SStanislaw Gruszka prot[2] |= MT_PROT_CTRL_RTS_CTS; 100026a7b547SStanislaw Gruszka prot[3] |= MT_PROT_CTRL_RTS_CTS; 100126a7b547SStanislaw Gruszka prot[4] |= MT_PROT_CTRL_RTS_CTS; 100226a7b547SStanislaw Gruszka prot[5] |= MT_PROT_CTRL_RTS_CTS; 100326a7b547SStanislaw Gruszka vht_prot[0] |= MT_PROT_CTRL_RTS_CTS; 100426a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 100526a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 100626a7b547SStanislaw Gruszka break; 100726a7b547SStanislaw Gruszka case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 100826a7b547SStanislaw Gruszka prot[3] |= MT_PROT_CTRL_RTS_CTS; 100926a7b547SStanislaw Gruszka prot[5] |= MT_PROT_CTRL_RTS_CTS; 101026a7b547SStanislaw Gruszka vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 101126a7b547SStanislaw Gruszka vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 101226a7b547SStanislaw Gruszka break; 101326a7b547SStanislaw Gruszka } 101426a7b547SStanislaw Gruszka 101526a7b547SStanislaw Gruszka if (non_gf) { 101626a7b547SStanislaw Gruszka prot[4] |= MT_PROT_CTRL_RTS_CTS; 101726a7b547SStanislaw Gruszka prot[5] |= MT_PROT_CTRL_RTS_CTS; 101826a7b547SStanislaw Gruszka } 101926a7b547SStanislaw Gruszka 102026a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(prot); i++) 102126a7b547SStanislaw Gruszka mt76_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]); 102226a7b547SStanislaw Gruszka 102326a7b547SStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(vht_prot); i++) 102426a7b547SStanislaw Gruszka mt76_wr(dev, MT_TX_PROT_CFG6 + i * 4, vht_prot[i]); 102526a7b547SStanislaw Gruszka } 102626a7b547SStanislaw Gruszka 1027c560b137SRyder Lee void mt76x02_update_channel(struct mt76_phy *mphy) 102862503186SLorenzo Bianconi { 1029c560b137SRyder Lee struct mt76x02_dev *dev = container_of(mphy->dev, struct mt76x02_dev, mt76); 103062503186SLorenzo Bianconi struct mt76_channel_state *state; 103162503186SLorenzo Bianconi 1032c560b137SRyder Lee state = mphy->chan_state; 1033aec65e48SFelix Fietkau state->cc_busy += mt76_rr(dev, MT_CH_BUSY); 1034237312c5SLorenzo Bianconi 1035237312c5SLorenzo Bianconi spin_lock_bh(&dev->mt76.cc_lock); 1036355f8d00SFelix Fietkau state->cc_tx += dev->tx_airtime; 1037355f8d00SFelix Fietkau dev->tx_airtime = 0; 1038237312c5SLorenzo Bianconi spin_unlock_bh(&dev->mt76.cc_lock); 103962503186SLorenzo Bianconi } 104062503186SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_update_channel); 10417dd73588SLorenzo Bianconi 104273556561SLorenzo Bianconi static void mt76x02_check_mac_err(struct mt76x02_dev *dev) 104373556561SLorenzo Bianconi { 10442aa6c0fbSFelix Fietkau if (dev->mt76.beacon_mask) { 10452aa6c0fbSFelix Fietkau if (mt76_rr(dev, MT_TX_STA_0) & MT_TX_STA_0_BEACONS) { 10462aa6c0fbSFelix Fietkau dev->beacon_hang_check = 0; 10472aa6c0fbSFelix Fietkau return; 10482aa6c0fbSFelix Fietkau } 104973556561SLorenzo Bianconi 10508916e4e5SFelix Fietkau if (dev->beacon_hang_check < 10) 105173556561SLorenzo Bianconi return; 105273556561SLorenzo Bianconi 10532aa6c0fbSFelix Fietkau } else { 10542aa6c0fbSFelix Fietkau u32 val = mt76_rr(dev, 0x10f4); 10552aa6c0fbSFelix Fietkau if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) 10562aa6c0fbSFelix Fietkau return; 10572aa6c0fbSFelix Fietkau } 10582aa6c0fbSFelix Fietkau 10592aa6c0fbSFelix Fietkau dev_err(dev->mt76.dev, "MAC error detected\n"); 10602aa6c0fbSFelix Fietkau 10612aa6c0fbSFelix Fietkau mt76_wr(dev, MT_MAC_SYS_CTRL, 0); 10628916e4e5SFelix Fietkau if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) { 10638916e4e5SFelix Fietkau dev_err(dev->mt76.dev, "MAC stop failed\n"); 10648916e4e5SFelix Fietkau goto out; 10658916e4e5SFelix Fietkau } 106673556561SLorenzo Bianconi 10678916e4e5SFelix Fietkau dev->beacon_hang_check = 0; 106873556561SLorenzo Bianconi mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); 106973556561SLorenzo Bianconi udelay(10); 10708916e4e5SFelix Fietkau 10718916e4e5SFelix Fietkau out: 1072374eb1b5SLorenzo Bianconi mt76_wr(dev, MT_MAC_SYS_CTRL, 107373556561SLorenzo Bianconi MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 107473556561SLorenzo Bianconi } 107573556561SLorenzo Bianconi 1076f82ce8d9SLorenzo Bianconi static void 1077f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(struct mt76x02_dev *dev, bool enable) 1078f82ce8d9SLorenzo Bianconi { 1079f82ce8d9SLorenzo Bianconi if (enable) { 1080f82ce8d9SLorenzo Bianconi u32 data; 1081f82ce8d9SLorenzo Bianconi 1082f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 1083f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 1084f82ce8d9SLorenzo Bianconi /* enable pa-lna */ 1085f82ce8d9SLorenzo Bianconi data = mt76_rr(dev, MT_TX_PIN_CFG); 1086f82ce8d9SLorenzo Bianconi data |= MT_TX_PIN_CFG_TXANT | 1087f82ce8d9SLorenzo Bianconi MT_TX_PIN_CFG_RXANT | 1088f82ce8d9SLorenzo Bianconi MT_TX_PIN_RFTR_EN | 1089f82ce8d9SLorenzo Bianconi MT_TX_PIN_TRSW_EN; 1090f82ce8d9SLorenzo Bianconi mt76_wr(dev, MT_TX_PIN_CFG, data); 1091f82ce8d9SLorenzo Bianconi } else { 1092f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 1093f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 1094f82ce8d9SLorenzo Bianconi /* disable pa-lna */ 1095f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT); 1096f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT); 1097f82ce8d9SLorenzo Bianconi } 1098f82ce8d9SLorenzo Bianconi dev->ed_tx_blocked = !enable; 1099f82ce8d9SLorenzo Bianconi } 1100f82ce8d9SLorenzo Bianconi 1101a78f1547SLorenzo Bianconi void mt76x02_edcca_init(struct mt76x02_dev *dev) 1102f82ce8d9SLorenzo Bianconi { 1103f82ce8d9SLorenzo Bianconi dev->ed_trigger = 0; 1104f82ce8d9SLorenzo Bianconi dev->ed_silent = 0; 1105f82ce8d9SLorenzo Bianconi 1106a78f1547SLorenzo Bianconi if (dev->ed_monitor) { 110796747a51SFelix Fietkau struct ieee80211_channel *chan = dev->mphy.chandef.chan; 1108f82ce8d9SLorenzo Bianconi u8 ed_th = chan->band == NL80211_BAND_5GHZ ? 0x0e : 0x20; 1109f82ce8d9SLorenzo Bianconi 1110f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 1111f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 1112f82ce8d9SLorenzo Bianconi mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0), 1113f82ce8d9SLorenzo Bianconi ed_th << 8 | ed_th); 11145c8b0a33SFelix Fietkau mt76_set(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); 1115f82ce8d9SLorenzo Bianconi } else { 1116f82ce8d9SLorenzo Bianconi mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 1117f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 1118f82ce8d9SLorenzo Bianconi if (is_mt76x2(dev)) { 1119f82ce8d9SLorenzo Bianconi mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); 11205c8b0a33SFelix Fietkau mt76_set(dev, MT_TXOP_HLDR_ET, 11215c8b0a33SFelix Fietkau MT_TXOP_HLDR_TX40M_BLK_EN); 1122f82ce8d9SLorenzo Bianconi } else { 1123f82ce8d9SLorenzo Bianconi mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464); 1124f82ce8d9SLorenzo Bianconi mt76_clear(dev, MT_TXOP_HLDR_ET, 1125f82ce8d9SLorenzo Bianconi MT_TXOP_HLDR_TX40M_BLK_EN); 1126f82ce8d9SLorenzo Bianconi } 1127f82ce8d9SLorenzo Bianconi } 1128f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(dev, true); 1129a0ac8061SFelix Fietkau dev->ed_monitor_learning = true; 1130c15b7cefSFelix Fietkau 1131c15b7cefSFelix Fietkau /* clear previous CCA timer value */ 1132c15b7cefSFelix Fietkau mt76_rr(dev, MT_ED_CCA_TIMER); 1133ccdaf7b4SFelix Fietkau dev->ed_time = ktime_get_boottime(); 1134f82ce8d9SLorenzo Bianconi } 1135f82ce8d9SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_edcca_init); 1136f82ce8d9SLorenzo Bianconi 1137f1906fb2SFelix Fietkau #define MT_EDCCA_TH 92 1138f82ce8d9SLorenzo Bianconi #define MT_EDCCA_BLOCK_TH 2 1139a0ac8061SFelix Fietkau #define MT_EDCCA_LEARN_TH 50 1140a0ac8061SFelix Fietkau #define MT_EDCCA_LEARN_CCA 180 1141a0ac8061SFelix Fietkau #define MT_EDCCA_LEARN_TIMEOUT (20 * HZ) 1142a0ac8061SFelix Fietkau 1143f82ce8d9SLorenzo Bianconi static void mt76x02_edcca_check(struct mt76x02_dev *dev) 1144f82ce8d9SLorenzo Bianconi { 1145ccdaf7b4SFelix Fietkau ktime_t cur_time; 1146ccdaf7b4SFelix Fietkau u32 active, val, busy; 1147f82ce8d9SLorenzo Bianconi 1148ccdaf7b4SFelix Fietkau cur_time = ktime_get_boottime(); 1149f82ce8d9SLorenzo Bianconi val = mt76_rr(dev, MT_ED_CCA_TIMER); 1150ccdaf7b4SFelix Fietkau 1151ccdaf7b4SFelix Fietkau active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 1152ccdaf7b4SFelix Fietkau dev->ed_time = cur_time; 1153ccdaf7b4SFelix Fietkau 1154ccdaf7b4SFelix Fietkau busy = (val * 100) / active; 1155f82ce8d9SLorenzo Bianconi busy = min_t(u32, busy, 100); 1156f82ce8d9SLorenzo Bianconi 1157f82ce8d9SLorenzo Bianconi if (busy > MT_EDCCA_TH) { 1158f82ce8d9SLorenzo Bianconi dev->ed_trigger++; 1159f82ce8d9SLorenzo Bianconi dev->ed_silent = 0; 1160f82ce8d9SLorenzo Bianconi } else { 1161f82ce8d9SLorenzo Bianconi dev->ed_silent++; 1162f82ce8d9SLorenzo Bianconi dev->ed_trigger = 0; 1163f82ce8d9SLorenzo Bianconi } 1164f82ce8d9SLorenzo Bianconi 1165a0ac8061SFelix Fietkau if (dev->cal.agc_lowest_gain && 1166a0ac8061SFelix Fietkau dev->cal.false_cca > MT_EDCCA_LEARN_CCA && 1167a0ac8061SFelix Fietkau dev->ed_trigger > MT_EDCCA_LEARN_TH) { 1168a0ac8061SFelix Fietkau dev->ed_monitor_learning = false; 1169a0ac8061SFelix Fietkau dev->ed_trigger_timeout = jiffies + 20 * HZ; 1170a0ac8061SFelix Fietkau } else if (!dev->ed_monitor_learning && 1171a0ac8061SFelix Fietkau time_is_after_jiffies(dev->ed_trigger_timeout)) { 1172a0ac8061SFelix Fietkau dev->ed_monitor_learning = true; 1173a0ac8061SFelix Fietkau mt76x02_edcca_tx_enable(dev, true); 1174a0ac8061SFelix Fietkau } 1175a0ac8061SFelix Fietkau 1176a0ac8061SFelix Fietkau if (dev->ed_monitor_learning) 1177a0ac8061SFelix Fietkau return; 1178a0ac8061SFelix Fietkau 1179a0ac8061SFelix Fietkau if (dev->ed_trigger > MT_EDCCA_BLOCK_TH && !dev->ed_tx_blocked) 1180f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(dev, false); 1181a0ac8061SFelix Fietkau else if (dev->ed_silent > MT_EDCCA_BLOCK_TH && dev->ed_tx_blocked) 1182f82ce8d9SLorenzo Bianconi mt76x02_edcca_tx_enable(dev, true); 1183f82ce8d9SLorenzo Bianconi } 1184f82ce8d9SLorenzo Bianconi 11857dd73588SLorenzo Bianconi void mt76x02_mac_work(struct work_struct *work) 11867dd73588SLorenzo Bianconi { 11877dd73588SLorenzo Bianconi struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 1188a782f8bfSLorenzo Bianconi mphy.mac_work.work); 11897dd73588SLorenzo Bianconi int i, idx; 11907dd73588SLorenzo Bianconi 11914989338eSLorenzo Bianconi mutex_lock(&dev->mt76.mutex); 11924989338eSLorenzo Bianconi 1193c560b137SRyder Lee mt76_update_survey(&dev->mphy); 11947dd73588SLorenzo Bianconi for (i = 0, idx = 0; i < 16; i++) { 11957dd73588SLorenzo Bianconi u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 11967dd73588SLorenzo Bianconi 1197d107501aSLorenzo Bianconi dev->mphy.aggr_stats[idx++] += val & 0xffff; 1198d107501aSLorenzo Bianconi dev->mphy.aggr_stats[idx++] += val >> 16; 11997dd73588SLorenzo Bianconi } 12007dd73588SLorenzo Bianconi 120173556561SLorenzo Bianconi mt76x02_check_mac_err(dev); 120273556561SLorenzo Bianconi 1203f82ce8d9SLorenzo Bianconi if (dev->ed_monitor) 1204f82ce8d9SLorenzo Bianconi mt76x02_edcca_check(dev); 1205f82ce8d9SLorenzo Bianconi 12064989338eSLorenzo Bianconi mutex_unlock(&dev->mt76.mutex); 12074989338eSLorenzo Bianconi 1208c02f86eeSLorenzo Bianconi mt76_tx_status_check(&dev->mt76, false); 120988046b2cSFelix Fietkau 1210a782f8bfSLorenzo Bianconi ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 12112e405024SFelix Fietkau MT_MAC_WORK_INTERVAL); 12127dd73588SLorenzo Bianconi } 1213dc33b251SLorenzo Bianconi 1214aec65e48SFelix Fietkau void mt76x02_mac_cc_reset(struct mt76x02_dev *dev) 1215aec65e48SFelix Fietkau { 121696747a51SFelix Fietkau dev->mphy.survey_time = ktime_get_boottime(); 1217aec65e48SFelix Fietkau 1218b02f42f4SFelix Fietkau mt76_wr(dev, MT_CH_TIME_CFG, 1219b02f42f4SFelix Fietkau MT_CH_TIME_CFG_TIMER_EN | 1220b02f42f4SFelix Fietkau MT_CH_TIME_CFG_TX_AS_BUSY | 1221b02f42f4SFelix Fietkau MT_CH_TIME_CFG_RX_AS_BUSY | 1222b02f42f4SFelix Fietkau MT_CH_TIME_CFG_NAV_AS_BUSY | 1223b02f42f4SFelix Fietkau MT_CH_TIME_CFG_EIFS_AS_BUSY | 1224b02f42f4SFelix Fietkau MT_CH_CCA_RC_EN | 1225b02f42f4SFelix Fietkau FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1)); 1226b02f42f4SFelix Fietkau 1227aec65e48SFelix Fietkau /* channel cycle counters read-and-clear */ 1228aec65e48SFelix Fietkau mt76_rr(dev, MT_CH_BUSY); 1229aec65e48SFelix Fietkau mt76_rr(dev, MT_CH_IDLE); 1230aec65e48SFelix Fietkau } 1231aec65e48SFelix Fietkau EXPORT_SYMBOL_GPL(mt76x02_mac_cc_reset); 1232aec65e48SFelix Fietkau 1233dc33b251SLorenzo Bianconi void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr) 1234dc33b251SLorenzo Bianconi { 1235dc33b251SLorenzo Bianconi idx &= 7; 1236dc33b251SLorenzo Bianconi mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr)); 1237dc33b251SLorenzo Bianconi mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR, 1238dc33b251SLorenzo Bianconi get_unaligned_le16(addr + 4)); 1239dc33b251SLorenzo Bianconi } 1240