1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 #define FW_FEATURE_SET_ENCRYPT BIT(0) 10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 11 #define FW_FEATURE_ENCRY_MODE BIT(4) 12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5) 13 #define FW_FEATURE_NON_DL BIT(6) 14 15 #define DL_MODE_ENCRYPT BIT(0) 16 #define DL_MODE_KEY_IDX GENMASK(2, 1) 17 #define DL_MODE_RESET_SEC_IV BIT(3) 18 #define DL_MODE_WORKING_PDA_CR4 BIT(4) 19 #define DL_MODE_VALID_RAM_ENTRY BIT(5) 20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6) 21 #define DL_MODE_NEED_RSP BIT(31) 22 23 #define FW_START_OVERRIDE BIT(0) 24 #define FW_START_WORKING_PDA_CR4 BIT(2) 25 #define FW_START_WORKING_PDA_DSP BIT(3) 26 27 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) 28 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0) 29 #define PATCH_SEC_TYPE_INFO 0x2 30 31 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24) 32 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00 33 #define PATCH_SEC_ENC_TYPE_AES 0x01 34 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02 35 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0) 36 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0) 37 38 enum { 39 FW_TYPE_DEFAULT = 0, 40 FW_TYPE_CLC = 2, 41 FW_TYPE_MAX_NUM = 255 42 }; 43 44 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 45 #define MCU_PKT_ID 0xa0 46 47 struct mt76_connac2_mcu_txd { 48 __le32 txd[8]; 49 50 __le16 len; 51 __le16 pq_id; 52 53 u8 cid; 54 u8 pkt_type; 55 u8 set_query; /* FW don't care */ 56 u8 seq; 57 58 u8 uc_d2b0_rev; 59 u8 ext_cid; 60 u8 s2d_index; 61 u8 ext_cid_ack; 62 63 u32 rsv[5]; 64 } __packed __aligned(4); 65 66 /** 67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3 68 * @txd: hardware descriptor 69 * @len: total length not including txd 70 * @cid: command identifier 71 * @pkt_type: must be 0xa0 (cmd packet by long format) 72 * @frag_n: fragment number 73 * @seq: sequence number 74 * @checksum: 0 mean there is no checksum 75 * @s2d_index: index for command source and destination 76 * Definition | value | note 77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 81 * 82 * @option: command option 83 * BIT[0]: UNI_CMD_OPT_BIT_ACK 84 * set to 1 to request a fw reply 85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 86 * is set, mcu firmware will send response event EID = 0x01 87 * (UNI_EVENT_ID_CMD_RESULT) to the host. 88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 89 * 0: original command 90 * 1: unified command 91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 92 * 0: QUERY command 93 * 1: SET command 94 */ 95 struct mt76_connac2_mcu_uni_txd { 96 __le32 txd[8]; 97 98 /* DW1 */ 99 __le16 len; 100 __le16 cid; 101 102 /* DW2 */ 103 u8 rsv; 104 u8 pkt_type; 105 u8 frag_n; 106 u8 seq; 107 108 /* DW3 */ 109 __le16 checksum; 110 u8 s2d_index; 111 u8 option; 112 113 /* DW4 */ 114 u8 rsv1[4]; 115 } __packed __aligned(4); 116 117 struct mt76_connac2_mcu_rxd { 118 __le32 rxd[6]; 119 120 __le16 len; 121 __le16 pkt_type_id; 122 123 u8 eid; 124 u8 seq; 125 u8 option; 126 u8 rsv; 127 u8 ext_eid; 128 u8 rsv1[2]; 129 u8 s2d_index; 130 131 u8 tlv[]; 132 }; 133 134 struct mt76_connac2_patch_hdr { 135 char build_date[16]; 136 char platform[4]; 137 __be32 hw_sw_ver; 138 __be32 patch_ver; 139 __be16 checksum; 140 u16 rsv; 141 struct { 142 __be32 patch_ver; 143 __be32 subsys; 144 __be32 feature; 145 __be32 n_region; 146 __be32 crc; 147 u32 rsv[11]; 148 } desc; 149 } __packed; 150 151 struct mt76_connac2_patch_sec { 152 __be32 type; 153 __be32 offs; 154 __be32 size; 155 union { 156 __be32 spec[13]; 157 struct { 158 __be32 addr; 159 __be32 len; 160 __be32 sec_key_idx; 161 __be32 align_len; 162 u32 rsv[9]; 163 } info; 164 }; 165 } __packed; 166 167 struct mt76_connac2_fw_trailer { 168 u8 chip_id; 169 u8 eco_code; 170 u8 n_region; 171 u8 format_ver; 172 u8 format_flag; 173 u8 rsv[2]; 174 char fw_ver[10]; 175 char build_date[15]; 176 __le32 crc; 177 } __packed; 178 179 struct mt76_connac2_fw_region { 180 __le32 decomp_crc; 181 __le32 decomp_len; 182 __le32 decomp_blk_sz; 183 u8 rsv[4]; 184 __le32 addr; 185 __le32 len; 186 u8 feature_set; 187 u8 type; 188 u8 rsv1[14]; 189 } __packed; 190 191 struct tlv { 192 __le16 tag; 193 __le16 len; 194 u8 data[]; 195 } __packed; 196 197 struct bss_info_omac { 198 __le16 tag; 199 __le16 len; 200 u8 hw_bss_idx; 201 u8 omac_idx; 202 u8 band_idx; 203 u8 rsv0; 204 __le32 conn_type; 205 u32 rsv1; 206 } __packed; 207 208 struct bss_info_basic { 209 __le16 tag; 210 __le16 len; 211 __le32 network_type; 212 u8 active; 213 u8 rsv0; 214 __le16 bcn_interval; 215 u8 bssid[ETH_ALEN]; 216 u8 wmm_idx; 217 u8 dtim_period; 218 u8 bmc_wcid_lo; 219 u8 cipher; 220 u8 phy_mode; 221 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 222 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 223 u8 bmc_wcid_hi; /* high Byte and version */ 224 u8 rsv[2]; 225 } __packed; 226 227 struct bss_info_rf_ch { 228 __le16 tag; 229 __le16 len; 230 u8 pri_ch; 231 u8 center_ch0; 232 u8 center_ch1; 233 u8 bw; 234 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 235 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 236 u8 rsv[2]; 237 } __packed; 238 239 struct bss_info_ext_bss { 240 __le16 tag; 241 __le16 len; 242 __le32 mbss_tsf_offset; /* in unit of us */ 243 u8 rsv[8]; 244 } __packed; 245 246 enum { 247 BSS_INFO_OMAC, 248 BSS_INFO_BASIC, 249 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 250 BSS_INFO_PM, /* sta only */ 251 BSS_INFO_UAPSD, /* sta only */ 252 BSS_INFO_ROAM_DETECT, /* obsoleted */ 253 BSS_INFO_LQ_RM, /* obsoleted */ 254 BSS_INFO_EXT_BSS, 255 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 256 BSS_INFO_SYNC_MODE, /* obsoleted */ 257 BSS_INFO_RA, 258 BSS_INFO_HW_AMSDU, 259 BSS_INFO_BSS_COLOR, 260 BSS_INFO_HE_BASIC, 261 BSS_INFO_PROTECT_INFO, 262 BSS_INFO_OFFLOAD, 263 BSS_INFO_11V_MBSSID, 264 BSS_INFO_MAX_NUM 265 }; 266 267 /* sta_rec */ 268 269 struct sta_ntlv_hdr { 270 u8 rsv[2]; 271 __le16 tlv_num; 272 } __packed; 273 274 struct sta_req_hdr { 275 u8 bss_idx; 276 u8 wlan_idx_lo; 277 __le16 tlv_num; 278 u8 is_tlv_append; 279 u8 muar_idx; 280 u8 wlan_idx_hi; 281 u8 rsv; 282 } __packed; 283 284 struct sta_rec_basic { 285 __le16 tag; 286 __le16 len; 287 __le32 conn_type; 288 u8 conn_state; 289 u8 qos; 290 __le16 aid; 291 u8 peer_addr[ETH_ALEN]; 292 #define EXTRA_INFO_VER BIT(0) 293 #define EXTRA_INFO_NEW BIT(1) 294 __le16 extra_info; 295 } __packed; 296 297 struct sta_rec_ht { 298 __le16 tag; 299 __le16 len; 300 __le16 ht_cap; 301 u16 rsv; 302 } __packed; 303 304 struct sta_rec_vht { 305 __le16 tag; 306 __le16 len; 307 __le32 vht_cap; 308 __le16 vht_rx_mcs_map; 309 __le16 vht_tx_mcs_map; 310 /* mt7915 - mt7921 */ 311 u8 rts_bw_sig; 312 u8 rsv[3]; 313 } __packed; 314 315 struct sta_rec_uapsd { 316 __le16 tag; 317 __le16 len; 318 u8 dac_map; 319 u8 tac_map; 320 u8 max_sp; 321 u8 rsv0; 322 __le16 listen_interval; 323 u8 rsv1[2]; 324 } __packed; 325 326 struct sta_rec_ba { 327 __le16 tag; 328 __le16 len; 329 u8 tid; 330 u8 ba_type; 331 u8 amsdu; 332 u8 ba_en; 333 __le16 ssn; 334 __le16 winsize; 335 } __packed; 336 337 struct sta_rec_he { 338 __le16 tag; 339 __le16 len; 340 341 __le32 he_cap; 342 343 u8 t_frame_dur; 344 u8 max_ampdu_exp; 345 u8 bw_set; 346 u8 device_class; 347 u8 dcm_tx_mode; 348 u8 dcm_tx_max_nss; 349 u8 dcm_rx_mode; 350 u8 dcm_rx_max_nss; 351 u8 dcm_max_ru; 352 u8 punc_pream_rx; 353 u8 pkt_ext; 354 u8 rsv1; 355 356 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 357 358 u8 rsv2[2]; 359 } __packed; 360 361 struct sta_rec_he_v2 { 362 __le16 tag; 363 __le16 len; 364 u8 he_mac_cap[6]; 365 u8 he_phy_cap[11]; 366 u8 pkt_ext; 367 /* 0: BW80, 1: BW160, 2: BW8080 */ 368 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 369 } __packed; 370 371 struct sta_rec_amsdu { 372 __le16 tag; 373 __le16 len; 374 u8 max_amsdu_num; 375 u8 max_mpdu_size; 376 u8 amsdu_en; 377 u8 rsv; 378 } __packed; 379 380 struct sta_rec_state { 381 __le16 tag; 382 __le16 len; 383 __le32 flags; 384 u8 state; 385 u8 vht_opmode; 386 u8 action; 387 u8 rsv[1]; 388 } __packed; 389 390 #define RA_LEGACY_OFDM GENMASK(13, 6) 391 #define RA_LEGACY_CCK GENMASK(3, 0) 392 #define HT_MCS_MASK_NUM 10 393 struct sta_rec_ra_info { 394 __le16 tag; 395 __le16 len; 396 __le16 legacy; 397 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 398 } __packed; 399 400 struct sta_rec_phy { 401 __le16 tag; 402 __le16 len; 403 __le16 basic_rate; 404 u8 phy_type; 405 u8 ampdu; 406 u8 rts_policy; 407 u8 rcpi; 408 u8 max_ampdu_len; /* connac3 */ 409 u8 rsv[1]; 410 } __packed; 411 412 struct sta_rec_he_6g_capa { 413 __le16 tag; 414 __le16 len; 415 __le16 capa; 416 u8 rsv[2]; 417 } __packed; 418 419 struct sec_key { 420 u8 cipher_id; 421 u8 cipher_len; 422 u8 key_id; 423 u8 key_len; 424 u8 key[32]; 425 } __packed; 426 427 struct sta_rec_sec { 428 __le16 tag; 429 __le16 len; 430 u8 add; 431 u8 n_cipher; 432 u8 rsv[2]; 433 434 struct sec_key key[2]; 435 } __packed; 436 437 struct sta_rec_bf { 438 __le16 tag; 439 __le16 len; 440 441 __le16 pfmu; /* 0xffff: no access right for PFMU */ 442 bool su_mu; /* 0: SU, 1: MU */ 443 u8 bf_cap; /* 0: iBF, 1: eBF */ 444 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 445 u8 ndpa_rate; 446 u8 ndp_rate; 447 u8 rept_poll_rate; 448 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 449 u8 ncol; 450 u8 nrow; 451 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 452 453 u8 mem_total; 454 u8 mem_20m; 455 struct { 456 u8 row; 457 u8 col: 6, row_msb: 2; 458 } mem[4]; 459 460 __le16 smart_ant; 461 u8 se_idx; 462 u8 auto_sounding; /* b7: low traffic indicator 463 * b6: Stop sounding for this entry 464 * b5 ~ b0: postpone sounding 465 */ 466 u8 ibf_timeout; 467 u8 ibf_dbw; 468 u8 ibf_ncol; 469 u8 ibf_nrow; 470 u8 nrow_gt_bw80; 471 u8 ncol_gt_bw80; 472 u8 ru_start_idx; 473 u8 ru_end_idx; 474 475 bool trigger_su; 476 bool trigger_mu; 477 bool ng16_su; 478 bool ng16_mu; 479 bool codebook42_su; 480 bool codebook75_mu; 481 482 u8 he_ltf; 483 u8 rsv[3]; 484 } __packed; 485 486 struct sta_rec_bfee { 487 __le16 tag; 488 __le16 len; 489 bool fb_identity_matrix; /* 1: feedback identity matrix */ 490 bool ignore_feedback; /* 1: ignore */ 491 u8 rsv[2]; 492 } __packed; 493 494 struct sta_rec_muru { 495 __le16 tag; 496 __le16 len; 497 498 struct { 499 bool ofdma_dl_en; 500 bool ofdma_ul_en; 501 bool mimo_dl_en; 502 bool mimo_ul_en; 503 u8 rsv[4]; 504 } cfg; 505 506 struct { 507 u8 punc_pream_rx; 508 bool he_20m_in_40m_2g; 509 bool he_20m_in_160m; 510 bool he_80m_in_160m; 511 bool lt16_sigb; 512 bool rx_su_comp_sigb; 513 bool rx_su_non_comp_sigb; 514 u8 rsv; 515 } ofdma_dl; 516 517 struct { 518 u8 t_frame_dur; 519 u8 mu_cascading; 520 u8 uo_ra; 521 u8 he_2x996_tone; 522 u8 rx_t_frame_11ac; 523 u8 rx_ctrl_frame_to_mbss; 524 u8 rsv[2]; 525 } ofdma_ul; 526 527 struct { 528 bool vht_mu_bfee; 529 bool partial_bw_dl_mimo; 530 u8 rsv[2]; 531 } mimo_dl; 532 533 struct { 534 bool full_ul_mimo; 535 bool partial_ul_mimo; 536 u8 rsv[2]; 537 } mimo_ul; 538 } __packed; 539 540 struct sta_phy { 541 u8 type; 542 u8 flag; 543 u8 stbc; 544 u8 sgi; 545 u8 bw; 546 u8 ldpc; 547 u8 mcs; 548 u8 nss; 549 u8 he_ltf; 550 }; 551 552 struct sta_rec_ra { 553 __le16 tag; 554 __le16 len; 555 556 u8 valid; 557 u8 auto_rate; 558 u8 phy_mode; 559 u8 channel; 560 u8 bw; 561 u8 disable_cck; 562 u8 ht_mcs32; 563 u8 ht_gf; 564 u8 ht_mcs[4]; 565 u8 mmps_mode; 566 u8 gband_256; 567 u8 af; 568 u8 auth_wapi_mode; 569 u8 rate_len; 570 571 u8 supp_mode; 572 u8 supp_cck_rate; 573 u8 supp_ofdm_rate; 574 __le32 supp_ht_mcs; 575 __le16 supp_vht_mcs[4]; 576 577 u8 op_mode; 578 u8 op_vht_chan_width; 579 u8 op_vht_rx_nss; 580 u8 op_vht_rx_nss_type; 581 582 __le32 sta_cap; 583 584 struct sta_phy phy; 585 } __packed; 586 587 struct sta_rec_ra_fixed { 588 __le16 tag; 589 __le16 len; 590 591 __le32 field; 592 u8 op_mode; 593 u8 op_vht_chan_width; 594 u8 op_vht_rx_nss; 595 u8 op_vht_rx_nss_type; 596 597 struct sta_phy phy; 598 599 u8 spe_idx; 600 u8 short_preamble; 601 u8 is_5g; 602 u8 mmps_mode; 603 } __packed; 604 605 /* wtbl_rec */ 606 607 struct wtbl_req_hdr { 608 u8 wlan_idx_lo; 609 u8 operation; 610 __le16 tlv_num; 611 u8 wlan_idx_hi; 612 u8 rsv[3]; 613 } __packed; 614 615 struct wtbl_generic { 616 __le16 tag; 617 __le16 len; 618 u8 peer_addr[ETH_ALEN]; 619 u8 muar_idx; 620 u8 skip_tx; 621 u8 cf_ack; 622 u8 qos; 623 u8 mesh; 624 u8 adm; 625 __le16 partial_aid; 626 u8 baf_en; 627 u8 aad_om; 628 } __packed; 629 630 struct wtbl_rx { 631 __le16 tag; 632 __le16 len; 633 u8 rcid; 634 u8 rca1; 635 u8 rca2; 636 u8 rv; 637 u8 rsv[4]; 638 } __packed; 639 640 struct wtbl_ht { 641 __le16 tag; 642 __le16 len; 643 u8 ht; 644 u8 ldpc; 645 u8 af; 646 u8 mm; 647 u8 rsv[4]; 648 } __packed; 649 650 struct wtbl_vht { 651 __le16 tag; 652 __le16 len; 653 u8 ldpc; 654 u8 dyn_bw; 655 u8 vht; 656 u8 txop_ps; 657 u8 rsv[4]; 658 } __packed; 659 660 struct wtbl_tx_ps { 661 __le16 tag; 662 __le16 len; 663 u8 txps; 664 u8 rsv[3]; 665 } __packed; 666 667 struct wtbl_hdr_trans { 668 __le16 tag; 669 __le16 len; 670 u8 to_ds; 671 u8 from_ds; 672 u8 no_rx_trans; 673 u8 rsv; 674 } __packed; 675 676 struct wtbl_ba { 677 __le16 tag; 678 __le16 len; 679 /* common */ 680 u8 tid; 681 u8 ba_type; 682 u8 rsv0[2]; 683 /* originator only */ 684 __le16 sn; 685 u8 ba_en; 686 u8 ba_winsize_idx; 687 /* originator & recipient */ 688 __le16 ba_winsize; 689 /* recipient only */ 690 u8 peer_addr[ETH_ALEN]; 691 u8 rst_ba_tid; 692 u8 rst_ba_sel; 693 u8 rst_ba_sb; 694 u8 band_idx; 695 u8 rsv1[4]; 696 } __packed; 697 698 struct wtbl_smps { 699 __le16 tag; 700 __le16 len; 701 u8 smps; 702 u8 rsv[3]; 703 } __packed; 704 705 /* mt7615 only */ 706 707 struct wtbl_bf { 708 __le16 tag; 709 __le16 len; 710 u8 ibf; 711 u8 ebf; 712 u8 ibf_vht; 713 u8 ebf_vht; 714 u8 gid; 715 u8 pfmu_idx; 716 u8 rsv[2]; 717 } __packed; 718 719 struct wtbl_pn { 720 __le16 tag; 721 __le16 len; 722 u8 pn[6]; 723 u8 rsv[2]; 724 } __packed; 725 726 struct wtbl_spe { 727 __le16 tag; 728 __le16 len; 729 u8 spe_idx; 730 u8 rsv[3]; 731 } __packed; 732 733 struct wtbl_raw { 734 __le16 tag; 735 __le16 len; 736 u8 wtbl_idx; 737 u8 dw; 738 u8 rsv[2]; 739 __le32 msk; 740 __le32 val; 741 } __packed; 742 743 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 744 sizeof(struct wtbl_generic) + \ 745 sizeof(struct wtbl_rx) + \ 746 sizeof(struct wtbl_ht) + \ 747 sizeof(struct wtbl_vht) + \ 748 sizeof(struct wtbl_tx_ps) + \ 749 sizeof(struct wtbl_hdr_trans) +\ 750 sizeof(struct wtbl_ba) + \ 751 sizeof(struct wtbl_bf) + \ 752 sizeof(struct wtbl_smps) + \ 753 sizeof(struct wtbl_pn) + \ 754 sizeof(struct wtbl_spe)) 755 756 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 757 sizeof(struct sta_rec_basic) + \ 758 sizeof(struct sta_rec_bf) + \ 759 sizeof(struct sta_rec_ht) + \ 760 sizeof(struct sta_rec_he) + \ 761 sizeof(struct sta_rec_ba) + \ 762 sizeof(struct sta_rec_vht) + \ 763 sizeof(struct sta_rec_uapsd) + \ 764 sizeof(struct sta_rec_amsdu) + \ 765 sizeof(struct sta_rec_muru) + \ 766 sizeof(struct sta_rec_bfee) + \ 767 sizeof(struct sta_rec_ra) + \ 768 sizeof(struct sta_rec_sec) + \ 769 sizeof(struct sta_rec_ra_fixed) + \ 770 sizeof(struct sta_rec_he_6g_capa) + \ 771 sizeof(struct tlv) + \ 772 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 773 774 enum { 775 STA_REC_BASIC, 776 STA_REC_RA, 777 STA_REC_RA_CMM_INFO, 778 STA_REC_RA_UPDATE, 779 STA_REC_BF, 780 STA_REC_AMSDU, 781 STA_REC_BA, 782 STA_REC_STATE, 783 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 784 STA_REC_HT, 785 STA_REC_VHT, 786 STA_REC_APPS, 787 STA_REC_KEY, 788 STA_REC_WTBL, 789 STA_REC_HE, 790 STA_REC_HW_AMSDU, 791 STA_REC_WTBL_AADOM, 792 STA_REC_KEY_V2, 793 STA_REC_MURU, 794 STA_REC_MUEDCA, 795 STA_REC_BFEE, 796 STA_REC_PHY = 0x15, 797 STA_REC_HE_6G = 0x17, 798 STA_REC_HE_V2 = 0x19, 799 STA_REC_MLD = 0x20, 800 STA_REC_EHT = 0x22, 801 STA_REC_HDRT = 0x28, 802 STA_REC_HDR_TRANS = 0x2B, 803 STA_REC_MAX_NUM 804 }; 805 806 enum { 807 WTBL_GENERIC, 808 WTBL_RX, 809 WTBL_HT, 810 WTBL_VHT, 811 WTBL_PEER_PS, /* not used */ 812 WTBL_TX_PS, 813 WTBL_HDR_TRANS, 814 WTBL_SEC_KEY, 815 WTBL_BA, 816 WTBL_RDG, /* obsoleted */ 817 WTBL_PROTECT, /* not used */ 818 WTBL_CLEAR, /* not used */ 819 WTBL_BF, 820 WTBL_SMPS, 821 WTBL_RAW_DATA, /* debug only */ 822 WTBL_PN, 823 WTBL_SPE, 824 WTBL_MAX_NUM 825 }; 826 827 #define STA_TYPE_STA BIT(0) 828 #define STA_TYPE_AP BIT(1) 829 #define STA_TYPE_ADHOC BIT(2) 830 #define STA_TYPE_WDS BIT(4) 831 #define STA_TYPE_BC BIT(5) 832 833 #define NETWORK_INFRA BIT(16) 834 #define NETWORK_P2P BIT(17) 835 #define NETWORK_IBSS BIT(18) 836 #define NETWORK_WDS BIT(21) 837 838 #define SCAN_FUNC_RANDOM_MAC BIT(0) 839 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 840 841 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 842 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 843 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 844 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 845 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 846 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 847 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 848 849 #define CONN_STATE_DISCONNECT 0 850 #define CONN_STATE_CONNECT 1 851 #define CONN_STATE_PORT_SECURE 2 852 853 /* HE MAC */ 854 #define STA_REC_HE_CAP_HTC BIT(0) 855 #define STA_REC_HE_CAP_BQR BIT(1) 856 #define STA_REC_HE_CAP_BSR BIT(2) 857 #define STA_REC_HE_CAP_OM BIT(3) 858 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 859 /* HE PHY */ 860 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 861 #define STA_REC_HE_CAP_LDPC BIT(6) 862 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 863 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 864 /* STBC */ 865 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 866 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 867 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 868 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 869 /* GI */ 870 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 871 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 872 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 873 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 874 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 875 /* 242 TONE */ 876 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 877 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 878 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 879 880 #define PHY_MODE_A BIT(0) 881 #define PHY_MODE_B BIT(1) 882 #define PHY_MODE_G BIT(2) 883 #define PHY_MODE_GN BIT(3) 884 #define PHY_MODE_AN BIT(4) 885 #define PHY_MODE_AC BIT(5) 886 #define PHY_MODE_AX_24G BIT(6) 887 #define PHY_MODE_AX_5G BIT(7) 888 889 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 890 #define PHY_MODE_BE_24G BIT(1) 891 #define PHY_MODE_BE_5G BIT(2) 892 #define PHY_MODE_BE_6G BIT(3) 893 894 #define MODE_CCK BIT(0) 895 #define MODE_OFDM BIT(1) 896 #define MODE_HT BIT(2) 897 #define MODE_VHT BIT(3) 898 #define MODE_HE BIT(4) 899 #define MODE_EHT BIT(5) 900 901 #define STA_CAP_WMM BIT(0) 902 #define STA_CAP_SGI_20 BIT(4) 903 #define STA_CAP_SGI_40 BIT(5) 904 #define STA_CAP_TX_STBC BIT(6) 905 #define STA_CAP_RX_STBC BIT(7) 906 #define STA_CAP_VHT_SGI_80 BIT(16) 907 #define STA_CAP_VHT_SGI_160 BIT(17) 908 #define STA_CAP_VHT_TX_STBC BIT(18) 909 #define STA_CAP_VHT_RX_STBC BIT(19) 910 #define STA_CAP_VHT_LDPC BIT(23) 911 #define STA_CAP_LDPC BIT(24) 912 #define STA_CAP_HT BIT(26) 913 #define STA_CAP_VHT BIT(27) 914 #define STA_CAP_HE BIT(28) 915 916 enum { 917 PHY_TYPE_HR_DSSS_INDEX = 0, 918 PHY_TYPE_ERP_INDEX, 919 PHY_TYPE_ERP_P2P_INDEX, 920 PHY_TYPE_OFDM_INDEX, 921 PHY_TYPE_HT_INDEX, 922 PHY_TYPE_VHT_INDEX, 923 PHY_TYPE_HE_INDEX, 924 PHY_TYPE_BE_INDEX, 925 PHY_TYPE_INDEX_NUM 926 }; 927 928 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 929 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 930 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 931 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 932 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 933 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 934 #define PHY_TYPE_BIT_BE BIT(PHY_TYPE_BE_INDEX) 935 936 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 937 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 938 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 939 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 940 #define MT_WTBL_RATE_GI GENMASK(3, 0) 941 942 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 943 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 944 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 945 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 946 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 947 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 948 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 949 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 950 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 951 952 enum { 953 WTBL_RESET_AND_SET = 1, 954 WTBL_SET, 955 WTBL_QUERY, 956 WTBL_RESET_ALL 957 }; 958 959 enum { 960 MT_BA_TYPE_INVALID, 961 MT_BA_TYPE_ORIGINATOR, 962 MT_BA_TYPE_RECIPIENT 963 }; 964 965 enum { 966 RST_BA_MAC_TID_MATCH, 967 RST_BA_MAC_MATCH, 968 RST_BA_NO_MATCH 969 }; 970 971 enum { 972 DEV_INFO_ACTIVE, 973 DEV_INFO_MAX_NUM 974 }; 975 976 /* event table */ 977 enum { 978 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 979 MCU_EVENT_FW_START = 0x01, 980 MCU_EVENT_GENERIC = 0x01, 981 MCU_EVENT_ACCESS_REG = 0x02, 982 MCU_EVENT_MT_PATCH_SEM = 0x04, 983 MCU_EVENT_REG_ACCESS = 0x05, 984 MCU_EVENT_LP_INFO = 0x07, 985 MCU_EVENT_SCAN_DONE = 0x0d, 986 MCU_EVENT_TX_DONE = 0x0f, 987 MCU_EVENT_ROC = 0x10, 988 MCU_EVENT_BSS_ABSENCE = 0x11, 989 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 990 MCU_EVENT_CH_PRIVILEGE = 0x18, 991 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 992 MCU_EVENT_DBG_MSG = 0x27, 993 MCU_EVENT_TXPWR = 0xd0, 994 MCU_EVENT_EXT = 0xed, 995 MCU_EVENT_RESTART_DL = 0xef, 996 MCU_EVENT_COREDUMP = 0xf0, 997 }; 998 999 /* ext event table */ 1000 enum { 1001 MCU_EXT_EVENT_PS_SYNC = 0x5, 1002 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 1003 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 1004 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 1005 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 1006 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 1007 MCU_EXT_EVENT_WA_TX_STAT = 0x74, 1008 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 1009 MCU_EXT_EVENT_MURU_CTRL = 0x9f, 1010 }; 1011 1012 /* unified event table */ 1013 enum { 1014 MCU_UNI_EVENT_RESULT = 0x01, 1015 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04, 1016 MCU_UNI_EVENT_ACCESS_REG = 0x6, 1017 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09, 1018 MCU_UNI_EVENT_COREDUMP = 0x0a, 1019 MCU_UNI_EVENT_BSS_BEACON_LOSS = 0x0c, 1020 MCU_UNI_EVENT_SCAN_DONE = 0x0e, 1021 MCU_UNI_EVENT_RDD_REPORT = 0x11, 1022 MCU_UNI_EVENT_ROC = 0x27, 1023 MCU_UNI_EVENT_TX_DONE = 0x2d, 1024 MCU_UNI_EVENT_NIC_CAPAB = 0x43, 1025 MCU_UNI_EVENT_PER_STA_INFO = 0x6d, 1026 MCU_UNI_EVENT_ALL_STA_INFO = 0x6e, 1027 }; 1028 1029 #define MCU_UNI_CMD_EVENT BIT(1) 1030 #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2) 1031 1032 enum { 1033 MCU_Q_QUERY, 1034 MCU_Q_SET, 1035 MCU_Q_RESERVED, 1036 MCU_Q_NA 1037 }; 1038 1039 enum { 1040 MCU_S2D_H2N, 1041 MCU_S2D_C2N, 1042 MCU_S2D_H2C, 1043 MCU_S2D_H2CN 1044 }; 1045 1046 enum { 1047 PATCH_NOT_DL_SEM_FAIL, 1048 PATCH_IS_DL, 1049 PATCH_NOT_DL_SEM_SUCCESS, 1050 PATCH_REL_SEM_SUCCESS 1051 }; 1052 1053 enum { 1054 FW_STATE_INITIAL, 1055 FW_STATE_FW_DOWNLOAD, 1056 FW_STATE_NORMAL_OPERATION, 1057 FW_STATE_NORMAL_TRX, 1058 FW_STATE_RDY = 7 1059 }; 1060 1061 enum { 1062 CH_SWITCH_NORMAL = 0, 1063 CH_SWITCH_SCAN = 3, 1064 CH_SWITCH_MCC = 4, 1065 CH_SWITCH_DFS = 5, 1066 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1067 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1068 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1069 CH_SWITCH_SCAN_BYPASS_DPD = 9 1070 }; 1071 1072 enum { 1073 THERMAL_SENSOR_TEMP_QUERY, 1074 THERMAL_SENSOR_MANUAL_CTRL, 1075 THERMAL_SENSOR_INFO_QUERY, 1076 THERMAL_SENSOR_TASK_CTRL, 1077 }; 1078 1079 enum mcu_cipher_type { 1080 MCU_CIPHER_NONE = 0, 1081 MCU_CIPHER_WEP40, 1082 MCU_CIPHER_WEP104, 1083 MCU_CIPHER_WEP128, 1084 MCU_CIPHER_TKIP, 1085 MCU_CIPHER_AES_CCMP, 1086 MCU_CIPHER_CCMP_256, 1087 MCU_CIPHER_GCMP, 1088 MCU_CIPHER_GCMP_256, 1089 MCU_CIPHER_WAPI, 1090 MCU_CIPHER_BIP_CMAC_128, 1091 }; 1092 1093 enum { 1094 EE_MODE_EFUSE, 1095 EE_MODE_BUFFER, 1096 }; 1097 1098 enum { 1099 EE_FORMAT_BIN, 1100 EE_FORMAT_WHOLE, 1101 EE_FORMAT_MULTIPLE, 1102 }; 1103 1104 enum { 1105 MCU_PHY_STATE_TX_RATE, 1106 MCU_PHY_STATE_RX_RATE, 1107 MCU_PHY_STATE_RSSI, 1108 MCU_PHY_STATE_CONTENTION_RX_RATE, 1109 MCU_PHY_STATE_OFDMLQ_CNINFO, 1110 }; 1111 1112 #define MCU_CMD_ACK BIT(0) 1113 #define MCU_CMD_UNI BIT(1) 1114 #define MCU_CMD_SET BIT(2) 1115 1116 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 1117 MCU_CMD_SET) 1118 #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI) 1119 1120 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 1121 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 1122 #define __MCU_CMD_FIELD_QUERY BIT(16) 1123 #define __MCU_CMD_FIELD_UNI BIT(17) 1124 #define __MCU_CMD_FIELD_CE BIT(18) 1125 #define __MCU_CMD_FIELD_WA BIT(19) 1126 #define __MCU_CMD_FIELD_WM BIT(20) 1127 1128 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1129 MCU_CMD_##_t) 1130 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 1131 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1132 MCU_EXT_CMD_##_t)) 1133 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1134 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 1135 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1136 MCU_UNI_CMD_##_t)) 1137 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 1138 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1139 MCU_CE_CMD_##_t)) 1140 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1141 1142 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 1143 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 1144 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 1145 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1146 MCU_WA_PARAM_CMD_##_t)) 1147 1148 #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1149 __MCU_CMD_FIELD_WM) 1150 #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \ 1151 __MCU_CMD_FIELD_QUERY | \ 1152 __MCU_CMD_FIELD_WM) 1153 #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1154 __MCU_CMD_FIELD_WA) 1155 #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \ 1156 __MCU_CMD_FIELD_WA) 1157 1158 enum { 1159 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 1160 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 1161 MCU_EXT_CMD_RF_TEST = 0x04, 1162 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 1163 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 1164 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 1165 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 1166 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 1167 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 1168 MCU_EXT_CMD_THERMAL_PROT = 0x23, 1169 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 1170 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 1171 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 1172 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 1173 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 1174 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 1175 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 1176 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 1177 MCU_EXT_CMD_ATE_CTRL = 0x3d, 1178 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 1179 MCU_EXT_CMD_DBDC_CTRL = 0x45, 1180 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 1181 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 1182 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 1183 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 1184 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 1185 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 1186 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 1187 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 1188 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 1189 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 1190 MCU_EXT_CMD_TXDPD_CAL = 0x60, 1191 MCU_EXT_CMD_CAL_CACHE = 0x67, 1192 MCU_EXT_CMD_RED_ENABLE = 0x68, 1193 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 1194 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 1195 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 1196 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 1197 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 1198 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 1199 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 1200 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 1201 MCU_EXT_CMD_MURU_CTRL = 0x9f, 1202 MCU_EXT_CMD_SET_SPR = 0xa8, 1203 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 1204 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 1205 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 1206 }; 1207 1208 enum { 1209 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 1210 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 1211 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 1212 MCU_UNI_CMD_EDCA_UPDATE = 0x04, 1213 MCU_UNI_CMD_SUSPEND = 0x05, 1214 MCU_UNI_CMD_OFFLOAD = 0x06, 1215 MCU_UNI_CMD_HIF_CTRL = 0x07, 1216 MCU_UNI_CMD_BAND_CONFIG = 0x08, 1217 MCU_UNI_CMD_REPT_MUAR = 0x09, 1218 MCU_UNI_CMD_WSYS_CONFIG = 0x0b, 1219 MCU_UNI_CMD_REG_ACCESS = 0x0d, 1220 MCU_UNI_CMD_CHIP_CONFIG = 0x0e, 1221 MCU_UNI_CMD_POWER_CTRL = 0x0f, 1222 MCU_UNI_CMD_RX_HDR_TRANS = 0x12, 1223 MCU_UNI_CMD_SER = 0x13, 1224 MCU_UNI_CMD_TWT = 0x14, 1225 MCU_UNI_CMD_SET_DOMAIN_INFO = 0x15, 1226 MCU_UNI_CMD_SCAN_REQ = 0x16, 1227 MCU_UNI_CMD_RDD_CTRL = 0x19, 1228 MCU_UNI_CMD_GET_MIB_INFO = 0x22, 1229 MCU_UNI_CMD_GET_STAT_INFO = 0x23, 1230 MCU_UNI_CMD_SNIFFER = 0x24, 1231 MCU_UNI_CMD_SR = 0x25, 1232 MCU_UNI_CMD_ROC = 0x27, 1233 MCU_UNI_CMD_SET_DBDC_PARMS = 0x28, 1234 MCU_UNI_CMD_TXPOWER = 0x2b, 1235 MCU_UNI_CMD_SET_POWER_LIMIT = 0x2c, 1236 MCU_UNI_CMD_EFUSE_CTRL = 0x2d, 1237 MCU_UNI_CMD_RA = 0x2f, 1238 MCU_UNI_CMD_MURU = 0x31, 1239 MCU_UNI_CMD_BF = 0x33, 1240 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34, 1241 MCU_UNI_CMD_THERMAL = 0x35, 1242 MCU_UNI_CMD_VOW = 0x37, 1243 MCU_UNI_CMD_RRO = 0x57, 1244 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58, 1245 MCU_UNI_CMD_PER_STA_INFO = 0x6d, 1246 MCU_UNI_CMD_ALL_STA_INFO = 0x6e, 1247 MCU_UNI_CMD_ASSERT_DUMP = 0x6f, 1248 }; 1249 1250 enum { 1251 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 1252 MCU_CMD_FW_START_REQ = 0x02, 1253 MCU_CMD_INIT_ACCESS_REG = 0x3, 1254 MCU_CMD_NIC_POWER_CTRL = 0x4, 1255 MCU_CMD_PATCH_START_REQ = 0x05, 1256 MCU_CMD_PATCH_FINISH_REQ = 0x07, 1257 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 1258 MCU_CMD_WA_PARAM = 0xc4, 1259 MCU_CMD_EXT_CID = 0xed, 1260 MCU_CMD_FW_SCATTER = 0xee, 1261 MCU_CMD_RESTART_DL_REQ = 0xef, 1262 }; 1263 1264 /* offload mcu commands */ 1265 enum { 1266 MCU_CE_CMD_TEST_CTRL = 0x01, 1267 MCU_CE_CMD_START_HW_SCAN = 0x03, 1268 MCU_CE_CMD_SET_PS_PROFILE = 0x05, 1269 MCU_CE_CMD_SET_RX_FILTER = 0x0a, 1270 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 1271 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 1272 MCU_CE_CMD_SET_BSS_ABORT = 0x17, 1273 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 1274 MCU_CE_CMD_SET_ROC = 0x1c, 1275 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, 1276 MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 1277 MCU_CE_CMD_SET_CLC = 0x5c, 1278 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 1279 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 1280 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 1281 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 1282 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 1283 MCU_CE_CMD_REG_WRITE = 0xc0, 1284 MCU_CE_CMD_REG_READ = 0xc0, 1285 MCU_CE_CMD_CHIP_CONFIG = 0xca, 1286 MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 1287 MCU_CE_CMD_GET_WTBL = 0xcd, 1288 MCU_CE_CMD_GET_TXPWR = 0xd0, 1289 }; 1290 1291 enum { 1292 PATCH_SEM_RELEASE, 1293 PATCH_SEM_GET 1294 }; 1295 1296 enum { 1297 UNI_BSS_INFO_BASIC = 0, 1298 UNI_BSS_INFO_RA = 1, 1299 UNI_BSS_INFO_RLM = 2, 1300 UNI_BSS_INFO_BSS_COLOR = 4, 1301 UNI_BSS_INFO_HE_BASIC = 5, 1302 UNI_BSS_INFO_11V_MBSSID = 6, 1303 UNI_BSS_INFO_BCN_CONTENT = 7, 1304 UNI_BSS_INFO_BCN_CSA = 8, 1305 UNI_BSS_INFO_BCN_BCC = 9, 1306 UNI_BSS_INFO_BCN_MBSSID = 10, 1307 UNI_BSS_INFO_RATE = 11, 1308 UNI_BSS_INFO_QBSS = 15, 1309 UNI_BSS_INFO_SEC = 16, 1310 UNI_BSS_INFO_TXCMD = 18, 1311 UNI_BSS_INFO_UAPSD = 19, 1312 UNI_BSS_INFO_PS = 21, 1313 UNI_BSS_INFO_BCNFT = 22, 1314 UNI_BSS_INFO_IFS_TIME = 23, 1315 UNI_BSS_INFO_OFFLOAD = 25, 1316 UNI_BSS_INFO_MLD = 26, 1317 UNI_BSS_INFO_PM_DISABLE = 27, 1318 }; 1319 1320 enum { 1321 UNI_OFFLOAD_OFFLOAD_ARP, 1322 UNI_OFFLOAD_OFFLOAD_ND, 1323 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 1324 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 1325 }; 1326 1327 enum UNI_ALL_STA_INFO_TAG { 1328 UNI_ALL_STA_TX_RATE, 1329 UNI_ALL_STA_TX_STAT, 1330 UNI_ALL_STA_TXRX_ADM_STAT, 1331 UNI_ALL_STA_TXRX_AIR_TIME, 1332 UNI_ALL_STA_DATA_TX_RETRY_COUNT, 1333 UNI_ALL_STA_GI_MODE, 1334 UNI_ALL_STA_TXRX_MSDU_COUNT, 1335 UNI_ALL_STA_MAX_NUM 1336 }; 1337 1338 enum { 1339 MT_NIC_CAP_TX_RESOURCE, 1340 MT_NIC_CAP_TX_EFUSE_ADDR, 1341 MT_NIC_CAP_COEX, 1342 MT_NIC_CAP_SINGLE_SKU, 1343 MT_NIC_CAP_CSUM_OFFLOAD, 1344 MT_NIC_CAP_HW_VER, 1345 MT_NIC_CAP_SW_VER, 1346 MT_NIC_CAP_MAC_ADDR, 1347 MT_NIC_CAP_PHY, 1348 MT_NIC_CAP_MAC, 1349 MT_NIC_CAP_FRAME_BUF, 1350 MT_NIC_CAP_BEAM_FORM, 1351 MT_NIC_CAP_LOCATION, 1352 MT_NIC_CAP_MUMIMO, 1353 MT_NIC_CAP_BUFFER_MODE_INFO, 1354 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1355 MT_NIC_CAP_ANTSWP = 0x16, 1356 MT_NIC_CAP_WFDMA_REALLOC, 1357 MT_NIC_CAP_6G, 1358 MT_NIC_CAP_CHIP_CAP = 0x20, 1359 }; 1360 1361 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 1362 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 1363 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 1364 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 1365 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 1366 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 1367 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 1368 1369 enum { 1370 UNI_SUSPEND_MODE_SETTING, 1371 UNI_SUSPEND_WOW_CTRL, 1372 UNI_SUSPEND_WOW_GPIO_PARAM, 1373 UNI_SUSPEND_WOW_WAKEUP_PORT, 1374 UNI_SUSPEND_WOW_PATTERN, 1375 }; 1376 1377 enum { 1378 WOW_USB = 1, 1379 WOW_PCIE = 2, 1380 WOW_GPIO = 3, 1381 }; 1382 1383 struct mt76_connac_bss_basic_tlv { 1384 __le16 tag; 1385 __le16 len; 1386 u8 active; 1387 u8 omac_idx; 1388 u8 hw_bss_idx; 1389 u8 band_idx; 1390 __le32 conn_type; 1391 u8 conn_state; 1392 u8 wmm_idx; 1393 u8 bssid[ETH_ALEN]; 1394 __le16 bmc_tx_wlan_idx; 1395 __le16 bcn_interval; 1396 u8 dtim_period; 1397 u8 phymode; /* bit(0): A 1398 * bit(1): B 1399 * bit(2): G 1400 * bit(3): GN 1401 * bit(4): AN 1402 * bit(5): AC 1403 * bit(6): AX2 1404 * bit(7): AX5 1405 * bit(8): AX6 1406 */ 1407 __le16 sta_idx; 1408 __le16 nonht_basic_phy; 1409 u8 phymode_ext; /* bit(0) AX_6G */ 1410 u8 pad[1]; 1411 } __packed; 1412 1413 struct mt76_connac_bss_qos_tlv { 1414 __le16 tag; 1415 __le16 len; 1416 u8 qos; 1417 u8 pad[3]; 1418 } __packed; 1419 1420 struct mt76_connac_beacon_loss_event { 1421 u8 bss_idx; 1422 u8 reason; 1423 u8 pad[2]; 1424 } __packed; 1425 1426 struct mt76_connac_mcu_bss_event { 1427 u8 bss_idx; 1428 u8 is_absent; 1429 u8 free_quota; 1430 u8 pad; 1431 } __packed; 1432 1433 struct mt76_connac_mcu_scan_ssid { 1434 __le32 ssid_len; 1435 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1436 } __packed; 1437 1438 struct mt76_connac_mcu_scan_channel { 1439 u8 band; /* 1: 2.4GHz 1440 * 2: 5.0GHz 1441 * Others: Reserved 1442 */ 1443 u8 channel_num; 1444 } __packed; 1445 1446 struct mt76_connac_mcu_scan_match { 1447 __le32 rssi_th; 1448 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1449 u8 ssid_len; 1450 u8 rsv[3]; 1451 } __packed; 1452 1453 struct mt76_connac_hw_scan_req { 1454 u8 seq_num; 1455 u8 bss_idx; 1456 u8 scan_type; /* 0: PASSIVE SCAN 1457 * 1: ACTIVE SCAN 1458 */ 1459 u8 ssid_type; /* BIT(0) wildcard SSID 1460 * BIT(1) P2P wildcard SSID 1461 * BIT(2) specified SSID + wildcard SSID 1462 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 1463 */ 1464 u8 ssids_num; 1465 u8 probe_req_num; /* Number of probe request for each SSID */ 1466 u8 scan_func; /* BIT(0) Enable random MAC scan 1467 * BIT(1) Disable DBDC scan type 1~3. 1468 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 1469 */ 1470 u8 version; /* 0: Not support fields after ies. 1471 * 1: Support fields after ies. 1472 */ 1473 struct mt76_connac_mcu_scan_ssid ssids[4]; 1474 __le16 probe_delay_time; 1475 __le16 channel_dwell_time; /* channel Dwell interval */ 1476 __le16 timeout_value; 1477 u8 channel_type; /* 0: Full channels 1478 * 1: Only 2.4GHz channels 1479 * 2: Only 5GHz channels 1480 * 3: P2P social channel only (channel #1, #6 and #11) 1481 * 4: Specified channels 1482 * Others: Reserved 1483 */ 1484 u8 channels_num; /* valid when channel_type is 4 */ 1485 /* valid when channels_num is set */ 1486 struct mt76_connac_mcu_scan_channel channels[32]; 1487 __le16 ies_len; 1488 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 1489 /* following fields are valid if version > 0 */ 1490 u8 ext_channels_num; 1491 u8 ext_ssids_num; 1492 __le16 channel_min_dwell_time; 1493 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1494 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1495 u8 bssid[ETH_ALEN]; 1496 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 1497 u8 pad[63]; 1498 u8 ssid_type_ext; 1499 } __packed; 1500 1501 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 1502 1503 struct mt76_connac_hw_scan_done { 1504 u8 seq_num; 1505 u8 sparse_channel_num; 1506 struct mt76_connac_mcu_scan_channel sparse_channel; 1507 u8 complete_channel_num; 1508 u8 current_state; 1509 u8 version; 1510 u8 pad; 1511 __le32 beacon_scan_num; 1512 u8 pno_enabled; 1513 u8 pad2[3]; 1514 u8 sparse_channel_valid_num; 1515 u8 pad3[3]; 1516 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1517 /* idle format for channel_idle_time 1518 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1519 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1520 * 2: dwell time (16us) 1521 */ 1522 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1523 /* beacon and probe response count */ 1524 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1525 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1526 __le32 beacon_2g_num; 1527 __le32 beacon_5g_num; 1528 } __packed; 1529 1530 struct mt76_connac_sched_scan_req { 1531 u8 version; 1532 u8 seq_num; 1533 u8 stop_on_match; 1534 u8 ssids_num; 1535 u8 match_num; 1536 u8 pad; 1537 __le16 ie_len; 1538 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 1539 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 1540 u8 channel_type; 1541 u8 channels_num; 1542 u8 intervals_num; 1543 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 1544 struct mt76_connac_mcu_scan_channel channels[64]; 1545 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 1546 union { 1547 struct { 1548 u8 random_mac[ETH_ALEN]; 1549 u8 pad2[58]; 1550 } mt7663; 1551 struct { 1552 u8 bss_idx; 1553 u8 pad1[3]; 1554 __le32 delay; 1555 u8 pad2[12]; 1556 u8 random_mac[ETH_ALEN]; 1557 u8 pad3[38]; 1558 } mt7921; 1559 }; 1560 } __packed; 1561 1562 struct mt76_connac_sched_scan_done { 1563 u8 seq_num; 1564 u8 status; /* 0: ssid found */ 1565 __le16 pad; 1566 } __packed; 1567 1568 struct bss_info_uni_bss_color { 1569 __le16 tag; 1570 __le16 len; 1571 u8 enable; 1572 u8 bss_color; 1573 u8 rsv[2]; 1574 } __packed; 1575 1576 struct bss_info_uni_he { 1577 __le16 tag; 1578 __le16 len; 1579 __le16 he_rts_thres; 1580 u8 he_pe_duration; 1581 u8 su_disable; 1582 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 1583 u8 rsv[2]; 1584 } __packed; 1585 1586 struct bss_info_uni_mbssid { 1587 __le16 tag; 1588 __le16 len; 1589 u8 max_indicator; 1590 u8 mbss_idx; 1591 u8 tx_bss_omac_idx; 1592 u8 rsv; 1593 } __packed; 1594 1595 struct mt76_connac_gtk_rekey_tlv { 1596 __le16 tag; 1597 __le16 len; 1598 u8 kek[NL80211_KEK_LEN]; 1599 u8 kck[NL80211_KCK_LEN]; 1600 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 1601 u8 rekey_mode; /* 0: rekey offload enable 1602 * 1: rekey offload disable 1603 * 2: rekey update 1604 */ 1605 u8 keyid; 1606 u8 option; /* 1: rekey data update without enabling offload */ 1607 u8 pad[1]; 1608 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 1609 __le32 pairwise_cipher; 1610 __le32 group_cipher; 1611 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 1612 __le32 mgmt_group_cipher; 1613 u8 reserverd[4]; 1614 } __packed; 1615 1616 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 1617 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 1618 1619 struct mt76_connac_wow_pattern_tlv { 1620 __le16 tag; 1621 __le16 len; 1622 u8 index; /* pattern index */ 1623 u8 enable; /* 0: disable 1624 * 1: enable 1625 */ 1626 u8 data_len; /* pattern length */ 1627 u8 pad; 1628 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 1629 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 1630 u8 rsv[4]; 1631 } __packed; 1632 1633 struct mt76_connac_wow_ctrl_tlv { 1634 __le16 tag; 1635 __le16 len; 1636 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 1637 * 0x2: PM_WOWLAN_REQ_STOP 1638 * 0x3: PM_WOWLAN_PARAM_CLEAR 1639 */ 1640 u8 trigger; /* 0: NONE 1641 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 1642 * BIT(1): NL80211_WOWLAN_TRIG_ANY 1643 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 1644 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 1645 * BIT(4): BEACON_LOST 1646 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 1647 */ 1648 u8 wakeup_hif; /* 0x0: HIF_SDIO 1649 * 0x1: HIF_USB 1650 * 0x2: HIF_PCIE 1651 * 0x3: HIF_GPIO 1652 */ 1653 u8 pad; 1654 u8 rsv[4]; 1655 } __packed; 1656 1657 struct mt76_connac_wow_gpio_param_tlv { 1658 __le16 tag; 1659 __le16 len; 1660 u8 gpio_pin; 1661 u8 trigger_lvl; 1662 u8 pad[2]; 1663 __le32 gpio_interval; 1664 u8 rsv[4]; 1665 } __packed; 1666 1667 struct mt76_connac_arpns_tlv { 1668 __le16 tag; 1669 __le16 len; 1670 u8 mode; 1671 u8 ips_num; 1672 u8 option; 1673 u8 pad[1]; 1674 } __packed; 1675 1676 struct mt76_connac_suspend_tlv { 1677 __le16 tag; 1678 __le16 len; 1679 u8 enable; /* 0: suspend mode disabled 1680 * 1: suspend mode enabled 1681 */ 1682 u8 mdtim; /* LP parameter */ 1683 u8 wow_suspend; /* 0: update by origin policy 1684 * 1: update by wow dtim 1685 */ 1686 u8 pad[5]; 1687 } __packed; 1688 1689 enum mt76_sta_info_state { 1690 MT76_STA_INFO_STATE_NONE, 1691 MT76_STA_INFO_STATE_AUTH, 1692 MT76_STA_INFO_STATE_ASSOC 1693 }; 1694 1695 struct mt76_sta_cmd_info { 1696 struct ieee80211_sta *sta; 1697 struct mt76_wcid *wcid; 1698 1699 struct ieee80211_vif *vif; 1700 1701 bool offload_fw; 1702 bool enable; 1703 bool newly; 1704 int cmd; 1705 u8 rcpi; 1706 u8 state; 1707 }; 1708 1709 #define MT_SKU_POWER_LIMIT 161 1710 1711 struct mt76_connac_sku_tlv { 1712 u8 channel; 1713 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1714 } __packed; 1715 1716 struct mt76_connac_tx_power_limit_tlv { 1717 /* DW0 - common info*/ 1718 u8 ver; 1719 u8 pad0; 1720 __le16 len; 1721 /* DW1 - cmd hint */ 1722 u8 n_chan; /* # channel */ 1723 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1724 u8 last_msg; 1725 u8 pad1; 1726 /* DW3 */ 1727 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1728 u8 pad2[32]; 1729 } __packed; 1730 1731 struct mt76_connac_config { 1732 __le16 id; 1733 u8 type; 1734 u8 resp_type; 1735 __le16 data_size; 1736 __le16 resv; 1737 u8 data[320]; 1738 } __packed; 1739 1740 struct mt76_connac_mcu_uni_event { 1741 u8 cid; 1742 u8 pad[3]; 1743 __le32 status; /* 0: success, others: fail */ 1744 } __packed; 1745 1746 struct mt76_connac_mcu_reg_event { 1747 __le32 reg; 1748 __le32 val; 1749 } __packed; 1750 1751 static inline enum mcu_cipher_type 1752 mt76_connac_mcu_get_cipher(int cipher) 1753 { 1754 switch (cipher) { 1755 case WLAN_CIPHER_SUITE_WEP40: 1756 return MCU_CIPHER_WEP40; 1757 case WLAN_CIPHER_SUITE_WEP104: 1758 return MCU_CIPHER_WEP104; 1759 case WLAN_CIPHER_SUITE_TKIP: 1760 return MCU_CIPHER_TKIP; 1761 case WLAN_CIPHER_SUITE_AES_CMAC: 1762 return MCU_CIPHER_BIP_CMAC_128; 1763 case WLAN_CIPHER_SUITE_CCMP: 1764 return MCU_CIPHER_AES_CCMP; 1765 case WLAN_CIPHER_SUITE_CCMP_256: 1766 return MCU_CIPHER_CCMP_256; 1767 case WLAN_CIPHER_SUITE_GCMP: 1768 return MCU_CIPHER_GCMP; 1769 case WLAN_CIPHER_SUITE_GCMP_256: 1770 return MCU_CIPHER_GCMP_256; 1771 case WLAN_CIPHER_SUITE_SMS4: 1772 return MCU_CIPHER_WAPI; 1773 default: 1774 return MCU_CIPHER_NONE; 1775 } 1776 } 1777 1778 static inline u32 1779 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) 1780 { 1781 u32 ret = 0; 1782 1783 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? 1784 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; 1785 if (is_mt7921(dev) || is_mt7925(dev)) 1786 ret |= feature_set & FW_FEATURE_ENCRY_MODE ? 1787 DL_CONFIG_ENCRY_MODE_SEL : 0; 1788 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1789 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1790 ret |= DL_MODE_NEED_RSP; 1791 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; 1792 1793 return ret; 1794 } 1795 1796 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1797 #define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id) 1798 1799 static inline void 1800 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1801 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1802 { 1803 *wlan_idx_hi = 0; 1804 1805 if (!is_connac_v1(dev)) { 1806 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1807 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1808 } else { 1809 *wlan_idx_lo = wcid ? wcid->idx : 0; 1810 } 1811 } 1812 1813 struct sk_buff * 1814 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1815 struct mt76_wcid *wcid, int len); 1816 static inline struct sk_buff * 1817 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1818 struct mt76_wcid *wcid) 1819 { 1820 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, 1821 MT76_CONNAC_STA_UPDATE_MAX_SIZE); 1822 } 1823 1824 struct wtbl_req_hdr * 1825 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1826 int cmd, void *sta_wtbl, struct sk_buff **skb); 1827 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1828 int len, void *sta_ntlv, 1829 void *sta_wtbl); 1830 static inline struct tlv * 1831 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1832 { 1833 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1834 } 1835 1836 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1837 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1838 void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1839 struct ieee80211_vif *vif, 1840 struct ieee80211_sta *sta, bool enable, 1841 bool newly); 1842 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1843 struct ieee80211_vif *vif, 1844 struct ieee80211_sta *sta, void *sta_wtbl, 1845 void *wtbl_tlv); 1846 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1847 struct ieee80211_vif *vif, 1848 struct mt76_wcid *wcid, 1849 void *sta_wtbl, void *wtbl_tlv); 1850 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1851 struct ieee80211_vif *vif, 1852 struct mt76_wcid *wcid, int cmd); 1853 void mt76_connac_mcu_sta_he_tlv_v2(struct sk_buff *skb, struct ieee80211_sta *sta); 1854 u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif, 1855 enum nl80211_band band, struct ieee80211_sta *sta); 1856 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, 1857 struct ieee80211_vif *vif, 1858 struct ieee80211_sta *sta); 1859 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1860 struct ieee80211_sta *sta, 1861 struct ieee80211_vif *vif, 1862 u8 rcpi, u8 state); 1863 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1864 struct ieee80211_sta *sta, void *sta_wtbl, 1865 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); 1866 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1867 struct ieee80211_ampdu_params *params, 1868 bool enable, bool tx, void *sta_wtbl, 1869 void *wtbl_tlv); 1870 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1871 struct ieee80211_ampdu_params *params, 1872 bool enable, bool tx); 1873 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1874 struct ieee80211_vif *vif, 1875 struct mt76_wcid *wcid, 1876 bool enable); 1877 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1878 struct ieee80211_ampdu_params *params, 1879 int cmd, bool enable, bool tx); 1880 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy, 1881 struct mt76_vif *vif, 1882 struct ieee80211_chanctx_conf *ctx); 1883 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1884 struct ieee80211_vif *vif, 1885 struct mt76_wcid *wcid, 1886 bool enable, 1887 struct ieee80211_chanctx_conf *ctx); 1888 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1889 struct mt76_sta_cmd_info *info); 1890 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1891 struct ieee80211_vif *vif); 1892 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1893 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1894 bool hdr_trans); 1895 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1896 u32 mode); 1897 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1898 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1899 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1900 1901 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1902 struct ieee80211_scan_request *scan_req); 1903 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1904 struct ieee80211_vif *vif); 1905 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1906 struct ieee80211_vif *vif, 1907 struct cfg80211_sched_scan_request *sreq); 1908 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1909 struct ieee80211_vif *vif, 1910 bool enable); 1911 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1912 struct mt76_vif *vif, 1913 struct ieee80211_bss_conf *info); 1914 int mt76_connac_mcu_set_gtk_rekey(struct mt76_dev *dev, struct ieee80211_vif *vif, 1915 bool suspend); 1916 int mt76_connac_mcu_set_wow_ctrl(struct mt76_phy *phy, struct ieee80211_vif *vif, 1917 bool suspend, struct cfg80211_wowlan *wowlan); 1918 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1919 struct ieee80211_vif *vif, 1920 struct cfg80211_gtk_rekey_data *key); 1921 int mt76_connac_mcu_set_suspend_mode(struct mt76_dev *dev, 1922 struct ieee80211_vif *vif, 1923 bool enable, u8 mdtim, 1924 bool wow_suspend); 1925 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1926 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1927 struct ieee80211_vif *vif); 1928 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1929 enum ieee80211_sta_state old_state, 1930 enum ieee80211_sta_state new_state); 1931 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1932 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1933 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1934 struct mt76_connac_coredump *coredump); 1935 s8 mt76_connac_get_ch_power(struct mt76_phy *phy, 1936 struct ieee80211_channel *chan, 1937 s8 target_power); 1938 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1939 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 1940 struct ieee80211_vif *vif); 1941 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 1942 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 1943 1944 const struct ieee80211_sta_he_cap * 1945 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 1946 const struct ieee80211_sta_eht_cap * 1947 mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 1948 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, 1949 enum nl80211_band band, struct ieee80211_sta *sta); 1950 u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_vif *vif, 1951 enum nl80211_band band); 1952 1953 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 1954 struct mt76_connac_sta_key_conf *sta_key_conf, 1955 struct ieee80211_key_conf *key, int mcu_cmd, 1956 struct mt76_wcid *wcid, enum set_key_cmd cmd); 1957 1958 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif); 1959 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, 1960 struct ieee80211_vif *vif); 1961 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, 1962 struct ieee80211_vif *vif, 1963 struct ieee80211_sta *sta, 1964 struct mt76_phy *phy, u16 wlan_idx, 1965 bool enable); 1966 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 1967 struct ieee80211_sta *sta); 1968 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, 1969 struct ieee80211_sta *sta, 1970 void *sta_wtbl, void *wtbl_tlv); 1971 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); 1972 int mt76_connac_mcu_restart(struct mt76_dev *dev); 1973 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, 1974 u8 rx_sel, u8 val); 1975 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb); 1976 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, 1977 const char *fw_wa); 1978 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); 1979 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb, 1980 int cmd, int *wait_seq); 1981 #endif /* __MT76_CONNAC_MCU_H */ 1982