1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_H 5 #define __MT76_CONNAC_H 6 7 #include "mt76.h" 8 9 enum rx_pkt_type { 10 PKT_TYPE_TXS, 11 PKT_TYPE_TXRXV, 12 PKT_TYPE_NORMAL, 13 PKT_TYPE_RX_DUP_RFB, 14 PKT_TYPE_RX_TMR, 15 PKT_TYPE_RETRIEVE, 16 PKT_TYPE_TXRX_NOTIFY, 17 PKT_TYPE_RX_EVENT, 18 PKT_TYPE_NORMAL_MCU, 19 PKT_TYPE_RX_FW_MONITOR = 0x0c, 20 PKT_TYPE_TXRX_NOTIFY_V0 = 0x18, 21 }; 22 23 #define MT76_CONNAC_SCAN_IE_LEN 600 24 #define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL 10 25 #define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX 26 #define MT76_CONNAC_MAX_SCHED_SCAN_SSID 10 27 #define MT76_CONNAC_MAX_SCAN_MATCH 16 28 29 #define MT76_CONNAC_MAX_WMM_SETS 4 30 31 #define MT76_CONNAC_COREDUMP_TIMEOUT (HZ / 20) 32 #define MT76_CONNAC_COREDUMP_SZ (1300 * 1024) 33 34 #define MT_TXD_SIZE (8 * 4) 35 36 #define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 37 #define MT_USB_HDR_SIZE 4 38 #define MT_USB_TAIL_SIZE 4 39 40 #define MT_SDIO_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 41 #define MT_SDIO_TAIL_SIZE 8 42 #define MT_SDIO_HDR_SIZE 4 43 44 #define MT_MSDU_ID_VALID BIT(15) 45 46 #define MT_TXD_LEN_LAST BIT(15) 47 #define MT_TXD_LEN_MASK GENMASK(11, 0) 48 #define MT_TXD_LEN_MSDU_LAST BIT(14) 49 #define MT_TXD_LEN_AMSDU_LAST BIT(15) 50 51 /* PCIE part */ 52 #define PCIE_AER_UNC_STATUS_OFFSET 0x204 53 #define PCIE_AER_UNC_MASK_OFFSET 0x208 54 #define PCIE_AER_CO_STATUS_OFFSET 0x210 55 56 enum { 57 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 58 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 59 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 60 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 61 CMD_CBW_10MHZ, 62 CMD_CBW_5MHZ, 63 CMD_CBW_8080MHZ, 64 CMD_CBW_320MHZ, 65 66 CMD_HE_MCS_BW80 = 0, 67 CMD_HE_MCS_BW160, 68 CMD_HE_MCS_BW8080, 69 CMD_HE_MCS_BW_NUM 70 }; 71 72 enum { 73 HW_BSSID_0 = 0x0, 74 HW_BSSID_1, 75 HW_BSSID_2, 76 HW_BSSID_3, 77 HW_BSSID_MAX = HW_BSSID_3, 78 EXT_BSSID_START = 0x10, 79 EXT_BSSID_1, 80 EXT_BSSID_15 = 0x1f, 81 EXT_BSSID_MAX = EXT_BSSID_15, 82 REPEATER_BSSID_START = 0x20, 83 REPEATER_BSSID_MAX = 0x3f, 84 }; 85 86 struct mt76_connac_reg_map { 87 u32 phys; 88 u32 maps; 89 u32 size; 90 }; 91 92 struct mt76_connac_pm { 93 bool enable:1; 94 bool enable_user:1; 95 bool ds_enable:1; 96 bool ds_enable_user:1; 97 bool suspended:1; 98 99 spinlock_t txq_lock; 100 struct { 101 struct mt76_wcid *wcid; 102 struct sk_buff *skb; 103 } tx_q[IEEE80211_NUM_ACS]; 104 105 struct work_struct wake_work; 106 wait_queue_head_t wait; 107 108 struct { 109 spinlock_t lock; 110 u32 count; 111 } wake; 112 struct mutex mutex; 113 114 struct delayed_work ps_work; 115 unsigned long last_activity; 116 unsigned long idle_timeout; 117 118 struct { 119 unsigned long last_wake_event; 120 unsigned long awake_time; 121 unsigned long last_doze_event; 122 unsigned long doze_time; 123 unsigned int lp_wake; 124 } stats; 125 }; 126 127 struct mt76_connac_coredump { 128 struct sk_buff_head msg_list; 129 struct delayed_work work; 130 unsigned long last_activity; 131 }; 132 133 struct mt76_connac_sta_key_conf { 134 s8 keyidx; 135 u8 key[16]; 136 }; 137 138 #define MT_TXP_MAX_BUF_NUM 6 139 140 struct mt76_connac_fw_txp { 141 __le16 flags; 142 __le16 token; 143 u8 bss_idx; 144 __le16 rept_wds_wcid; 145 u8 nbuf; 146 __le32 buf[MT_TXP_MAX_BUF_NUM]; 147 __le16 len[MT_TXP_MAX_BUF_NUM]; 148 } __packed __aligned(4); 149 150 #define MT_HW_TXP_MAX_MSDU_NUM 4 151 #define MT_HW_TXP_MAX_BUF_NUM 4 152 153 struct mt76_connac_txp_ptr { 154 __le32 buf0; 155 __le16 len0; 156 __le16 len1; 157 __le32 buf1; 158 } __packed __aligned(4); 159 160 struct mt76_connac_hw_txp { 161 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM]; 162 struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2]; 163 } __packed __aligned(4); 164 165 struct mt76_connac_txp_common { 166 union { 167 struct mt76_connac_fw_txp fw; 168 struct mt76_connac_hw_txp hw; 169 }; 170 }; 171 172 struct mt76_connac_tx_free { 173 __le16 rx_byte_cnt; 174 __le16 ctrl; 175 __le32 txd; 176 } __packed __aligned(4); 177 178 extern const struct wiphy_wowlan_support mt76_connac_wowlan_support; 179 180 static inline bool is_connac3(struct mt76_dev *dev) 181 { 182 return mt76_chip(dev) == 0x7925 || mt76_chip(dev) == 0x7927 || mt76_chip(dev) == 0x7928; 183 } 184 185 static inline bool is_mt7925(struct mt76_dev *dev) 186 { 187 return mt76_chip(dev) == 0x7925; 188 } 189 190 static inline bool is_mt7927(struct mt76_dev *dev) 191 { 192 return mt76_chip(dev) == 0x7927; 193 } 194 195 static inline bool is_mt7928(struct mt76_dev *dev) 196 { 197 return mt76_chip(dev) == 0x7928; 198 } 199 200 static inline bool is_320mhz_supported(struct mt76_dev *dev) 201 { 202 return mt76_chip(dev) == 0x7927; 203 } 204 205 static inline bool is_mt7920(struct mt76_dev *dev) 206 { 207 return mt76_chip(dev) == 0x7920; 208 } 209 210 static inline bool is_mt7902(struct mt76_dev *dev) 211 { 212 return mt76_chip(dev) == 0x7902; 213 } 214 215 static inline bool is_mt7922(struct mt76_dev *dev) 216 { 217 return mt76_chip(dev) == 0x7922; 218 } 219 220 static inline bool is_connac2(struct mt76_dev *dev) 221 { 222 return mt76_chip(dev) == 0x7961 || is_mt7922(dev) || is_mt7920(dev) || 223 is_mt7902(dev); 224 } 225 226 static inline bool is_mt7663(struct mt76_dev *dev) 227 { 228 return mt76_chip(dev) == 0x7663; 229 } 230 231 static inline bool is_mt7915(struct mt76_dev *dev) 232 { 233 return mt76_chip(dev) == 0x7915; 234 } 235 236 static inline bool is_mt7916(struct mt76_dev *dev) 237 { 238 return mt76_chip(dev) == 0x7906; 239 } 240 241 static inline bool is_mt7981(struct mt76_dev *dev) 242 { 243 return mt76_chip(dev) == 0x7981; 244 } 245 246 static inline bool is_mt7986(struct mt76_dev *dev) 247 { 248 return mt76_chip(dev) == 0x7986; 249 } 250 251 static inline bool is_mt798x(struct mt76_dev *dev) 252 { 253 return is_mt7981(dev) || is_mt7986(dev); 254 } 255 256 static inline bool is_mt7996(struct mt76_dev *dev) 257 { 258 u16 chip = mt76_chip(dev); 259 return chip == 0x7990 || chip == 0x7991; 260 } 261 262 static inline bool is_mt7992(struct mt76_dev *dev) 263 { 264 return mt76_chip(dev) == 0x7992; 265 } 266 267 static inline bool is_mt7990(struct mt76_dev *dev) 268 { 269 return mt76_chip(dev) == 0x7993; 270 } 271 272 static inline bool is_mt799x(struct mt76_dev *dev) 273 { 274 return is_mt7996(dev) || is_mt7992(dev) || is_mt7990(dev); 275 } 276 277 static inline bool is_mt7622(struct mt76_dev *dev) 278 { 279 if (!IS_ENABLED(CONFIG_MT7622_WMAC)) 280 return false; 281 282 return mt76_chip(dev) == 0x7622; 283 } 284 285 static inline bool is_mt7615(struct mt76_dev *dev) 286 { 287 return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611; 288 } 289 290 static inline bool is_mt7611(struct mt76_dev *dev) 291 { 292 return mt76_chip(dev) == 0x7611; 293 } 294 295 static inline bool is_connac_v1(struct mt76_dev *dev) 296 { 297 return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev); 298 } 299 300 static inline bool is_mt76_fw_txp(struct mt76_dev *dev) 301 { 302 switch (mt76_chip(dev)) { 303 case 0x7961: 304 case 0x7920: 305 case 0x7922: 306 case 0x7902: 307 case 0x7925: 308 case 0x7927: 309 case 0x7928: 310 case 0x7663: 311 case 0x7622: 312 return false; 313 default: 314 return true; 315 } 316 } 317 318 static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef) 319 { 320 static const u8 width_to_bw[] = { 321 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ, 322 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ, 323 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ, 324 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ, 325 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ, 326 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ, 327 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ, 328 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ, 329 [NL80211_CHAN_WIDTH_320] = CMD_CBW_320MHZ, 330 }; 331 332 if (chandef->width >= ARRAY_SIZE(width_to_bw)) 333 return 0; 334 335 return width_to_bw[chandef->width]; 336 } 337 338 static inline u8 mt76_connac_lmac_mapping(u8 ac) 339 { 340 /* LMAC uses the reverse order of mac80211 AC indexes */ 341 return 3 - ac; 342 } 343 344 static inline void * 345 mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t) 346 { 347 u8 *txwi; 348 349 if (!t) 350 return NULL; 351 352 txwi = mt76_get_txwi_ptr(dev, t); 353 354 return (void *)(txwi + MT_TXD_SIZE); 355 } 356 357 static inline u8 mt76_connac_spe_idx(u8 antenna_mask) 358 { 359 static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0, 360 9, 8, 6, 10, 16, 12, 18, 0}; 361 362 if (antenna_mask >= sizeof(ant_to_spe)) 363 return 0; 364 365 return ant_to_spe[antenna_mask]; 366 } 367 368 static inline void mt76_connac_irq_enable(struct mt76_dev *dev, u32 mask) 369 { 370 mt76_set_irq_mask(dev, 0, 0, mask); 371 tasklet_schedule(&dev->irq_tasklet); 372 } 373 374 int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm); 375 void mt76_connac_power_save_sched(struct mt76_phy *phy, 376 struct mt76_connac_pm *pm); 377 void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm, 378 struct mt76_wcid *wcid); 379 380 static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev) 381 { 382 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false); 383 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false); 384 } 385 386 static inline bool 387 mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 388 { 389 bool ret = false; 390 391 spin_lock_bh(&pm->wake.lock); 392 if (test_bit(MT76_STATE_PM, &phy->state)) 393 goto out; 394 395 pm->wake.count++; 396 ret = true; 397 out: 398 spin_unlock_bh(&pm->wake.lock); 399 400 return ret; 401 } 402 403 static inline void 404 mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 405 { 406 spin_lock_bh(&pm->wake.lock); 407 408 pm->last_activity = jiffies; 409 if (--pm->wake.count == 0 && 410 test_bit(MT76_STATE_MCU_RUNNING, &phy->state)) 411 mt76_connac_power_save_sched(phy, pm); 412 413 spin_unlock_bh(&pm->wake.lock); 414 } 415 416 static inline bool 417 mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm) 418 { 419 struct mt76_dev *dev = phy->dev; 420 bool ret; 421 422 if (dev->token_count) 423 return true; 424 425 spin_lock_bh(&pm->wake.lock); 426 ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state); 427 spin_unlock_bh(&pm->wake.lock); 428 429 return ret; 430 } 431 432 static inline void 433 mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm) 434 __acquires(&dev->mutex) 435 { 436 mutex_lock(&dev->mutex); 437 mt76_connac_pm_wake(&dev->phy, pm); 438 } 439 440 static inline void 441 mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm) 442 __releases(&dev->mutex) 443 { 444 mt76_connac_power_save_sched(&dev->phy, pm); 445 mutex_unlock(&dev->mutex); 446 } 447 448 void mt76_connac_gen_ppe_thresh(u8 *he_ppet, int nss, enum nl80211_band band); 449 int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc, 450 int ring_base, void *wed, u32 flags); 451 void mt76_connac_set_txpower_cur(struct mt76_phy *phy, s8 max_power); 452 s8 mt76_connac_get_rate_power_limit(struct mt76_phy *phy, 453 struct ieee80211_channel *chan, 454 struct mt76_power_limits *limits); 455 void mt76_connac_write_hw_txp(struct mt76_dev *dev, 456 struct mt76_tx_info *tx_info, 457 void *txp_ptr, u32 id); 458 void mt76_connac_txp_skb_unmap(struct mt76_dev *dev, 459 struct mt76_txwi_cache *txwi); 460 void mt76_connac_tx_complete_skb(struct mt76_dev *mdev, 461 struct mt76_queue_entry *e); 462 void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw, 463 struct mt76_connac_pm *pm, 464 struct mt76_wcid *wcid, 465 struct sk_buff *skb); 466 void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy, 467 struct mt76_connac_pm *pm); 468 void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 469 struct sk_buff *skb, struct mt76_wcid *wcid, 470 struct ieee80211_key_conf *key, int pid, 471 enum mt76_txq_id qid, u32 changed); 472 u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy, 473 struct ieee80211_bss_conf *conf, 474 bool beacon, bool mcast); 475 bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid, 476 __le32 *txs_data); 477 bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid, 478 int pid, __le32 *txs_data); 479 void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev, 480 struct sk_buff *skb, 481 __le32 *rxv, u32 mode); 482 int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif, 483 struct sk_buff *skb, u16 hdr_offset); 484 int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev, 485 struct mt76_rx_status *status, 486 struct ieee80211_supported_band *sband, 487 __le32 *rxv, u8 *mode); 488 void mt76_connac2_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi); 489 void mt76_connac2_txwi_free(struct mt76_dev *dev, struct mt76_txwi_cache *t, 490 struct ieee80211_sta *sta, 491 struct list_head *free_list); 492 void mt76_connac2_tx_token_put(struct mt76_dev *dev); 493 494 /* connac3 */ 495 void mt76_connac3_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, 496 u8 mode); 497 void mt76_connac3_mac_decode_eht_radiotap(struct sk_buff *skb, __le32 *rxv, 498 u8 mode); 499 #endif /* __MT76_CONNAC_H */ 500