1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2019 MediaTek Inc. */ 3 4 #ifndef __MT7615_MCU_H 5 #define __MT7615_MCU_H 6 7 struct mt7615_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /* event table */ 27 enum { 28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 29 MCU_EVENT_FW_START = 0x01, 30 MCU_EVENT_GENERIC = 0x01, 31 MCU_EVENT_ACCESS_REG = 0x02, 32 MCU_EVENT_MT_PATCH_SEM = 0x04, 33 MCU_EVENT_CH_PRIVILEGE = 0x18, 34 MCU_EVENT_EXT = 0xed, 35 MCU_EVENT_RESTART_DL = 0xef, 36 }; 37 38 /* ext event table */ 39 enum { 40 MCU_EXT_EVENT_PS_SYNC = 0x5, 41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 44 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 46 }; 47 48 enum { 49 MT_SKU_CCK_1_2 = 0, 50 MT_SKU_CCK_55_11, 51 MT_SKU_OFDM_6_9, 52 MT_SKU_OFDM_12_18, 53 MT_SKU_OFDM_24_36, 54 MT_SKU_OFDM_48, 55 MT_SKU_OFDM_54, 56 MT_SKU_HT20_0_8, 57 MT_SKU_HT20_32, 58 MT_SKU_HT20_1_2_9_10, 59 MT_SKU_HT20_3_4_11_12, 60 MT_SKU_HT20_5_13, 61 MT_SKU_HT20_6_14, 62 MT_SKU_HT20_7_15, 63 MT_SKU_HT40_0_8, 64 MT_SKU_HT40_32, 65 MT_SKU_HT40_1_2_9_10, 66 MT_SKU_HT40_3_4_11_12, 67 MT_SKU_HT40_5_13, 68 MT_SKU_HT40_6_14, 69 MT_SKU_HT40_7_15, 70 MT_SKU_VHT20_0, 71 MT_SKU_VHT20_1_2, 72 MT_SKU_VHT20_3_4, 73 MT_SKU_VHT20_5_6, 74 MT_SKU_VHT20_7, 75 MT_SKU_VHT20_8, 76 MT_SKU_VHT20_9, 77 MT_SKU_VHT40_0, 78 MT_SKU_VHT40_1_2, 79 MT_SKU_VHT40_3_4, 80 MT_SKU_VHT40_5_6, 81 MT_SKU_VHT40_7, 82 MT_SKU_VHT40_8, 83 MT_SKU_VHT40_9, 84 MT_SKU_VHT80_0, 85 MT_SKU_VHT80_1_2, 86 MT_SKU_VHT80_3_4, 87 MT_SKU_VHT80_5_6, 88 MT_SKU_VHT80_7, 89 MT_SKU_VHT80_8, 90 MT_SKU_VHT80_9, 91 MT_SKU_VHT160_0, 92 MT_SKU_VHT160_1_2, 93 MT_SKU_VHT160_3_4, 94 MT_SKU_VHT160_5_6, 95 MT_SKU_VHT160_7, 96 MT_SKU_VHT160_8, 97 MT_SKU_VHT160_9, 98 MT_SKU_1SS_DELTA, 99 MT_SKU_2SS_DELTA, 100 MT_SKU_3SS_DELTA, 101 MT_SKU_4SS_DELTA, 102 }; 103 104 struct mt7615_mcu_rxd { 105 __le32 rxd[4]; 106 107 __le16 len; 108 __le16 pkt_type_id; 109 110 u8 eid; 111 u8 seq; 112 __le16 __rsv; 113 114 u8 ext_eid; 115 u8 __rsv1[2]; 116 u8 s2d_index; 117 }; 118 119 struct mt7615_mcu_rdd_report { 120 struct mt7615_mcu_rxd rxd; 121 122 u8 idx; 123 u8 long_detected; 124 u8 constant_prf_detected; 125 u8 staggered_prf_detected; 126 u8 radar_type_idx; 127 u8 periodic_pulse_num; 128 u8 long_pulse_num; 129 u8 hw_pulse_num; 130 131 u8 out_lpn; 132 u8 out_spn; 133 u8 out_crpn; 134 u8 out_crpw; 135 u8 out_crbn; 136 u8 out_stgpn; 137 u8 out_stgpw; 138 139 u8 _rsv[2]; 140 141 __le32 out_pri_const; 142 __le32 out_pri_stg[3]; 143 144 struct { 145 __le32 start; 146 __le16 pulse_width; 147 __le16 pulse_power; 148 } long_pulse[32]; 149 150 struct { 151 __le32 start; 152 __le16 pulse_width; 153 __le16 pulse_power; 154 } periodic_pulse[32]; 155 156 struct { 157 __le32 start; 158 __le16 pulse_width; 159 __le16 pulse_power; 160 u8 sc_pass; 161 u8 sw_reset; 162 } hw_pulse[32]; 163 }; 164 165 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 166 #define MCU_PKT_ID 0xa0 167 168 enum { 169 MCU_Q_QUERY, 170 MCU_Q_SET, 171 MCU_Q_RESERVED, 172 MCU_Q_NA 173 }; 174 175 enum { 176 MCU_S2D_H2N, 177 MCU_S2D_C2N, 178 MCU_S2D_H2C, 179 MCU_S2D_H2CN 180 }; 181 182 enum { 183 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 184 MCU_CMD_FW_START_REQ = 0x02, 185 MCU_CMD_INIT_ACCESS_REG = 0x3, 186 MCU_CMD_PATCH_START_REQ = 0x05, 187 MCU_CMD_PATCH_FINISH_REQ = 0x07, 188 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 189 MCU_CMD_EXT_CID = 0xED, 190 MCU_CMD_FW_SCATTER = 0xEE, 191 MCU_CMD_RESTART_DL_REQ = 0xEF, 192 }; 193 194 enum { 195 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 196 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 197 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 198 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 199 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 200 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 201 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 202 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 203 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 204 MCU_EXT_CMD_GET_TEMP = 0x2c, 205 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 206 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 207 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 208 MCU_EXT_CMD_DBDC_CTRL = 0x45, 209 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 210 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 211 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 212 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 213 MCU_EXT_CMD_SET_RDD_TH = 0x7c, 214 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 215 }; 216 217 enum { 218 PATCH_SEM_RELEASE = 0x0, 219 PATCH_SEM_GET = 0x1 220 }; 221 222 enum { 223 PATCH_NOT_DL_SEM_FAIL = 0x0, 224 PATCH_IS_DL = 0x1, 225 PATCH_NOT_DL_SEM_SUCCESS = 0x2, 226 PATCH_REL_SEM_SUCCESS = 0x3 227 }; 228 229 enum { 230 FW_STATE_INITIAL = 0, 231 FW_STATE_FW_DOWNLOAD = 1, 232 FW_STATE_NORMAL_OPERATION = 2, 233 FW_STATE_NORMAL_TRX = 3, 234 FW_STATE_CR4_RDY = 7 235 }; 236 237 #define STA_TYPE_STA BIT(0) 238 #define STA_TYPE_AP BIT(1) 239 #define STA_TYPE_ADHOC BIT(2) 240 #define STA_TYPE_WDS BIT(4) 241 #define STA_TYPE_BC BIT(5) 242 243 #define NETWORK_INFRA BIT(16) 244 #define NETWORK_P2P BIT(17) 245 #define NETWORK_IBSS BIT(18) 246 #define NETWORK_WDS BIT(21) 247 248 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 249 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 250 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 251 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 252 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 253 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 254 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 255 256 #define CONN_STATE_DISCONNECT 0 257 #define CONN_STATE_CONNECT 1 258 #define CONN_STATE_PORT_SECURE 2 259 260 enum { 261 DEV_INFO_ACTIVE, 262 DEV_INFO_MAX_NUM 263 }; 264 265 enum { 266 DBDC_TYPE_WMM, 267 DBDC_TYPE_MGMT, 268 DBDC_TYPE_BSS, 269 DBDC_TYPE_MBSS, 270 DBDC_TYPE_REPEATER, 271 DBDC_TYPE_MU, 272 DBDC_TYPE_BF, 273 DBDC_TYPE_PTA, 274 __DBDC_TYPE_MAX, 275 }; 276 277 struct bss_info_omac { 278 __le16 tag; 279 __le16 len; 280 u8 hw_bss_idx; 281 u8 omac_idx; 282 u8 band_idx; 283 u8 rsv0; 284 __le32 conn_type; 285 u32 rsv1; 286 } __packed; 287 288 struct bss_info_basic { 289 __le16 tag; 290 __le16 len; 291 __le32 network_type; 292 u8 active; 293 u8 rsv0; 294 __le16 bcn_interval; 295 u8 bssid[ETH_ALEN]; 296 u8 wmm_idx; 297 u8 dtim_period; 298 u8 bmc_tx_wlan_idx; 299 u8 cipher; /* not used */ 300 u8 phymode; /* not used */ 301 u8 rsv1[5]; 302 } __packed; 303 304 struct bss_info_rf_ch { 305 __le16 tag; 306 __le16 len; 307 u8 pri_ch; 308 u8 central_ch0; 309 u8 central_ch1; 310 u8 bw; 311 } __packed; 312 313 struct bss_info_ext_bss { 314 __le16 tag; 315 __le16 len; 316 __le32 mbss_tsf_offset; /* in unit of us */ 317 u8 rsv[8]; 318 } __packed; 319 320 enum { 321 BSS_INFO_OMAC, 322 BSS_INFO_BASIC, 323 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 324 BSS_INFO_PM, /* sta only */ 325 BSS_INFO_UAPSD, /* sta only */ 326 BSS_INFO_ROAM_DETECTION, /* obsoleted */ 327 BSS_INFO_LQ_RM, /* obsoleted */ 328 BSS_INFO_EXT_BSS, 329 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 330 BSS_INFO_SYNC_MODE, /* obsoleted */ 331 BSS_INFO_RA, 332 BSS_INFO_MAX_NUM 333 }; 334 335 enum { 336 WTBL_RESET_AND_SET = 1, 337 WTBL_SET, 338 WTBL_QUERY, 339 WTBL_RESET_ALL 340 }; 341 342 struct wtbl_req_hdr { 343 u8 wlan_idx; 344 u8 operation; 345 __le16 tlv_num; 346 u8 rsv[4]; 347 } __packed; 348 349 struct wtbl_generic { 350 __le16 tag; 351 __le16 len; 352 u8 peer_addr[ETH_ALEN]; 353 u8 muar_idx; 354 u8 skip_tx; 355 u8 cf_ack; 356 u8 qos; 357 u8 mesh; 358 u8 adm; 359 __le16 partial_aid; 360 u8 baf_en; 361 u8 aad_om; 362 } __packed; 363 364 struct wtbl_rx { 365 __le16 tag; 366 __le16 len; 367 u8 rcid; 368 u8 rca1; 369 u8 rca2; 370 u8 rv; 371 u8 rsv[4]; 372 } __packed; 373 374 struct wtbl_ht { 375 __le16 tag; 376 __le16 len; 377 u8 ht; 378 u8 ldpc; 379 u8 af; 380 u8 mm; 381 u8 rsv[4]; 382 } __packed; 383 384 struct wtbl_vht { 385 __le16 tag; 386 __le16 len; 387 u8 ldpc; 388 u8 dyn_bw; 389 u8 vht; 390 u8 txop_ps; 391 u8 rsv[4]; 392 } __packed; 393 394 struct wtbl_tx_ps { 395 __le16 tag; 396 __le16 len; 397 u8 txps; 398 u8 rsv[3]; 399 } __packed; 400 401 struct wtbl_hdr_trans { 402 __le16 tag; 403 __le16 len; 404 u8 to_ds; 405 u8 from_ds; 406 u8 disable_rx_trans; 407 u8 rsv; 408 } __packed; 409 410 enum { 411 MT_BA_TYPE_INVALID, 412 MT_BA_TYPE_ORIGINATOR, 413 MT_BA_TYPE_RECIPIENT 414 }; 415 416 enum { 417 RST_BA_MAC_TID_MATCH, 418 RST_BA_MAC_MATCH, 419 RST_BA_NO_MATCH 420 }; 421 422 struct wtbl_ba { 423 __le16 tag; 424 __le16 len; 425 /* common */ 426 u8 tid; 427 u8 ba_type; 428 u8 rsv0[2]; 429 /* originator only */ 430 __le16 sn; 431 u8 ba_en; 432 u8 ba_winsize_idx; 433 __le16 ba_winsize; 434 /* recipient only */ 435 u8 peer_addr[ETH_ALEN]; 436 u8 rst_ba_tid; 437 u8 rst_ba_sel; 438 u8 rst_ba_sb; 439 u8 band_idx; 440 u8 rsv1[4]; 441 } __packed; 442 443 struct wtbl_bf { 444 __le16 tag; 445 __le16 len; 446 u8 ibf; 447 u8 ebf; 448 u8 ibf_vht; 449 u8 ebf_vht; 450 u8 gid; 451 u8 pfmu_idx; 452 u8 rsv[2]; 453 } __packed; 454 455 struct wtbl_smps { 456 __le16 tag; 457 __le16 len; 458 u8 smps; 459 u8 rsv[3]; 460 } __packed; 461 462 struct wtbl_pn { 463 __le16 tag; 464 __le16 len; 465 u8 pn[6]; 466 u8 rsv[2]; 467 } __packed; 468 469 struct wtbl_spe { 470 __le16 tag; 471 __le16 len; 472 u8 spe_idx; 473 u8 rsv[3]; 474 } __packed; 475 476 struct wtbl_raw { 477 __le16 tag; 478 __le16 len; 479 u8 wtbl_idx; 480 u8 dw; 481 u8 rsv[2]; 482 __le32 msk; 483 __le32 val; 484 } __packed; 485 486 #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 487 sizeof(struct wtbl_generic) + \ 488 sizeof(struct wtbl_rx) + \ 489 sizeof(struct wtbl_ht) + \ 490 sizeof(struct wtbl_vht) + \ 491 sizeof(struct wtbl_tx_ps) + \ 492 sizeof(struct wtbl_hdr_trans) + \ 493 sizeof(struct wtbl_ba) + \ 494 sizeof(struct wtbl_bf) + \ 495 sizeof(struct wtbl_smps) + \ 496 sizeof(struct wtbl_pn) + \ 497 sizeof(struct wtbl_spe)) 498 499 enum { 500 WTBL_GENERIC, 501 WTBL_RX, 502 WTBL_HT, 503 WTBL_VHT, 504 WTBL_PEER_PS, /* not used */ 505 WTBL_TX_PS, 506 WTBL_HDR_TRANS, 507 WTBL_SEC_KEY, 508 WTBL_BA, 509 WTBL_RDG, /* obsoleted */ 510 WTBL_PROTECT, /* not used */ 511 WTBL_CLEAR, /* not used */ 512 WTBL_BF, 513 WTBL_SMPS, 514 WTBL_RAW_DATA, /* debug only */ 515 WTBL_PN, 516 WTBL_SPE, 517 WTBL_MAX_NUM 518 }; 519 520 struct sta_req_hdr { 521 u8 bss_idx; 522 u8 wlan_idx; 523 __le16 tlv_num; 524 u8 is_tlv_append; 525 u8 muar_idx; 526 u8 rsv[2]; 527 } __packed; 528 529 struct sta_rec_basic { 530 __le16 tag; 531 __le16 len; 532 __le32 conn_type; 533 u8 conn_state; 534 u8 qos; 535 __le16 aid; 536 u8 peer_addr[ETH_ALEN]; 537 #define EXTRA_INFO_VER BIT(0) 538 #define EXTRA_INFO_NEW BIT(1) 539 __le16 extra_info; 540 } __packed; 541 542 struct sta_rec_ht { 543 __le16 tag; 544 __le16 len; 545 __le16 ht_cap; 546 u16 rsv; 547 } __packed; 548 549 struct sta_rec_vht { 550 __le16 tag; 551 __le16 len; 552 __le32 vht_cap; 553 __le16 vht_rx_mcs_map; 554 __le16 vht_tx_mcs_map; 555 } __packed; 556 557 struct sta_rec_ba { 558 __le16 tag; 559 __le16 len; 560 u8 tid; 561 u8 ba_type; 562 u8 amsdu; 563 u8 ba_en; 564 __le16 ssn; 565 __le16 winsize; 566 } __packed; 567 568 struct sta_rec_wtbl { 569 __le16 tag; 570 __le16 len; 571 } __packed; 572 573 enum { 574 STA_REC_BASIC, 575 STA_REC_RA, 576 STA_REC_RA_CMM_INFO, 577 STA_REC_RA_UPDATE, 578 STA_REC_BF, 579 STA_REC_AMSDU, /* for CR4 */ 580 STA_REC_BA, 581 STA_REC_RED, /* not used */ 582 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 583 STA_REC_HT, 584 STA_REC_VHT, 585 STA_REC_APPS, 586 STA_REC_WTBL = 13, 587 STA_REC_MAX_NUM 588 }; 589 590 enum { 591 CMD_CBW_20MHZ, 592 CMD_CBW_40MHZ, 593 CMD_CBW_80MHZ, 594 CMD_CBW_160MHZ, 595 CMD_CBW_10MHZ, 596 CMD_CBW_5MHZ, 597 CMD_CBW_8080MHZ 598 }; 599 600 enum { 601 CH_SWITCH_NORMAL = 0, 602 CH_SWITCH_SCAN = 3, 603 CH_SWITCH_MCC = 4, 604 CH_SWITCH_DFS = 5, 605 CH_SWITCH_BACKGROUND_SCAN_START = 6, 606 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 607 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 608 CH_SWITCH_SCAN_BYPASS_DPD = 9 609 }; 610 611 static inline struct sk_buff * 612 mt7615_mcu_msg_alloc(const void *data, int len) 613 { 614 return mt76_mcu_msg_alloc(data, sizeof(struct mt7615_mcu_txd), 615 len, 0); 616 } 617 618 #endif 619