1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2019 MediaTek Inc. */ 3 4 #ifndef __MT7615_MCU_H 5 #define __MT7615_MCU_H 6 7 #include "../mt76_connac_mcu.h" 8 9 struct mt7615_mcu_txd { 10 __le32 txd[8]; 11 12 __le16 len; 13 __le16 pq_id; 14 15 u8 cid; 16 u8 pkt_type; 17 u8 set_query; /* FW don't care */ 18 u8 seq; 19 20 u8 uc_d2b0_rev; 21 u8 ext_cid; 22 u8 s2d_index; 23 u8 ext_cid_ack; 24 25 u32 reserved[5]; 26 } __packed __aligned(4); 27 28 /** 29 * struct mt7615_uni_txd - mcu command descriptor for firmware v3 30 * @txd: hardware descriptor 31 * @len: total length not including txd 32 * @cid: command identifier 33 * @pkt_type: must be 0xa0 (cmd packet by long format) 34 * @frag_n: fragment number 35 * @seq: sequence number 36 * @checksum: 0 mean there is no checksum 37 * @s2d_index: index for command source and destination 38 * Definition | value | note 39 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 40 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 41 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 42 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 43 * 44 * @option: command option 45 * BIT[0]: UNI_CMD_OPT_BIT_ACK 46 * set to 1 to request a fw reply 47 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 48 * is set, mcu firmware will send response event EID = 0x01 49 * (UNI_EVENT_ID_CMD_RESULT) to the host. 50 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 51 * 0: original command 52 * 1: unified command 53 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 54 * 0: QUERY command 55 * 1: SET command 56 */ 57 struct mt7615_uni_txd { 58 __le32 txd[8]; 59 60 /* DW1 */ 61 __le16 len; 62 __le16 cid; 63 64 /* DW2 */ 65 u8 reserved; 66 u8 pkt_type; 67 u8 frag_n; 68 u8 seq; 69 70 /* DW3 */ 71 __le16 checksum; 72 u8 s2d_index; 73 u8 option; 74 75 /* DW4 */ 76 u8 reserved2[4]; 77 } __packed __aligned(4); 78 79 /* event table */ 80 enum { 81 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 82 MCU_EVENT_FW_START = 0x01, 83 MCU_EVENT_GENERIC = 0x01, 84 MCU_EVENT_ACCESS_REG = 0x02, 85 MCU_EVENT_MT_PATCH_SEM = 0x04, 86 MCU_EVENT_REG_ACCESS = 0x05, 87 MCU_EVENT_SCAN_DONE = 0x0d, 88 MCU_EVENT_ROC = 0x10, 89 MCU_EVENT_BSS_ABSENCE = 0x11, 90 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 91 MCU_EVENT_CH_PRIVILEGE = 0x18, 92 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 93 MCU_EVENT_EXT = 0xed, 94 MCU_EVENT_RESTART_DL = 0xef, 95 MCU_EVENT_COREDUMP = 0xf0, 96 }; 97 98 /* ext event table */ 99 enum { 100 MCU_EXT_EVENT_PS_SYNC = 0x5, 101 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 102 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 103 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 104 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 105 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 106 }; 107 108 enum { 109 MT_SKU_CCK_1_2 = 0, 110 MT_SKU_CCK_55_11, 111 MT_SKU_OFDM_6_9, 112 MT_SKU_OFDM_12_18, 113 MT_SKU_OFDM_24_36, 114 MT_SKU_OFDM_48, 115 MT_SKU_OFDM_54, 116 MT_SKU_HT20_0_8, 117 MT_SKU_HT20_32, 118 MT_SKU_HT20_1_2_9_10, 119 MT_SKU_HT20_3_4_11_12, 120 MT_SKU_HT20_5_13, 121 MT_SKU_HT20_6_14, 122 MT_SKU_HT20_7_15, 123 MT_SKU_HT40_0_8, 124 MT_SKU_HT40_32, 125 MT_SKU_HT40_1_2_9_10, 126 MT_SKU_HT40_3_4_11_12, 127 MT_SKU_HT40_5_13, 128 MT_SKU_HT40_6_14, 129 MT_SKU_HT40_7_15, 130 MT_SKU_VHT20_0, 131 MT_SKU_VHT20_1_2, 132 MT_SKU_VHT20_3_4, 133 MT_SKU_VHT20_5_6, 134 MT_SKU_VHT20_7, 135 MT_SKU_VHT20_8, 136 MT_SKU_VHT20_9, 137 MT_SKU_VHT40_0, 138 MT_SKU_VHT40_1_2, 139 MT_SKU_VHT40_3_4, 140 MT_SKU_VHT40_5_6, 141 MT_SKU_VHT40_7, 142 MT_SKU_VHT40_8, 143 MT_SKU_VHT40_9, 144 MT_SKU_VHT80_0, 145 MT_SKU_VHT80_1_2, 146 MT_SKU_VHT80_3_4, 147 MT_SKU_VHT80_5_6, 148 MT_SKU_VHT80_7, 149 MT_SKU_VHT80_8, 150 MT_SKU_VHT80_9, 151 MT_SKU_VHT160_0, 152 MT_SKU_VHT160_1_2, 153 MT_SKU_VHT160_3_4, 154 MT_SKU_VHT160_5_6, 155 MT_SKU_VHT160_7, 156 MT_SKU_VHT160_8, 157 MT_SKU_VHT160_9, 158 MT_SKU_1SS_DELTA, 159 MT_SKU_2SS_DELTA, 160 MT_SKU_3SS_DELTA, 161 MT_SKU_4SS_DELTA, 162 }; 163 164 struct mt7615_mcu_rxd { 165 __le32 rxd[4]; 166 167 __le16 len; 168 __le16 pkt_type_id; 169 170 u8 eid; 171 u8 seq; 172 __le16 __rsv; 173 174 u8 ext_eid; 175 u8 __rsv1[2]; 176 u8 s2d_index; 177 }; 178 179 struct mt7615_mcu_csa_notify { 180 struct mt7615_mcu_rxd rxd; 181 182 u8 omac_idx; 183 u8 csa_count; 184 u8 rsv[2]; 185 } __packed; 186 187 struct mt7615_mcu_rdd_report { 188 struct mt7615_mcu_rxd rxd; 189 190 u8 band_idx; 191 u8 long_detected; 192 u8 constant_prf_detected; 193 u8 staggered_prf_detected; 194 u8 radar_type_idx; 195 u8 periodic_pulse_num; 196 u8 long_pulse_num; 197 u8 hw_pulse_num; 198 199 u8 out_lpn; 200 u8 out_spn; 201 u8 out_crpn; 202 u8 out_crpw; 203 u8 out_crbn; 204 u8 out_stgpn; 205 u8 out_stgpw; 206 207 u8 _rsv[2]; 208 209 __le32 out_pri_const; 210 __le32 out_pri_stg[3]; 211 212 struct { 213 __le32 start; 214 __le16 pulse_width; 215 __le16 pulse_power; 216 } long_pulse[32]; 217 218 struct { 219 __le32 start; 220 __le16 pulse_width; 221 __le16 pulse_power; 222 } periodic_pulse[32]; 223 224 struct { 225 __le32 start; 226 __le16 pulse_width; 227 __le16 pulse_power; 228 u8 sc_pass; 229 u8 sw_reset; 230 } hw_pulse[32]; 231 }; 232 233 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 234 #define MCU_PKT_ID 0xa0 235 236 enum { 237 MCU_Q_QUERY, 238 MCU_Q_SET, 239 MCU_Q_RESERVED, 240 MCU_Q_NA 241 }; 242 243 enum { 244 MCU_S2D_H2N, 245 MCU_S2D_C2N, 246 MCU_S2D_H2C, 247 MCU_S2D_H2CN 248 }; 249 250 enum { 251 MCU_ATE_SET_FREQ_OFFSET = 0xa, 252 MCU_ATE_SET_TX_POWER_CONTROL = 0x15, 253 }; 254 255 struct mt7615_mcu_uni_event { 256 u8 cid; 257 u8 pad[3]; 258 __le32 status; /* 0: success, others: fail */ 259 } __packed; 260 261 struct mt7615_mcu_reg_event { 262 __le32 reg; 263 __le32 val; 264 } __packed; 265 266 struct mt7615_roc_tlv { 267 u8 bss_idx; 268 u8 token; 269 u8 active; 270 u8 primary_chan; 271 u8 sco; 272 u8 band; 273 u8 width; /* To support 80/160MHz bandwidth */ 274 u8 freq_seg1; /* To support 80/160MHz bandwidth */ 275 u8 freq_seg2; /* To support 80/160MHz bandwidth */ 276 u8 req_type; 277 u8 dbdc_band; 278 u8 rsv0; 279 __le32 max_interval; /* ms */ 280 u8 rsv1[8]; 281 } __packed; 282 283 enum { 284 PATCH_NOT_DL_SEM_FAIL = 0x0, 285 PATCH_IS_DL = 0x1, 286 PATCH_NOT_DL_SEM_SUCCESS = 0x2, 287 PATCH_REL_SEM_SUCCESS = 0x3 288 }; 289 290 enum { 291 FW_STATE_INITIAL = 0, 292 FW_STATE_FW_DOWNLOAD = 1, 293 FW_STATE_NORMAL_OPERATION = 2, 294 FW_STATE_NORMAL_TRX = 3, 295 FW_STATE_CR4_RDY = 7 296 }; 297 298 enum { 299 FW_STATE_PWR_ON = 1, 300 FW_STATE_N9_RDY = 2, 301 }; 302 303 enum { 304 DBDC_TYPE_WMM, 305 DBDC_TYPE_MGMT, 306 DBDC_TYPE_BSS, 307 DBDC_TYPE_MBSS, 308 DBDC_TYPE_REPEATER, 309 DBDC_TYPE_MU, 310 DBDC_TYPE_BF, 311 DBDC_TYPE_PTA, 312 __DBDC_TYPE_MAX, 313 }; 314 315 struct bss_info_omac { 316 __le16 tag; 317 __le16 len; 318 u8 hw_bss_idx; 319 u8 omac_idx; 320 u8 band_idx; 321 u8 rsv0; 322 __le32 conn_type; 323 u32 rsv1; 324 } __packed; 325 326 struct bss_info_basic { 327 __le16 tag; 328 __le16 len; 329 __le32 network_type; 330 u8 active; 331 u8 rsv0; 332 __le16 bcn_interval; 333 u8 bssid[ETH_ALEN]; 334 u8 wmm_idx; 335 u8 dtim_period; 336 u8 bmc_tx_wlan_idx; 337 u8 cipher; /* not used */ 338 u8 phymode; /* not used */ 339 u8 rsv1[5]; 340 } __packed; 341 342 struct bss_info_rf_ch { 343 __le16 tag; 344 __le16 len; 345 u8 pri_ch; 346 u8 central_ch0; 347 u8 central_ch1; 348 u8 bw; 349 } __packed; 350 351 struct bss_info_ext_bss { 352 __le16 tag; 353 __le16 len; 354 __le32 mbss_tsf_offset; /* in unit of us */ 355 u8 rsv[8]; 356 } __packed; 357 358 enum { 359 BSS_INFO_OMAC, 360 BSS_INFO_BASIC, 361 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 362 BSS_INFO_PM, /* sta only */ 363 BSS_INFO_UAPSD, /* sta only */ 364 BSS_INFO_ROAM_DETECTION, /* obsoleted */ 365 BSS_INFO_LQ_RM, /* obsoleted */ 366 BSS_INFO_EXT_BSS, 367 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 368 BSS_INFO_SYNC_MODE, /* obsoleted */ 369 BSS_INFO_RA, 370 BSS_INFO_MAX_NUM 371 }; 372 373 enum { 374 CH_SWITCH_NORMAL = 0, 375 CH_SWITCH_SCAN = 3, 376 CH_SWITCH_MCC = 4, 377 CH_SWITCH_DFS = 5, 378 CH_SWITCH_BACKGROUND_SCAN_START = 6, 379 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 380 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 381 CH_SWITCH_SCAN_BYPASS_DPD = 9 382 }; 383 384 #endif 385