1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Roy Luo <royluo@google.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 */ 7 8 #include <linux/firmware.h> 9 #include "mt7615.h" 10 #include "mcu.h" 11 #include "mac.h" 12 #include "eeprom.h" 13 14 static bool prefer_offload_fw = true; 15 module_param(prefer_offload_fw, bool, 0644); 16 MODULE_PARM_DESC(prefer_offload_fw, 17 "Prefer client mode offload firmware (MT7663)"); 18 19 struct mt7615_patch_hdr { 20 char build_date[16]; 21 char platform[4]; 22 __be32 hw_sw_ver; 23 __be32 patch_ver; 24 __be16 checksum; 25 } __packed; 26 27 struct mt7615_fw_trailer { 28 __le32 addr; 29 u8 chip_id; 30 u8 feature_set; 31 u8 eco_code; 32 char fw_ver[10]; 33 char build_date[15]; 34 __le32 len; 35 } __packed; 36 37 #define FW_V3_COMMON_TAILER_SIZE 36 38 #define FW_V3_REGION_TAILER_SIZE 40 39 #define FW_START_OVERRIDE BIT(0) 40 #define FW_START_DLYCAL BIT(1) 41 #define FW_START_WORKING_PDA_CR4 BIT(2) 42 43 struct mt7663_fw_trailer { 44 u8 chip_id; 45 u8 eco_code; 46 u8 n_region; 47 u8 format_ver; 48 u8 format_flag; 49 u8 reserv[2]; 50 char fw_ver[10]; 51 char build_date[15]; 52 __le32 crc; 53 } __packed; 54 55 struct mt7663_fw_buf { 56 __le32 crc; 57 __le32 d_img_size; 58 __le32 block_size; 59 u8 rsv[4]; 60 __le32 img_dest_addr; 61 __le32 img_size; 62 u8 feature_set; 63 }; 64 65 #define MT7615_PATCH_ADDRESS 0x80000 66 #define MT7622_PATCH_ADDRESS 0x9c000 67 #define MT7663_PATCH_ADDRESS 0xdc000 68 69 #define N9_REGION_NUM 2 70 #define CR4_REGION_NUM 1 71 72 #define IMG_CRC_LEN 4 73 74 #define FW_FEATURE_SET_ENCRYPT BIT(0) 75 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 76 77 #define DL_MODE_ENCRYPT BIT(0) 78 #define DL_MODE_KEY_IDX GENMASK(2, 1) 79 #define DL_MODE_RESET_SEC_IV BIT(3) 80 #define DL_MODE_WORKING_PDA_CR4 BIT(4) 81 #define DL_MODE_VALID_RAM_ENTRY BIT(5) 82 #define DL_MODE_NEED_RSP BIT(31) 83 84 #define FW_START_OVERRIDE BIT(0) 85 #define FW_START_WORKING_PDA_CR4 BIT(2) 86 87 void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb, 88 int cmd, int *wait_seq) 89 { 90 int txd_len, mcu_cmd = cmd & MCU_CMD_MASK; 91 struct mt7615_uni_txd *uni_txd; 92 struct mt7615_mcu_txd *mcu_txd; 93 u8 seq, q_idx, pkt_fmt; 94 __le32 *txd; 95 u32 val; 96 97 /* TODO: make dynamic based on msg type */ 98 dev->mt76.mcu.timeout = 20 * HZ; 99 100 seq = ++dev->mt76.mcu.msg_seq & 0xf; 101 if (!seq) 102 seq = ++dev->mt76.mcu.msg_seq & 0xf; 103 if (wait_seq) 104 *wait_seq = seq; 105 106 txd_len = cmd & MCU_UNI_PREFIX ? sizeof(*uni_txd) : sizeof(*mcu_txd); 107 txd = (__le32 *)skb_push(skb, txd_len); 108 109 if (cmd != MCU_CMD_FW_SCATTER) { 110 q_idx = MT_TX_MCU_PORT_RX_Q0; 111 pkt_fmt = MT_TX_TYPE_CMD; 112 } else { 113 q_idx = MT_TX_MCU_PORT_RX_FWDL; 114 pkt_fmt = MT_TX_TYPE_FW; 115 } 116 117 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) | 118 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_MCU) | 119 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 120 txd[0] = cpu_to_le32(val); 121 122 val = MT_TXD1_LONG_FORMAT | 123 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD) | 124 FIELD_PREP(MT_TXD1_PKT_FMT, pkt_fmt); 125 txd[1] = cpu_to_le32(val); 126 127 if (cmd & MCU_UNI_PREFIX) { 128 uni_txd = (struct mt7615_uni_txd *)txd; 129 uni_txd->len = cpu_to_le16(skb->len - sizeof(uni_txd->txd)); 130 uni_txd->option = MCU_CMD_UNI_EXT_ACK; 131 uni_txd->cid = cpu_to_le16(mcu_cmd); 132 uni_txd->s2d_index = MCU_S2D_H2N; 133 uni_txd->pkt_type = MCU_PKT_ID; 134 uni_txd->seq = seq; 135 136 return; 137 } 138 139 mcu_txd = (struct mt7615_mcu_txd *)txd; 140 mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd)); 141 mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, q_idx)); 142 mcu_txd->s2d_index = MCU_S2D_H2N; 143 mcu_txd->pkt_type = MCU_PKT_ID; 144 mcu_txd->seq = seq; 145 146 switch (cmd & ~MCU_CMD_MASK) { 147 case MCU_FW_PREFIX: 148 mcu_txd->set_query = MCU_Q_NA; 149 mcu_txd->cid = mcu_cmd; 150 break; 151 case MCU_CE_PREFIX: 152 if (cmd & MCU_QUERY_MASK) 153 mcu_txd->set_query = MCU_Q_QUERY; 154 else 155 mcu_txd->set_query = MCU_Q_SET; 156 mcu_txd->cid = mcu_cmd; 157 break; 158 default: 159 mcu_txd->cid = MCU_CMD_EXT_CID; 160 if (cmd & MCU_QUERY_PREFIX) 161 mcu_txd->set_query = MCU_Q_QUERY; 162 else 163 mcu_txd->set_query = MCU_Q_SET; 164 mcu_txd->ext_cid = mcu_cmd; 165 mcu_txd->ext_cid_ack = 1; 166 break; 167 } 168 } 169 EXPORT_SYMBOL_GPL(mt7615_mcu_fill_msg); 170 171 int mt7615_mcu_parse_response(struct mt76_dev *mdev, int cmd, 172 struct sk_buff *skb, int seq) 173 { 174 struct mt7615_mcu_rxd *rxd; 175 int ret = 0; 176 177 if (!skb) { 178 dev_err(mdev->dev, "Message %08x (seq %d) timeout\n", 179 cmd, seq); 180 return -ETIMEDOUT; 181 } 182 183 rxd = (struct mt7615_mcu_rxd *)skb->data; 184 if (seq != rxd->seq) 185 return -EAGAIN; 186 187 switch (cmd) { 188 case MCU_CMD_PATCH_SEM_CONTROL: 189 skb_pull(skb, sizeof(*rxd) - 4); 190 ret = *skb->data; 191 break; 192 case MCU_EXT_CMD_GET_TEMP: 193 skb_pull(skb, sizeof(*rxd)); 194 ret = le32_to_cpu(*(__le32 *)skb->data); 195 break; 196 case MCU_EXT_CMD_RF_REG_ACCESS | MCU_QUERY_PREFIX: 197 skb_pull(skb, sizeof(*rxd)); 198 ret = le32_to_cpu(*(__le32 *)&skb->data[8]); 199 break; 200 case MCU_UNI_CMD_DEV_INFO_UPDATE: 201 case MCU_UNI_CMD_BSS_INFO_UPDATE: 202 case MCU_UNI_CMD_STA_REC_UPDATE: 203 case MCU_UNI_CMD_HIF_CTRL: 204 case MCU_UNI_CMD_OFFLOAD: 205 case MCU_UNI_CMD_SUSPEND: { 206 struct mt7615_mcu_uni_event *event; 207 208 skb_pull(skb, sizeof(*rxd)); 209 event = (struct mt7615_mcu_uni_event *)skb->data; 210 ret = le32_to_cpu(event->status); 211 break; 212 } 213 case MCU_CMD_REG_READ: { 214 struct mt7615_mcu_reg_event *event; 215 216 skb_pull(skb, sizeof(*rxd)); 217 event = (struct mt7615_mcu_reg_event *)skb->data; 218 ret = (int)le32_to_cpu(event->val); 219 break; 220 } 221 default: 222 break; 223 } 224 225 return ret; 226 } 227 EXPORT_SYMBOL_GPL(mt7615_mcu_parse_response); 228 229 static int 230 mt7615_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, 231 int cmd, int *seq) 232 { 233 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 234 enum mt76_mcuq_id qid; 235 236 mt7615_mcu_fill_msg(dev, skb, cmd, seq); 237 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state)) 238 qid = MT_MCUQ_WM; 239 else 240 qid = MT_MCUQ_FWDL; 241 242 return mt76_tx_queue_skb_raw(dev, dev->mt76.q_mcu[qid], skb, 0); 243 } 244 245 u32 mt7615_rf_rr(struct mt7615_dev *dev, u32 wf, u32 reg) 246 { 247 struct { 248 __le32 wifi_stream; 249 __le32 address; 250 __le32 data; 251 } req = { 252 .wifi_stream = cpu_to_le32(wf), 253 .address = cpu_to_le32(reg), 254 }; 255 256 return mt76_mcu_send_msg(&dev->mt76, 257 MCU_EXT_CMD_RF_REG_ACCESS | MCU_QUERY_PREFIX, 258 &req, sizeof(req), true); 259 } 260 261 int mt7615_rf_wr(struct mt7615_dev *dev, u32 wf, u32 reg, u32 val) 262 { 263 struct { 264 __le32 wifi_stream; 265 __le32 address; 266 __le32 data; 267 } req = { 268 .wifi_stream = cpu_to_le32(wf), 269 .address = cpu_to_le32(reg), 270 .data = cpu_to_le32(val), 271 }; 272 273 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_RF_REG_ACCESS, &req, 274 sizeof(req), false); 275 } 276 277 void mt7622_trigger_hif_int(struct mt7615_dev *dev, bool en) 278 { 279 if (!is_mt7622(&dev->mt76)) 280 return; 281 282 regmap_update_bits(dev->infracfg, MT_INFRACFG_MISC, 283 MT_INFRACFG_MISC_AP2CONN_WAKE, 284 !en * MT_INFRACFG_MISC_AP2CONN_WAKE); 285 } 286 EXPORT_SYMBOL_GPL(mt7622_trigger_hif_int); 287 288 static int mt7615_mcu_drv_pmctrl(struct mt7615_dev *dev) 289 { 290 struct mt76_phy *mphy = &dev->mt76.phy; 291 struct mt76_connac_pm *pm = &dev->pm; 292 struct mt76_dev *mdev = &dev->mt76; 293 u32 addr; 294 int err; 295 296 if (is_mt7663(mdev)) { 297 /* Clear firmware own via N9 eint */ 298 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN); 299 mt76_poll(dev, MT_CONN_ON_MISC, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000); 300 301 addr = MT_CONN_HIF_ON_LPCTL; 302 } else { 303 addr = MT_CFG_LPCR_HOST; 304 } 305 306 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_DRV_OWN); 307 308 mt7622_trigger_hif_int(dev, true); 309 310 err = !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000); 311 312 mt7622_trigger_hif_int(dev, false); 313 314 if (err) { 315 dev_err(mdev->dev, "driver own failed\n"); 316 return -ETIMEDOUT; 317 } 318 319 clear_bit(MT76_STATE_PM, &mphy->state); 320 321 pm->stats.last_wake_event = jiffies; 322 pm->stats.doze_time += pm->stats.last_wake_event - 323 pm->stats.last_doze_event; 324 325 return 0; 326 } 327 328 static int mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev *dev) 329 { 330 struct mt76_phy *mphy = &dev->mt76.phy; 331 struct mt76_connac_pm *pm = &dev->pm; 332 int i, err = 0; 333 334 mutex_lock(&pm->mutex); 335 336 if (!test_bit(MT76_STATE_PM, &mphy->state)) 337 goto out; 338 339 for (i = 0; i < MT7615_DRV_OWN_RETRY_COUNT; i++) { 340 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN); 341 if (mt76_poll_msec(dev, MT_CONN_HIF_ON_LPCTL, 342 MT_CFG_LPCR_HOST_FW_OWN, 0, 50)) 343 break; 344 } 345 346 if (i == MT7615_DRV_OWN_RETRY_COUNT) { 347 dev_err(dev->mt76.dev, "driver own failed\n"); 348 err = -EIO; 349 goto out; 350 } 351 clear_bit(MT76_STATE_PM, &mphy->state); 352 353 pm->stats.last_wake_event = jiffies; 354 pm->stats.doze_time += pm->stats.last_wake_event - 355 pm->stats.last_doze_event; 356 out: 357 mutex_unlock(&pm->mutex); 358 359 return err; 360 } 361 362 static int mt7615_mcu_fw_pmctrl(struct mt7615_dev *dev) 363 { 364 struct mt76_phy *mphy = &dev->mt76.phy; 365 struct mt76_connac_pm *pm = &dev->pm; 366 int err = 0; 367 u32 addr; 368 369 mutex_lock(&pm->mutex); 370 371 if (mt76_connac_skip_fw_pmctrl(mphy, pm)) 372 goto out; 373 374 mt7622_trigger_hif_int(dev, true); 375 376 addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST; 377 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_FW_OWN); 378 379 if (is_mt7622(&dev->mt76) && 380 !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 381 MT_CFG_LPCR_HOST_FW_OWN, 3000)) { 382 dev_err(dev->mt76.dev, "Timeout for firmware own\n"); 383 clear_bit(MT76_STATE_PM, &mphy->state); 384 err = -EIO; 385 } 386 387 mt7622_trigger_hif_int(dev, false); 388 389 pm->stats.last_doze_event = jiffies; 390 pm->stats.awake_time += pm->stats.last_doze_event - 391 pm->stats.last_wake_event; 392 out: 393 mutex_unlock(&pm->mutex); 394 395 return err; 396 } 397 398 static void 399 mt7615_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif) 400 { 401 if (vif->csa_active) 402 ieee80211_csa_finish(vif); 403 } 404 405 static void 406 mt7615_mcu_rx_csa_notify(struct mt7615_dev *dev, struct sk_buff *skb) 407 { 408 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev); 409 struct mt76_phy *mphy = &dev->mt76.phy; 410 struct mt7615_mcu_csa_notify *c; 411 412 c = (struct mt7615_mcu_csa_notify *)skb->data; 413 414 if (c->omac_idx > EXT_BSSID_MAX) 415 return; 416 417 if (ext_phy && ext_phy->omac_mask & BIT_ULL(c->omac_idx)) 418 mphy = dev->mt76.phy2; 419 420 ieee80211_iterate_active_interfaces_atomic(mphy->hw, 421 IEEE80211_IFACE_ITER_RESUME_ALL, 422 mt7615_mcu_csa_finish, mphy->hw); 423 } 424 425 static void 426 mt7615_mcu_rx_radar_detected(struct mt7615_dev *dev, struct sk_buff *skb) 427 { 428 struct mt76_phy *mphy = &dev->mt76.phy; 429 struct mt7615_mcu_rdd_report *r; 430 431 r = (struct mt7615_mcu_rdd_report *)skb->data; 432 433 if (!dev->radar_pattern.n_pulses && !r->long_detected && 434 !r->constant_prf_detected && !r->staggered_prf_detected) 435 return; 436 437 if (r->band_idx && dev->mt76.phy2) 438 mphy = dev->mt76.phy2; 439 440 ieee80211_radar_detected(mphy->hw); 441 dev->hw_pattern++; 442 } 443 444 static void 445 mt7615_mcu_rx_log_message(struct mt7615_dev *dev, struct sk_buff *skb) 446 { 447 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 448 const char *data = (char *)&rxd[1]; 449 const char *type; 450 451 switch (rxd->s2d_index) { 452 case 0: 453 type = "N9"; 454 break; 455 case 2: 456 type = "CR4"; 457 break; 458 default: 459 type = "unknown"; 460 break; 461 } 462 463 wiphy_info(mt76_hw(dev)->wiphy, "%s: %.*s", type, 464 (int)(skb->len - sizeof(*rxd)), data); 465 } 466 467 static void 468 mt7615_mcu_rx_ext_event(struct mt7615_dev *dev, struct sk_buff *skb) 469 { 470 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 471 472 switch (rxd->ext_eid) { 473 case MCU_EXT_EVENT_RDD_REPORT: 474 mt7615_mcu_rx_radar_detected(dev, skb); 475 break; 476 case MCU_EXT_EVENT_CSA_NOTIFY: 477 mt7615_mcu_rx_csa_notify(dev, skb); 478 break; 479 case MCU_EXT_EVENT_FW_LOG_2_HOST: 480 mt7615_mcu_rx_log_message(dev, skb); 481 break; 482 default: 483 break; 484 } 485 } 486 487 static void 488 mt7615_mcu_scan_event(struct mt7615_dev *dev, struct sk_buff *skb) 489 { 490 u8 *seq_num = skb->data + sizeof(struct mt7615_mcu_rxd); 491 struct mt7615_phy *phy; 492 struct mt76_phy *mphy; 493 494 if (*seq_num & BIT(7) && dev->mt76.phy2) 495 mphy = dev->mt76.phy2; 496 else 497 mphy = &dev->mt76.phy; 498 499 phy = (struct mt7615_phy *)mphy->priv; 500 501 spin_lock_bh(&dev->mt76.lock); 502 __skb_queue_tail(&phy->scan_event_list, skb); 503 spin_unlock_bh(&dev->mt76.lock); 504 505 ieee80211_queue_delayed_work(mphy->hw, &phy->scan_work, 506 MT7615_HW_SCAN_TIMEOUT); 507 } 508 509 static void 510 mt7615_mcu_roc_event(struct mt7615_dev *dev, struct sk_buff *skb) 511 { 512 struct mt7615_roc_tlv *event; 513 struct mt7615_phy *phy; 514 struct mt76_phy *mphy; 515 int duration; 516 517 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 518 event = (struct mt7615_roc_tlv *)skb->data; 519 520 if (event->dbdc_band && dev->mt76.phy2) 521 mphy = dev->mt76.phy2; 522 else 523 mphy = &dev->mt76.phy; 524 525 ieee80211_ready_on_channel(mphy->hw); 526 527 phy = (struct mt7615_phy *)mphy->priv; 528 phy->roc_grant = true; 529 wake_up(&phy->roc_wait); 530 531 duration = le32_to_cpu(event->max_interval); 532 mod_timer(&phy->roc_timer, 533 round_jiffies_up(jiffies + msecs_to_jiffies(duration))); 534 } 535 536 static void 537 mt7615_mcu_beacon_loss_event(struct mt7615_dev *dev, struct sk_buff *skb) 538 { 539 struct mt76_connac_beacon_loss_event *event; 540 struct mt76_phy *mphy; 541 u8 band_idx = 0; /* DBDC support */ 542 543 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 544 event = (struct mt76_connac_beacon_loss_event *)skb->data; 545 if (band_idx && dev->mt76.phy2) 546 mphy = dev->mt76.phy2; 547 else 548 mphy = &dev->mt76.phy; 549 550 ieee80211_iterate_active_interfaces_atomic(mphy->hw, 551 IEEE80211_IFACE_ITER_RESUME_ALL, 552 mt76_connac_mcu_beacon_loss_iter, 553 event); 554 } 555 556 static void 557 mt7615_mcu_bss_event(struct mt7615_dev *dev, struct sk_buff *skb) 558 { 559 struct mt76_connac_mcu_bss_event *event; 560 struct mt76_phy *mphy; 561 u8 band_idx = 0; /* DBDC support */ 562 563 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 564 event = (struct mt76_connac_mcu_bss_event *)skb->data; 565 566 if (band_idx && dev->mt76.phy2) 567 mphy = dev->mt76.phy2; 568 else 569 mphy = &dev->mt76.phy; 570 571 if (event->is_absent) 572 ieee80211_stop_queues(mphy->hw); 573 else 574 ieee80211_wake_queues(mphy->hw); 575 } 576 577 static void 578 mt7615_mcu_rx_unsolicited_event(struct mt7615_dev *dev, struct sk_buff *skb) 579 { 580 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 581 582 switch (rxd->eid) { 583 case MCU_EVENT_EXT: 584 mt7615_mcu_rx_ext_event(dev, skb); 585 break; 586 case MCU_EVENT_BSS_BEACON_LOSS: 587 mt7615_mcu_beacon_loss_event(dev, skb); 588 break; 589 case MCU_EVENT_ROC: 590 mt7615_mcu_roc_event(dev, skb); 591 break; 592 case MCU_EVENT_SCHED_SCAN_DONE: 593 case MCU_EVENT_SCAN_DONE: 594 mt7615_mcu_scan_event(dev, skb); 595 return; 596 case MCU_EVENT_BSS_ABSENCE: 597 mt7615_mcu_bss_event(dev, skb); 598 break; 599 case MCU_EVENT_COREDUMP: 600 mt76_connac_mcu_coredump_event(&dev->mt76, skb, 601 &dev->coredump); 602 return; 603 default: 604 break; 605 } 606 dev_kfree_skb(skb); 607 } 608 609 void mt7615_mcu_rx_event(struct mt7615_dev *dev, struct sk_buff *skb) 610 { 611 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 612 613 if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT || 614 rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST || 615 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP || 616 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC || 617 rxd->eid == MCU_EVENT_BSS_BEACON_LOSS || 618 rxd->eid == MCU_EVENT_SCHED_SCAN_DONE || 619 rxd->eid == MCU_EVENT_BSS_ABSENCE || 620 rxd->eid == MCU_EVENT_SCAN_DONE || 621 rxd->eid == MCU_EVENT_COREDUMP || 622 rxd->eid == MCU_EVENT_ROC || 623 !rxd->seq) 624 mt7615_mcu_rx_unsolicited_event(dev, skb); 625 else 626 mt76_mcu_rx_event(&dev->mt76, skb); 627 } 628 629 static int 630 mt7615_mcu_muar_config(struct mt7615_dev *dev, struct ieee80211_vif *vif, 631 bool bssid, bool enable) 632 { 633 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 634 u32 idx = mvif->mt76.omac_idx - REPEATER_BSSID_START; 635 u32 mask = dev->omac_mask >> 32 & ~BIT(idx); 636 const u8 *addr = vif->addr; 637 struct { 638 u8 mode; 639 u8 force_clear; 640 u8 clear_bitmap[8]; 641 u8 entry_count; 642 u8 write; 643 644 u8 index; 645 u8 bssid; 646 u8 addr[ETH_ALEN]; 647 } __packed req = { 648 .mode = !!mask || enable, 649 .entry_count = 1, 650 .write = 1, 651 652 .index = idx * 2 + bssid, 653 }; 654 655 if (bssid) 656 addr = vif->bss_conf.bssid; 657 658 if (enable) 659 ether_addr_copy(req.addr, addr); 660 661 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_MUAR_UPDATE, &req, 662 sizeof(req), true); 663 } 664 665 static int 666 mt7615_mcu_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif, 667 bool enable) 668 { 669 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 670 struct mt7615_dev *dev = phy->dev; 671 struct { 672 struct req_hdr { 673 u8 omac_idx; 674 u8 band_idx; 675 __le16 tlv_num; 676 u8 is_tlv_append; 677 u8 rsv[3]; 678 } __packed hdr; 679 struct req_tlv { 680 __le16 tag; 681 __le16 len; 682 u8 active; 683 u8 band_idx; 684 u8 omac_addr[ETH_ALEN]; 685 } __packed tlv; 686 } data = { 687 .hdr = { 688 .omac_idx = mvif->mt76.omac_idx, 689 .band_idx = mvif->mt76.band_idx, 690 .tlv_num = cpu_to_le16(1), 691 .is_tlv_append = 1, 692 }, 693 .tlv = { 694 .tag = cpu_to_le16(DEV_INFO_ACTIVE), 695 .len = cpu_to_le16(sizeof(struct req_tlv)), 696 .active = enable, 697 .band_idx = mvif->mt76.band_idx, 698 }, 699 }; 700 701 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START) 702 return mt7615_mcu_muar_config(dev, vif, false, enable); 703 704 memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN); 705 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_DEV_INFO_UPDATE, 706 &data, sizeof(data), true); 707 } 708 709 static int 710 mt7615_mcu_add_beacon_offload(struct mt7615_dev *dev, 711 struct ieee80211_hw *hw, 712 struct ieee80211_vif *vif, bool enable) 713 { 714 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 715 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 716 struct ieee80211_mutable_offsets offs; 717 struct ieee80211_tx_info *info; 718 struct req { 719 u8 omac_idx; 720 u8 enable; 721 u8 wlan_idx; 722 u8 band_idx; 723 u8 pkt_type; 724 u8 need_pre_tbtt_int; 725 __le16 csa_ie_pos; 726 __le16 pkt_len; 727 __le16 tim_ie_pos; 728 u8 pkt[512]; 729 u8 csa_cnt; 730 /* bss color change */ 731 u8 bcc_cnt; 732 __le16 bcc_ie_pos; 733 } __packed req = { 734 .omac_idx = mvif->mt76.omac_idx, 735 .enable = enable, 736 .wlan_idx = wcid->idx, 737 .band_idx = mvif->mt76.band_idx, 738 }; 739 struct sk_buff *skb; 740 741 if (!enable) 742 goto out; 743 744 skb = ieee80211_beacon_get_template(hw, vif, &offs); 745 if (!skb) 746 return -EINVAL; 747 748 if (skb->len > 512 - MT_TXD_SIZE) { 749 dev_err(dev->mt76.dev, "Bcn size limit exceed\n"); 750 dev_kfree_skb(skb); 751 return -EINVAL; 752 } 753 754 if (mvif->mt76.band_idx) { 755 info = IEEE80211_SKB_CB(skb); 756 info->hw_queue |= MT_TX_HW_QUEUE_EXT_PHY; 757 } 758 759 mt7615_mac_write_txwi(dev, (__le32 *)(req.pkt), skb, wcid, NULL, 760 0, NULL, true); 761 memcpy(req.pkt + MT_TXD_SIZE, skb->data, skb->len); 762 req.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 763 req.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 764 if (offs.cntdwn_counter_offs[0]) { 765 u16 csa_offs; 766 767 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4; 768 req.csa_ie_pos = cpu_to_le16(csa_offs); 769 req.csa_cnt = skb->data[offs.cntdwn_counter_offs[0]]; 770 } 771 dev_kfree_skb(skb); 772 773 out: 774 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_BCN_OFFLOAD, &req, 775 sizeof(req), true); 776 } 777 778 static int 779 mt7615_mcu_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 780 { 781 #define ENTER_PM_STATE 1 782 #define EXIT_PM_STATE 2 783 struct { 784 u8 pm_number; 785 u8 pm_state; 786 u8 bssid[ETH_ALEN]; 787 u8 dtim_period; 788 u8 wlan_idx; 789 __le16 bcn_interval; 790 __le32 aid; 791 __le32 rx_filter; 792 u8 band_idx; 793 u8 rsv[3]; 794 __le32 feature; 795 u8 omac_idx; 796 u8 wmm_idx; 797 u8 bcn_loss_cnt; 798 u8 bcn_sp_duration; 799 } __packed req = { 800 .pm_number = 5, 801 .pm_state = state ? ENTER_PM_STATE : EXIT_PM_STATE, 802 .band_idx = band, 803 }; 804 805 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_PM_STATE_CTRL, &req, 806 sizeof(req), true); 807 } 808 809 static int 810 mt7615_mcu_bss_basic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif, 811 struct ieee80211_sta *sta, struct mt7615_phy *phy, 812 bool enable) 813 { 814 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 815 u32 type = vif->p2p ? NETWORK_P2P : NETWORK_INFRA; 816 struct bss_info_basic *bss; 817 u8 wlan_idx = mvif->sta.wcid.idx; 818 struct tlv *tlv; 819 820 tlv = mt76_connac_mcu_add_tlv(skb, BSS_INFO_BASIC, sizeof(*bss)); 821 822 switch (vif->type) { 823 case NL80211_IFTYPE_MESH_POINT: 824 case NL80211_IFTYPE_AP: 825 case NL80211_IFTYPE_MONITOR: 826 break; 827 case NL80211_IFTYPE_STATION: 828 /* TODO: enable BSS_INFO_UAPSD & BSS_INFO_PM */ 829 if (enable && sta) { 830 struct mt7615_sta *msta; 831 832 msta = (struct mt7615_sta *)sta->drv_priv; 833 wlan_idx = msta->wcid.idx; 834 } 835 break; 836 case NL80211_IFTYPE_ADHOC: 837 type = NETWORK_IBSS; 838 break; 839 default: 840 WARN_ON(1); 841 break; 842 } 843 844 bss = (struct bss_info_basic *)tlv; 845 bss->network_type = cpu_to_le32(type); 846 bss->bmc_tx_wlan_idx = wlan_idx; 847 bss->wmm_idx = mvif->mt76.wmm_idx; 848 bss->active = enable; 849 850 if (vif->type != NL80211_IFTYPE_MONITOR) { 851 memcpy(bss->bssid, vif->bss_conf.bssid, ETH_ALEN); 852 bss->bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int); 853 bss->dtim_period = vif->bss_conf.dtim_period; 854 } else { 855 memcpy(bss->bssid, phy->mt76->macaddr, ETH_ALEN); 856 } 857 858 return 0; 859 } 860 861 static void 862 mt7615_mcu_bss_omac_tlv(struct sk_buff *skb, struct ieee80211_vif *vif) 863 { 864 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 865 u8 omac_idx = mvif->mt76.omac_idx; 866 struct bss_info_omac *omac; 867 struct tlv *tlv; 868 u32 type = 0; 869 870 tlv = mt76_connac_mcu_add_tlv(skb, BSS_INFO_OMAC, sizeof(*omac)); 871 872 switch (vif->type) { 873 case NL80211_IFTYPE_MONITOR: 874 case NL80211_IFTYPE_MESH_POINT: 875 case NL80211_IFTYPE_AP: 876 if (vif->p2p) 877 type = CONNECTION_P2P_GO; 878 else 879 type = CONNECTION_INFRA_AP; 880 break; 881 case NL80211_IFTYPE_STATION: 882 if (vif->p2p) 883 type = CONNECTION_P2P_GC; 884 else 885 type = CONNECTION_INFRA_STA; 886 break; 887 case NL80211_IFTYPE_ADHOC: 888 type = CONNECTION_IBSS_ADHOC; 889 break; 890 default: 891 WARN_ON(1); 892 break; 893 } 894 895 omac = (struct bss_info_omac *)tlv; 896 omac->conn_type = cpu_to_le32(type); 897 omac->omac_idx = mvif->mt76.omac_idx; 898 omac->band_idx = mvif->mt76.band_idx; 899 omac->hw_bss_idx = omac_idx > EXT_BSSID_START ? HW_BSSID_0 : omac_idx; 900 } 901 902 /* SIFS 20us + 512 byte beacon tranmitted by 1Mbps (3906us) */ 903 #define BCN_TX_ESTIMATE_TIME (4096 + 20) 904 static void 905 mt7615_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt7615_vif *mvif) 906 { 907 struct bss_info_ext_bss *ext; 908 int ext_bss_idx, tsf_offset; 909 struct tlv *tlv; 910 911 ext_bss_idx = mvif->mt76.omac_idx - EXT_BSSID_START; 912 if (ext_bss_idx < 0) 913 return; 914 915 tlv = mt76_connac_mcu_add_tlv(skb, BSS_INFO_EXT_BSS, sizeof(*ext)); 916 917 ext = (struct bss_info_ext_bss *)tlv; 918 tsf_offset = ext_bss_idx * BCN_TX_ESTIMATE_TIME; 919 ext->mbss_tsf_offset = cpu_to_le32(tsf_offset); 920 } 921 922 static int 923 mt7615_mcu_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif, 924 struct ieee80211_sta *sta, bool enable) 925 { 926 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 927 struct mt7615_dev *dev = phy->dev; 928 struct sk_buff *skb; 929 930 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START) 931 mt7615_mcu_muar_config(dev, vif, true, enable); 932 933 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, NULL); 934 if (IS_ERR(skb)) 935 return PTR_ERR(skb); 936 937 if (enable) 938 mt7615_mcu_bss_omac_tlv(skb, vif); 939 940 mt7615_mcu_bss_basic_tlv(skb, vif, sta, phy, enable); 941 942 if (enable && mvif->mt76.omac_idx >= EXT_BSSID_START && 943 mvif->mt76.omac_idx < REPEATER_BSSID_START) 944 mt7615_mcu_bss_ext_tlv(skb, mvif); 945 946 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 947 MCU_EXT_CMD_BSS_INFO_UPDATE, true); 948 } 949 950 static int 951 mt7615_mcu_wtbl_tx_ba(struct mt7615_dev *dev, 952 struct ieee80211_ampdu_params *params, 953 bool enable) 954 { 955 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 956 struct mt7615_vif *mvif = msta->vif; 957 struct wtbl_req_hdr *wtbl_hdr; 958 struct sk_buff *skb = NULL; 959 int err; 960 961 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 962 WTBL_SET, NULL, &skb); 963 if (IS_ERR(wtbl_hdr)) 964 return PTR_ERR(wtbl_hdr); 965 966 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, true, 967 NULL, wtbl_hdr); 968 969 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, MCU_EXT_CMD_WTBL_UPDATE, 970 true); 971 if (err < 0) 972 return err; 973 974 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 975 &msta->wcid); 976 if (IS_ERR(skb)) 977 return PTR_ERR(skb); 978 979 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, true); 980 981 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 982 MCU_EXT_CMD_STA_REC_UPDATE, true); 983 } 984 985 static int 986 mt7615_mcu_wtbl_rx_ba(struct mt7615_dev *dev, 987 struct ieee80211_ampdu_params *params, 988 bool enable) 989 { 990 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 991 struct mt7615_vif *mvif = msta->vif; 992 struct wtbl_req_hdr *wtbl_hdr; 993 struct sk_buff *skb; 994 int err; 995 996 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 997 &msta->wcid); 998 if (IS_ERR(skb)) 999 return PTR_ERR(skb); 1000 1001 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false); 1002 1003 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, 1004 MCU_EXT_CMD_STA_REC_UPDATE, true); 1005 if (err < 0 || !enable) 1006 return err; 1007 1008 skb = NULL; 1009 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 1010 WTBL_SET, NULL, &skb); 1011 if (IS_ERR(wtbl_hdr)) 1012 return PTR_ERR(wtbl_hdr); 1013 1014 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false, 1015 NULL, wtbl_hdr); 1016 1017 return mt76_mcu_skb_send_msg(&dev->mt76, skb, MCU_EXT_CMD_WTBL_UPDATE, 1018 true); 1019 } 1020 1021 static int 1022 mt7615_mcu_wtbl_sta_add(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1023 struct ieee80211_sta *sta, bool enable) 1024 { 1025 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1026 struct sk_buff *skb, *sskb, *wskb = NULL; 1027 struct mt7615_dev *dev = phy->dev; 1028 struct wtbl_req_hdr *wtbl_hdr; 1029 struct mt7615_sta *msta; 1030 int cmd, err; 1031 1032 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta; 1033 1034 sskb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 1035 &msta->wcid); 1036 if (IS_ERR(sskb)) 1037 return PTR_ERR(sskb); 1038 1039 mt76_connac_mcu_sta_basic_tlv(sskb, vif, sta, enable, true); 1040 if (enable && sta) 1041 mt76_connac_mcu_sta_tlv(phy->mt76, sskb, sta, vif, 0, 1042 MT76_STA_INFO_STATE_ASSOC); 1043 1044 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 1045 WTBL_RESET_AND_SET, NULL, 1046 &wskb); 1047 if (IS_ERR(wtbl_hdr)) 1048 return PTR_ERR(wtbl_hdr); 1049 1050 if (enable) { 1051 mt76_connac_mcu_wtbl_generic_tlv(&dev->mt76, wskb, vif, sta, 1052 NULL, wtbl_hdr); 1053 if (sta) 1054 mt76_connac_mcu_wtbl_ht_tlv(&dev->mt76, wskb, sta, 1055 NULL, wtbl_hdr); 1056 mt76_connac_mcu_wtbl_hdr_trans_tlv(wskb, vif, &msta->wcid, 1057 NULL, wtbl_hdr); 1058 } 1059 1060 cmd = enable ? MCU_EXT_CMD_WTBL_UPDATE : MCU_EXT_CMD_STA_REC_UPDATE; 1061 skb = enable ? wskb : sskb; 1062 1063 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1064 if (err < 0) { 1065 skb = enable ? sskb : wskb; 1066 dev_kfree_skb(skb); 1067 1068 return err; 1069 } 1070 1071 cmd = enable ? MCU_EXT_CMD_STA_REC_UPDATE : MCU_EXT_CMD_WTBL_UPDATE; 1072 skb = enable ? sskb : wskb; 1073 1074 return mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1075 } 1076 1077 static int 1078 mt7615_mcu_wtbl_update_hdr_trans(struct mt7615_dev *dev, 1079 struct ieee80211_vif *vif, 1080 struct ieee80211_sta *sta) 1081 { 1082 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 1083 struct wtbl_req_hdr *wtbl_hdr; 1084 struct sk_buff *skb = NULL; 1085 1086 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 1087 WTBL_SET, NULL, &skb); 1088 if (IS_ERR(wtbl_hdr)) 1089 return PTR_ERR(wtbl_hdr); 1090 1091 mt76_connac_mcu_wtbl_hdr_trans_tlv(skb, vif, &msta->wcid, NULL, 1092 wtbl_hdr); 1093 return mt76_mcu_skb_send_msg(&dev->mt76, skb, MCU_EXT_CMD_WTBL_UPDATE, 1094 true); 1095 } 1096 1097 static const struct mt7615_mcu_ops wtbl_update_ops = { 1098 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 1099 .set_pm_state = mt7615_mcu_ctrl_pm_state, 1100 .add_dev_info = mt7615_mcu_add_dev, 1101 .add_bss_info = mt7615_mcu_add_bss, 1102 .add_tx_ba = mt7615_mcu_wtbl_tx_ba, 1103 .add_rx_ba = mt7615_mcu_wtbl_rx_ba, 1104 .sta_add = mt7615_mcu_wtbl_sta_add, 1105 .set_drv_ctrl = mt7615_mcu_drv_pmctrl, 1106 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1107 .set_sta_decap_offload = mt7615_mcu_wtbl_update_hdr_trans, 1108 }; 1109 1110 static int 1111 mt7615_mcu_sta_ba(struct mt7615_dev *dev, 1112 struct ieee80211_ampdu_params *params, 1113 bool enable, bool tx) 1114 { 1115 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1116 struct mt7615_vif *mvif = msta->vif; 1117 struct wtbl_req_hdr *wtbl_hdr; 1118 struct tlv *sta_wtbl; 1119 struct sk_buff *skb; 1120 1121 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 1122 &msta->wcid); 1123 if (IS_ERR(skb)) 1124 return PTR_ERR(skb); 1125 1126 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx); 1127 1128 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1129 1130 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 1131 WTBL_SET, sta_wtbl, &skb); 1132 if (IS_ERR(wtbl_hdr)) 1133 return PTR_ERR(wtbl_hdr); 1134 1135 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, tx, 1136 sta_wtbl, wtbl_hdr); 1137 1138 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 1139 MCU_EXT_CMD_STA_REC_UPDATE, true); 1140 } 1141 1142 static int 1143 mt7615_mcu_sta_tx_ba(struct mt7615_dev *dev, 1144 struct ieee80211_ampdu_params *params, 1145 bool enable) 1146 { 1147 return mt7615_mcu_sta_ba(dev, params, enable, true); 1148 } 1149 1150 static int 1151 mt7615_mcu_sta_rx_ba(struct mt7615_dev *dev, 1152 struct ieee80211_ampdu_params *params, 1153 bool enable) 1154 { 1155 return mt7615_mcu_sta_ba(dev, params, enable, false); 1156 } 1157 1158 static int 1159 __mt7615_mcu_add_sta(struct mt76_phy *phy, struct ieee80211_vif *vif, 1160 struct ieee80211_sta *sta, bool enable, int cmd, 1161 bool offload_fw) 1162 { 1163 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1164 struct mt76_sta_cmd_info info = { 1165 .sta = sta, 1166 .vif = vif, 1167 .offload_fw = offload_fw, 1168 .enable = enable, 1169 .newly = true, 1170 .cmd = cmd, 1171 }; 1172 1173 info.wcid = sta ? (struct mt76_wcid *)sta->drv_priv : &mvif->sta.wcid; 1174 return mt76_connac_mcu_sta_cmd(phy, &info); 1175 } 1176 1177 static int 1178 mt7615_mcu_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1179 struct ieee80211_sta *sta, bool enable) 1180 { 1181 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable, 1182 MCU_EXT_CMD_STA_REC_UPDATE, false); 1183 } 1184 1185 static int 1186 mt7615_mcu_sta_update_hdr_trans(struct mt7615_dev *dev, 1187 struct ieee80211_vif *vif, 1188 struct ieee80211_sta *sta) 1189 { 1190 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 1191 1192 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76, 1193 vif, &msta->wcid, 1194 MCU_EXT_CMD_STA_REC_UPDATE); 1195 } 1196 1197 static const struct mt7615_mcu_ops sta_update_ops = { 1198 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 1199 .set_pm_state = mt7615_mcu_ctrl_pm_state, 1200 .add_dev_info = mt7615_mcu_add_dev, 1201 .add_bss_info = mt7615_mcu_add_bss, 1202 .add_tx_ba = mt7615_mcu_sta_tx_ba, 1203 .add_rx_ba = mt7615_mcu_sta_rx_ba, 1204 .sta_add = mt7615_mcu_add_sta, 1205 .set_drv_ctrl = mt7615_mcu_drv_pmctrl, 1206 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1207 .set_sta_decap_offload = mt7615_mcu_sta_update_hdr_trans, 1208 }; 1209 1210 static int 1211 mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 1212 { 1213 return 0; 1214 } 1215 1216 static int 1217 mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev *dev, 1218 struct ieee80211_hw *hw, 1219 struct ieee80211_vif *vif, 1220 bool enable) 1221 { 1222 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1223 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 1224 struct ieee80211_mutable_offsets offs; 1225 struct { 1226 struct req_hdr { 1227 u8 bss_idx; 1228 u8 pad[3]; 1229 } __packed hdr; 1230 struct bcn_content_tlv { 1231 __le16 tag; 1232 __le16 len; 1233 __le16 tim_ie_pos; 1234 __le16 csa_ie_pos; 1235 __le16 bcc_ie_pos; 1236 /* 0: disable beacon offload 1237 * 1: enable beacon offload 1238 * 2: update probe respond offload 1239 */ 1240 u8 enable; 1241 /* 0: legacy format (TXD + payload) 1242 * 1: only cap field IE 1243 */ 1244 u8 type; 1245 __le16 pkt_len; 1246 u8 pkt[512]; 1247 } __packed beacon_tlv; 1248 } req = { 1249 .hdr = { 1250 .bss_idx = mvif->mt76.idx, 1251 }, 1252 .beacon_tlv = { 1253 .tag = cpu_to_le16(UNI_BSS_INFO_BCN_CONTENT), 1254 .len = cpu_to_le16(sizeof(struct bcn_content_tlv)), 1255 .enable = enable, 1256 }, 1257 }; 1258 struct sk_buff *skb; 1259 1260 if (!enable) 1261 goto out; 1262 1263 skb = ieee80211_beacon_get_template(mt76_hw(dev), vif, &offs); 1264 if (!skb) 1265 return -EINVAL; 1266 1267 if (skb->len > 512 - MT_TXD_SIZE) { 1268 dev_err(dev->mt76.dev, "beacon size limit exceed\n"); 1269 dev_kfree_skb(skb); 1270 return -EINVAL; 1271 } 1272 1273 mt7615_mac_write_txwi(dev, (__le32 *)(req.beacon_tlv.pkt), skb, 1274 wcid, NULL, 0, NULL, true); 1275 memcpy(req.beacon_tlv.pkt + MT_TXD_SIZE, skb->data, skb->len); 1276 req.beacon_tlv.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 1277 req.beacon_tlv.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 1278 1279 if (offs.cntdwn_counter_offs[0]) { 1280 u16 csa_offs; 1281 1282 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4; 1283 req.beacon_tlv.csa_ie_pos = cpu_to_le16(csa_offs); 1284 } 1285 dev_kfree_skb(skb); 1286 1287 out: 1288 return mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_BSS_INFO_UPDATE, 1289 &req, sizeof(req), true); 1290 } 1291 1292 static int 1293 mt7615_mcu_uni_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1294 bool enable) 1295 { 1296 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1297 1298 return mt76_connac_mcu_uni_add_dev(phy->mt76, vif, &mvif->sta.wcid, 1299 enable); 1300 } 1301 1302 static int 1303 mt7615_mcu_uni_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1304 struct ieee80211_sta *sta, bool enable) 1305 { 1306 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1307 1308 return mt76_connac_mcu_uni_add_bss(phy->mt76, vif, &mvif->sta.wcid, 1309 enable); 1310 } 1311 1312 static inline int 1313 mt7615_mcu_uni_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1314 struct ieee80211_sta *sta, bool enable) 1315 { 1316 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable, 1317 MCU_UNI_CMD_STA_REC_UPDATE, true); 1318 } 1319 1320 static int 1321 mt7615_mcu_uni_tx_ba(struct mt7615_dev *dev, 1322 struct ieee80211_ampdu_params *params, 1323 bool enable) 1324 { 1325 struct mt7615_sta *sta = (struct mt7615_sta *)params->sta->drv_priv; 1326 1327 return mt76_connac_mcu_sta_ba(&dev->mt76, &sta->vif->mt76, params, 1328 enable, true); 1329 } 1330 1331 static int 1332 mt7615_mcu_uni_rx_ba(struct mt7615_dev *dev, 1333 struct ieee80211_ampdu_params *params, 1334 bool enable) 1335 { 1336 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1337 struct mt7615_vif *mvif = msta->vif; 1338 struct wtbl_req_hdr *wtbl_hdr; 1339 struct tlv *sta_wtbl; 1340 struct sk_buff *skb; 1341 int err; 1342 1343 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 1344 &msta->wcid); 1345 if (IS_ERR(skb)) 1346 return PTR_ERR(skb); 1347 1348 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false); 1349 1350 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, 1351 MCU_UNI_CMD_STA_REC_UPDATE, true); 1352 if (err < 0 || !enable) 1353 return err; 1354 1355 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 1356 &msta->wcid); 1357 if (IS_ERR(skb)) 1358 return PTR_ERR(skb); 1359 1360 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL, 1361 sizeof(struct tlv)); 1362 1363 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 1364 WTBL_SET, sta_wtbl, &skb); 1365 if (IS_ERR(wtbl_hdr)) 1366 return PTR_ERR(wtbl_hdr); 1367 1368 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false, 1369 sta_wtbl, wtbl_hdr); 1370 1371 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 1372 MCU_UNI_CMD_STA_REC_UPDATE, true); 1373 } 1374 1375 static int 1376 mt7615_mcu_sta_uni_update_hdr_trans(struct mt7615_dev *dev, 1377 struct ieee80211_vif *vif, 1378 struct ieee80211_sta *sta) 1379 { 1380 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 1381 1382 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76, 1383 vif, &msta->wcid, 1384 MCU_UNI_CMD_STA_REC_UPDATE); 1385 } 1386 1387 static const struct mt7615_mcu_ops uni_update_ops = { 1388 .add_beacon_offload = mt7615_mcu_uni_add_beacon_offload, 1389 .set_pm_state = mt7615_mcu_uni_ctrl_pm_state, 1390 .add_dev_info = mt7615_mcu_uni_add_dev, 1391 .add_bss_info = mt7615_mcu_uni_add_bss, 1392 .add_tx_ba = mt7615_mcu_uni_tx_ba, 1393 .add_rx_ba = mt7615_mcu_uni_rx_ba, 1394 .sta_add = mt7615_mcu_uni_add_sta, 1395 .set_drv_ctrl = mt7615_mcu_lp_drv_pmctrl, 1396 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1397 .set_sta_decap_offload = mt7615_mcu_sta_uni_update_hdr_trans, 1398 }; 1399 1400 int mt7615_mcu_restart(struct mt76_dev *dev) 1401 { 1402 return mt76_mcu_send_msg(dev, MCU_CMD_RESTART_DL_REQ, NULL, 0, true); 1403 } 1404 EXPORT_SYMBOL_GPL(mt7615_mcu_restart); 1405 1406 static int mt7615_load_patch(struct mt7615_dev *dev, u32 addr, const char *name) 1407 { 1408 const struct mt7615_patch_hdr *hdr; 1409 const struct firmware *fw = NULL; 1410 int len, ret, sem; 1411 1412 ret = firmware_request_nowarn(&fw, name, dev->mt76.dev); 1413 if (ret) 1414 return ret; 1415 1416 if (!fw || !fw->data || fw->size < sizeof(*hdr)) { 1417 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1418 ret = -EINVAL; 1419 goto release_fw; 1420 } 1421 1422 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, true); 1423 switch (sem) { 1424 case PATCH_IS_DL: 1425 goto release_fw; 1426 case PATCH_NOT_DL_SEM_SUCCESS: 1427 break; 1428 default: 1429 dev_err(dev->mt76.dev, "Failed to get patch semaphore\n"); 1430 ret = -EAGAIN; 1431 goto release_fw; 1432 } 1433 1434 hdr = (const struct mt7615_patch_hdr *)(fw->data); 1435 1436 dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n", 1437 be32_to_cpu(hdr->hw_sw_ver), hdr->build_date); 1438 1439 len = fw->size - sizeof(*hdr); 1440 1441 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len, 1442 DL_MODE_NEED_RSP); 1443 if (ret) { 1444 dev_err(dev->mt76.dev, "Download request failed\n"); 1445 goto out; 1446 } 1447 1448 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD_FW_SCATTER, 1449 fw->data + sizeof(*hdr), len); 1450 if (ret) { 1451 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 1452 goto out; 1453 } 1454 1455 ret = mt76_connac_mcu_start_patch(&dev->mt76); 1456 if (ret) 1457 dev_err(dev->mt76.dev, "Failed to start patch\n"); 1458 1459 out: 1460 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, false); 1461 switch (sem) { 1462 case PATCH_REL_SEM_SUCCESS: 1463 break; 1464 default: 1465 ret = -EAGAIN; 1466 dev_err(dev->mt76.dev, "Failed to release patch semaphore\n"); 1467 break; 1468 } 1469 1470 release_fw: 1471 release_firmware(fw); 1472 1473 return ret; 1474 } 1475 1476 static u32 mt7615_mcu_gen_dl_mode(u8 feature_set, bool is_cr4) 1477 { 1478 u32 ret = 0; 1479 1480 ret |= (feature_set & FW_FEATURE_SET_ENCRYPT) ? 1481 (DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV) : 0; 1482 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1483 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1484 ret |= DL_MODE_NEED_RSP; 1485 ret |= is_cr4 ? DL_MODE_WORKING_PDA_CR4 : 0; 1486 1487 return ret; 1488 } 1489 1490 static int 1491 mt7615_mcu_send_ram_firmware(struct mt7615_dev *dev, 1492 const struct mt7615_fw_trailer *hdr, 1493 const u8 *data, bool is_cr4) 1494 { 1495 int n_region = is_cr4 ? CR4_REGION_NUM : N9_REGION_NUM; 1496 int err, i, offset = 0; 1497 u32 len, addr, mode; 1498 1499 for (i = 0; i < n_region; i++) { 1500 mode = mt7615_mcu_gen_dl_mode(hdr[i].feature_set, is_cr4); 1501 len = le32_to_cpu(hdr[i].len) + IMG_CRC_LEN; 1502 addr = le32_to_cpu(hdr[i].addr); 1503 1504 err = mt76_connac_mcu_init_download(&dev->mt76, addr, len, 1505 mode); 1506 if (err) { 1507 dev_err(dev->mt76.dev, "Download request failed\n"); 1508 return err; 1509 } 1510 1511 err = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD_FW_SCATTER, 1512 data + offset, len); 1513 if (err) { 1514 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 1515 return err; 1516 } 1517 1518 offset += len; 1519 } 1520 1521 return 0; 1522 } 1523 1524 static int mt7615_load_n9(struct mt7615_dev *dev, const char *name) 1525 { 1526 const struct mt7615_fw_trailer *hdr; 1527 const struct firmware *fw; 1528 int ret; 1529 1530 ret = request_firmware(&fw, name, dev->mt76.dev); 1531 if (ret) 1532 return ret; 1533 1534 if (!fw || !fw->data || fw->size < N9_REGION_NUM * sizeof(*hdr)) { 1535 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1536 ret = -EINVAL; 1537 goto out; 1538 } 1539 1540 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 1541 N9_REGION_NUM * sizeof(*hdr)); 1542 1543 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 1544 hdr->fw_ver, hdr->build_date); 1545 1546 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, false); 1547 if (ret) 1548 goto out; 1549 1550 ret = mt76_connac_mcu_start_firmware(&dev->mt76, 1551 le32_to_cpu(hdr->addr), 1552 FW_START_OVERRIDE); 1553 if (ret) { 1554 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 1555 goto out; 1556 } 1557 1558 snprintf(dev->mt76.hw->wiphy->fw_version, 1559 sizeof(dev->mt76.hw->wiphy->fw_version), 1560 "%.10s-%.15s", hdr->fw_ver, hdr->build_date); 1561 1562 if (!is_mt7615(&dev->mt76)) { 1563 dev->fw_ver = MT7615_FIRMWARE_V2; 1564 dev->mcu_ops = &sta_update_ops; 1565 } else { 1566 dev->fw_ver = MT7615_FIRMWARE_V1; 1567 dev->mcu_ops = &wtbl_update_ops; 1568 } 1569 1570 out: 1571 release_firmware(fw); 1572 return ret; 1573 } 1574 1575 static int mt7615_load_cr4(struct mt7615_dev *dev, const char *name) 1576 { 1577 const struct mt7615_fw_trailer *hdr; 1578 const struct firmware *fw; 1579 int ret; 1580 1581 ret = request_firmware(&fw, name, dev->mt76.dev); 1582 if (ret) 1583 return ret; 1584 1585 if (!fw || !fw->data || fw->size < CR4_REGION_NUM * sizeof(*hdr)) { 1586 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1587 ret = -EINVAL; 1588 goto out; 1589 } 1590 1591 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 1592 CR4_REGION_NUM * sizeof(*hdr)); 1593 1594 dev_info(dev->mt76.dev, "CR4 Firmware Version: %.10s, Build Time: %.15s\n", 1595 hdr->fw_ver, hdr->build_date); 1596 1597 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, true); 1598 if (ret) 1599 goto out; 1600 1601 ret = mt76_connac_mcu_start_firmware(&dev->mt76, 0, 1602 FW_START_WORKING_PDA_CR4); 1603 if (ret) { 1604 dev_err(dev->mt76.dev, "Failed to start CR4 firmware\n"); 1605 goto out; 1606 } 1607 1608 out: 1609 release_firmware(fw); 1610 1611 return ret; 1612 } 1613 1614 static int mt7615_load_ram(struct mt7615_dev *dev) 1615 { 1616 int ret; 1617 1618 ret = mt7615_load_n9(dev, MT7615_FIRMWARE_N9); 1619 if (ret) 1620 return ret; 1621 1622 return mt7615_load_cr4(dev, MT7615_FIRMWARE_CR4); 1623 } 1624 1625 static int mt7615_load_firmware(struct mt7615_dev *dev) 1626 { 1627 int ret; 1628 u32 val; 1629 1630 val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE); 1631 1632 if (val != FW_STATE_FW_DOWNLOAD) { 1633 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 1634 return -EIO; 1635 } 1636 1637 ret = mt7615_load_patch(dev, MT7615_PATCH_ADDRESS, MT7615_ROM_PATCH); 1638 if (ret) 1639 return ret; 1640 1641 ret = mt7615_load_ram(dev); 1642 if (ret) 1643 return ret; 1644 1645 if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE, 1646 FIELD_PREP(MT_TOP_MISC2_FW_STATE, 1647 FW_STATE_CR4_RDY), 500)) { 1648 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1649 return -EIO; 1650 } 1651 1652 return 0; 1653 } 1654 1655 static int mt7622_load_firmware(struct mt7615_dev *dev) 1656 { 1657 int ret; 1658 u32 val; 1659 1660 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1661 1662 val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE); 1663 if (val != FW_STATE_FW_DOWNLOAD) { 1664 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 1665 return -EIO; 1666 } 1667 1668 ret = mt7615_load_patch(dev, MT7622_PATCH_ADDRESS, MT7622_ROM_PATCH); 1669 if (ret) 1670 return ret; 1671 1672 ret = mt7615_load_n9(dev, MT7622_FIRMWARE_N9); 1673 if (ret) 1674 return ret; 1675 1676 if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE, 1677 FIELD_PREP(MT_TOP_OFF_RSV_FW_STATE, 1678 FW_STATE_NORMAL_TRX), 1500)) { 1679 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1680 return -EIO; 1681 } 1682 1683 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1684 1685 return 0; 1686 } 1687 1688 int mt7615_mcu_fw_log_2_host(struct mt7615_dev *dev, u8 ctrl) 1689 { 1690 struct { 1691 u8 ctrl_val; 1692 u8 pad[3]; 1693 } data = { 1694 .ctrl_val = ctrl 1695 }; 1696 1697 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_FW_LOG_2_HOST, &data, 1698 sizeof(data), true); 1699 } 1700 1701 static int mt7663_load_n9(struct mt7615_dev *dev, const char *name) 1702 { 1703 u32 offset = 0, override_addr = 0, flag = FW_START_DLYCAL; 1704 const struct mt7663_fw_trailer *hdr; 1705 const struct mt7663_fw_buf *buf; 1706 const struct firmware *fw; 1707 const u8 *base_addr; 1708 int i, ret; 1709 1710 ret = request_firmware(&fw, name, dev->mt76.dev); 1711 if (ret) 1712 return ret; 1713 1714 if (!fw || !fw->data || fw->size < FW_V3_COMMON_TAILER_SIZE) { 1715 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1716 ret = -EINVAL; 1717 goto out; 1718 } 1719 1720 hdr = (const struct mt7663_fw_trailer *)(fw->data + fw->size - 1721 FW_V3_COMMON_TAILER_SIZE); 1722 1723 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 1724 hdr->fw_ver, hdr->build_date); 1725 dev_info(dev->mt76.dev, "Region number: 0x%x\n", hdr->n_region); 1726 1727 base_addr = fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE; 1728 for (i = 0; i < hdr->n_region; i++) { 1729 u32 shift = (hdr->n_region - i) * FW_V3_REGION_TAILER_SIZE; 1730 u32 len, addr, mode; 1731 1732 dev_info(dev->mt76.dev, "Parsing tailer Region: %d\n", i); 1733 1734 buf = (const struct mt7663_fw_buf *)(base_addr - shift); 1735 mode = mt7615_mcu_gen_dl_mode(buf->feature_set, false); 1736 addr = le32_to_cpu(buf->img_dest_addr); 1737 len = le32_to_cpu(buf->img_size); 1738 1739 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len, 1740 mode); 1741 if (ret) { 1742 dev_err(dev->mt76.dev, "Download request failed\n"); 1743 goto out; 1744 } 1745 1746 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD_FW_SCATTER, 1747 fw->data + offset, len); 1748 if (ret) { 1749 dev_err(dev->mt76.dev, "Failed to send firmware\n"); 1750 goto out; 1751 } 1752 1753 offset += le32_to_cpu(buf->img_size); 1754 if (buf->feature_set & DL_MODE_VALID_RAM_ENTRY) { 1755 override_addr = le32_to_cpu(buf->img_dest_addr); 1756 dev_info(dev->mt76.dev, "Region %d, override_addr = 0x%08x\n", 1757 i, override_addr); 1758 } 1759 } 1760 1761 if (override_addr) 1762 flag |= FW_START_OVERRIDE; 1763 1764 dev_info(dev->mt76.dev, "override_addr = 0x%08x, option = %d\n", 1765 override_addr, flag); 1766 1767 ret = mt76_connac_mcu_start_firmware(&dev->mt76, override_addr, flag); 1768 if (ret) { 1769 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 1770 goto out; 1771 } 1772 1773 snprintf(dev->mt76.hw->wiphy->fw_version, 1774 sizeof(dev->mt76.hw->wiphy->fw_version), 1775 "%.10s-%.15s", hdr->fw_ver, hdr->build_date); 1776 1777 out: 1778 release_firmware(fw); 1779 1780 return ret; 1781 } 1782 1783 static int 1784 mt7663_load_rom_patch(struct mt7615_dev *dev, const char **n9_firmware) 1785 { 1786 const char *selected_rom, *secondary_rom = MT7663_ROM_PATCH; 1787 const char *primary_rom = MT7663_OFFLOAD_ROM_PATCH; 1788 int ret; 1789 1790 if (!prefer_offload_fw) { 1791 secondary_rom = MT7663_OFFLOAD_ROM_PATCH; 1792 primary_rom = MT7663_ROM_PATCH; 1793 } 1794 selected_rom = primary_rom; 1795 1796 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, primary_rom); 1797 if (ret) { 1798 dev_info(dev->mt76.dev, "%s not found, switching to %s", 1799 primary_rom, secondary_rom); 1800 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, 1801 secondary_rom); 1802 if (ret) { 1803 dev_err(dev->mt76.dev, "failed to load %s", 1804 secondary_rom); 1805 return ret; 1806 } 1807 selected_rom = secondary_rom; 1808 } 1809 1810 if (!strcmp(selected_rom, MT7663_OFFLOAD_ROM_PATCH)) { 1811 *n9_firmware = MT7663_OFFLOAD_FIRMWARE_N9; 1812 dev->fw_ver = MT7615_FIRMWARE_V3; 1813 dev->mcu_ops = &uni_update_ops; 1814 } else { 1815 *n9_firmware = MT7663_FIRMWARE_N9; 1816 dev->fw_ver = MT7615_FIRMWARE_V2; 1817 dev->mcu_ops = &sta_update_ops; 1818 } 1819 1820 return 0; 1821 } 1822 1823 int __mt7663_load_firmware(struct mt7615_dev *dev) 1824 { 1825 const char *n9_firmware; 1826 int ret; 1827 1828 ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY); 1829 if (ret) { 1830 dev_dbg(dev->mt76.dev, "Firmware is already download\n"); 1831 return -EIO; 1832 } 1833 1834 ret = mt7663_load_rom_patch(dev, &n9_firmware); 1835 if (ret) 1836 return ret; 1837 1838 ret = mt7663_load_n9(dev, n9_firmware); 1839 if (ret) 1840 return ret; 1841 1842 if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY, 1843 MT_TOP_MISC2_FW_N9_RDY, 1500)) { 1844 ret = mt76_get_field(dev, MT_CONN_ON_MISC, 1845 MT7663_TOP_MISC2_FW_STATE); 1846 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1847 return -EIO; 1848 } 1849 1850 #ifdef CONFIG_PM 1851 if (mt7615_firmware_offload(dev)) 1852 dev->mt76.hw->wiphy->wowlan = &mt76_connac_wowlan_support; 1853 #endif /* CONFIG_PM */ 1854 1855 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 1856 1857 return 0; 1858 } 1859 EXPORT_SYMBOL_GPL(__mt7663_load_firmware); 1860 1861 static int mt7663_load_firmware(struct mt7615_dev *dev) 1862 { 1863 int ret; 1864 1865 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1866 1867 ret = __mt7663_load_firmware(dev); 1868 if (ret) 1869 return ret; 1870 1871 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1872 1873 return 0; 1874 } 1875 1876 int mt7615_mcu_init(struct mt7615_dev *dev) 1877 { 1878 static const struct mt76_mcu_ops mt7615_mcu_ops = { 1879 .headroom = sizeof(struct mt7615_mcu_txd), 1880 .mcu_skb_send_msg = mt7615_mcu_send_message, 1881 .mcu_parse_response = mt7615_mcu_parse_response, 1882 .mcu_restart = mt7615_mcu_restart, 1883 }; 1884 int ret; 1885 1886 dev->mt76.mcu_ops = &mt7615_mcu_ops, 1887 1888 ret = mt7615_mcu_drv_pmctrl(dev); 1889 if (ret) 1890 return ret; 1891 1892 switch (mt76_chip(&dev->mt76)) { 1893 case 0x7622: 1894 ret = mt7622_load_firmware(dev); 1895 break; 1896 case 0x7663: 1897 ret = mt7663_load_firmware(dev); 1898 break; 1899 default: 1900 ret = mt7615_load_firmware(dev); 1901 break; 1902 } 1903 if (ret) 1904 return ret; 1905 1906 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_FWDL], false); 1907 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 1908 set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1909 mt7615_mcu_fw_log_2_host(dev, 0); 1910 1911 return 0; 1912 } 1913 EXPORT_SYMBOL_GPL(mt7615_mcu_init); 1914 1915 void mt7615_mcu_exit(struct mt7615_dev *dev) 1916 { 1917 __mt76_mcu_restart(&dev->mt76); 1918 mt7615_mcu_set_fw_ctrl(dev); 1919 skb_queue_purge(&dev->mt76.mcu.res_q); 1920 } 1921 EXPORT_SYMBOL_GPL(mt7615_mcu_exit); 1922 1923 int mt7615_mcu_set_eeprom(struct mt7615_dev *dev) 1924 { 1925 struct { 1926 u8 buffer_mode; 1927 u8 content_format; 1928 __le16 len; 1929 } __packed req_hdr = { 1930 .buffer_mode = 1, 1931 }; 1932 u8 *eep = (u8 *)dev->mt76.eeprom.data; 1933 struct sk_buff *skb; 1934 int eep_len, offset; 1935 1936 switch (mt76_chip(&dev->mt76)) { 1937 case 0x7622: 1938 eep_len = MT7622_EE_MAX - MT_EE_NIC_CONF_0; 1939 offset = MT_EE_NIC_CONF_0; 1940 break; 1941 case 0x7663: 1942 eep_len = MT7663_EE_MAX - MT_EE_CHIP_ID; 1943 req_hdr.content_format = 1; 1944 offset = MT_EE_CHIP_ID; 1945 break; 1946 default: 1947 eep_len = MT7615_EE_MAX - MT_EE_NIC_CONF_0; 1948 offset = MT_EE_NIC_CONF_0; 1949 break; 1950 } 1951 1952 req_hdr.len = cpu_to_le16(eep_len); 1953 1954 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + eep_len); 1955 if (!skb) 1956 return -ENOMEM; 1957 1958 skb_put_data(skb, &req_hdr, sizeof(req_hdr)); 1959 skb_put_data(skb, eep + offset, eep_len); 1960 1961 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 1962 MCU_EXT_CMD_EFUSE_BUFFER_MODE, true); 1963 } 1964 1965 int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue, 1966 const struct ieee80211_tx_queue_params *params) 1967 { 1968 #define WMM_AIFS_SET BIT(0) 1969 #define WMM_CW_MIN_SET BIT(1) 1970 #define WMM_CW_MAX_SET BIT(2) 1971 #define WMM_TXOP_SET BIT(3) 1972 #define WMM_PARAM_SET (WMM_AIFS_SET | WMM_CW_MIN_SET | \ 1973 WMM_CW_MAX_SET | WMM_TXOP_SET) 1974 struct req_data { 1975 u8 number; 1976 u8 rsv[3]; 1977 u8 queue; 1978 u8 valid; 1979 u8 aifs; 1980 u8 cw_min; 1981 __le16 cw_max; 1982 __le16 txop; 1983 } __packed req = { 1984 .number = 1, 1985 .queue = queue, 1986 .valid = WMM_PARAM_SET, 1987 .aifs = params->aifs, 1988 .cw_min = 5, 1989 .cw_max = cpu_to_le16(10), 1990 .txop = cpu_to_le16(params->txop), 1991 }; 1992 1993 if (params->cw_min) 1994 req.cw_min = fls(params->cw_min); 1995 if (params->cw_max) 1996 req.cw_max = cpu_to_le16(fls(params->cw_max)); 1997 1998 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_EDCA_UPDATE, &req, 1999 sizeof(req), true); 2000 } 2001 2002 int mt7615_mcu_set_dbdc(struct mt7615_dev *dev) 2003 { 2004 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev); 2005 struct dbdc_entry { 2006 u8 type; 2007 u8 index; 2008 u8 band; 2009 u8 _rsv; 2010 }; 2011 struct { 2012 u8 enable; 2013 u8 num; 2014 u8 _rsv[2]; 2015 struct dbdc_entry entry[64]; 2016 } req = { 2017 .enable = !!ext_phy, 2018 }; 2019 int i; 2020 2021 if (!ext_phy) 2022 goto out; 2023 2024 #define ADD_DBDC_ENTRY(_type, _idx, _band) \ 2025 do { \ 2026 req.entry[req.num].type = _type; \ 2027 req.entry[req.num].index = _idx; \ 2028 req.entry[req.num++].band = _band; \ 2029 } while (0) 2030 2031 for (i = 0; i < 4; i++) { 2032 bool band = !!(ext_phy->omac_mask & BIT_ULL(i)); 2033 2034 ADD_DBDC_ENTRY(DBDC_TYPE_BSS, i, band); 2035 } 2036 2037 for (i = 0; i < 14; i++) { 2038 bool band = !!(ext_phy->omac_mask & BIT_ULL(0x11 + i)); 2039 2040 ADD_DBDC_ENTRY(DBDC_TYPE_MBSS, i, band); 2041 } 2042 2043 ADD_DBDC_ENTRY(DBDC_TYPE_MU, 0, 1); 2044 2045 for (i = 0; i < 3; i++) 2046 ADD_DBDC_ENTRY(DBDC_TYPE_BF, i, 1); 2047 2048 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 0, 0); 2049 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 1, 0); 2050 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 2, 1); 2051 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 3, 1); 2052 2053 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 0, 0); 2054 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 1, 1); 2055 2056 out: 2057 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_DBDC_CTRL, &req, 2058 sizeof(req), true); 2059 } 2060 2061 int mt7615_mcu_del_wtbl_all(struct mt7615_dev *dev) 2062 { 2063 struct wtbl_req_hdr req = { 2064 .operation = WTBL_RESET_ALL, 2065 }; 2066 2067 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_WTBL_UPDATE, &req, 2068 sizeof(req), true); 2069 } 2070 2071 int mt7615_mcu_rdd_cmd(struct mt7615_dev *dev, 2072 enum mt7615_rdd_cmd cmd, u8 index, 2073 u8 rx_sel, u8 val) 2074 { 2075 struct { 2076 u8 ctrl; 2077 u8 rdd_idx; 2078 u8 rdd_rx_sel; 2079 u8 val; 2080 u8 rsv[4]; 2081 } req = { 2082 .ctrl = cmd, 2083 .rdd_idx = index, 2084 .rdd_rx_sel = rx_sel, 2085 .val = val, 2086 }; 2087 2088 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_CTRL, &req, 2089 sizeof(req), true); 2090 } 2091 2092 int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val) 2093 { 2094 struct { 2095 __le16 tag; 2096 __le16 min_lpn; 2097 } req = { 2098 .tag = cpu_to_le16(0x1), 2099 .min_lpn = cpu_to_le16(val), 2100 }; 2101 2102 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, &req, 2103 sizeof(req), true); 2104 } 2105 2106 int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev, 2107 const struct mt7615_dfs_pulse *pulse) 2108 { 2109 struct { 2110 __le16 tag; 2111 __le32 max_width; /* us */ 2112 __le32 max_pwr; /* dbm */ 2113 __le32 min_pwr; /* dbm */ 2114 __le32 min_stgr_pri; /* us */ 2115 __le32 max_stgr_pri; /* us */ 2116 __le32 min_cr_pri; /* us */ 2117 __le32 max_cr_pri; /* us */ 2118 } req = { 2119 .tag = cpu_to_le16(0x3), 2120 #define __req_field(field) .field = cpu_to_le32(pulse->field) 2121 __req_field(max_width), 2122 __req_field(max_pwr), 2123 __req_field(min_pwr), 2124 __req_field(min_stgr_pri), 2125 __req_field(max_stgr_pri), 2126 __req_field(min_cr_pri), 2127 __req_field(max_cr_pri), 2128 #undef __req_field 2129 }; 2130 2131 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, &req, 2132 sizeof(req), true); 2133 } 2134 2135 int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index, 2136 const struct mt7615_dfs_pattern *pattern) 2137 { 2138 struct { 2139 __le16 tag; 2140 __le16 radar_type; 2141 u8 enb; 2142 u8 stgr; 2143 u8 min_crpn; 2144 u8 max_crpn; 2145 u8 min_crpr; 2146 u8 min_pw; 2147 u8 max_pw; 2148 __le32 min_pri; 2149 __le32 max_pri; 2150 u8 min_crbn; 2151 u8 max_crbn; 2152 u8 min_stgpn; 2153 u8 max_stgpn; 2154 u8 min_stgpr; 2155 } req = { 2156 .tag = cpu_to_le16(0x2), 2157 .radar_type = cpu_to_le16(index), 2158 #define __req_field_u8(field) .field = pattern->field 2159 #define __req_field_u32(field) .field = cpu_to_le32(pattern->field) 2160 __req_field_u8(enb), 2161 __req_field_u8(stgr), 2162 __req_field_u8(min_crpn), 2163 __req_field_u8(max_crpn), 2164 __req_field_u8(min_crpr), 2165 __req_field_u8(min_pw), 2166 __req_field_u8(max_pw), 2167 __req_field_u32(min_pri), 2168 __req_field_u32(max_pri), 2169 __req_field_u8(min_crbn), 2170 __req_field_u8(max_crbn), 2171 __req_field_u8(min_stgpn), 2172 __req_field_u8(max_stgpn), 2173 __req_field_u8(min_stgpr), 2174 #undef __req_field_u8 2175 #undef __req_field_u32 2176 }; 2177 2178 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, &req, 2179 sizeof(req), true); 2180 } 2181 2182 int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev) 2183 { 2184 struct { 2185 u8 pulse_num; 2186 u8 rsv[3]; 2187 struct { 2188 __le32 start_time; 2189 __le16 width; 2190 __le16 power; 2191 } pattern[32]; 2192 } req = { 2193 .pulse_num = dev->radar_pattern.n_pulses, 2194 }; 2195 u32 start_time = ktime_to_ms(ktime_get_boottime()); 2196 int i; 2197 2198 if (dev->radar_pattern.n_pulses > ARRAY_SIZE(req.pattern)) 2199 return -EINVAL; 2200 2201 /* TODO: add some noise here */ 2202 for (i = 0; i < dev->radar_pattern.n_pulses; i++) { 2203 u32 ts = start_time + i * dev->radar_pattern.period; 2204 2205 req.pattern[i].width = cpu_to_le16(dev->radar_pattern.width); 2206 req.pattern[i].power = cpu_to_le16(dev->radar_pattern.power); 2207 req.pattern[i].start_time = cpu_to_le32(ts); 2208 } 2209 2210 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_PATTERN, 2211 &req, sizeof(req), false); 2212 } 2213 2214 static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku) 2215 { 2216 struct mt76_phy *mphy = phy->mt76; 2217 struct ieee80211_hw *hw = mphy->hw; 2218 struct mt76_power_limits limits; 2219 s8 *limits_array = (s8 *)&limits; 2220 int n_chains = hweight8(mphy->antenna_mask); 2221 int tx_power; 2222 int i; 2223 static const u8 sku_mapping[] = { 2224 #define SKU_FIELD(_type, _field) \ 2225 [MT_SKU_##_type] = offsetof(struct mt76_power_limits, _field) 2226 SKU_FIELD(CCK_1_2, cck[0]), 2227 SKU_FIELD(CCK_55_11, cck[2]), 2228 SKU_FIELD(OFDM_6_9, ofdm[0]), 2229 SKU_FIELD(OFDM_12_18, ofdm[2]), 2230 SKU_FIELD(OFDM_24_36, ofdm[4]), 2231 SKU_FIELD(OFDM_48, ofdm[6]), 2232 SKU_FIELD(OFDM_54, ofdm[7]), 2233 SKU_FIELD(HT20_0_8, mcs[0][0]), 2234 SKU_FIELD(HT20_32, ofdm[0]), 2235 SKU_FIELD(HT20_1_2_9_10, mcs[0][1]), 2236 SKU_FIELD(HT20_3_4_11_12, mcs[0][3]), 2237 SKU_FIELD(HT20_5_13, mcs[0][5]), 2238 SKU_FIELD(HT20_6_14, mcs[0][6]), 2239 SKU_FIELD(HT20_7_15, mcs[0][7]), 2240 SKU_FIELD(HT40_0_8, mcs[1][0]), 2241 SKU_FIELD(HT40_32, ofdm[0]), 2242 SKU_FIELD(HT40_1_2_9_10, mcs[1][1]), 2243 SKU_FIELD(HT40_3_4_11_12, mcs[1][3]), 2244 SKU_FIELD(HT40_5_13, mcs[1][5]), 2245 SKU_FIELD(HT40_6_14, mcs[1][6]), 2246 SKU_FIELD(HT40_7_15, mcs[1][7]), 2247 SKU_FIELD(VHT20_0, mcs[0][0]), 2248 SKU_FIELD(VHT20_1_2, mcs[0][1]), 2249 SKU_FIELD(VHT20_3_4, mcs[0][3]), 2250 SKU_FIELD(VHT20_5_6, mcs[0][5]), 2251 SKU_FIELD(VHT20_7, mcs[0][7]), 2252 SKU_FIELD(VHT20_8, mcs[0][8]), 2253 SKU_FIELD(VHT20_9, mcs[0][9]), 2254 SKU_FIELD(VHT40_0, mcs[1][0]), 2255 SKU_FIELD(VHT40_1_2, mcs[1][1]), 2256 SKU_FIELD(VHT40_3_4, mcs[1][3]), 2257 SKU_FIELD(VHT40_5_6, mcs[1][5]), 2258 SKU_FIELD(VHT40_7, mcs[1][7]), 2259 SKU_FIELD(VHT40_8, mcs[1][8]), 2260 SKU_FIELD(VHT40_9, mcs[1][9]), 2261 SKU_FIELD(VHT80_0, mcs[2][0]), 2262 SKU_FIELD(VHT80_1_2, mcs[2][1]), 2263 SKU_FIELD(VHT80_3_4, mcs[2][3]), 2264 SKU_FIELD(VHT80_5_6, mcs[2][5]), 2265 SKU_FIELD(VHT80_7, mcs[2][7]), 2266 SKU_FIELD(VHT80_8, mcs[2][8]), 2267 SKU_FIELD(VHT80_9, mcs[2][9]), 2268 SKU_FIELD(VHT160_0, mcs[3][0]), 2269 SKU_FIELD(VHT160_1_2, mcs[3][1]), 2270 SKU_FIELD(VHT160_3_4, mcs[3][3]), 2271 SKU_FIELD(VHT160_5_6, mcs[3][5]), 2272 SKU_FIELD(VHT160_7, mcs[3][7]), 2273 SKU_FIELD(VHT160_8, mcs[3][8]), 2274 SKU_FIELD(VHT160_9, mcs[3][9]), 2275 #undef SKU_FIELD 2276 }; 2277 2278 tx_power = hw->conf.power_level * 2 - 2279 mt76_tx_power_nss_delta(n_chains); 2280 2281 tx_power = mt76_get_rate_power_limits(mphy, mphy->chandef.chan, 2282 &limits, tx_power); 2283 mphy->txpower_cur = tx_power; 2284 2285 if (is_mt7663(mphy->dev)) { 2286 memset(sku, tx_power, MT_SKU_4SS_DELTA + 1); 2287 return; 2288 } 2289 2290 for (i = 0; i < MT_SKU_1SS_DELTA; i++) 2291 sku[i] = limits_array[sku_mapping[i]]; 2292 2293 for (i = 0; i < 4; i++) { 2294 int delta = 0; 2295 2296 if (i < n_chains - 1) 2297 delta = mt76_tx_power_nss_delta(n_chains) - 2298 mt76_tx_power_nss_delta(i + 1); 2299 sku[MT_SKU_1SS_DELTA + i] = delta; 2300 } 2301 } 2302 2303 static u8 mt7615_mcu_chan_bw(struct cfg80211_chan_def *chandef) 2304 { 2305 static const u8 width_to_bw[] = { 2306 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ, 2307 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ, 2308 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ, 2309 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ, 2310 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ, 2311 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ, 2312 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ, 2313 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ, 2314 }; 2315 2316 if (chandef->width >= ARRAY_SIZE(width_to_bw)) 2317 return 0; 2318 2319 return width_to_bw[chandef->width]; 2320 } 2321 2322 int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd) 2323 { 2324 struct mt7615_dev *dev = phy->dev; 2325 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2326 int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2; 2327 struct { 2328 u8 control_chan; 2329 u8 center_chan; 2330 u8 bw; 2331 u8 tx_streams; 2332 u8 rx_streams_mask; 2333 u8 switch_reason; 2334 u8 band_idx; 2335 /* for 80+80 only */ 2336 u8 center_chan2; 2337 __le16 cac_case; 2338 u8 channel_band; 2339 u8 rsv0; 2340 __le32 outband_freq; 2341 u8 txpower_drop; 2342 u8 rsv1[3]; 2343 u8 txpower_sku[53]; 2344 u8 rsv2[3]; 2345 } req = { 2346 .control_chan = chandef->chan->hw_value, 2347 .center_chan = ieee80211_frequency_to_channel(freq1), 2348 .tx_streams = hweight8(phy->mt76->antenna_mask), 2349 .rx_streams_mask = phy->mt76->chainmask, 2350 .center_chan2 = ieee80211_frequency_to_channel(freq2), 2351 }; 2352 2353 if (phy->mt76->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 2354 req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD; 2355 else if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) && 2356 chandef->chan->dfs_state != NL80211_DFS_AVAILABLE) 2357 req.switch_reason = CH_SWITCH_DFS; 2358 else 2359 req.switch_reason = CH_SWITCH_NORMAL; 2360 2361 req.band_idx = phy != &dev->phy; 2362 req.bw = mt7615_mcu_chan_bw(chandef); 2363 2364 if (mt76_testmode_enabled(phy->mt76)) 2365 memset(req.txpower_sku, 0x3f, 49); 2366 else 2367 mt7615_mcu_set_txpower_sku(phy, req.txpower_sku); 2368 2369 return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true); 2370 } 2371 2372 int mt7615_mcu_get_temperature(struct mt7615_dev *dev) 2373 { 2374 struct { 2375 u8 action; 2376 u8 rsv[3]; 2377 } req = {}; 2378 2379 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_GET_TEMP, &req, 2380 sizeof(req), true); 2381 } 2382 2383 int mt7615_mcu_set_test_param(struct mt7615_dev *dev, u8 param, bool test_mode, 2384 u32 val) 2385 { 2386 struct { 2387 u8 test_mode_en; 2388 u8 param_idx; 2389 u8 _rsv[2]; 2390 2391 __le32 value; 2392 2393 u8 pad[8]; 2394 } req = { 2395 .test_mode_en = test_mode, 2396 .param_idx = param, 2397 .value = cpu_to_le32(val), 2398 }; 2399 2400 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_ATE_CTRL, &req, 2401 sizeof(req), false); 2402 } 2403 2404 int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable) 2405 { 2406 struct mt7615_dev *dev = phy->dev; 2407 struct { 2408 u8 format_id; 2409 u8 sku_enable; 2410 u8 band_idx; 2411 u8 rsv; 2412 } req = { 2413 .format_id = 0, 2414 .band_idx = phy != &dev->phy, 2415 .sku_enable = enable, 2416 }; 2417 2418 return mt76_mcu_send_msg(&dev->mt76, 2419 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL, &req, 2420 sizeof(req), true); 2421 } 2422 2423 static int mt7615_find_freq_idx(const u16 *freqs, int n_freqs, u16 cur) 2424 { 2425 int i; 2426 2427 for (i = 0; i < n_freqs; i++) 2428 if (cur == freqs[i]) 2429 return i; 2430 2431 return -1; 2432 } 2433 2434 static int mt7615_dcoc_freq_idx(u16 freq, u8 bw) 2435 { 2436 static const u16 freq_list[] = { 2437 4980, 5805, 5905, 5190, 2438 5230, 5270, 5310, 5350, 2439 5390, 5430, 5470, 5510, 2440 5550, 5590, 5630, 5670, 2441 5710, 5755, 5795, 5835, 2442 5875, 5210, 5290, 5370, 2443 5450, 5530, 5610, 5690, 2444 5775, 5855 2445 }; 2446 static const u16 freq_bw40[] = { 2447 5190, 5230, 5270, 5310, 2448 5350, 5390, 5430, 5470, 2449 5510, 5550, 5590, 5630, 2450 5670, 5710, 5755, 5795, 2451 5835, 5875 2452 }; 2453 int offset_2g = ARRAY_SIZE(freq_list); 2454 int idx; 2455 2456 if (freq < 4000) { 2457 if (freq < 2427) 2458 return offset_2g; 2459 if (freq < 2442) 2460 return offset_2g + 1; 2461 if (freq < 2457) 2462 return offset_2g + 2; 2463 2464 return offset_2g + 3; 2465 } 2466 2467 switch (bw) { 2468 case NL80211_CHAN_WIDTH_80: 2469 case NL80211_CHAN_WIDTH_80P80: 2470 case NL80211_CHAN_WIDTH_160: 2471 break; 2472 default: 2473 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 2474 freq + 10); 2475 if (idx >= 0) { 2476 freq = freq_bw40[idx]; 2477 break; 2478 } 2479 2480 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 2481 freq - 10); 2482 if (idx >= 0) { 2483 freq = freq_bw40[idx]; 2484 break; 2485 } 2486 fallthrough; 2487 case NL80211_CHAN_WIDTH_40: 2488 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 2489 freq); 2490 if (idx >= 0) 2491 break; 2492 2493 return -1; 2494 2495 } 2496 2497 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq); 2498 } 2499 2500 int mt7615_mcu_apply_rx_dcoc(struct mt7615_phy *phy) 2501 { 2502 struct mt7615_dev *dev = phy->dev; 2503 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2504 int freq2 = chandef->center_freq2; 2505 int ret; 2506 struct { 2507 u8 direction; 2508 u8 runtime_calibration; 2509 u8 _rsv[2]; 2510 2511 __le16 center_freq; 2512 u8 bw; 2513 u8 band; 2514 u8 is_freq2; 2515 u8 success; 2516 u8 dbdc_en; 2517 2518 u8 _rsv2; 2519 2520 struct { 2521 __le32 sx0_i_lna[4]; 2522 __le32 sx0_q_lna[4]; 2523 2524 __le32 sx2_i_lna[4]; 2525 __le32 sx2_q_lna[4]; 2526 } dcoc_data[4]; 2527 } req = { 2528 .direction = 1, 2529 2530 .bw = mt7615_mcu_chan_bw(chandef), 2531 .band = chandef->center_freq1 > 4000, 2532 .dbdc_en = !!dev->mt76.phy2, 2533 }; 2534 u16 center_freq = chandef->center_freq1; 2535 int freq_idx; 2536 u8 *eep = dev->mt76.eeprom.data; 2537 2538 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_RX_CAL)) 2539 return 0; 2540 2541 if (chandef->width == NL80211_CHAN_WIDTH_160) { 2542 freq2 = center_freq + 40; 2543 center_freq -= 40; 2544 } 2545 2546 again: 2547 req.runtime_calibration = 1; 2548 freq_idx = mt7615_dcoc_freq_idx(center_freq, chandef->width); 2549 if (freq_idx < 0) 2550 goto out; 2551 2552 memcpy(req.dcoc_data, eep + MT7615_EEPROM_DCOC_OFFSET + 2553 freq_idx * MT7615_EEPROM_DCOC_SIZE, 2554 sizeof(req.dcoc_data)); 2555 req.runtime_calibration = 0; 2556 2557 out: 2558 req.center_freq = cpu_to_le16(center_freq); 2559 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_RXDCOC_CAL, &req, 2560 sizeof(req), true); 2561 2562 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 || 2563 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) { 2564 req.is_freq2 = true; 2565 center_freq = freq2; 2566 goto again; 2567 } 2568 2569 return ret; 2570 } 2571 2572 static int mt7615_dpd_freq_idx(u16 freq, u8 bw) 2573 { 2574 static const u16 freq_list[] = { 2575 4920, 4940, 4960, 4980, 2576 5040, 5060, 5080, 5180, 2577 5200, 5220, 5240, 5260, 2578 5280, 5300, 5320, 5340, 2579 5360, 5380, 5400, 5420, 2580 5440, 5460, 5480, 5500, 2581 5520, 5540, 5560, 5580, 2582 5600, 5620, 5640, 5660, 2583 5680, 5700, 5720, 5745, 2584 5765, 5785, 5805, 5825, 2585 5845, 5865, 5885, 5905 2586 }; 2587 int offset_2g = ARRAY_SIZE(freq_list); 2588 int idx; 2589 2590 if (freq < 4000) { 2591 if (freq < 2432) 2592 return offset_2g; 2593 if (freq < 2457) 2594 return offset_2g + 1; 2595 2596 return offset_2g + 2; 2597 } 2598 2599 if (bw != NL80211_CHAN_WIDTH_20) { 2600 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), 2601 freq + 10); 2602 if (idx >= 0) 2603 return idx; 2604 2605 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), 2606 freq - 10); 2607 if (idx >= 0) 2608 return idx; 2609 } 2610 2611 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq); 2612 } 2613 2614 2615 int mt7615_mcu_apply_tx_dpd(struct mt7615_phy *phy) 2616 { 2617 struct mt7615_dev *dev = phy->dev; 2618 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2619 int freq2 = chandef->center_freq2; 2620 int ret; 2621 struct { 2622 u8 direction; 2623 u8 runtime_calibration; 2624 u8 _rsv[2]; 2625 2626 __le16 center_freq; 2627 u8 bw; 2628 u8 band; 2629 u8 is_freq2; 2630 u8 success; 2631 u8 dbdc_en; 2632 2633 u8 _rsv2; 2634 2635 struct { 2636 struct { 2637 u32 dpd_g0; 2638 u8 data[32]; 2639 } wf0, wf1; 2640 2641 struct { 2642 u32 dpd_g0_prim; 2643 u32 dpd_g0_sec; 2644 u8 data_prim[32]; 2645 u8 data_sec[32]; 2646 } wf2, wf3; 2647 } dpd_data; 2648 } req = { 2649 .direction = 1, 2650 2651 .bw = mt7615_mcu_chan_bw(chandef), 2652 .band = chandef->center_freq1 > 4000, 2653 .dbdc_en = !!dev->mt76.phy2, 2654 }; 2655 u16 center_freq = chandef->center_freq1; 2656 int freq_idx; 2657 u8 *eep = dev->mt76.eeprom.data; 2658 2659 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_TX_DPD)) 2660 return 0; 2661 2662 if (chandef->width == NL80211_CHAN_WIDTH_160) { 2663 freq2 = center_freq + 40; 2664 center_freq -= 40; 2665 } 2666 2667 again: 2668 req.runtime_calibration = 1; 2669 freq_idx = mt7615_dpd_freq_idx(center_freq, chandef->width); 2670 if (freq_idx < 0) 2671 goto out; 2672 2673 memcpy(&req.dpd_data, eep + MT7615_EEPROM_TXDPD_OFFSET + 2674 freq_idx * MT7615_EEPROM_TXDPD_SIZE, 2675 sizeof(req.dpd_data)); 2676 req.runtime_calibration = 0; 2677 2678 out: 2679 req.center_freq = cpu_to_le16(center_freq); 2680 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_TXDPD_CAL, &req, 2681 sizeof(req), true); 2682 2683 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 || 2684 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) { 2685 req.is_freq2 = true; 2686 center_freq = freq2; 2687 goto again; 2688 } 2689 2690 return ret; 2691 } 2692 2693 int mt7615_mcu_set_rx_hdr_trans_blacklist(struct mt7615_dev *dev) 2694 { 2695 struct { 2696 u8 operation; 2697 u8 count; 2698 u8 _rsv[2]; 2699 u8 index; 2700 u8 enable; 2701 __le16 etype; 2702 } req = { 2703 .operation = 1, 2704 .count = 1, 2705 .enable = 1, 2706 .etype = cpu_to_le16(ETH_P_PAE), 2707 }; 2708 2709 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_RX_HDR_TRANS, 2710 &req, sizeof(req), false); 2711 } 2712 2713 int mt7615_mcu_set_bss_pm(struct mt7615_dev *dev, struct ieee80211_vif *vif, 2714 bool enable) 2715 { 2716 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 2717 struct { 2718 u8 bss_idx; 2719 u8 dtim_period; 2720 __le16 aid; 2721 __le16 bcn_interval; 2722 __le16 atim_window; 2723 u8 uapsd; 2724 u8 bmc_delivered_ac; 2725 u8 bmc_triggered_ac; 2726 u8 pad; 2727 } req = { 2728 .bss_idx = mvif->mt76.idx, 2729 .aid = cpu_to_le16(vif->bss_conf.aid), 2730 .dtim_period = vif->bss_conf.dtim_period, 2731 .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int), 2732 }; 2733 struct { 2734 u8 bss_idx; 2735 u8 pad[3]; 2736 } req_hdr = { 2737 .bss_idx = mvif->mt76.idx, 2738 }; 2739 int err; 2740 2741 if (vif->type != NL80211_IFTYPE_STATION) 2742 return 0; 2743 2744 err = mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_BSS_ABORT, &req_hdr, 2745 sizeof(req_hdr), false); 2746 if (err < 0 || !enable) 2747 return err; 2748 2749 return mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_BSS_CONNECTED, &req, 2750 sizeof(req), false); 2751 } 2752 2753 int mt7615_mcu_set_roc(struct mt7615_phy *phy, struct ieee80211_vif *vif, 2754 struct ieee80211_channel *chan, int duration) 2755 { 2756 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 2757 struct mt7615_dev *dev = phy->dev; 2758 struct mt7615_roc_tlv req = { 2759 .bss_idx = mvif->mt76.idx, 2760 .active = !chan, 2761 .max_interval = cpu_to_le32(duration), 2762 .primary_chan = chan ? chan->hw_value : 0, 2763 .band = chan ? chan->band : 0, 2764 .req_type = 2, 2765 }; 2766 2767 phy->roc_grant = false; 2768 2769 return mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_ROC, &req, 2770 sizeof(req), false); 2771 } 2772