1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Felix Fietkau <nbd@nbd.name> 7 * Lorenzo Bianconi <lorenzo@kernel.org> 8 */ 9 10 #include <linux/devcoredump.h> 11 #include <linux/etherdevice.h> 12 #include <linux/timekeeping.h> 13 #include "mt7615.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 #include "mt7615_trace.h" 17 #include "mac.h" 18 #include "mcu.h" 19 20 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 21 22 static const struct mt7615_dfs_radar_spec etsi_radar_specs = { 23 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 24 .radar_pattern = { 25 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 }, 26 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 }, 27 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 }, 28 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 }, 29 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 }, 30 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 }, 31 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 }, 32 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 }, 33 }, 34 }; 35 36 static const struct mt7615_dfs_radar_spec fcc_radar_specs = { 37 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 38 .radar_pattern = { 39 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 }, 40 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 41 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 42 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 43 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 }, 44 }, 45 }; 46 47 static const struct mt7615_dfs_radar_spec jp_radar_specs = { 48 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 49 .radar_pattern = { 50 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 }, 51 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 52 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 53 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 54 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 }, 55 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 }, 56 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 }, 57 }, 58 }; 59 60 static enum mt76_cipher_type 61 mt7615_mac_get_cipher(int cipher) 62 { 63 switch (cipher) { 64 case WLAN_CIPHER_SUITE_WEP40: 65 return MT_CIPHER_WEP40; 66 case WLAN_CIPHER_SUITE_WEP104: 67 return MT_CIPHER_WEP104; 68 case WLAN_CIPHER_SUITE_TKIP: 69 return MT_CIPHER_TKIP; 70 case WLAN_CIPHER_SUITE_AES_CMAC: 71 return MT_CIPHER_BIP_CMAC_128; 72 case WLAN_CIPHER_SUITE_CCMP: 73 return MT_CIPHER_AES_CCMP; 74 case WLAN_CIPHER_SUITE_CCMP_256: 75 return MT_CIPHER_CCMP_256; 76 case WLAN_CIPHER_SUITE_GCMP: 77 return MT_CIPHER_GCMP; 78 case WLAN_CIPHER_SUITE_GCMP_256: 79 return MT_CIPHER_GCMP_256; 80 case WLAN_CIPHER_SUITE_SMS4: 81 return MT_CIPHER_WAPI; 82 default: 83 return MT_CIPHER_NONE; 84 } 85 } 86 87 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev, 88 u8 idx, bool unicast) 89 { 90 struct mt7615_sta *sta; 91 struct mt76_wcid *wcid; 92 93 if (idx >= MT7615_WTBL_SIZE) 94 return NULL; 95 96 wcid = rcu_dereference(dev->mt76.wcid[idx]); 97 if (unicast || !wcid) 98 return wcid; 99 100 if (!wcid->sta) 101 return NULL; 102 103 sta = container_of(wcid, struct mt7615_sta, wcid); 104 if (!sta->vif) 105 return NULL; 106 107 return &sta->vif->sta.wcid; 108 } 109 110 void mt7615_mac_reset_counters(struct mt7615_phy *phy) 111 { 112 struct mt7615_dev *dev = phy->dev; 113 int i; 114 115 for (i = 0; i < 4; i++) { 116 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 117 mt76_rr(dev, MT_TX_AGG_CNT(1, i)); 118 } 119 120 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 121 phy->mt76->survey_time = ktime_get_boottime(); 122 123 /* reset airtime counters */ 124 mt76_rr(dev, MT_MIB_SDR9(0)); 125 mt76_rr(dev, MT_MIB_SDR9(1)); 126 127 mt76_rr(dev, MT_MIB_SDR36(0)); 128 mt76_rr(dev, MT_MIB_SDR36(1)); 129 130 mt76_rr(dev, MT_MIB_SDR37(0)); 131 mt76_rr(dev, MT_MIB_SDR37(1)); 132 133 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 134 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 135 } 136 137 void mt7615_mac_set_timing(struct mt7615_phy *phy) 138 { 139 s16 coverage_class = phy->coverage_class; 140 struct mt7615_dev *dev = phy->dev; 141 bool ext_phy = phy != &dev->phy; 142 u32 val, reg_offset; 143 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 144 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 145 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 146 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 147 int sifs, offset; 148 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 149 150 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 151 return; 152 153 if (is_5ghz) 154 sifs = 16; 155 else 156 sifs = 10; 157 158 if (ext_phy) { 159 coverage_class = max_t(s16, dev->phy.coverage_class, 160 coverage_class); 161 mt76_set(dev, MT_ARB_SCR, 162 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 163 } else { 164 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev); 165 166 if (phy_ext) 167 coverage_class = max_t(s16, phy_ext->coverage_class, 168 coverage_class); 169 mt76_set(dev, MT_ARB_SCR, 170 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 171 } 172 udelay(1); 173 174 offset = 3 * coverage_class; 175 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 176 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 177 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset); 178 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset); 179 180 mt76_wr(dev, MT_TMAC_ICR(ext_phy), 181 FIELD_PREP(MT_IFS_EIFS, 360) | 182 FIELD_PREP(MT_IFS_RIFS, 2) | 183 FIELD_PREP(MT_IFS_SIFS, sifs) | 184 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 185 186 if (phy->slottime < 20 || is_5ghz) 187 val = MT7615_CFEND_RATE_DEFAULT; 188 else 189 val = MT7615_CFEND_RATE_11B; 190 191 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 192 if (ext_phy) 193 mt76_clear(dev, MT_ARB_SCR, 194 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 195 else 196 mt76_clear(dev, MT_ARB_SCR, 197 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 198 199 } 200 201 static void 202 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy, 203 struct mt76_rx_status *status, u8 chfreq) 204 { 205 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 206 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 207 !test_bit(MT76_STATE_ROC, &mphy->state)) { 208 status->freq = mphy->chandef.chan->center_freq; 209 status->band = mphy->chandef.chan->band; 210 return; 211 } 212 213 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 214 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 215 } 216 217 static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv) 218 { 219 #ifdef CONFIG_NL80211_TESTMODE 220 u32 rxv1 = le32_to_cpu(rxv[0]); 221 u32 rxv3 = le32_to_cpu(rxv[2]); 222 u32 rxv4 = le32_to_cpu(rxv[3]); 223 u32 rxv5 = le32_to_cpu(rxv[4]); 224 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1); 225 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1); 226 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5); 227 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000; 228 229 if (!mode) { 230 /* CCK */ 231 foe &= ~BIT(11); 232 foe *= 1000; 233 foe >>= 11; 234 } else { 235 if (foe > 2048) 236 foe -= 4096; 237 238 foe = (foe * foe_const) >> 15; 239 } 240 241 phy->test.last_freq_offset = foe; 242 phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4); 243 phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4); 244 phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4); 245 phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4); 246 phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3); 247 phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3); 248 #endif 249 } 250 251 /* The HW does not translate the mac header to 802.3 for mesh point */ 252 static int mt7615_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 253 { 254 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 255 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 256 struct mt7615_sta *msta = (struct mt7615_sta *)status->wcid; 257 __le32 *rxd = (__le32 *)skb->data; 258 struct ieee80211_sta *sta; 259 struct ieee80211_vif *vif; 260 struct ieee80211_hdr hdr; 261 u16 frame_control; 262 263 if (le32_get_bits(rxd[1], MT_RXD1_NORMAL_ADDR_TYPE) != 264 MT_RXD1_NORMAL_U2M) 265 return -EINVAL; 266 267 if (!(le32_to_cpu(rxd[0]) & MT_RXD0_NORMAL_GROUP_4)) 268 return -EINVAL; 269 270 if (!msta || !msta->vif) 271 return -EINVAL; 272 273 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 274 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 275 276 /* store the info from RXD and ethhdr to avoid being overridden */ 277 frame_control = le32_get_bits(rxd[4], MT_RXD4_FRAME_CONTROL); 278 hdr.frame_control = cpu_to_le16(frame_control); 279 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_SEQ_CTRL)); 280 hdr.duration_id = 0; 281 282 ether_addr_copy(hdr.addr1, vif->addr); 283 ether_addr_copy(hdr.addr2, sta->addr); 284 switch (frame_control & (IEEE80211_FCTL_TODS | 285 IEEE80211_FCTL_FROMDS)) { 286 case 0: 287 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 288 break; 289 case IEEE80211_FCTL_FROMDS: 290 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 291 break; 292 case IEEE80211_FCTL_TODS: 293 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 294 break; 295 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 296 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 297 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 298 break; 299 default: 300 break; 301 } 302 303 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 304 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 305 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 306 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 307 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 308 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 309 else 310 skb_pull(skb, 2); 311 312 if (ieee80211_has_order(hdr.frame_control)) 313 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[7], 314 IEEE80211_HT_CTL_LEN); 315 316 if (ieee80211_is_data_qos(hdr.frame_control)) { 317 __le16 qos_ctrl; 318 319 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_QOS_CTL)); 320 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 321 IEEE80211_QOS_CTL_LEN); 322 } 323 324 if (ieee80211_has_a4(hdr.frame_control)) 325 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 326 else 327 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 328 329 status->flag &= ~(RX_FLAG_RADIOTAP_HE | RX_FLAG_RADIOTAP_HE_MU); 330 return 0; 331 } 332 333 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb) 334 { 335 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 336 struct mt76_phy *mphy = &dev->mt76.phy; 337 struct mt7615_phy *phy = &dev->phy; 338 struct ieee80211_supported_band *sband; 339 struct ieee80211_hdr *hdr; 340 struct mt7615_phy *phy2; 341 __le32 *rxd = (__le32 *)skb->data; 342 u32 rxd0 = le32_to_cpu(rxd[0]); 343 u32 rxd1 = le32_to_cpu(rxd[1]); 344 u32 rxd2 = le32_to_cpu(rxd[2]); 345 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 346 u32 csum_status = *(u32 *)skb->cb; 347 bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false; 348 u16 hdr_gap; 349 int phy_idx; 350 int i, idx; 351 u8 chfreq, amsdu_info, qos_ctl = 0; 352 u16 seq_ctrl = 0; 353 __le16 fc = 0; 354 355 memset(status, 0, sizeof(*status)); 356 357 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 358 359 phy2 = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL; 360 if (!phy2) 361 phy_idx = 0; 362 else if (phy2->chfreq == phy->chfreq) 363 phy_idx = -1; 364 else if (phy->chfreq == chfreq) 365 phy_idx = 0; 366 else if (phy2->chfreq == chfreq) 367 phy_idx = 1; 368 else 369 phy_idx = -1; 370 371 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 372 return -EINVAL; 373 374 hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS; 375 if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_CM)) 376 return -EINVAL; 377 378 /* ICV error or CCMP/BIP/WPI MIC error */ 379 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR) 380 status->flag |= RX_FLAG_ONLY_MONITOR; 381 382 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M; 383 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 384 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast); 385 386 if (status->wcid) { 387 struct mt7615_sta *msta; 388 389 msta = container_of(status->wcid, struct mt7615_sta, wcid); 390 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 391 } 392 393 if (mt76_is_mmio(&dev->mt76) && (rxd0 & csum_mask) == csum_mask && 394 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 395 skb->ip_summed = CHECKSUM_UNNECESSARY; 396 397 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 398 status->flag |= RX_FLAG_FAILED_FCS_CRC; 399 400 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 401 status->flag |= RX_FLAG_MMIC_ERROR; 402 403 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 404 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 405 status->flag |= RX_FLAG_DECRYPTED; 406 status->flag |= RX_FLAG_IV_STRIPPED; 407 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 408 } 409 410 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 411 412 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 413 return -EINVAL; 414 415 rxd += 4; 416 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 417 u32 v0 = le32_to_cpu(rxd[0]); 418 u32 v2 = le32_to_cpu(rxd[2]); 419 420 fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0)); 421 qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2); 422 seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2); 423 424 rxd += 4; 425 if ((u8 *)rxd - skb->data >= skb->len) 426 return -EINVAL; 427 } 428 429 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 430 u8 *data = (u8 *)rxd; 431 432 if (status->flag & RX_FLAG_DECRYPTED) { 433 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 434 case MT_CIPHER_AES_CCMP: 435 case MT_CIPHER_CCMP_CCX: 436 case MT_CIPHER_CCMP_256: 437 insert_ccmp_hdr = 438 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 439 fallthrough; 440 case MT_CIPHER_TKIP: 441 case MT_CIPHER_TKIP_NO_MIC: 442 case MT_CIPHER_GCMP: 443 case MT_CIPHER_GCMP_256: 444 status->iv[0] = data[5]; 445 status->iv[1] = data[4]; 446 status->iv[2] = data[3]; 447 status->iv[3] = data[2]; 448 status->iv[4] = data[1]; 449 status->iv[5] = data[0]; 450 break; 451 default: 452 break; 453 } 454 } 455 rxd += 4; 456 if ((u8 *)rxd - skb->data >= skb->len) 457 return -EINVAL; 458 } 459 460 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 461 status->timestamp = le32_to_cpu(rxd[0]); 462 status->flag |= RX_FLAG_MACTIME_START; 463 464 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 465 MT_RXD2_NORMAL_NON_AMPDU))) { 466 status->flag |= RX_FLAG_AMPDU_DETAILS; 467 468 /* all subframes of an A-MPDU have the same timestamp */ 469 if (phy->rx_ampdu_ts != status->timestamp) { 470 if (!++phy->ampdu_ref) 471 phy->ampdu_ref++; 472 } 473 phy->rx_ampdu_ts = status->timestamp; 474 475 status->ampdu_ref = phy->ampdu_ref; 476 } 477 478 rxd += 2; 479 if ((u8 *)rxd - skb->data >= skb->len) 480 return -EINVAL; 481 } 482 483 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 484 u32 rxdg5 = le32_to_cpu(rxd[5]); 485 486 /* 487 * If both PHYs are on the same channel and we don't have a WCID, 488 * we need to figure out which PHY this packet was received on. 489 * On the primary PHY, the noise value for the chains belonging to the 490 * second PHY will be set to the noise value of the last packet from 491 * that PHY. 492 */ 493 if (phy_idx < 0) { 494 int first_chain = ffs(phy2->mt76->chainmask) - 1; 495 496 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0; 497 } 498 } 499 500 if (phy_idx == 1 && phy2) { 501 mphy = dev->mt76.phys[MT_BAND1]; 502 phy = phy2; 503 status->phy_idx = phy_idx; 504 } 505 506 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq) 507 return -EINVAL; 508 509 mt7615_get_status_freq_info(dev, mphy, status, chfreq); 510 if (status->band == NL80211_BAND_5GHZ) 511 sband = &mphy->sband_5g.sband; 512 else 513 sband = &mphy->sband_2g.sband; 514 515 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 516 return -EINVAL; 517 518 if (!sband->channels) 519 return -EINVAL; 520 521 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 522 u32 rxdg0 = le32_to_cpu(rxd[0]); 523 u32 rxdg1 = le32_to_cpu(rxd[1]); 524 u32 rxdg3 = le32_to_cpu(rxd[3]); 525 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 526 bool cck = false; 527 528 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 529 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 530 case MT_PHY_TYPE_CCK: 531 cck = true; 532 fallthrough; 533 case MT_PHY_TYPE_OFDM: 534 i = mt76_get_rate(&dev->mt76, sband, i, cck); 535 break; 536 case MT_PHY_TYPE_HT_GF: 537 case MT_PHY_TYPE_HT: 538 status->encoding = RX_ENC_HT; 539 if (i > 31) 540 return -EINVAL; 541 break; 542 case MT_PHY_TYPE_VHT: 543 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1; 544 status->encoding = RX_ENC_VHT; 545 break; 546 default: 547 return -EINVAL; 548 } 549 status->rate_idx = i; 550 551 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) { 552 case MT_PHY_BW_20: 553 break; 554 case MT_PHY_BW_40: 555 status->bw = RATE_INFO_BW_40; 556 break; 557 case MT_PHY_BW_80: 558 status->bw = RATE_INFO_BW_80; 559 break; 560 case MT_PHY_BW_160: 561 status->bw = RATE_INFO_BW_160; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 568 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 569 if (rxdg0 & MT_RXV1_HT_AD_CODE) 570 status->enc_flags |= RX_ENC_FLAG_LDPC; 571 572 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 573 574 status->chains = mphy->antenna_mask; 575 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3); 576 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3); 577 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3); 578 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3); 579 580 mt7615_mac_fill_tm_rx(mphy->priv, rxd); 581 582 rxd += 6; 583 if ((u8 *)rxd - skb->data >= skb->len) 584 return -EINVAL; 585 } 586 587 amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1); 588 status->amsdu = !!amsdu_info; 589 if (status->amsdu) { 590 status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME; 591 status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME; 592 } 593 594 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 595 if (hdr_trans && ieee80211_has_morefrags(fc)) { 596 if (mt7615_reverse_frag0_hdr_trans(skb, hdr_gap)) 597 return -EINVAL; 598 hdr_trans = false; 599 } else { 600 int pad_start = 0; 601 602 skb_pull(skb, hdr_gap); 603 if (!hdr_trans && status->amsdu) { 604 pad_start = ieee80211_get_hdrlen_from_skb(skb); 605 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 606 /* 607 * When header translation failure is indicated, 608 * the hardware will insert an extra 2-byte field 609 * containing the data length after the protocol 610 * type field. This happens either when the LLC-SNAP 611 * pattern did not match, or if a VLAN header was 612 * detected. 613 */ 614 pad_start = 12; 615 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 616 pad_start += 4; 617 else 618 pad_start = 0; 619 } 620 621 if (pad_start) { 622 memmove(skb->data + 2, skb->data, pad_start); 623 skb_pull(skb, 2); 624 } 625 } 626 627 if (insert_ccmp_hdr && !hdr_trans) { 628 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 629 630 mt76_insert_ccmp_hdr(skb, key_id); 631 } 632 633 if (!hdr_trans) { 634 hdr = (struct ieee80211_hdr *)skb->data; 635 fc = hdr->frame_control; 636 if (ieee80211_is_data_qos(fc)) { 637 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 638 qos_ctl = *ieee80211_get_qos_ctl(hdr); 639 } 640 } else { 641 status->flag |= RX_FLAG_8023; 642 } 643 644 if (!status->wcid || !ieee80211_is_data_qos(fc)) 645 return 0; 646 647 status->aggr = unicast && 648 !ieee80211_is_qos_nullfunc(fc); 649 status->qos_ctl = qos_ctl; 650 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 651 652 return 0; 653 } 654 655 static u16 656 mt7615_mac_tx_rate_val(struct mt7615_dev *dev, 657 struct mt76_phy *mphy, 658 const struct ieee80211_tx_rate *rate, 659 bool stbc, u8 *bw) 660 { 661 u8 phy, nss, rate_idx; 662 u16 rateval = 0; 663 664 *bw = 0; 665 666 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 667 rate_idx = ieee80211_rate_get_vht_mcs(rate); 668 nss = ieee80211_rate_get_vht_nss(rate); 669 phy = MT_PHY_TYPE_VHT; 670 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 671 *bw = 1; 672 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 673 *bw = 2; 674 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 675 *bw = 3; 676 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 677 rate_idx = rate->idx; 678 nss = 1 + (rate->idx >> 3); 679 phy = MT_PHY_TYPE_HT; 680 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 681 phy = MT_PHY_TYPE_HT_GF; 682 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 683 *bw = 1; 684 } else { 685 const struct ieee80211_rate *r; 686 int band = mphy->chandef.chan->band; 687 u16 val; 688 689 nss = 1; 690 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx]; 691 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 692 val = r->hw_value_short; 693 else 694 val = r->hw_value; 695 696 phy = val >> 8; 697 rate_idx = val & 0xff; 698 } 699 700 if (stbc && nss == 1) { 701 nss++; 702 rateval |= MT_TX_RATE_STBC; 703 } 704 705 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 706 FIELD_PREP(MT_TX_RATE_MODE, phy) | 707 FIELD_PREP(MT_TX_RATE_NSS, nss - 1)); 708 709 return rateval; 710 } 711 712 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi, 713 struct sk_buff *skb, struct mt76_wcid *wcid, 714 struct ieee80211_sta *sta, int pid, 715 struct ieee80211_key_conf *key, 716 enum mt76_txq_id qid, bool beacon) 717 { 718 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 719 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 720 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 721 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 722 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 723 bool multicast = is_multicast_ether_addr(hdr->addr1); 724 struct ieee80211_vif *vif = info->control.vif; 725 bool is_mmio = mt76_is_mmio(&dev->mt76); 726 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE; 727 struct mt76_phy *mphy = &dev->mphy; 728 __le16 fc = hdr->frame_control; 729 int tx_count = 8; 730 u16 seqno = 0; 731 732 if (vif) { 733 struct mt76_vif_link *mvif = (struct mt76_vif_link *)vif->drv_priv; 734 735 omac_idx = mvif->omac_idx; 736 wmm_idx = mvif->wmm_idx; 737 } 738 739 if (sta) { 740 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 741 742 tx_count = msta->rate_count; 743 } 744 745 if (phy_idx && dev->mt76.phys[MT_BAND1]) 746 mphy = dev->mt76.phys[MT_BAND1]; 747 748 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 749 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 750 751 if (beacon) { 752 p_fmt = MT_TX_TYPE_FW; 753 q_idx = phy_idx ? MT_LMAC_BCN1 : MT_LMAC_BCN0; 754 } else if (qid >= MT_TXQ_PSD) { 755 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 756 q_idx = phy_idx ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0; 757 } else { 758 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 759 q_idx = wmm_idx * MT7615_MAX_WMM_SETS + 760 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb)); 761 } 762 763 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | 764 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) | 765 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 766 txwi[0] = cpu_to_le32(val); 767 768 val = MT_TXD1_LONG_FORMAT | 769 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 770 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 771 FIELD_PREP(MT_TXD1_HDR_INFO, 772 ieee80211_get_hdrlen_from_skb(skb) / 2) | 773 FIELD_PREP(MT_TXD1_TID, 774 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 775 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) | 776 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 777 txwi[1] = cpu_to_le32(val); 778 779 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 780 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 781 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 782 if (key) { 783 if (multicast && ieee80211_is_robust_mgmt_frame(skb) && 784 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 785 val |= MT_TXD2_BIP; 786 txwi[3] = 0; 787 } else { 788 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME); 789 } 790 } else { 791 txwi[3] = 0; 792 } 793 txwi[2] = cpu_to_le32(val); 794 795 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 796 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 797 798 txwi[4] = 0; 799 txwi[6] = 0; 800 801 if (rate->idx >= 0 && rate->count && 802 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 803 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 804 u8 bw; 805 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc, 806 &bw); 807 808 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 809 810 val = MT_TXD6_FIXED_BW | 811 FIELD_PREP(MT_TXD6_BW, bw) | 812 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 813 txwi[6] |= cpu_to_le32(val); 814 815 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 816 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 817 818 if (info->flags & IEEE80211_TX_CTL_LDPC) 819 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC); 820 821 if (!(rate->flags & (IEEE80211_TX_RC_MCS | 822 IEEE80211_TX_RC_VHT_MCS))) 823 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 824 825 tx_count = rate->count; 826 } 827 828 if (!ieee80211_is_beacon(fc)) { 829 struct ieee80211_hw *hw = mt76_hw(dev); 830 831 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid); 832 if (!ieee80211_hw_check(hw, SUPPORTS_PS)) 833 val |= MT_TXD5_SW_POWER_MGMT; 834 txwi[5] = cpu_to_le32(val); 835 } else { 836 txwi[5] = 0; 837 /* use maximum tx count for beacons */ 838 tx_count = 0x1f; 839 } 840 841 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 842 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 843 seqno = le16_to_cpu(hdr->seq_ctrl); 844 845 if (ieee80211_is_back_req(hdr->frame_control)) { 846 struct ieee80211_bar *bar; 847 848 bar = (struct ieee80211_bar *)skb->data; 849 seqno = le16_to_cpu(bar->start_seq_num); 850 } 851 852 val |= MT_TXD3_SN_VALID | 853 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 854 } 855 856 txwi[3] |= cpu_to_le32(val); 857 858 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 859 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK); 860 861 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 862 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) | 863 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18); 864 txwi[7] = cpu_to_le32(val); 865 if (!is_mmio) { 866 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) | 867 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype); 868 txwi[8] = cpu_to_le32(val); 869 } 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi); 874 875 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask) 876 { 877 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 878 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 879 880 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 881 0, 5000); 882 } 883 884 void mt7615_mac_sta_poll(struct mt7615_dev *dev) 885 { 886 static const u8 ac_to_tid[4] = { 887 [IEEE80211_AC_BE] = 0, 888 [IEEE80211_AC_BK] = 1, 889 [IEEE80211_AC_VI] = 4, 890 [IEEE80211_AC_VO] = 6 891 }; 892 static const u8 hw_queue_map[] = { 893 [IEEE80211_AC_BK] = 0, 894 [IEEE80211_AC_BE] = 1, 895 [IEEE80211_AC_VI] = 2, 896 [IEEE80211_AC_VO] = 3, 897 }; 898 struct ieee80211_sta *sta; 899 struct mt7615_sta *msta; 900 u32 addr, tx_time[4], rx_time[4]; 901 struct list_head sta_poll_list; 902 int i; 903 904 INIT_LIST_HEAD(&sta_poll_list); 905 spin_lock_bh(&dev->mt76.sta_poll_lock); 906 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 907 spin_unlock_bh(&dev->mt76.sta_poll_lock); 908 909 while (!list_empty(&sta_poll_list)) { 910 bool clear = false; 911 912 msta = list_first_entry(&sta_poll_list, struct mt7615_sta, 913 wcid.poll_list); 914 915 spin_lock_bh(&dev->mt76.sta_poll_lock); 916 list_del_init(&msta->wcid.poll_list); 917 spin_unlock_bh(&dev->mt76.sta_poll_lock); 918 919 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4; 920 921 for (i = 0; i < 4; i++, addr += 8) { 922 u32 tx_last = msta->airtime_ac[i]; 923 u32 rx_last = msta->airtime_ac[i + 4]; 924 925 msta->airtime_ac[i] = mt76_rr(dev, addr); 926 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 927 tx_time[i] = msta->airtime_ac[i] - tx_last; 928 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 929 930 if ((tx_last | rx_last) & BIT(30)) 931 clear = true; 932 } 933 934 if (clear) { 935 mt7615_mac_wtbl_update(dev, msta->wcid.idx, 936 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 937 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 938 } 939 940 if (!msta->wcid.sta) 941 continue; 942 943 sta = container_of((void *)msta, struct ieee80211_sta, 944 drv_priv); 945 for (i = 0; i < 4; i++) { 946 u32 tx_cur = tx_time[i]; 947 u32 rx_cur = rx_time[hw_queue_map[i]]; 948 u8 tid = ac_to_tid[i]; 949 950 if (!tx_cur && !rx_cur) 951 continue; 952 953 ieee80211_sta_register_airtime(sta, tid, tx_cur, 954 rx_cur); 955 } 956 } 957 } 958 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll); 959 960 static void 961 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta, 962 struct ieee80211_tx_rate *probe_rate, 963 struct ieee80211_tx_rate *rates, 964 struct mt7615_rate_desc *rd) 965 { 966 struct mt7615_dev *dev = phy->dev; 967 struct mt76_phy *mphy = phy->mt76; 968 struct ieee80211_tx_rate *ref; 969 bool rateset, stbc = false; 970 int n_rates = sta->n_rates; 971 u8 bw, bw_prev; 972 int i, j; 973 974 for (i = n_rates; i < 4; i++) 975 rates[i] = rates[n_rates - 1]; 976 977 rateset = !(sta->rate_set_tsf & BIT(0)); 978 memcpy(sta->rateset[rateset].rates, rates, 979 sizeof(sta->rateset[rateset].rates)); 980 if (probe_rate) { 981 sta->rateset[rateset].probe_rate = *probe_rate; 982 ref = &sta->rateset[rateset].probe_rate; 983 } else { 984 sta->rateset[rateset].probe_rate.idx = -1; 985 ref = &sta->rateset[rateset].rates[0]; 986 } 987 988 rates = sta->rateset[rateset].rates; 989 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 990 /* 991 * We don't support switching between short and long GI 992 * within the rate set. For accurate tx status reporting, we 993 * need to make sure that flags match. 994 * For improved performance, avoid duplicate entries by 995 * decrementing the MCS index if necessary 996 */ 997 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 998 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 999 1000 for (j = 0; j < i; j++) { 1001 if (rates[i].idx != rates[j].idx) 1002 continue; 1003 if ((rates[i].flags ^ rates[j].flags) & 1004 (IEEE80211_TX_RC_40_MHZ_WIDTH | 1005 IEEE80211_TX_RC_80_MHZ_WIDTH | 1006 IEEE80211_TX_RC_160_MHZ_WIDTH)) 1007 continue; 1008 1009 if (!rates[i].idx) 1010 continue; 1011 1012 rates[i].idx--; 1013 } 1014 } 1015 1016 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw); 1017 bw_prev = bw; 1018 1019 if (probe_rate) { 1020 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate, 1021 stbc, &bw); 1022 if (bw) 1023 rd->bw_idx = 1; 1024 else 1025 bw_prev = 0; 1026 } else { 1027 rd->probe_val = rd->val[0]; 1028 } 1029 1030 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw); 1031 if (bw_prev) { 1032 rd->bw_idx = 3; 1033 bw_prev = bw; 1034 } 1035 1036 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw); 1037 if (bw_prev) { 1038 rd->bw_idx = 5; 1039 bw_prev = bw; 1040 } 1041 1042 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw); 1043 if (bw_prev) 1044 rd->bw_idx = 7; 1045 1046 rd->rateset = rateset; 1047 rd->bw = bw; 1048 } 1049 1050 static int 1051 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta, 1052 struct ieee80211_tx_rate *probe_rate, 1053 struct ieee80211_tx_rate *rates) 1054 { 1055 struct mt7615_dev *dev = phy->dev; 1056 struct mt7615_wtbl_rate_desc *wrd; 1057 1058 if (work_pending(&dev->rate_work)) 1059 return -EBUSY; 1060 1061 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC); 1062 if (!wrd) 1063 return -ENOMEM; 1064 1065 wrd->sta = sta; 1066 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, 1067 &wrd->rate); 1068 list_add_tail(&wrd->node, &dev->wrd_head); 1069 queue_work(dev->mt76.wq, &dev->rate_work); 1070 1071 return 0; 1072 } 1073 1074 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid) 1075 { 1076 u32 addr, val, val2; 1077 u8 offset; 1078 1079 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4; 1080 1081 offset = tid * 12; 1082 addr += 4 * (offset / 32); 1083 offset %= 32; 1084 1085 val = mt76_rr(dev, addr); 1086 val >>= offset; 1087 1088 if (offset > 20) { 1089 addr += 4; 1090 val2 = mt76_rr(dev, addr); 1091 val |= val2 << (32 - offset); 1092 } 1093 1094 return val & GENMASK(11, 0); 1095 } 1096 1097 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta, 1098 struct ieee80211_tx_rate *probe_rate, 1099 struct ieee80211_tx_rate *rates) 1100 { 1101 int wcid = sta->wcid.idx, n_rates = sta->n_rates; 1102 struct mt7615_dev *dev = phy->dev; 1103 struct mt7615_rate_desc rd; 1104 u32 w5, w27, addr; 1105 u16 idx = sta->vif->mt76.omac_idx; 1106 1107 if (!mt76_is_mmio(&dev->mt76)) { 1108 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates); 1109 return; 1110 } 1111 1112 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1113 return; 1114 1115 memset(&rd, 0, sizeof(struct mt7615_rate_desc)); 1116 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd); 1117 1118 addr = mt7615_mac_wtbl_addr(dev, wcid); 1119 w27 = mt76_rr(dev, addr + 27 * 4); 1120 w27 &= ~MT_WTBL_W27_CC_BW_SEL; 1121 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw); 1122 1123 w5 = mt76_rr(dev, addr + 5 * 4); 1124 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE | 1125 MT_WTBL_W5_MPDU_OK_COUNT | 1126 MT_WTBL_W5_MPDU_FAIL_COUNT | 1127 MT_WTBL_W5_RATE_IDX); 1128 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) | 1129 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, 1130 rd.bw_idx ? rd.bw_idx - 1 : 7); 1131 1132 mt76_wr(dev, MT_WTBL_RIUCR0, w5); 1133 1134 mt76_wr(dev, MT_WTBL_RIUCR1, 1135 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) | 1136 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) | 1137 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1])); 1138 1139 mt76_wr(dev, MT_WTBL_RIUCR2, 1140 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) | 1141 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) | 1142 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) | 1143 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2])); 1144 1145 mt76_wr(dev, MT_WTBL_RIUCR3, 1146 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) | 1147 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) | 1148 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3])); 1149 1150 mt76_wr(dev, MT_WTBL_UPDATE, 1151 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 1152 MT_WTBL_UPDATE_RATE_UPDATE | 1153 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 1154 1155 mt76_wr(dev, addr + 27 * 4, w27); 1156 1157 idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx; 1158 addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx); 1159 1160 mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */ 1161 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0); 1162 sta->rate_set_tsf |= rd.rateset; 1163 1164 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 1165 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 1166 1167 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates; 1168 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 1169 sta->rate_probe = !!probe_rate; 1170 } 1171 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates); 1172 1173 void mt7615_mac_enable_rtscts(struct mt7615_dev *dev, 1174 struct ieee80211_vif *vif, bool enable) 1175 { 1176 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1177 u32 addr; 1178 1179 addr = mt7615_mac_wtbl_addr(dev, mvif->sta.wcid.idx) + 3 * 4; 1180 1181 if (enable) 1182 mt76_set(dev, addr, MT_WTBL_W3_RTS); 1183 else 1184 mt76_clear(dev, addr, MT_WTBL_W3_RTS); 1185 } 1186 EXPORT_SYMBOL_GPL(mt7615_mac_enable_rtscts); 1187 1188 static int 1189 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1190 struct ieee80211_key_conf *key, 1191 enum mt76_cipher_type cipher, u16 cipher_mask) 1192 { 1193 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4; 1194 u8 data[32] = {}; 1195 1196 if (key->keylen > sizeof(data)) 1197 return -EINVAL; 1198 1199 mt76_rr_copy(dev, addr, data, sizeof(data)); 1200 if (cipher == MT_CIPHER_TKIP) { 1201 /* Rx/Tx MIC keys are swapped */ 1202 memcpy(data, key->key, 16); 1203 memcpy(data + 16, key->key + 24, 8); 1204 memcpy(data + 24, key->key + 16, 8); 1205 } else { 1206 if (cipher_mask == BIT(cipher)) 1207 memcpy(data, key->key, key->keylen); 1208 else if (cipher != MT_CIPHER_BIP_CMAC_128) 1209 memcpy(data, key->key, 16); 1210 if (cipher == MT_CIPHER_BIP_CMAC_128) 1211 memcpy(data + 16, key->key, 16); 1212 } 1213 1214 mt76_wr_copy(dev, addr, data, sizeof(data)); 1215 1216 return 0; 1217 } 1218 1219 static int 1220 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1221 enum mt76_cipher_type cipher, u16 cipher_mask, 1222 int keyidx) 1223 { 1224 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1; 1225 1226 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1227 return -ETIMEDOUT; 1228 1229 w0 = mt76_rr(dev, addr); 1230 w1 = mt76_rr(dev, addr + 4); 1231 1232 if (cipher_mask) 1233 w0 |= MT_WTBL_W0_RX_KEY_VALID; 1234 else 1235 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX); 1236 if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128)) 1237 w0 |= MT_WTBL_W0_RX_IK_VALID; 1238 else 1239 w0 &= ~MT_WTBL_W0_RX_IK_VALID; 1240 1241 if (cipher != MT_CIPHER_BIP_CMAC_128 || cipher_mask == BIT(cipher)) { 1242 w0 &= ~MT_WTBL_W0_KEY_IDX; 1243 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx); 1244 } 1245 1246 mt76_wr(dev, MT_WTBL_RICR0, w0); 1247 mt76_wr(dev, MT_WTBL_RICR1, w1); 1248 1249 if (!mt7615_mac_wtbl_update(dev, wcid->idx, 1250 MT_WTBL_UPDATE_RXINFO_UPDATE)) 1251 return -ETIMEDOUT; 1252 1253 return 0; 1254 } 1255 1256 static void 1257 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1258 enum mt76_cipher_type cipher, u16 cipher_mask) 1259 { 1260 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx); 1261 1262 if (cipher == MT_CIPHER_BIP_CMAC_128 && 1263 cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128)) 1264 return; 1265 1266 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE, 1267 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher)); 1268 } 1269 1270 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1271 struct mt76_wcid *wcid, 1272 struct ieee80211_key_conf *key) 1273 { 1274 enum mt76_cipher_type cipher; 1275 u16 cipher_mask = wcid->cipher; 1276 int err; 1277 1278 cipher = mt7615_mac_get_cipher(key->cipher); 1279 if (cipher == MT_CIPHER_NONE) 1280 return -EOPNOTSUPP; 1281 1282 cipher_mask |= BIT(cipher); 1283 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask); 1284 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask); 1285 if (err < 0) 1286 return err; 1287 1288 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask, 1289 key->keyidx); 1290 if (err < 0) 1291 return err; 1292 1293 wcid->cipher = cipher_mask; 1294 1295 return 0; 1296 } 1297 1298 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1299 struct mt76_wcid *wcid, 1300 struct ieee80211_key_conf *key) 1301 { 1302 int err; 1303 1304 spin_lock_bh(&dev->mt76.lock); 1305 err = __mt7615_mac_wtbl_set_key(dev, wcid, key); 1306 spin_unlock_bh(&dev->mt76.lock); 1307 1308 return err; 1309 } 1310 1311 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta, 1312 struct ieee80211_tx_info *info, __le32 *txs_data) 1313 { 1314 struct ieee80211_supported_band *sband; 1315 struct mt7615_rate_set *rs; 1316 struct mt76_phy *mphy; 1317 int first_idx = 0, last_idx; 1318 int i, idx, count; 1319 bool fixed_rate, ack_timeout; 1320 bool ampdu, cck = false; 1321 bool rs_idx; 1322 u32 rate_set_tsf; 1323 u32 final_rate, final_rate_flags, final_nss, txs; 1324 1325 txs = le32_to_cpu(txs_data[1]); 1326 ampdu = txs & MT_TXS1_AMPDU; 1327 1328 txs = le32_to_cpu(txs_data[3]); 1329 count = FIELD_GET(MT_TXS3_TX_COUNT, txs); 1330 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs); 1331 1332 txs = le32_to_cpu(txs_data[0]); 1333 fixed_rate = txs & MT_TXS0_FIXED_RATE; 1334 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1335 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1336 1337 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1338 return false; 1339 1340 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1341 return false; 1342 1343 if (!ack_timeout) 1344 info->flags |= IEEE80211_TX_STAT_ACK; 1345 1346 info->status.ampdu_len = 1; 1347 info->status.ampdu_ack_len = !!(info->flags & 1348 IEEE80211_TX_STAT_ACK); 1349 1350 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1351 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1352 1353 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY); 1354 1355 if (fixed_rate) { 1356 info->status.rates[0].count = count; 1357 i = 0; 1358 goto out; 1359 } 1360 1361 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1362 rs_idx = !((u32)(le32_get_bits(txs_data[4], MT_TXS4_F0_TIMESTAMP) - 1363 rate_set_tsf) < 1000000); 1364 rs_idx ^= rate_set_tsf & BIT(0); 1365 rs = &sta->rateset[rs_idx]; 1366 1367 if (!first_idx && rs->probe_rate.idx >= 0) { 1368 info->status.rates[0] = rs->probe_rate; 1369 1370 spin_lock_bh(&dev->mt76.lock); 1371 if (sta->rate_probe) { 1372 struct mt7615_phy *phy = &dev->phy; 1373 1374 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1]) 1375 phy = dev->mt76.phys[MT_BAND1]->priv; 1376 1377 mt7615_mac_set_rates(phy, sta, NULL, sta->rates); 1378 } 1379 spin_unlock_bh(&dev->mt76.lock); 1380 } else { 1381 info->status.rates[0] = rs->rates[first_idx / 2]; 1382 } 1383 info->status.rates[0].count = 0; 1384 1385 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1386 struct ieee80211_tx_rate *cur_rate; 1387 int cur_count; 1388 1389 cur_rate = &rs->rates[idx / 2]; 1390 cur_count = min_t(int, MT7615_RATE_RETRY, count); 1391 count -= cur_count; 1392 1393 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1394 cur_rate->flags != info->status.rates[i].flags)) { 1395 i++; 1396 if (i == ARRAY_SIZE(info->status.rates)) { 1397 i--; 1398 break; 1399 } 1400 1401 info->status.rates[i] = *cur_rate; 1402 info->status.rates[i].count = 0; 1403 } 1404 1405 info->status.rates[i].count += cur_count; 1406 } 1407 1408 out: 1409 final_rate_flags = info->status.rates[i].flags; 1410 1411 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1412 case MT_PHY_TYPE_CCK: 1413 cck = true; 1414 fallthrough; 1415 case MT_PHY_TYPE_OFDM: 1416 mphy = &dev->mphy; 1417 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1]) 1418 mphy = dev->mt76.phys[MT_BAND1]; 1419 1420 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1421 sband = &mphy->sband_5g.sband; 1422 else 1423 sband = &mphy->sband_2g.sband; 1424 final_rate &= MT_TX_RATE_IDX; 1425 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1426 cck); 1427 final_rate_flags = 0; 1428 break; 1429 case MT_PHY_TYPE_HT_GF: 1430 case MT_PHY_TYPE_HT: 1431 final_rate_flags |= IEEE80211_TX_RC_MCS; 1432 final_rate &= MT_TX_RATE_IDX; 1433 if (final_rate > 31) 1434 return false; 1435 break; 1436 case MT_PHY_TYPE_VHT: 1437 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate); 1438 1439 if ((final_rate & MT_TX_RATE_STBC) && final_nss) 1440 final_nss--; 1441 1442 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS; 1443 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4); 1444 break; 1445 default: 1446 return false; 1447 } 1448 1449 info->status.rates[i].idx = final_rate; 1450 info->status.rates[i].flags = final_rate_flags; 1451 1452 return true; 1453 } 1454 1455 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev, 1456 struct mt7615_sta *sta, int pid, 1457 __le32 *txs_data) 1458 { 1459 struct mt76_dev *mdev = &dev->mt76; 1460 struct sk_buff_head list; 1461 struct sk_buff *skb; 1462 1463 if (pid < MT_PACKET_ID_FIRST) 1464 return false; 1465 1466 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1467 1468 mt76_tx_status_lock(mdev, &list); 1469 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1470 if (skb) { 1471 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1472 1473 if (!mt7615_fill_txs(dev, sta, info, txs_data)) { 1474 info->status.rates[0].count = 0; 1475 info->status.rates[0].idx = -1; 1476 } 1477 1478 mt76_tx_status_skb_done(mdev, skb, &list); 1479 } 1480 mt76_tx_status_unlock(mdev, &list); 1481 1482 return !!skb; 1483 } 1484 1485 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data) 1486 { 1487 struct ieee80211_tx_info info = {}; 1488 struct ieee80211_sta *sta = NULL; 1489 struct mt7615_sta *msta = NULL; 1490 struct mt76_wcid *wcid; 1491 struct mt76_phy *mphy = &dev->mt76.phy; 1492 __le32 *txs_data = data; 1493 u8 wcidx; 1494 u8 pid; 1495 1496 pid = le32_get_bits(txs_data[0], MT_TXS0_PID); 1497 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1498 1499 if (pid == MT_PACKET_ID_NO_ACK) 1500 return; 1501 1502 if (wcidx >= MT7615_WTBL_SIZE) 1503 return; 1504 1505 rcu_read_lock(); 1506 1507 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1508 if (!wcid) 1509 goto out; 1510 1511 msta = container_of(wcid, struct mt7615_sta, wcid); 1512 sta = wcid_to_sta(wcid); 1513 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1514 1515 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data)) 1516 goto out; 1517 1518 if (wcidx >= MT7615_WTBL_STA || !sta) 1519 goto out; 1520 1521 if (wcid->phy_idx && dev->mt76.phys[MT_BAND1]) 1522 mphy = dev->mt76.phys[MT_BAND1]; 1523 1524 if (mt7615_fill_txs(dev, msta, &info, txs_data)) { 1525 spin_lock_bh(&dev->mt76.rx_lock); 1526 ieee80211_tx_status_noskb(mphy->hw, sta, &info); 1527 spin_unlock_bh(&dev->mt76.rx_lock); 1528 } 1529 1530 out: 1531 rcu_read_unlock(); 1532 } 1533 1534 static void 1535 mt7615_txwi_free(struct mt7615_dev *dev, struct mt76_txwi_cache *txwi) 1536 { 1537 struct mt76_dev *mdev = &dev->mt76; 1538 __le32 *txwi_data; 1539 u32 val; 1540 u8 wcid; 1541 1542 mt76_connac_txp_skb_unmap(mdev, txwi); 1543 if (!txwi->skb) 1544 goto out; 1545 1546 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi); 1547 val = le32_to_cpu(txwi_data[1]); 1548 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val); 1549 mt76_tx_complete_skb(mdev, wcid, txwi->skb); 1550 1551 out: 1552 txwi->skb = NULL; 1553 mt76_put_txwi(mdev, txwi); 1554 } 1555 1556 static void 1557 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token) 1558 { 1559 struct mt76_dev *mdev = &dev->mt76; 1560 struct mt76_txwi_cache *txwi; 1561 1562 trace_mac_tx_free(dev, token); 1563 txwi = mt76_token_put(mdev, token); 1564 if (!txwi) 1565 return; 1566 1567 mt7615_txwi_free(dev, txwi); 1568 } 1569 1570 static void mt7615_mac_tx_free(struct mt7615_dev *dev, void *data, int len) 1571 { 1572 struct mt76_connac_tx_free *free = data; 1573 void *tx_token = data + sizeof(*free); 1574 void *end = data + len; 1575 u8 i, count; 1576 1577 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1578 if (is_mt7615(&dev->mt76)) { 1579 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1580 } else { 1581 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1582 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); 1583 } 1584 1585 count = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_ID_CNT); 1586 if (is_mt7615(&dev->mt76)) { 1587 __le16 *token = tx_token; 1588 1589 if (WARN_ON_ONCE((void *)&token[count] > end)) 1590 return; 1591 1592 for (i = 0; i < count; i++) 1593 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i])); 1594 } else { 1595 __le32 *token = tx_token; 1596 1597 if (WARN_ON_ONCE((void *)&token[count] > end)) 1598 return; 1599 1600 for (i = 0; i < count; i++) 1601 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i])); 1602 } 1603 1604 rcu_read_lock(); 1605 mt7615_mac_sta_poll(dev); 1606 rcu_read_unlock(); 1607 1608 mt76_worker_schedule(&dev->mt76.tx_worker); 1609 } 1610 1611 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len) 1612 { 1613 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1614 __le32 *rxd = (__le32 *)data; 1615 __le32 *end = (__le32 *)&rxd[len / 4]; 1616 enum rx_pkt_type type; 1617 1618 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1619 1620 switch (type) { 1621 case PKT_TYPE_TXRX_NOTIFY: 1622 mt7615_mac_tx_free(dev, data, len); 1623 return false; 1624 case PKT_TYPE_TXS: 1625 for (rxd++; rxd + 7 <= end; rxd += 7) 1626 mt7615_mac_add_txs(dev, rxd); 1627 return false; 1628 default: 1629 return true; 1630 } 1631 } 1632 EXPORT_SYMBOL_GPL(mt7615_rx_check); 1633 1634 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1635 struct sk_buff *skb, u32 *info) 1636 { 1637 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1638 __le32 *rxd = (__le32 *)skb->data; 1639 __le32 *end = (__le32 *)&skb->data[skb->len]; 1640 enum rx_pkt_type type; 1641 u16 flag; 1642 1643 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1644 flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG); 1645 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1646 type = PKT_TYPE_NORMAL_MCU; 1647 1648 switch (type) { 1649 case PKT_TYPE_TXS: 1650 for (rxd++; rxd + 7 <= end; rxd += 7) 1651 mt7615_mac_add_txs(dev, rxd); 1652 dev_kfree_skb(skb); 1653 break; 1654 case PKT_TYPE_TXRX_NOTIFY: 1655 mt7615_mac_tx_free(dev, skb->data, skb->len); 1656 dev_kfree_skb(skb); 1657 break; 1658 case PKT_TYPE_RX_EVENT: 1659 mt7615_mcu_rx_event(dev, skb); 1660 break; 1661 case PKT_TYPE_NORMAL_MCU: 1662 case PKT_TYPE_NORMAL: 1663 if (!mt7615_mac_fill_rx(dev, skb)) { 1664 mt76_rx(&dev->mt76, q, skb); 1665 return; 1666 } 1667 fallthrough; 1668 default: 1669 dev_kfree_skb(skb); 1670 break; 1671 } 1672 } 1673 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb); 1674 1675 static void 1676 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm) 1677 { 1678 struct mt7615_dev *dev = phy->dev; 1679 bool ext_phy = phy != &dev->phy; 1680 1681 if (is_mt7663(&dev->mt76)) { 1682 if (ofdm) 1683 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy), 1684 MT_WF_PHY_PD_OFDM_MASK(0), 1685 MT_WF_PHY_PD_OFDM(0, val)); 1686 else 1687 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy), 1688 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1689 MT_WF_PHY_PD_CCK(ext_phy, val)); 1690 return; 1691 } 1692 1693 if (ofdm) 1694 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy), 1695 MT_WF_PHY_PD_OFDM_MASK(ext_phy), 1696 MT_WF_PHY_PD_OFDM(ext_phy, val)); 1697 else 1698 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy), 1699 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1700 MT_WF_PHY_PD_CCK(ext_phy, val)); 1701 } 1702 1703 static void 1704 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy) 1705 { 1706 /* ofdm */ 1707 mt7615_mac_set_sensitivity(phy, 0x13c, true); 1708 /* cck */ 1709 mt7615_mac_set_sensitivity(phy, 0x92, false); 1710 1711 phy->ofdm_sensitivity = -98; 1712 phy->cck_sensitivity = -110; 1713 phy->last_cca_adj = jiffies; 1714 } 1715 1716 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable) 1717 { 1718 struct mt7615_dev *dev = phy->dev; 1719 bool ext_phy = phy != &dev->phy; 1720 u32 reg, mask; 1721 1722 mt7615_mutex_acquire(dev); 1723 1724 if (phy->scs_en == enable) 1725 goto out; 1726 1727 if (is_mt7663(&dev->mt76)) { 1728 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy); 1729 mask = MT_WF_PHY_PD_BLK(0); 1730 } else { 1731 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy); 1732 mask = MT_WF_PHY_PD_BLK(ext_phy); 1733 } 1734 1735 if (enable) { 1736 mt76_set(dev, reg, mask); 1737 if (is_mt7622(&dev->mt76)) { 1738 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); 1739 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); 1740 } 1741 } else { 1742 mt76_clear(dev, reg, mask); 1743 } 1744 1745 mt7615_mac_set_default_sensitivity(phy); 1746 phy->scs_en = enable; 1747 1748 out: 1749 mt7615_mutex_release(dev); 1750 } 1751 1752 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy) 1753 { 1754 u32 rxtd, reg; 1755 1756 if (is_mt7663(&dev->mt76)) 1757 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1758 else 1759 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1760 1761 if (ext_phy) 1762 rxtd = MT_WF_PHY_RXTD2(10); 1763 else 1764 rxtd = MT_WF_PHY_RXTD(12); 1765 1766 mt76_set(dev, rxtd, BIT(18) | BIT(29)); 1767 mt76_set(dev, reg, 0x5 << 12); 1768 } 1769 1770 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy) 1771 { 1772 struct mt7615_dev *dev = phy->dev; 1773 bool ext_phy = phy != &dev->phy; 1774 u32 reg; 1775 1776 if (is_mt7663(&dev->mt76)) 1777 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1778 else 1779 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1780 1781 /* reset PD and MDRDY counters */ 1782 mt76_clear(dev, reg, GENMASK(22, 20)); 1783 mt76_set(dev, reg, BIT(22) | BIT(20)); 1784 } 1785 1786 static void 1787 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy, 1788 u32 rts_err_rate, bool ofdm) 1789 { 1790 struct mt7615_dev *dev = phy->dev; 1791 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck; 1792 bool ext_phy = phy != &dev->phy; 1793 s16 def_th = ofdm ? -98 : -110; 1794 bool update = false; 1795 s8 *sensitivity; 1796 int signal; 1797 1798 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity; 1799 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy); 1800 if (!signal) { 1801 mt7615_mac_set_default_sensitivity(phy); 1802 return; 1803 } 1804 1805 signal = min(signal, -72); 1806 if (false_cca > 500) { 1807 if (rts_err_rate > MT_FRAC(40, 100)) 1808 return; 1809 1810 /* decrease coverage */ 1811 if (*sensitivity == def_th && signal > -90) { 1812 *sensitivity = -90; 1813 update = true; 1814 } else if (*sensitivity + 2 < signal) { 1815 *sensitivity += 2; 1816 update = true; 1817 } 1818 } else if ((false_cca > 0 && false_cca < 50) || 1819 rts_err_rate > MT_FRAC(60, 100)) { 1820 /* increase coverage */ 1821 if (*sensitivity - 2 >= def_th) { 1822 *sensitivity -= 2; 1823 update = true; 1824 } 1825 } 1826 1827 if (*sensitivity > signal) { 1828 *sensitivity = signal; 1829 update = true; 1830 } 1831 1832 if (update) { 1833 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256; 1834 1835 mt7615_mac_set_sensitivity(phy, val, ofdm); 1836 phy->last_cca_adj = jiffies; 1837 } 1838 } 1839 1840 static void 1841 mt7615_mac_scs_check(struct mt7615_phy *phy) 1842 { 1843 struct mt7615_dev *dev = phy->dev; 1844 struct mib_stats *mib = &phy->mib; 1845 u32 val, rts_err_rate = 0; 1846 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm; 1847 bool ext_phy = phy != &dev->phy; 1848 1849 if (!phy->scs_en) 1850 return; 1851 1852 if (is_mt7663(&dev->mt76)) 1853 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1854 else 1855 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1856 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val); 1857 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val); 1858 1859 if (is_mt7663(&dev->mt76)) 1860 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1861 else 1862 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1863 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val); 1864 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val); 1865 1866 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1867 phy->false_cca_cck = pd_cck - mdrdy_cck; 1868 mt7615_mac_cca_stats_reset(phy); 1869 1870 if (mib->rts_cnt + mib->rts_retries_cnt) 1871 rts_err_rate = MT_FRAC(mib->rts_retries_cnt, 1872 mib->rts_cnt + mib->rts_retries_cnt); 1873 1874 /* cck */ 1875 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false); 1876 /* ofdm */ 1877 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true); 1878 1879 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ)) 1880 mt7615_mac_set_default_sensitivity(phy); 1881 } 1882 1883 static u8 1884 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx) 1885 { 1886 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1887 u32 reg, val, sum = 0, n = 0; 1888 int i; 1889 1890 if (is_mt7663(&dev->mt76)) 1891 reg = MT7663_WF_PHY_RXTD(20); 1892 else 1893 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20); 1894 1895 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1896 val = mt76_rr(dev, reg); 1897 sum += val * nf_power[i]; 1898 n += val; 1899 } 1900 1901 if (!n) 1902 return 0; 1903 1904 return sum / n; 1905 } 1906 1907 static void 1908 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx) 1909 { 1910 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1911 struct mt7615_phy *phy = mphy->priv; 1912 struct mt76_channel_state *state; 1913 u64 busy_time, tx_time, rx_time, obss_time; 1914 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5; 1915 int nf; 1916 1917 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1918 MT_MIB_SDR9_BUSY_MASK); 1919 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1920 MT_MIB_SDR36_TXTIME_MASK); 1921 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1922 MT_MIB_SDR37_RXTIME_MASK); 1923 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK); 1924 1925 nf = mt7615_phy_get_nf(dev, idx); 1926 if (!phy->noise) 1927 phy->noise = nf << 4; 1928 else if (nf) 1929 phy->noise += nf - (phy->noise >> 4); 1930 1931 state = mphy->chan_state; 1932 state->cc_busy += busy_time; 1933 state->cc_tx += tx_time; 1934 state->cc_rx += rx_time + obss_time; 1935 state->cc_bss_rx += rx_time; 1936 state->noise = -(phy->noise >> 4); 1937 } 1938 1939 static void mt7615_update_survey(struct mt7615_dev *dev) 1940 { 1941 struct mt76_dev *mdev = &dev->mt76; 1942 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 1943 ktime_t cur_time; 1944 1945 /* MT7615 can only update both phys simultaneously 1946 * since some reisters are shared across bands. 1947 */ 1948 1949 mt7615_phy_update_channel(&mdev->phy, 0); 1950 if (mphy_ext) 1951 mt7615_phy_update_channel(mphy_ext, 1); 1952 1953 cur_time = ktime_get_boottime(); 1954 1955 mt76_update_survey_active_time(&mdev->phy, cur_time); 1956 if (mphy_ext) 1957 mt76_update_survey_active_time(mphy_ext, cur_time); 1958 1959 /* reset obss airtime */ 1960 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 1961 } 1962 1963 void mt7615_update_channel(struct mt76_phy *mphy) 1964 { 1965 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1966 1967 if (mt76_connac_pm_wake(&dev->mphy, &dev->pm)) 1968 return; 1969 1970 mt7615_update_survey(dev); 1971 mt76_connac_power_save_sched(&dev->mphy, &dev->pm); 1972 } 1973 EXPORT_SYMBOL_GPL(mt7615_update_channel); 1974 1975 static void 1976 mt7615_mac_update_mib_stats(struct mt7615_phy *phy) 1977 { 1978 struct mt7615_dev *dev = phy->dev; 1979 struct mib_stats *mib = &phy->mib; 1980 bool ext_phy = phy != &dev->phy; 1981 int i, aggr = 0; 1982 u32 val, val2; 1983 1984 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 1985 MT_MIB_SDR3_FCS_ERR_MASK); 1986 1987 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy), 1988 MT_MIB_AMPDU_MPDU_COUNT); 1989 if (val) { 1990 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy), 1991 MT_MIB_AMPDU_ACK_COUNT); 1992 mib->aggr_per = 1000 * (val - val2) / val; 1993 } 1994 1995 for (i = 0; i < 4; i++) { 1996 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); 1997 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1998 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, 1999 val); 2000 2001 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); 2002 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 2003 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, 2004 val); 2005 2006 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 2007 phy->mt76->aggr_stats[aggr++] += val & 0xffff; 2008 phy->mt76->aggr_stats[aggr++] += val >> 16; 2009 } 2010 } 2011 2012 void mt7615_pm_wake_work(struct work_struct *work) 2013 { 2014 struct mt7615_dev *dev; 2015 struct mt76_phy *mphy; 2016 2017 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2018 pm.wake_work); 2019 mphy = dev->phy.mt76; 2020 2021 if (!mt7615_mcu_set_drv_ctrl(dev)) { 2022 struct mt76_dev *mdev = &dev->mt76; 2023 int i; 2024 2025 if (mt76_is_sdio(mdev)) { 2026 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 2027 mt76_worker_schedule(&mdev->sdio.txrx_worker); 2028 } else { 2029 local_bh_disable(); 2030 mt76_for_each_q_rx(mdev, i) 2031 napi_schedule(&mdev->napi[i]); 2032 local_bh_enable(); 2033 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 2034 mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM], 2035 false); 2036 } 2037 2038 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) { 2039 unsigned long timeout; 2040 2041 timeout = mt7615_get_macwork_timeout(dev); 2042 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2043 timeout); 2044 } 2045 } 2046 2047 ieee80211_wake_queues(mphy->hw); 2048 wake_up(&dev->pm.wait); 2049 } 2050 2051 void mt7615_pm_power_save_work(struct work_struct *work) 2052 { 2053 struct mt7615_dev *dev; 2054 unsigned long delta; 2055 2056 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2057 pm.ps_work.work); 2058 2059 delta = dev->pm.idle_timeout; 2060 if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) || 2061 test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state)) 2062 goto out; 2063 2064 if (mutex_is_locked(&dev->mt76.mutex)) 2065 /* if mt76 mutex is held we should not put the device 2066 * to sleep since we are currently accessing device 2067 * register map. We need to wait for the next power_save 2068 * trigger. 2069 */ 2070 goto out; 2071 2072 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 2073 delta = dev->pm.last_activity + delta - jiffies; 2074 goto out; 2075 } 2076 2077 if (!mt7615_mcu_set_fw_ctrl(dev)) 2078 return; 2079 out: 2080 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 2081 } 2082 2083 void mt7615_mac_work(struct work_struct *work) 2084 { 2085 struct mt7615_phy *phy; 2086 struct mt76_phy *mphy; 2087 unsigned long timeout; 2088 2089 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2090 mac_work.work); 2091 phy = mphy->priv; 2092 2093 mt7615_mutex_acquire(phy->dev); 2094 2095 mt7615_update_survey(phy->dev); 2096 if (++mphy->mac_work_count == 5) { 2097 mphy->mac_work_count = 0; 2098 2099 mt7615_mac_update_mib_stats(phy); 2100 mt7615_mac_scs_check(phy); 2101 } 2102 2103 mt7615_mutex_release(phy->dev); 2104 2105 mt76_tx_status_check(mphy->dev, false); 2106 2107 timeout = mt7615_get_macwork_timeout(phy->dev); 2108 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout); 2109 } 2110 2111 void mt7615_tx_token_put(struct mt7615_dev *dev) 2112 { 2113 struct mt76_txwi_cache *txwi; 2114 int id; 2115 2116 spin_lock_bh(&dev->mt76.token_lock); 2117 idr_for_each_entry(&dev->mt76.token, txwi, id) 2118 mt7615_txwi_free(dev, txwi); 2119 spin_unlock_bh(&dev->mt76.token_lock); 2120 idr_destroy(&dev->mt76.token); 2121 } 2122 EXPORT_SYMBOL_GPL(mt7615_tx_token_put); 2123 2124 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy) 2125 { 2126 struct mt7615_dev *dev = phy->dev; 2127 2128 if (phy->rdd_state & BIT(0)) 2129 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2130 MT_RX_SEL0, 0); 2131 if (phy->rdd_state & BIT(1)) 2132 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2133 MT_RX_SEL0, 0); 2134 } 2135 2136 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain) 2137 { 2138 int err; 2139 2140 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2141 MT_RX_SEL0, 0); 2142 if (err < 0) 2143 return err; 2144 2145 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2146 MT_RX_SEL0, 1); 2147 } 2148 2149 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy) 2150 { 2151 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2152 struct mt7615_dev *dev = phy->dev; 2153 bool ext_phy = phy != &dev->phy; 2154 int err; 2155 2156 /* start CAC */ 2157 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, ext_phy, 2158 MT_RX_SEL0, 0); 2159 if (err < 0) 2160 return err; 2161 2162 err = mt7615_dfs_start_rdd(dev, ext_phy); 2163 if (err < 0) 2164 return err; 2165 2166 phy->rdd_state |= BIT(ext_phy); 2167 2168 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2169 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2170 err = mt7615_dfs_start_rdd(dev, 1); 2171 if (err < 0) 2172 return err; 2173 2174 phy->rdd_state |= BIT(1); 2175 } 2176 2177 return 0; 2178 } 2179 2180 static int 2181 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy) 2182 { 2183 const struct mt7615_dfs_radar_spec *radar_specs; 2184 struct mt7615_dev *dev = phy->dev; 2185 int err, i, lpn = 500; 2186 2187 switch (dev->mt76.region) { 2188 case NL80211_DFS_FCC: 2189 radar_specs = &fcc_radar_specs; 2190 lpn = 8; 2191 break; 2192 case NL80211_DFS_ETSI: 2193 radar_specs = &etsi_radar_specs; 2194 break; 2195 case NL80211_DFS_JP: 2196 radar_specs = &jp_radar_specs; 2197 break; 2198 default: 2199 return -EINVAL; 2200 } 2201 2202 /* avoid FCC radar detection in non-FCC region */ 2203 err = mt7615_mcu_set_fcc5_lpn(dev, lpn); 2204 if (err < 0) 2205 return err; 2206 2207 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2208 err = mt7615_mcu_set_radar_th(dev, i, 2209 &radar_specs->radar_pattern[i]); 2210 if (err < 0) 2211 return err; 2212 } 2213 2214 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2215 } 2216 2217 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy) 2218 { 2219 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2220 struct mt7615_dev *dev = phy->dev; 2221 bool ext_phy = phy != &dev->phy; 2222 enum mt76_dfs_state dfs_state, prev_state; 2223 int err; 2224 2225 if (is_mt7663(&dev->mt76)) 2226 return 0; 2227 2228 prev_state = phy->mt76->dfs_state; 2229 dfs_state = mt76_phy_dfs_state(phy->mt76); 2230 if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) && 2231 dfs_state < MT_DFS_STATE_CAC) 2232 dfs_state = MT_DFS_STATE_ACTIVE; 2233 2234 if (prev_state == dfs_state) 2235 return 0; 2236 2237 if (dfs_state == MT_DFS_STATE_DISABLED) 2238 goto stop; 2239 2240 if (prev_state <= MT_DFS_STATE_DISABLED) { 2241 err = mt7615_dfs_init_radar_specs(phy); 2242 if (err < 0) 2243 return err; 2244 2245 err = mt7615_dfs_start_radar_detector(phy); 2246 if (err < 0) 2247 return err; 2248 2249 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2250 } 2251 2252 if (dfs_state == MT_DFS_STATE_CAC) 2253 return 0; 2254 2255 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2256 ext_phy, MT_RX_SEL0, 0); 2257 if (err < 0) { 2258 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2259 return err; 2260 } 2261 2262 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2263 return 0; 2264 2265 stop: 2266 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, ext_phy, 2267 MT_RX_SEL0, 0); 2268 if (err < 0) 2269 return err; 2270 2271 mt7615_dfs_stop_radar_detector(phy); 2272 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2273 2274 return 0; 2275 } 2276 2277 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy, 2278 struct ieee80211_vif *vif, 2279 bool enable) 2280 { 2281 struct mt7615_dev *dev = phy->dev; 2282 bool ext_phy = phy != &dev->phy; 2283 int err; 2284 2285 if (!mt7615_firmware_offload(dev)) 2286 return -EOPNOTSUPP; 2287 2288 switch (vif->type) { 2289 case NL80211_IFTYPE_MONITOR: 2290 return 0; 2291 case NL80211_IFTYPE_MESH_POINT: 2292 case NL80211_IFTYPE_ADHOC: 2293 case NL80211_IFTYPE_AP: 2294 if (enable) 2295 phy->n_beacon_vif++; 2296 else 2297 phy->n_beacon_vif--; 2298 fallthrough; 2299 default: 2300 break; 2301 } 2302 2303 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif); 2304 if (err) 2305 return err; 2306 2307 if (phy->n_beacon_vif) { 2308 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER; 2309 mt76_clear(dev, MT_WF_RFCR(ext_phy), 2310 MT_WF_RFCR_DROP_OTHER_BEACON); 2311 } else { 2312 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER; 2313 mt76_set(dev, MT_WF_RFCR(ext_phy), 2314 MT_WF_RFCR_DROP_OTHER_BEACON); 2315 } 2316 2317 return 0; 2318 } 2319 2320 void mt7615_coredump_work(struct work_struct *work) 2321 { 2322 struct mt7615_dev *dev; 2323 char *dump, *data; 2324 2325 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2326 coredump.work.work); 2327 2328 if (time_is_after_jiffies(dev->coredump.last_activity + 2329 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 2330 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 2331 MT76_CONNAC_COREDUMP_TIMEOUT); 2332 return; 2333 } 2334 2335 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 2336 data = dump; 2337 2338 while (true) { 2339 struct sk_buff *skb; 2340 2341 spin_lock_bh(&dev->mt76.lock); 2342 skb = __skb_dequeue(&dev->coredump.msg_list); 2343 spin_unlock_bh(&dev->mt76.lock); 2344 2345 if (!skb) 2346 break; 2347 2348 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 2349 if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 2350 dev_kfree_skb(skb); 2351 continue; 2352 } 2353 2354 memcpy(data, skb->data, skb->len); 2355 data += skb->len; 2356 2357 dev_kfree_skb(skb); 2358 } 2359 2360 if (dump) 2361 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 2362 GFP_KERNEL); 2363 } 2364