1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Roy Luo <royluo@google.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 * Felix Fietkau <nbd@nbd.name> 7 */ 8 9 #include <linux/etherdevice.h> 10 #include "mt7615.h" 11 #include "mac.h" 12 #include "eeprom.h" 13 14 static void mt7615_phy_init(struct mt7615_dev *dev) 15 { 16 /* disable band 0 rf low power beacon mode */ 17 mt76_rmw(dev, MT_WF_PHY_WF2_RFCTRL0, MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN, 18 MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN); 19 } 20 21 static void mt7615_mac_init(struct mt7615_dev *dev) 22 { 23 u32 val, mask, set; 24 int i; 25 26 /* enable band 0/1 clk */ 27 mt76_set(dev, MT_CFG_CCR, 28 MT_CFG_CCR_MAC_D0_1X_GC_EN | MT_CFG_CCR_MAC_D0_2X_GC_EN | 29 MT_CFG_CCR_MAC_D1_1X_GC_EN | MT_CFG_CCR_MAC_D1_2X_GC_EN); 30 31 val = mt76_rmw(dev, MT_TMAC_TRCR0, 32 MT_TMAC_TRCR_CCA_SEL | MT_TMAC_TRCR_SEC_CCA_SEL, 33 FIELD_PREP(MT_TMAC_TRCR_CCA_SEL, 2) | 34 FIELD_PREP(MT_TMAC_TRCR_SEC_CCA_SEL, 0)); 35 mt76_wr(dev, MT_TMAC_TRCR1, val); 36 37 val = MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE | 38 FIELD_PREP(MT_AGG_ACR_CFEND_RATE, 0x49) | /* 24M */ 39 FIELD_PREP(MT_AGG_ACR_BAR_RATE, 0x4b); /* 6M */ 40 mt76_wr(dev, MT_AGG_ACR0, val); 41 mt76_wr(dev, MT_AGG_ACR1, val); 42 43 mt76_rmw_field(dev, MT_TMAC_CTCR0, 44 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 45 mt76_rmw_field(dev, MT_TMAC_CTCR0, 46 MT_TMAC_CTCR0_INS_DDLMT_DENSITY, 0x3); 47 mt76_rmw(dev, MT_TMAC_CTCR0, 48 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 49 MT_TMAC_CTCR0_INS_DDLMT_EN, 50 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 51 MT_TMAC_CTCR0_INS_DDLMT_EN); 52 53 mt7615_mcu_set_rts_thresh(dev, 0x92b); 54 mt7615_mac_set_scs(dev, true); 55 56 mt76_rmw(dev, MT_AGG_SCR, MT_AGG_SCR_NLNAV_MID_PTEC_DIS, 57 MT_AGG_SCR_NLNAV_MID_PTEC_DIS); 58 59 mt7615_mcu_init_mac(dev); 60 61 mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP | 62 FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072)); 63 64 mt76_wr(dev, MT_AGG_ARUCR, 65 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) | 66 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) | 67 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) | 68 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) | 69 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) | 70 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) | 71 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) | 72 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1)); 73 74 mt76_wr(dev, MT_AGG_ARDCR, 75 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7615_RATE_RETRY - 1) | 76 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7615_RATE_RETRY - 1) | 77 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7615_RATE_RETRY - 1) | 78 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7615_RATE_RETRY - 1) | 79 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7615_RATE_RETRY - 1) | 80 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7615_RATE_RETRY - 1) | 81 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7615_RATE_RETRY - 1) | 82 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7615_RATE_RETRY - 1)); 83 84 mt76_wr(dev, MT_AGG_ARCR, 85 (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) | 86 MT_AGG_ARCR_RATE_DOWN_RATIO_EN | 87 FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) | 88 FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4))); 89 90 mask = MT_DMA_RCFR0_MCU_RX_MGMT | 91 MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR | 92 MT_DMA_RCFR0_MCU_RX_CTL_BAR | 93 MT_DMA_RCFR0_MCU_RX_BYPASS | 94 MT_DMA_RCFR0_RX_DROPPED_UCAST | 95 MT_DMA_RCFR0_RX_DROPPED_MCAST; 96 set = FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_UCAST, 2) | 97 FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_MCAST, 2); 98 mt76_rmw(dev, MT_DMA_BN0RCFR0, mask, set); 99 mt76_rmw(dev, MT_DMA_BN1RCFR0, mask, set); 100 101 for (i = 0; i < MT7615_WTBL_SIZE; i++) 102 mt7615_mac_wtbl_update(dev, i, 103 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 104 105 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_EN); 106 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_EN); 107 } 108 109 static int mt7615_init_hardware(struct mt7615_dev *dev) 110 { 111 int ret, idx; 112 113 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 114 115 spin_lock_init(&dev->token_lock); 116 idr_init(&dev->token); 117 118 ret = mt7615_eeprom_init(dev); 119 if (ret < 0) 120 return ret; 121 122 ret = mt7615_dma_init(dev); 123 if (ret) 124 return ret; 125 126 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); 127 128 ret = mt7615_mcu_init(dev); 129 if (ret) 130 return ret; 131 132 mt7615_mcu_set_eeprom(dev); 133 mt7615_mac_init(dev); 134 mt7615_phy_init(dev); 135 mt7615_mcu_ctrl_pm_state(dev, 0); 136 mt7615_mcu_del_wtbl_all(dev); 137 138 /* Beacon and mgmt frames should occupy wcid 0 */ 139 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7615_WTBL_STA - 1); 140 if (idx) 141 return -ENOSPC; 142 143 dev->mt76.global_wcid.idx = idx; 144 dev->mt76.global_wcid.hw_key_idx = -1; 145 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 146 147 return 0; 148 } 149 150 #define CCK_RATE(_idx, _rate) { \ 151 .bitrate = _rate, \ 152 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 153 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 154 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + (_idx)), \ 155 } 156 157 #define OFDM_RATE(_idx, _rate) { \ 158 .bitrate = _rate, \ 159 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 160 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 161 } 162 163 static struct ieee80211_rate mt7615_rates[] = { 164 CCK_RATE(0, 10), 165 CCK_RATE(1, 20), 166 CCK_RATE(2, 55), 167 CCK_RATE(3, 110), 168 OFDM_RATE(11, 60), 169 OFDM_RATE(15, 90), 170 OFDM_RATE(10, 120), 171 OFDM_RATE(14, 180), 172 OFDM_RATE(9, 240), 173 OFDM_RATE(13, 360), 174 OFDM_RATE(8, 480), 175 OFDM_RATE(12, 540), 176 }; 177 178 static const struct ieee80211_iface_limit if_limits[] = { 179 { 180 .max = 1, 181 .types = BIT(NL80211_IFTYPE_ADHOC) 182 }, { 183 .max = MT7615_MAX_INTERFACES, 184 .types = BIT(NL80211_IFTYPE_AP) | 185 #ifdef CONFIG_MAC80211_MESH 186 BIT(NL80211_IFTYPE_MESH_POINT) | 187 #endif 188 BIT(NL80211_IFTYPE_STATION) 189 } 190 }; 191 192 static const struct ieee80211_iface_combination if_comb[] = { 193 { 194 .limits = if_limits, 195 .n_limits = ARRAY_SIZE(if_limits), 196 .max_interfaces = 4, 197 .num_different_channels = 1, 198 .beacon_int_infra_match = true, 199 } 200 }; 201 202 static void 203 mt7615_init_txpower(struct mt7615_dev *dev, 204 struct ieee80211_supported_band *sband) 205 { 206 int i, n_chains = hweight8(dev->mt76.antenna_mask), target_chains; 207 u8 *eep = (u8 *)dev->mt76.eeprom.data; 208 enum nl80211_band band = sband->band; 209 210 target_chains = mt7615_ext_pa_enabled(dev, band) ? 1 : n_chains; 211 for (i = 0; i < sband->n_channels; i++) { 212 struct ieee80211_channel *chan = &sband->channels[i]; 213 u8 target_power = 0; 214 int j; 215 216 for (j = 0; j < target_chains; j++) { 217 int index; 218 219 index = mt7615_eeprom_get_power_index(dev, chan, j); 220 target_power = max(target_power, eep[index]); 221 } 222 223 target_power = DIV_ROUND_UP(target_power, 2); 224 switch (n_chains) { 225 case 4: 226 target_power += 6; 227 break; 228 case 3: 229 target_power += 4; 230 break; 231 case 2: 232 target_power += 3; 233 break; 234 default: 235 break; 236 } 237 238 chan->max_power = min_t(int, chan->max_reg_power, 239 target_power); 240 chan->orig_mpwr = target_power; 241 } 242 } 243 244 static void 245 mt7615_regd_notifier(struct wiphy *wiphy, 246 struct regulatory_request *request) 247 { 248 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 249 struct mt7615_dev *dev = hw->priv; 250 struct cfg80211_chan_def *chandef = &dev->mt76.chandef; 251 252 if (request->dfs_region == dev->mt76.region) 253 return; 254 255 dev->mt76.region = request->dfs_region; 256 257 if (!(chandef->chan->flags & IEEE80211_CHAN_RADAR)) 258 return; 259 260 mt7615_dfs_stop_radar_detector(dev); 261 if (request->dfs_region == NL80211_DFS_UNSET) 262 mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, MT_HW_RDD0, 263 MT_RX_SEL0, 0); 264 else 265 mt7615_dfs_start_radar_detector(dev); 266 } 267 268 int mt7615_register_device(struct mt7615_dev *dev) 269 { 270 struct ieee80211_hw *hw = mt76_hw(dev); 271 struct wiphy *wiphy = hw->wiphy; 272 int ret; 273 274 INIT_DELAYED_WORK(&dev->mt76.mac_work, mt7615_mac_work); 275 INIT_LIST_HEAD(&dev->sta_poll_list); 276 spin_lock_init(&dev->sta_poll_lock); 277 278 ret = mt7615_init_hardware(dev); 279 if (ret) 280 return ret; 281 282 hw->queues = 4; 283 hw->max_rates = 3; 284 hw->max_report_rates = 7; 285 hw->max_rate_tries = 11; 286 287 hw->sta_data_size = sizeof(struct mt7615_sta); 288 hw->vif_data_size = sizeof(struct mt7615_vif); 289 290 wiphy->iface_combinations = if_comb; 291 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 292 wiphy->reg_notifier = mt7615_regd_notifier; 293 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 294 295 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 296 297 ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN); 298 299 dev->mt76.sband_2g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING; 300 dev->mt76.sband_5g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING; 301 dev->mt76.sband_5g.sband.vht_cap.cap |= 302 IEEE80211_VHT_CAP_SHORT_GI_160 | 303 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 304 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 305 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ; 306 dev->dfs_state = -1; 307 308 ret = mt76_register_device(&dev->mt76, true, mt7615_rates, 309 ARRAY_SIZE(mt7615_rates)); 310 if (ret) 311 return ret; 312 313 mt7615_init_txpower(dev, &dev->mt76.sband_2g.sband); 314 mt7615_init_txpower(dev, &dev->mt76.sband_5g.sband); 315 316 hw->max_tx_fragments = MT_TXP_MAX_BUF_NUM; 317 318 return mt7615_init_debugfs(dev); 319 } 320 321 void mt7615_unregister_device(struct mt7615_dev *dev) 322 { 323 struct mt76_txwi_cache *txwi; 324 int id; 325 326 mt76_unregister_device(&dev->mt76); 327 mt7615_mcu_exit(dev); 328 mt7615_dma_cleanup(dev); 329 330 spin_lock_bh(&dev->token_lock); 331 idr_for_each_entry(&dev->token, txwi, id) { 332 mt7615_txp_skb_unmap(&dev->mt76, txwi); 333 if (txwi->skb) 334 dev_kfree_skb_any(txwi->skb); 335 mt76_put_txwi(&dev->mt76, txwi); 336 } 337 spin_unlock_bh(&dev->token_lock); 338 idr_destroy(&dev->token); 339 340 mt76_free_device(&dev->mt76); 341 } 342