1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Roy Luo <royluo@google.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 * Felix Fietkau <nbd@nbd.name> 7 */ 8 9 #include <linux/etherdevice.h> 10 #include "mt7615.h" 11 #include "mac.h" 12 #include "eeprom.h" 13 14 static void mt7615_phy_init(struct mt7615_dev *dev) 15 { 16 /* disable rf low power beacon mode */ 17 mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(0), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN); 18 mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(1), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN); 19 } 20 21 static void mt7615_mac_init(struct mt7615_dev *dev) 22 { 23 u32 val, mask, set; 24 int i; 25 26 /* enable band 0/1 clk */ 27 mt76_set(dev, MT_CFG_CCR, 28 MT_CFG_CCR_MAC_D0_1X_GC_EN | MT_CFG_CCR_MAC_D0_2X_GC_EN | 29 MT_CFG_CCR_MAC_D1_1X_GC_EN | MT_CFG_CCR_MAC_D1_2X_GC_EN); 30 31 val = mt76_rmw(dev, MT_TMAC_TRCR(0), 32 MT_TMAC_TRCR_CCA_SEL | MT_TMAC_TRCR_SEC_CCA_SEL, 33 FIELD_PREP(MT_TMAC_TRCR_CCA_SEL, 2) | 34 FIELD_PREP(MT_TMAC_TRCR_SEC_CCA_SEL, 0)); 35 mt76_wr(dev, MT_TMAC_TRCR(1), val); 36 37 val = MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE | 38 FIELD_PREP(MT_AGG_ACR_CFEND_RATE, MT7615_CFEND_RATE_DEFAULT) | 39 FIELD_PREP(MT_AGG_ACR_BAR_RATE, MT7615_BAR_RATE_DEFAULT); 40 mt76_wr(dev, MT_AGG_ACR(0), val); 41 mt76_wr(dev, MT_AGG_ACR(1), val); 42 43 mt76_rmw_field(dev, MT_TMAC_CTCR0, 44 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 45 mt76_rmw_field(dev, MT_TMAC_CTCR0, 46 MT_TMAC_CTCR0_INS_DDLMT_DENSITY, 0x3); 47 mt76_rmw(dev, MT_TMAC_CTCR0, 48 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 49 MT_TMAC_CTCR0_INS_DDLMT_EN, 50 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 51 MT_TMAC_CTCR0_INS_DDLMT_EN); 52 53 mt7615_mcu_set_rts_thresh(&dev->phy, 0x92b); 54 mt7615_mac_set_scs(dev, true); 55 56 mt76_rmw(dev, MT_AGG_SCR, MT_AGG_SCR_NLNAV_MID_PTEC_DIS, 57 MT_AGG_SCR_NLNAV_MID_PTEC_DIS); 58 59 mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP | 60 FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072)); 61 62 val = FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) | 63 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) | 64 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) | 65 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) | 66 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) | 67 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) | 68 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) | 69 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1); 70 mt76_wr(dev, MT_AGG_ARUCR(0), val); 71 mt76_wr(dev, MT_AGG_ARUCR(1), val); 72 73 val = FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7615_RATE_RETRY - 1) | 74 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7615_RATE_RETRY - 1) | 75 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7615_RATE_RETRY - 1) | 76 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7615_RATE_RETRY - 1) | 77 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7615_RATE_RETRY - 1) | 78 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7615_RATE_RETRY - 1) | 79 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7615_RATE_RETRY - 1) | 80 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7615_RATE_RETRY - 1); 81 mt76_wr(dev, MT_AGG_ARDCR(0), val); 82 mt76_wr(dev, MT_AGG_ARDCR(1), val); 83 84 mt76_wr(dev, MT_AGG_ARCR, 85 (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) | 86 MT_AGG_ARCR_RATE_DOWN_RATIO_EN | 87 FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) | 88 FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4))); 89 90 mask = MT_DMA_RCFR0_MCU_RX_MGMT | 91 MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR | 92 MT_DMA_RCFR0_MCU_RX_CTL_BAR | 93 MT_DMA_RCFR0_MCU_RX_BYPASS | 94 MT_DMA_RCFR0_RX_DROPPED_UCAST | 95 MT_DMA_RCFR0_RX_DROPPED_MCAST; 96 set = FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_UCAST, 2) | 97 FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_MCAST, 2); 98 mt76_rmw(dev, MT_DMA_RCFR0(0), mask, set); 99 mt76_rmw(dev, MT_DMA_RCFR0(1), mask, set); 100 101 for (i = 0; i < MT7615_WTBL_SIZE; i++) 102 mt7615_mac_wtbl_update(dev, i, 103 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 104 105 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_EN); 106 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_EN); 107 } 108 109 bool mt7615_wait_for_mcu_init(struct mt7615_dev *dev) 110 { 111 flush_work(&dev->mcu_work); 112 113 return test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 114 } 115 116 static void mt7615_init_work(struct work_struct *work) 117 { 118 struct mt7615_dev *dev = container_of(work, struct mt7615_dev, mcu_work); 119 120 if (mt7615_mcu_init(dev)) 121 return; 122 123 mt7615_mcu_set_eeprom(dev); 124 mt7615_mac_init(dev); 125 mt7615_phy_init(dev); 126 mt7615_mcu_del_wtbl_all(dev); 127 } 128 129 static int mt7615_init_hardware(struct mt7615_dev *dev) 130 { 131 int ret, idx; 132 133 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 134 135 INIT_WORK(&dev->mcu_work, mt7615_init_work); 136 spin_lock_init(&dev->token_lock); 137 idr_init(&dev->token); 138 139 ret = mt7615_eeprom_init(dev); 140 if (ret < 0) 141 return ret; 142 143 ret = mt7615_dma_init(dev); 144 if (ret) 145 return ret; 146 147 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 148 149 /* Beacon and mgmt frames should occupy wcid 0 */ 150 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7615_WTBL_STA - 1); 151 if (idx) 152 return -ENOSPC; 153 154 dev->mt76.global_wcid.idx = idx; 155 dev->mt76.global_wcid.hw_key_idx = -1; 156 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 157 158 return 0; 159 } 160 161 #define CCK_RATE(_idx, _rate) { \ 162 .bitrate = _rate, \ 163 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 164 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 165 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + (_idx)), \ 166 } 167 168 #define OFDM_RATE(_idx, _rate) { \ 169 .bitrate = _rate, \ 170 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 171 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 172 } 173 174 static struct ieee80211_rate mt7615_rates[] = { 175 CCK_RATE(0, 10), 176 CCK_RATE(1, 20), 177 CCK_RATE(2, 55), 178 CCK_RATE(3, 110), 179 OFDM_RATE(11, 60), 180 OFDM_RATE(15, 90), 181 OFDM_RATE(10, 120), 182 OFDM_RATE(14, 180), 183 OFDM_RATE(9, 240), 184 OFDM_RATE(13, 360), 185 OFDM_RATE(8, 480), 186 OFDM_RATE(12, 540), 187 }; 188 189 static const struct ieee80211_iface_limit if_limits[] = { 190 { 191 .max = 1, 192 .types = BIT(NL80211_IFTYPE_ADHOC) 193 }, { 194 .max = MT7615_MAX_INTERFACES, 195 .types = BIT(NL80211_IFTYPE_AP) | 196 #ifdef CONFIG_MAC80211_MESH 197 BIT(NL80211_IFTYPE_MESH_POINT) | 198 #endif 199 BIT(NL80211_IFTYPE_STATION) 200 } 201 }; 202 203 static const struct ieee80211_iface_combination if_comb[] = { 204 { 205 .limits = if_limits, 206 .n_limits = ARRAY_SIZE(if_limits), 207 .max_interfaces = 4, 208 .num_different_channels = 1, 209 .beacon_int_infra_match = true, 210 } 211 }; 212 213 static void 214 mt7615_led_set_config(struct led_classdev *led_cdev, 215 u8 delay_on, u8 delay_off) 216 { 217 struct mt7615_dev *dev; 218 struct mt76_dev *mt76; 219 u32 val, addr; 220 221 mt76 = container_of(led_cdev, struct mt76_dev, led_cdev); 222 dev = container_of(mt76, struct mt7615_dev, mt76); 223 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 224 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 225 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 226 227 addr = mt7615_reg_map(dev, MT_LED_STATUS_0(mt76->led_pin)); 228 mt76_wr(dev, addr, val); 229 addr = mt7615_reg_map(dev, MT_LED_STATUS_1(mt76->led_pin)); 230 mt76_wr(dev, addr, val); 231 232 val = MT_LED_CTRL_REPLAY(mt76->led_pin) | 233 MT_LED_CTRL_KICK(mt76->led_pin); 234 if (mt76->led_al) 235 val |= MT_LED_CTRL_POLARITY(mt76->led_pin); 236 addr = mt7615_reg_map(dev, MT_LED_CTRL); 237 mt76_wr(dev, addr, val); 238 } 239 240 static int 241 mt7615_led_set_blink(struct led_classdev *led_cdev, 242 unsigned long *delay_on, 243 unsigned long *delay_off) 244 { 245 u8 delta_on, delta_off; 246 247 delta_off = max_t(u8, *delay_off / 10, 1); 248 delta_on = max_t(u8, *delay_on / 10, 1); 249 250 mt7615_led_set_config(led_cdev, delta_on, delta_off); 251 252 return 0; 253 } 254 255 static void 256 mt7615_led_set_brightness(struct led_classdev *led_cdev, 257 enum led_brightness brightness) 258 { 259 if (!brightness) 260 mt7615_led_set_config(led_cdev, 0, 0xff); 261 else 262 mt7615_led_set_config(led_cdev, 0xff, 0); 263 } 264 265 static void 266 mt7615_init_txpower(struct mt7615_dev *dev, 267 struct ieee80211_supported_band *sband) 268 { 269 int i, n_chains = hweight8(dev->mphy.antenna_mask), target_chains; 270 u8 *eep = (u8 *)dev->mt76.eeprom.data; 271 enum nl80211_band band = sband->band; 272 int delta = mt76_tx_power_nss_delta(n_chains); 273 274 target_chains = mt7615_ext_pa_enabled(dev, band) ? 1 : n_chains; 275 for (i = 0; i < sband->n_channels; i++) { 276 struct ieee80211_channel *chan = &sband->channels[i]; 277 u8 target_power = 0; 278 int j; 279 280 for (j = 0; j < target_chains; j++) { 281 int index; 282 283 index = mt7615_eeprom_get_power_index(dev, chan, j); 284 target_power = max(target_power, eep[index]); 285 } 286 287 target_power = DIV_ROUND_UP(target_power + delta, 2); 288 chan->max_power = min_t(int, chan->max_reg_power, 289 target_power); 290 chan->orig_mpwr = target_power; 291 } 292 } 293 294 static void 295 mt7615_regd_notifier(struct wiphy *wiphy, 296 struct regulatory_request *request) 297 { 298 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 299 struct mt7615_dev *dev = mt7615_hw_dev(hw); 300 struct mt76_phy *mphy = hw->priv; 301 struct mt7615_phy *phy = mphy->priv; 302 struct cfg80211_chan_def *chandef = &mphy->chandef; 303 304 dev->mt76.region = request->dfs_region; 305 306 if (!(chandef->chan->flags & IEEE80211_CHAN_RADAR)) 307 return; 308 309 mt7615_dfs_init_radar_detector(phy); 310 } 311 312 static void 313 mt7615_init_wiphy(struct ieee80211_hw *hw) 314 { 315 struct mt7615_phy *phy = mt7615_hw_phy(hw); 316 struct wiphy *wiphy = hw->wiphy; 317 318 hw->queues = 4; 319 hw->max_rates = 3; 320 hw->max_report_rates = 7; 321 hw->max_rate_tries = 11; 322 323 phy->slottime = 9; 324 325 hw->sta_data_size = sizeof(struct mt7615_sta); 326 hw->vif_data_size = sizeof(struct mt7615_vif); 327 328 wiphy->iface_combinations = if_comb; 329 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 330 wiphy->reg_notifier = mt7615_regd_notifier; 331 332 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 333 334 ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN); 335 336 if (is_mt7615(&phy->dev->mt76)) 337 hw->max_tx_fragments = MT_TXP_MAX_BUF_NUM; 338 else 339 hw->max_tx_fragments = MT_HW_TXP_MAX_BUF_NUM; 340 } 341 342 static void 343 mt7615_cap_dbdc_enable(struct mt7615_dev *dev) 344 { 345 dev->mphy.sband_5g.sband.vht_cap.cap &= 346 ~(IEEE80211_VHT_CAP_SHORT_GI_160 | 347 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ); 348 if (dev->chainmask == 0xf) 349 dev->mphy.antenna_mask = dev->chainmask >> 2; 350 else 351 dev->mphy.antenna_mask = dev->chainmask >> 1; 352 dev->phy.chainmask = dev->mphy.antenna_mask; 353 mt76_set_stream_caps(&dev->mt76, true); 354 } 355 356 static void 357 mt7615_cap_dbdc_disable(struct mt7615_dev *dev) 358 { 359 dev->mphy.sband_5g.sband.vht_cap.cap |= 360 IEEE80211_VHT_CAP_SHORT_GI_160 | 361 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ; 362 dev->mphy.antenna_mask = dev->chainmask; 363 dev->phy.chainmask = dev->chainmask; 364 mt76_set_stream_caps(&dev->mt76, true); 365 } 366 367 int mt7615_register_ext_phy(struct mt7615_dev *dev) 368 { 369 struct mt7615_phy *phy = mt7615_ext_phy(dev); 370 struct mt76_phy *mphy; 371 int ret; 372 373 if (!is_mt7615(&dev->mt76)) 374 return -EOPNOTSUPP; 375 376 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) 377 return -EINVAL; 378 379 if (phy) 380 return 0; 381 382 mt7615_cap_dbdc_enable(dev); 383 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7615_ops); 384 if (!mphy) 385 return -ENOMEM; 386 387 phy = mphy->priv; 388 phy->dev = dev; 389 phy->mt76 = mphy; 390 phy->chainmask = dev->chainmask & ~dev->phy.chainmask; 391 mphy->antenna_mask = BIT(hweight8(phy->chainmask)) - 1; 392 mt7615_init_wiphy(mphy->hw); 393 394 /* 395 * Make the secondary PHY MAC address local without overlapping with 396 * the usual MAC address allocation scheme on multiple virtual interfaces 397 */ 398 mphy->hw->wiphy->perm_addr[0] |= 2; 399 mphy->hw->wiphy->perm_addr[0] ^= BIT(7); 400 401 /* second phy can only handle 5 GHz */ 402 mphy->sband_2g.sband.n_channels = 0; 403 mphy->hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 404 405 /* The second interface does not get any packets unless it has a vif */ 406 ieee80211_hw_set(mphy->hw, WANT_MONITOR_VIF); 407 408 ret = mt76_register_phy(mphy); 409 if (ret) 410 ieee80211_free_hw(mphy->hw); 411 412 return ret; 413 } 414 415 void mt7615_unregister_ext_phy(struct mt7615_dev *dev) 416 { 417 struct mt7615_phy *phy = mt7615_ext_phy(dev); 418 struct mt76_phy *mphy = dev->mt76.phy2; 419 420 if (!phy) 421 return; 422 423 mt7615_cap_dbdc_disable(dev); 424 mt76_unregister_phy(mphy); 425 ieee80211_free_hw(mphy->hw); 426 } 427 428 429 int mt7615_register_device(struct mt7615_dev *dev) 430 { 431 struct ieee80211_hw *hw = mt76_hw(dev); 432 int ret; 433 434 dev->phy.dev = dev; 435 dev->phy.mt76 = &dev->mt76.phy; 436 dev->mt76.phy.priv = &dev->phy; 437 INIT_DELAYED_WORK(&dev->mt76.mac_work, mt7615_mac_work); 438 INIT_LIST_HEAD(&dev->sta_poll_list); 439 spin_lock_init(&dev->sta_poll_lock); 440 init_waitqueue_head(&dev->reset_wait); 441 INIT_WORK(&dev->reset_work, mt7615_mac_reset_work); 442 443 ret = mt7622_wmac_init(dev); 444 if (ret) 445 return ret; 446 447 ret = mt7615_init_hardware(dev); 448 if (ret) 449 return ret; 450 451 mt7615_init_wiphy(hw); 452 dev->mphy.sband_2g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING; 453 dev->mphy.sband_5g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING; 454 dev->mphy.sband_5g.sband.vht_cap.cap |= 455 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 456 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 457 mt7615_cap_dbdc_disable(dev); 458 dev->phy.dfs_state = -1; 459 460 /* init led callbacks */ 461 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 462 dev->mt76.led_cdev.brightness_set = mt7615_led_set_brightness; 463 dev->mt76.led_cdev.blink_set = mt7615_led_set_blink; 464 } 465 466 ret = mt76_register_device(&dev->mt76, true, mt7615_rates, 467 ARRAY_SIZE(mt7615_rates)); 468 if (ret) 469 return ret; 470 471 ieee80211_queue_work(mt76_hw(dev), &dev->mcu_work); 472 mt7615_init_txpower(dev, &dev->mphy.sband_2g.sband); 473 mt7615_init_txpower(dev, &dev->mphy.sband_5g.sband); 474 475 return mt7615_init_debugfs(dev); 476 } 477 478 void mt7615_unregister_device(struct mt7615_dev *dev) 479 { 480 struct mt76_txwi_cache *txwi; 481 bool mcu_running; 482 int id; 483 484 mcu_running = mt7615_wait_for_mcu_init(dev); 485 486 mt7615_unregister_ext_phy(dev); 487 mt76_unregister_device(&dev->mt76); 488 if (mcu_running) 489 mt7615_mcu_exit(dev); 490 mt7615_dma_cleanup(dev); 491 492 spin_lock_bh(&dev->token_lock); 493 idr_for_each_entry(&dev->token, txwi, id) { 494 mt7615_txp_skb_unmap(&dev->mt76, txwi); 495 if (txwi->skb) 496 dev_kfree_skb_any(txwi->skb); 497 mt76_put_txwi(&dev->mt76, txwi); 498 } 499 spin_unlock_bh(&dev->token_lock); 500 idr_destroy(&dev->token); 501 502 mt76_free_device(&dev->mt76); 503 } 504