1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Lorenzo Bianconi <lorenzo@kernel.org> 7 * Felix Fietkau <nbd@nbd.name> 8 */ 9 10 #include "mt7615.h" 11 #include "../dma.h" 12 #include "mac.h" 13 14 static int 15 mt7622_init_tx_queues_multi(struct mt7615_dev *dev) 16 { 17 static const u8 wmm_queue_map[] = { 18 [IEEE80211_AC_BK] = MT7622_TXQ_AC0, 19 [IEEE80211_AC_BE] = MT7622_TXQ_AC1, 20 [IEEE80211_AC_VI] = MT7622_TXQ_AC2, 21 [IEEE80211_AC_VO] = MT7622_TXQ_AC3, 22 }; 23 int ret; 24 int i; 25 26 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { 27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i], 28 MT7615_TX_RING_SIZE / 2, 29 MT_TX_RING_BASE); 30 if (ret) 31 return ret; 32 } 33 34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT, 35 MT7615_TX_MGMT_RING_SIZE, 36 MT_TX_RING_BASE); 37 if (ret) 38 return ret; 39 40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU, 41 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 42 } 43 44 static int 45 mt7615_init_tx_queues(struct mt7615_dev *dev) 46 { 47 int ret, i; 48 49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL, 50 MT7615_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 51 if (ret) 52 return ret; 53 54 if (!is_mt7615(&dev->mt76)) 55 return mt7622_init_tx_queues_multi(dev); 56 57 ret = mt76_init_tx_queue(&dev->mphy, 0, 0, MT7615_TX_RING_SIZE, 58 MT_TX_RING_BASE); 59 if (ret) 60 return ret; 61 62 for (i = 1; i <= MT_TXQ_PSD ; i++) 63 dev->mphy.q_tx[i] = dev->mphy.q_tx[0]; 64 65 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU, 66 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 67 } 68 69 static int mt7615_poll_tx(struct napi_struct *napi, int budget) 70 { 71 struct mt7615_dev *dev; 72 73 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi); 74 75 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); 76 77 if (napi_complete_done(napi, 0)) 78 mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev)); 79 80 return 0; 81 } 82 83 int mt7615_wait_pdma_busy(struct mt7615_dev *dev) 84 { 85 struct mt76_dev *mdev = &dev->mt76; 86 87 if (!is_mt7663(mdev)) { 88 u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY; 89 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY); 90 91 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) { 92 dev_err(mdev->dev, "PDMA engine busy\n"); 93 return -EIO; 94 } 95 96 return 0; 97 } 98 99 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, 100 MT_PDMA_TX_IDX_BUSY, 0, 1000)) { 101 dev_err(mdev->dev, "PDMA engine tx busy\n"); 102 return -EIO; 103 } 104 105 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO, 106 MT_PSE_SRC_CNT, 0, 1000)) { 107 dev_err(mdev->dev, "PSE engine busy\n"); 108 return -EIO; 109 } 110 111 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, 112 MT_PDMA_BUSY_IDX, 0, 1000)) { 113 dev_err(mdev->dev, "PDMA engine busy\n"); 114 return -EIO; 115 } 116 117 return 0; 118 } 119 120 static void mt7622_dma_sched_init(struct mt7615_dev *dev) 121 { 122 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE); 123 int i; 124 125 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE, 126 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE, 127 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | 128 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); 129 130 for (i = 0; i <= 5; i++) 131 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i), 132 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) | 133 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); 134 135 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210); 136 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210); 137 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5); 138 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0); 139 140 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f); 141 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987); 142 } 143 144 static void mt7663_dma_sched_init(struct mt7615_dev *dev) 145 { 146 int i; 147 148 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE), 149 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE, 150 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | 151 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); 152 153 /* enable refill control group 0, 1, 2, 4, 5 */ 154 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000); 155 /* enable group 0, 1, 2, 4, 5, 15 */ 156 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037); 157 158 /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */ 159 for (i = 0; i < 5; i++) 160 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)), 161 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | 162 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); 163 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)), 164 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | 165 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40)); 166 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)), 167 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) | 168 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20)); 169 170 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210); 171 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210); 172 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005); 173 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0); 174 /* ALTX0 and ALTX1 QID mapping to group 5 */ 175 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f); 176 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987); 177 } 178 179 int mt7615_dma_init(struct mt7615_dev *dev) 180 { 181 int rx_ring_size = MT7615_RX_RING_SIZE; 182 int rx_buf_size = MT_RX_BUF_SIZE; 183 int ret; 184 185 /* Increase buffer size to receive large VHT MPDUs */ 186 if (dev->mphy.cap.has_5ghz) 187 rx_buf_size *= 2; 188 189 mt76_dma_attach(&dev->mt76); 190 191 mt76_wr(dev, MT_WPDMA_GLO_CFG, 192 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE | 193 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN | 194 MT_WPDMA_GLO_CFG_OMIT_TX_INFO); 195 196 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 197 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1); 198 199 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 200 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1); 201 202 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 203 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3); 204 205 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 206 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3); 207 208 if (is_mt7615(&dev->mt76)) { 209 mt76_set(dev, MT_WPDMA_GLO_CFG, 210 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY); 211 212 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1); 213 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000); 214 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000); 215 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026); 216 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881); 217 mt76_set(dev, 0x7158, BIT(16)); 218 mt76_clear(dev, 0x7000, BIT(23)); 219 } 220 221 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); 222 223 ret = mt7615_init_tx_queues(dev); 224 if (ret) 225 return ret; 226 227 /* init rx queues */ 228 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, 229 MT7615_RX_MCU_RING_SIZE, rx_buf_size, 230 MT_RX_RING_BASE); 231 if (ret) 232 return ret; 233 234 if (!is_mt7615(&dev->mt76)) 235 rx_ring_size /= 2; 236 237 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 238 rx_ring_size, rx_buf_size, MT_RX_RING_BASE); 239 if (ret) 240 return ret; 241 242 mt76_wr(dev, MT_DELAY_INT_CFG, 0); 243 244 ret = mt76_init_queues(dev); 245 if (ret < 0) 246 return ret; 247 248 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 249 mt7615_poll_tx, NAPI_POLL_WEIGHT); 250 napi_enable(&dev->mt76.tx_napi); 251 252 mt76_poll(dev, MT_WPDMA_GLO_CFG, 253 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 254 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000); 255 256 /* start dma engine */ 257 mt76_set(dev, MT_WPDMA_GLO_CFG, 258 MT_WPDMA_GLO_CFG_TX_DMA_EN | 259 MT_WPDMA_GLO_CFG_RX_DMA_EN); 260 261 /* enable interrupts for TX/RX rings */ 262 mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev) | 263 MT_INT_MCU_CMD); 264 265 if (is_mt7622(&dev->mt76)) 266 mt7622_dma_sched_init(dev); 267 268 if (is_mt7663(&dev->mt76)) 269 mt7663_dma_sched_init(dev); 270 271 return 0; 272 } 273 274 void mt7615_dma_cleanup(struct mt7615_dev *dev) 275 { 276 mt76_clear(dev, MT_WPDMA_GLO_CFG, 277 MT_WPDMA_GLO_CFG_TX_DMA_EN | 278 MT_WPDMA_GLO_CFG_RX_DMA_EN); 279 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 280 281 mt76_dma_cleanup(&dev->mt76); 282 } 283