1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Lorenzo Bianconi <lorenzo@kernel.org> 7 * Felix Fietkau <nbd@nbd.name> 8 */ 9 10 #include "mt7615.h" 11 #include "../dma.h" 12 #include "mac.h" 13 14 static int 15 mt7615_init_tx_queue(struct mt7615_dev *dev, struct mt76_sw_queue *q, 16 int idx, int n_desc) 17 { 18 struct mt76_queue *hwq; 19 int err; 20 21 hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL); 22 if (!hwq) 23 return -ENOMEM; 24 25 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE); 26 if (err < 0) 27 return err; 28 29 INIT_LIST_HEAD(&q->swq); 30 q->q = hwq; 31 32 return 0; 33 } 34 35 static int 36 mt7622_init_tx_queues_multi(struct mt7615_dev *dev) 37 { 38 static const u8 wmm_queue_map[] = { 39 MT7622_TXQ_AC0, 40 MT7622_TXQ_AC1, 41 MT7622_TXQ_AC2, 42 MT7622_TXQ_AC3, 43 }; 44 int ret; 45 int i; 46 47 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { 48 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[i], 49 wmm_queue_map[i], 50 MT7615_TX_RING_SIZE / 2); 51 if (ret) 52 return ret; 53 } 54 55 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD], 56 MT7622_TXQ_MGMT, MT7615_TX_MGMT_RING_SIZE); 57 if (ret) 58 return ret; 59 60 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU], 61 MT7622_TXQ_MCU, MT7615_TX_MCU_RING_SIZE); 62 return ret; 63 } 64 65 static int 66 mt7615_init_tx_queues(struct mt7615_dev *dev) 67 { 68 struct mt76_sw_queue *q; 69 int ret, i; 70 71 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL], 72 MT7615_TXQ_FWDL, 73 MT7615_TX_FWDL_RING_SIZE); 74 if (ret) 75 return ret; 76 77 if (!is_mt7615(&dev->mt76)) 78 return mt7622_init_tx_queues_multi(dev); 79 80 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[0], 0, 81 MT7615_TX_RING_SIZE); 82 if (ret) 83 return ret; 84 85 for (i = 1; i < MT_TXQ_MCU; i++) { 86 q = &dev->mt76.q_tx[i]; 87 INIT_LIST_HEAD(&q->swq); 88 q->q = dev->mt76.q_tx[0].q; 89 } 90 91 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU], 92 MT7615_TXQ_MCU, 93 MT7615_TX_MCU_RING_SIZE); 94 return 0; 95 } 96 97 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 98 struct sk_buff *skb) 99 { 100 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 101 __le32 *rxd = (__le32 *)skb->data; 102 __le32 *end = (__le32 *)&skb->data[skb->len]; 103 enum rx_pkt_type type; 104 105 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 106 107 switch (type) { 108 case PKT_TYPE_TXS: 109 for (rxd++; rxd + 7 <= end; rxd += 7) 110 mt7615_mac_add_txs(dev, rxd); 111 dev_kfree_skb(skb); 112 break; 113 case PKT_TYPE_TXRX_NOTIFY: 114 mt7615_mac_tx_free(dev, skb); 115 break; 116 case PKT_TYPE_RX_EVENT: 117 mt7615_mcu_rx_event(dev, skb); 118 break; 119 case PKT_TYPE_NORMAL: 120 if (!mt7615_mac_fill_rx(dev, skb)) { 121 mt76_rx(&dev->mt76, q, skb); 122 return; 123 } 124 /* fall through */ 125 default: 126 dev_kfree_skb(skb); 127 break; 128 } 129 } 130 131 static void 132 mt7615_tx_cleanup(struct mt7615_dev *dev) 133 { 134 int i; 135 136 mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false); 137 if (is_mt7615(&dev->mt76)) { 138 mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false); 139 } else { 140 for (i = 0; i < IEEE80211_NUM_ACS; i++) 141 mt76_queue_tx_cleanup(dev, i, false); 142 } 143 } 144 145 static int mt7615_poll_tx(struct napi_struct *napi, int budget) 146 { 147 struct mt7615_dev *dev; 148 149 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi); 150 151 mt7615_tx_cleanup(dev); 152 153 if (napi_complete_done(napi, 0)) 154 mt7615_irq_enable(dev, MT_INT_TX_DONE_ALL); 155 156 mt7615_tx_cleanup(dev); 157 158 mt7615_mac_sta_poll(dev); 159 160 tasklet_schedule(&dev->mt76.tx_tasklet); 161 162 return 0; 163 } 164 165 static void mt7622_dma_sched_init(struct mt7615_dev *dev) 166 { 167 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE); 168 int i; 169 170 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE, 171 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE, 172 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | 173 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); 174 175 for (i = 0; i <= 5; i++) 176 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i), 177 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) | 178 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); 179 180 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210); 181 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210); 182 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5); 183 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0); 184 185 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f); 186 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987); 187 } 188 189 int mt7615_dma_init(struct mt7615_dev *dev) 190 { 191 int rx_ring_size = MT7615_RX_RING_SIZE; 192 int ret; 193 194 mt76_dma_attach(&dev->mt76); 195 196 mt76_wr(dev, MT_WPDMA_GLO_CFG, 197 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE | 198 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN | 199 MT_WPDMA_GLO_CFG_OMIT_TX_INFO); 200 201 if (!is_mt7622(&dev->mt76)) 202 mt76_set(dev, MT_WPDMA_GLO_CFG, 203 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY); 204 205 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 206 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1); 207 208 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 209 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1); 210 211 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 212 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3); 213 214 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 215 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3); 216 217 if (is_mt7615(&dev->mt76)) { 218 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1); 219 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000); 220 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000); 221 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026); 222 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881); 223 mt76_set(dev, 0x7158, BIT(16)); 224 mt76_clear(dev, 0x7000, BIT(23)); 225 } 226 227 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); 228 229 ret = mt7615_init_tx_queues(dev); 230 if (ret) 231 return ret; 232 233 /* init rx queues */ 234 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, 235 MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE, 236 MT_RX_RING_BASE); 237 if (ret) 238 return ret; 239 240 if (!is_mt7615(&dev->mt76)) 241 rx_ring_size /= 2; 242 243 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 244 rx_ring_size, MT_RX_BUF_SIZE, MT_RX_RING_BASE); 245 if (ret) 246 return ret; 247 248 mt76_wr(dev, MT_DELAY_INT_CFG, 0); 249 250 ret = mt76_init_queues(dev); 251 if (ret < 0) 252 return ret; 253 254 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 255 mt7615_poll_tx, NAPI_POLL_WEIGHT); 256 napi_enable(&dev->mt76.tx_napi); 257 258 mt76_poll(dev, MT_WPDMA_GLO_CFG, 259 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 260 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000); 261 262 /* start dma engine */ 263 mt76_set(dev, MT_WPDMA_GLO_CFG, 264 MT_WPDMA_GLO_CFG_TX_DMA_EN | 265 MT_WPDMA_GLO_CFG_RX_DMA_EN); 266 267 /* enable interrupts for TX/RX rings */ 268 mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | 269 MT_INT_MCU_CMD); 270 271 if (is_mt7622(&dev->mt76)) 272 mt7622_dma_sched_init(dev); 273 274 return 0; 275 } 276 277 void mt7615_dma_cleanup(struct mt7615_dev *dev) 278 { 279 mt76_clear(dev, MT_WPDMA_GLO_CFG, 280 MT_WPDMA_GLO_CFG_TX_DMA_EN | 281 MT_WPDMA_GLO_CFG_RX_DMA_EN); 282 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 283 284 tasklet_kill(&dev->mt76.tx_tasklet); 285 mt76_dma_cleanup(&dev->mt76); 286 } 287