1 // SPDX-License-Identifier: ISC 2 3 #include <linux/etherdevice.h> 4 #include <linux/timekeeping.h> 5 #include "mt7603.h" 6 #include "mac.h" 7 #include "../trace.h" 8 9 #define MT_PSE_PAGE_SIZE 128 10 11 static u32 12 mt7603_ac_queue_mask0(u32 mask) 13 { 14 u32 ret = 0; 15 16 ret |= GENMASK(3, 0) * !!(mask & BIT(0)); 17 ret |= GENMASK(8, 5) * !!(mask & BIT(1)); 18 ret |= GENMASK(13, 10) * !!(mask & BIT(2)); 19 ret |= GENMASK(19, 16) * !!(mask & BIT(3)); 20 return ret; 21 } 22 23 static void 24 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask) 25 { 26 mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask)); 27 } 28 29 static void 30 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask) 31 { 32 mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask)); 33 } 34 35 void mt7603_mac_reset_counters(struct mt7603_dev *dev) 36 { 37 int i; 38 39 for (i = 0; i < 2; i++) 40 mt76_rr(dev, MT_TX_AGG_CNT(i)); 41 42 memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats)); 43 } 44 45 void mt7603_mac_set_timing(struct mt7603_dev *dev) 46 { 47 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 48 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 49 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 50 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24); 51 int offset = 3 * dev->coverage_class; 52 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 53 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 54 bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ; 55 int sifs; 56 u32 val; 57 58 if (is_5ghz) 59 sifs = 16; 60 else 61 sifs = 10; 62 63 mt76_set(dev, MT_ARB_SCR, 64 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 65 udelay(1); 66 67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); 68 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); 69 mt76_wr(dev, MT_IFS, 70 FIELD_PREP(MT_IFS_EIFS, 360) | 71 FIELD_PREP(MT_IFS_RIFS, 2) | 72 FIELD_PREP(MT_IFS_SIFS, sifs) | 73 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); 74 75 if (dev->slottime < 20 || is_5ghz) 76 val = MT7603_CFEND_RATE_DEFAULT; 77 else 78 val = MT7603_CFEND_RATE_11B; 79 80 mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val); 81 82 mt76_clear(dev, MT_ARB_SCR, 83 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 84 } 85 86 static void 87 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask) 88 { 89 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 90 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 91 92 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 93 } 94 95 static u32 96 mt7603_wtbl1_addr(int idx) 97 { 98 return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 99 } 100 101 static u32 102 mt7603_wtbl2_addr(int idx) 103 { 104 /* Mapped to WTBL2 */ 105 return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE; 106 } 107 108 static u32 109 mt7603_wtbl3_addr(int idx) 110 { 111 u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE); 112 113 return base + idx * MT_WTBL3_SIZE; 114 } 115 116 static u32 117 mt7603_wtbl4_addr(int idx) 118 { 119 u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE); 120 121 return base + idx * MT_WTBL4_SIZE; 122 } 123 124 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, 125 const u8 *mac_addr) 126 { 127 const void *_mac = mac_addr; 128 u32 addr = mt7603_wtbl1_addr(idx); 129 u32 w0 = 0, w1 = 0; 130 int i; 131 132 if (_mac) { 133 w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI, 134 get_unaligned_le16(_mac + 4)); 135 w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO, 136 get_unaligned_le32(_mac)); 137 } 138 139 if (vif < 0) 140 vif = 0; 141 else 142 w0 |= MT_WTBL1_W0_RX_CHECK_A1; 143 w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif); 144 145 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 146 147 mt76_set(dev, addr + 0 * 4, w0); 148 mt76_set(dev, addr + 1 * 4, w1); 149 mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL); 150 151 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 152 addr = mt7603_wtbl2_addr(idx); 153 for (i = 0; i < MT_WTBL2_SIZE; i += 4) 154 mt76_wr(dev, addr + i, 0); 155 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 156 mt76_start_tx_ac(dev, GENMASK(3, 0)); 157 158 addr = mt7603_wtbl3_addr(idx); 159 for (i = 0; i < MT_WTBL3_SIZE; i += 4) 160 mt76_wr(dev, addr + i, 0); 161 162 addr = mt7603_wtbl4_addr(idx); 163 for (i = 0; i < MT_WTBL4_SIZE; i += 4) 164 mt76_wr(dev, addr + i, 0); 165 166 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 167 } 168 169 static void 170 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled) 171 { 172 u32 addr = mt7603_wtbl1_addr(idx); 173 u32 val = mt76_rr(dev, addr + 3 * 4); 174 175 val &= ~MT_WTBL1_W3_SKIP_TX; 176 val |= enabled * MT_WTBL1_W3_SKIP_TX; 177 178 mt76_wr(dev, addr + 3 * 4, val); 179 } 180 181 void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort) 182 { 183 u32 flush_mask; 184 int i, port, queue; 185 186 if (abort) { 187 port = 3; /* PSE */ 188 queue = 8; /* free queue */ 189 } else { 190 port = 0; /* HIF */ 191 queue = 1; /* MCU queue */ 192 } 193 194 mt7603_wtbl_set_skip_tx(dev, idx, true); 195 196 mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN | 197 FIELD_PREP(MT_TX_ABORT_WCID, idx)); 198 199 flush_mask = MT_WF_ARB_TX_FLUSH_AC0 | 200 MT_WF_ARB_TX_FLUSH_AC1 | 201 MT_WF_ARB_TX_FLUSH_AC2 | 202 MT_WF_ARB_TX_FLUSH_AC3; 203 flush_mask <<= mac_idx; 204 205 mt76_wr(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask); 206 mt76_poll(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask, 0, 20000); 207 mt76_wr(dev, MT_WF_ARB_TX_START_0, flush_mask); 208 209 mt76_wr(dev, MT_TX_ABORT, 0); 210 211 for (i = 0; i < 4; i++) { 212 mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY | 213 FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) | 214 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) | 215 FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) | 216 FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue)); 217 218 mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000); 219 } 220 221 WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY); 222 223 mt7603_wtbl_set_skip_tx(dev, idx, false); 224 } 225 226 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta, 227 bool enabled) 228 { 229 u32 addr = mt7603_wtbl1_addr(sta->wcid.idx); 230 231 if (sta->smps == enabled) 232 return; 233 234 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled); 235 sta->smps = enabled; 236 } 237 238 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta, 239 bool enabled) 240 { 241 int idx = sta->wcid.idx; 242 u32 addr; 243 244 spin_lock_bh(&dev->ps_lock); 245 246 if (sta->ps == enabled) 247 goto out; 248 249 mt76_wr(dev, MT_PSE_RTA, 250 FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) | 251 FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) | 252 FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) | 253 FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) | 254 MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY); 255 256 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); 257 258 if (enabled) 259 mt7603_filter_tx(dev, sta->vif->idx, idx, false); 260 261 addr = mt7603_wtbl1_addr(idx); 262 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 263 mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE, 264 enabled * MT_WTBL1_W3_POWER_SAVE); 265 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 266 sta->ps = enabled; 267 268 out: 269 spin_unlock_bh(&dev->ps_lock); 270 } 271 272 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx) 273 { 274 int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE; 275 int wtbl2_frame = idx / wtbl2_frame_size; 276 int wtbl2_entry = idx % wtbl2_frame_size; 277 278 int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE; 279 int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE; 280 int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size; 281 int wtbl3_entry = (idx % wtbl3_frame_size) * 2; 282 283 int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE; 284 int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE; 285 int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size; 286 int wtbl4_entry = idx % wtbl4_frame_size; 287 288 u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 289 int i; 290 291 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 292 293 mt76_wr(dev, addr + 0 * 4, 294 MT_WTBL1_W0_RX_CHECK_A1 | 295 MT_WTBL1_W0_RX_CHECK_A2 | 296 MT_WTBL1_W0_RX_VALID); 297 mt76_wr(dev, addr + 1 * 4, 0); 298 mt76_wr(dev, addr + 2 * 4, 0); 299 300 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 301 302 mt76_wr(dev, addr + 3 * 4, 303 FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) | 304 FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) | 305 FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) | 306 MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM); 307 mt76_wr(dev, addr + 4 * 4, 308 FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) | 309 FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) | 310 FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry)); 311 312 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 313 314 addr = mt7603_wtbl2_addr(idx); 315 316 /* Clear BA information */ 317 mt76_wr(dev, addr + (15 * 4), 0); 318 319 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 320 for (i = 2; i <= 4; i++) 321 mt76_wr(dev, addr + (i * 4), 0); 322 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 323 mt76_start_tx_ac(dev, GENMASK(3, 0)); 324 325 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR); 326 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR); 327 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 328 } 329 330 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta) 331 { 332 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 333 int idx = msta->wcid.idx; 334 u8 ampdu_density; 335 u32 addr; 336 u32 val; 337 338 addr = mt7603_wtbl1_addr(idx); 339 340 ampdu_density = sta->deflink.ht_cap.ampdu_density; 341 if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4) 342 ampdu_density = IEEE80211_HT_MPDU_DENSITY_4; 343 344 val = mt76_rr(dev, addr + 2 * 4); 345 val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL; 346 val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, 347 sta->deflink.ht_cap.ampdu_factor) | 348 FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, 349 sta->deflink.ht_cap.ampdu_density) | 350 MT_WTBL1_W2_TXS_BAF_REPORT; 351 352 if (sta->deflink.ht_cap.cap) 353 val |= MT_WTBL1_W2_HT; 354 if (sta->deflink.vht_cap.cap) 355 val |= MT_WTBL1_W2_VHT; 356 357 mt76_wr(dev, addr + 2 * 4, val); 358 359 addr = mt7603_wtbl2_addr(idx); 360 val = mt76_rr(dev, addr + 9 * 4); 361 val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 362 MT_WTBL2_W9_SHORT_GI_80); 363 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) 364 val |= MT_WTBL2_W9_SHORT_GI_20; 365 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 366 val |= MT_WTBL2_W9_SHORT_GI_40; 367 mt76_wr(dev, addr + 9 * 4, val); 368 } 369 370 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid) 371 { 372 mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr)); 373 mt76_wr(dev, MT_BA_CONTROL_1, 374 (get_unaligned_le16(addr + 4) | 375 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) | 376 MT_BA_CONTROL_1_RESET)); 377 } 378 379 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, 380 int ba_size) 381 { 382 u32 addr = mt7603_wtbl2_addr(wcid); 383 u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 384 (MT_WTBL2_W15_BA_WIN_SIZE << 385 (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT)); 386 u32 tid_val; 387 int i; 388 389 if (ba_size < 0) { 390 /* disable */ 391 mt76_clear(dev, addr + (15 * 4), tid_mask); 392 return; 393 } 394 395 for (i = 7; i > 0; i--) { 396 if (ba_size >= MT_AGG_SIZE_LIMIT(i)) 397 break; 398 } 399 400 tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 401 i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT); 402 403 mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val); 404 } 405 406 void mt7603_mac_sta_poll(struct mt7603_dev *dev) 407 { 408 static const u8 ac_to_tid[4] = { 409 [IEEE80211_AC_BE] = 0, 410 [IEEE80211_AC_BK] = 1, 411 [IEEE80211_AC_VI] = 4, 412 [IEEE80211_AC_VO] = 6 413 }; 414 struct ieee80211_sta *sta; 415 struct mt7603_sta *msta; 416 u32 total_airtime = 0; 417 u32 airtime[4]; 418 u32 addr; 419 int i; 420 421 rcu_read_lock(); 422 423 while (1) { 424 bool clear = false; 425 426 spin_lock_bh(&dev->mt76.sta_poll_lock); 427 if (list_empty(&dev->mt76.sta_poll_list)) { 428 spin_unlock_bh(&dev->mt76.sta_poll_lock); 429 break; 430 } 431 432 msta = list_first_entry(&dev->mt76.sta_poll_list, 433 struct mt7603_sta, wcid.poll_list); 434 list_del_init(&msta->wcid.poll_list); 435 spin_unlock_bh(&dev->mt76.sta_poll_lock); 436 437 addr = mt7603_wtbl4_addr(msta->wcid.idx); 438 for (i = 0; i < 4; i++) { 439 u32 airtime_last = msta->tx_airtime_ac[i]; 440 441 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8); 442 airtime[i] = msta->tx_airtime_ac[i] - airtime_last; 443 airtime[i] *= 32; 444 total_airtime += airtime[i]; 445 446 if (msta->tx_airtime_ac[i] & BIT(22)) 447 clear = true; 448 } 449 450 if (clear) { 451 mt7603_wtbl_update(dev, msta->wcid.idx, 452 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 453 memset(msta->tx_airtime_ac, 0, 454 sizeof(msta->tx_airtime_ac)); 455 } 456 457 if (!msta->wcid.sta) 458 continue; 459 460 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 461 for (i = 0; i < 4; i++) { 462 struct mt76_queue *q = dev->mphy.q_tx[i]; 463 u8 qidx = q->hw_idx; 464 u8 tid = ac_to_tid[i]; 465 u32 txtime = airtime[qidx]; 466 467 if (!txtime) 468 continue; 469 470 ieee80211_sta_register_airtime(sta, tid, txtime, 0); 471 } 472 } 473 474 rcu_read_unlock(); 475 476 if (!total_airtime) 477 return; 478 479 spin_lock_bh(&dev->mt76.cc_lock); 480 dev->mphy.chan_state->cc_tx += total_airtime; 481 spin_unlock_bh(&dev->mt76.cc_lock); 482 } 483 484 static struct mt76_wcid * 485 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast) 486 { 487 struct mt7603_sta *sta; 488 struct mt76_wcid *wcid; 489 490 wcid = mt76_wcid_ptr(dev, idx); 491 if (unicast || !wcid) 492 return wcid; 493 494 if (!wcid->sta) 495 return NULL; 496 497 sta = container_of(wcid, struct mt7603_sta, wcid); 498 if (!sta->vif) 499 return NULL; 500 501 return &sta->vif->sta.wcid; 502 } 503 504 int 505 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb) 506 { 507 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 508 struct ieee80211_supported_band *sband; 509 struct ieee80211_hdr *hdr; 510 __le32 *rxd = (__le32 *)skb->data; 511 u32 rxd0 = le32_to_cpu(rxd[0]); 512 u32 rxd1 = le32_to_cpu(rxd[1]); 513 u32 rxd2 = le32_to_cpu(rxd[2]); 514 bool unicast = rxd1 & MT_RXD1_NORMAL_U2M; 515 bool insert_ccmp_hdr = false; 516 bool remove_pad; 517 int idx; 518 int i; 519 520 memset(status, 0, sizeof(*status)); 521 522 i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 523 sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband; 524 i >>= 1; 525 526 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 527 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast); 528 529 status->band = sband->band; 530 if (i < sband->n_channels) 531 status->freq = sband->channels[i].center_freq; 532 533 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 534 status->flag |= RX_FLAG_FAILED_FCS_CRC; 535 536 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 537 status->flag |= RX_FLAG_MMIC_ERROR; 538 539 /* ICV error or CCMP/BIP/WPI MIC error */ 540 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR) 541 status->flag |= RX_FLAG_ONLY_MONITOR; 542 543 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 544 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 545 status->flag |= RX_FLAG_DECRYPTED; 546 status->flag |= RX_FLAG_IV_STRIPPED; 547 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 548 } 549 550 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 551 552 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 553 return -EINVAL; 554 555 if (!sband->channels) 556 return -EINVAL; 557 558 rxd += 4; 559 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 560 rxd += 4; 561 if ((u8 *)rxd - skb->data >= skb->len) 562 return -EINVAL; 563 } 564 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 565 u8 *data = (u8 *)rxd; 566 567 if (status->flag & RX_FLAG_DECRYPTED) { 568 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 569 case MT_CIPHER_AES_CCMP: 570 case MT_CIPHER_CCMP_CCX: 571 case MT_CIPHER_CCMP_256: 572 insert_ccmp_hdr = 573 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 574 fallthrough; 575 case MT_CIPHER_TKIP: 576 case MT_CIPHER_TKIP_NO_MIC: 577 case MT_CIPHER_GCMP: 578 case MT_CIPHER_GCMP_256: 579 status->iv[0] = data[5]; 580 status->iv[1] = data[4]; 581 status->iv[2] = data[3]; 582 status->iv[3] = data[2]; 583 status->iv[4] = data[1]; 584 status->iv[5] = data[0]; 585 break; 586 default: 587 break; 588 } 589 } 590 591 rxd += 4; 592 if ((u8 *)rxd - skb->data >= skb->len) 593 return -EINVAL; 594 } 595 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 596 status->timestamp = le32_to_cpu(rxd[0]); 597 status->flag |= RX_FLAG_MACTIME_START; 598 599 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 600 MT_RXD2_NORMAL_NON_AMPDU))) { 601 status->flag |= RX_FLAG_AMPDU_DETAILS; 602 603 /* all subframes of an A-MPDU have the same timestamp */ 604 if (dev->rx_ampdu_ts != status->timestamp) { 605 if (!++dev->ampdu_ref) 606 dev->ampdu_ref++; 607 } 608 dev->rx_ampdu_ts = status->timestamp; 609 610 status->ampdu_ref = dev->ampdu_ref; 611 } 612 613 rxd += 2; 614 if ((u8 *)rxd - skb->data >= skb->len) 615 return -EINVAL; 616 } 617 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 618 u32 rxdg0 = le32_to_cpu(rxd[0]); 619 u32 rxdg3 = le32_to_cpu(rxd[3]); 620 bool cck = false; 621 622 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 623 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 624 case MT_PHY_TYPE_CCK: 625 cck = true; 626 fallthrough; 627 case MT_PHY_TYPE_OFDM: 628 i = mt76_get_rate(&dev->mt76, sband, i, cck); 629 break; 630 case MT_PHY_TYPE_HT_GF: 631 case MT_PHY_TYPE_HT: 632 status->encoding = RX_ENC_HT; 633 if (i > 15) 634 return -EINVAL; 635 break; 636 default: 637 return -EINVAL; 638 } 639 640 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 641 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 642 if (rxdg0 & MT_RXV1_HT_AD_CODE) 643 status->enc_flags |= RX_ENC_FLAG_LDPC; 644 645 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * 646 FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 647 648 status->rate_idx = i; 649 650 status->chains = dev->mphy.antenna_mask; 651 status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) + 652 dev->rssi_offset[0]; 653 status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) + 654 dev->rssi_offset[1]; 655 656 if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1) 657 status->bw = RATE_INFO_BW_40; 658 659 rxd += 6; 660 if ((u8 *)rxd - skb->data >= skb->len) 661 return -EINVAL; 662 } else { 663 return -EINVAL; 664 } 665 666 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 667 668 if (insert_ccmp_hdr) { 669 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 670 671 mt76_insert_ccmp_hdr(skb, key_id); 672 } 673 674 hdr = (struct ieee80211_hdr *)skb->data; 675 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control)) 676 return 0; 677 678 status->aggr = unicast && 679 !ieee80211_is_qos_nullfunc(hdr->frame_control); 680 status->qos_ctl = *ieee80211_get_qos_ctl(hdr); 681 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 682 683 return 0; 684 } 685 686 static u16 687 mt7603_mac_tx_rate_val(struct mt7603_dev *dev, 688 const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw) 689 { 690 u8 phy, nss, rate_idx; 691 u16 rateval; 692 693 *bw = 0; 694 if (rate->flags & IEEE80211_TX_RC_MCS) { 695 rate_idx = rate->idx; 696 nss = 1 + (rate->idx >> 3); 697 phy = MT_PHY_TYPE_HT; 698 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 699 phy = MT_PHY_TYPE_HT_GF; 700 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 701 *bw = 1; 702 } else { 703 const struct ieee80211_rate *r; 704 int band = dev->mphy.chandef.chan->band; 705 u16 val; 706 707 nss = 1; 708 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx]; 709 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 710 val = r->hw_value_short; 711 else 712 val = r->hw_value; 713 714 phy = val >> 8; 715 rate_idx = val & 0xff; 716 } 717 718 rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 719 FIELD_PREP(MT_TX_RATE_MODE, phy)); 720 721 if (stbc && nss == 1) 722 rateval |= MT_TX_RATE_STBC; 723 724 return rateval; 725 } 726 727 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta, 728 struct ieee80211_tx_rate *probe_rate, 729 struct ieee80211_tx_rate *rates) 730 { 731 struct ieee80211_tx_rate *ref; 732 int wcid = sta->wcid.idx; 733 u32 addr = mt7603_wtbl2_addr(wcid); 734 bool stbc = false; 735 int n_rates = sta->n_rates; 736 u8 bw, bw_prev, bw_idx = 0; 737 u16 val[4]; 738 u16 probe_val; 739 u32 w9 = mt76_rr(dev, addr + 9 * 4); 740 bool rateset; 741 int i, k; 742 743 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 744 return; 745 746 for (i = n_rates; i < 4; i++) 747 rates[i] = rates[n_rates - 1]; 748 749 rateset = !(sta->rate_set_tsf & BIT(0)); 750 memcpy(sta->rateset[rateset].rates, rates, 751 sizeof(sta->rateset[rateset].rates)); 752 if (probe_rate) { 753 sta->rateset[rateset].probe_rate = *probe_rate; 754 ref = &sta->rateset[rateset].probe_rate; 755 } else { 756 sta->rateset[rateset].probe_rate.idx = -1; 757 ref = &sta->rateset[rateset].rates[0]; 758 } 759 760 rates = sta->rateset[rateset].rates; 761 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 762 /* 763 * We don't support switching between short and long GI 764 * within the rate set. For accurate tx status reporting, we 765 * need to make sure that flags match. 766 * For improved performance, avoid duplicate entries by 767 * decrementing the MCS index if necessary 768 */ 769 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 770 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 771 772 for (k = 0; k < i; k++) { 773 if (rates[i].idx != rates[k].idx) 774 continue; 775 if ((rates[i].flags ^ rates[k].flags) & 776 IEEE80211_TX_RC_40_MHZ_WIDTH) 777 continue; 778 779 if (!rates[i].idx) 780 continue; 781 782 rates[i].idx--; 783 } 784 } 785 786 w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 787 MT_WTBL2_W9_SHORT_GI_80; 788 789 val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); 790 bw_prev = bw; 791 792 if (probe_rate) { 793 probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw); 794 if (bw) 795 bw_idx = 1; 796 else 797 bw_prev = 0; 798 } else { 799 probe_val = val[0]; 800 } 801 802 w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw); 803 w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw); 804 805 val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); 806 if (bw_prev) { 807 bw_idx = 3; 808 bw_prev = bw; 809 } 810 811 val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); 812 if (bw_prev) { 813 bw_idx = 5; 814 bw_prev = bw; 815 } 816 817 val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); 818 if (bw_prev) 819 bw_idx = 7; 820 821 w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE, 822 bw_idx ? bw_idx - 1 : 7); 823 824 mt76_wr(dev, MT_WTBL_RIUCR0, w9); 825 826 mt76_wr(dev, MT_WTBL_RIUCR1, 827 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) | 828 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) | 829 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1])); 830 831 mt76_wr(dev, MT_WTBL_RIUCR2, 832 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) | 833 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) | 834 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) | 835 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2])); 836 837 mt76_wr(dev, MT_WTBL_RIUCR3, 838 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) | 839 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) | 840 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3])); 841 842 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */ 843 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; 844 845 mt76_wr(dev, MT_WTBL_UPDATE, 846 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 847 MT_WTBL_UPDATE_RATE_UPDATE | 848 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 849 850 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 851 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 852 853 sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates; 854 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 855 } 856 857 static enum mt76_cipher_type 858 mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 859 { 860 memset(key_data, 0, 32); 861 if (!key) 862 return MT_CIPHER_NONE; 863 864 if (key->keylen > 32) 865 return MT_CIPHER_NONE; 866 867 memcpy(key_data, key->key, key->keylen); 868 869 switch (key->cipher) { 870 case WLAN_CIPHER_SUITE_WEP40: 871 return MT_CIPHER_WEP40; 872 case WLAN_CIPHER_SUITE_WEP104: 873 return MT_CIPHER_WEP104; 874 case WLAN_CIPHER_SUITE_TKIP: 875 /* Rx/Tx MIC keys are swapped */ 876 memcpy(key_data + 16, key->key + 24, 8); 877 memcpy(key_data + 24, key->key + 16, 8); 878 return MT_CIPHER_TKIP; 879 case WLAN_CIPHER_SUITE_CCMP: 880 return MT_CIPHER_AES_CCMP; 881 default: 882 return MT_CIPHER_NONE; 883 } 884 } 885 886 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid, 887 struct ieee80211_key_conf *key) 888 { 889 enum mt76_cipher_type cipher; 890 u32 addr = mt7603_wtbl3_addr(wcid); 891 u8 key_data[32]; 892 int key_len = sizeof(key_data); 893 894 cipher = mt7603_mac_get_key_info(key, key_data); 895 if (cipher == MT_CIPHER_NONE && key) 896 return -EOPNOTSUPP; 897 898 if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) { 899 addr += key->keyidx * 16; 900 key_len = 16; 901 } 902 903 mt76_wr_copy(dev, addr, key_data, key_len); 904 905 addr = mt7603_wtbl1_addr(wcid); 906 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher); 907 if (key) 908 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx); 909 mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key); 910 911 return 0; 912 } 913 914 static int 915 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi, 916 struct sk_buff *skb, enum mt76_txq_id qid, 917 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 918 int pid, struct ieee80211_key_conf *key) 919 { 920 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 921 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 922 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 923 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data; 924 struct ieee80211_vif *vif = info->control.vif; 925 struct mt76_queue *q = dev->mphy.q_tx[qid]; 926 struct mt7603_vif *mvif; 927 int wlan_idx; 928 int hdr_len = ieee80211_get_hdrlen_from_skb(skb); 929 int tx_count = 8; 930 u8 frame_type, frame_subtype; 931 u16 fc = le16_to_cpu(hdr->frame_control); 932 u16 seqno = 0; 933 u8 vif_idx = 0; 934 u32 val; 935 u8 bw; 936 937 if (vif) { 938 mvif = (struct mt7603_vif *)vif->drv_priv; 939 vif_idx = mvif->idx; 940 if (vif_idx && qid >= MT_TXQ_BEACON) 941 vif_idx += 0x10; 942 } 943 944 if (sta) { 945 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 946 947 tx_count = msta->rate_count; 948 } 949 950 if (wcid) 951 wlan_idx = wcid->idx; 952 else 953 wlan_idx = MT7603_WTBL_RESERVED; 954 955 frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2; 956 frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4; 957 958 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 959 FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx); 960 txwi[0] = cpu_to_le32(val); 961 962 val = MT_TXD1_LONG_FORMAT | 963 FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) | 964 FIELD_PREP(MT_TXD1_TID, 965 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 966 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 967 FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) | 968 FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) | 969 FIELD_PREP(MT_TXD1_PROTECTED, !!key); 970 txwi[1] = cpu_to_le32(val); 971 972 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 973 txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK); 974 975 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) | 976 FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) | 977 FIELD_PREP(MT_TXD2_MULTICAST, 978 is_multicast_ether_addr(hdr->addr1)); 979 txwi[2] = cpu_to_le32(val); 980 981 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 982 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 983 984 txwi[4] = 0; 985 986 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT | 987 FIELD_PREP(MT_TXD5_PID, pid); 988 txwi[5] = cpu_to_le32(val); 989 990 txwi[6] = 0; 991 992 if (rate->idx >= 0 && rate->count && 993 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 994 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 995 u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw); 996 997 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 998 999 val = MT_TXD6_FIXED_BW | 1000 FIELD_PREP(MT_TXD6_BW, bw) | 1001 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 1002 txwi[6] |= cpu_to_le32(val); 1003 1004 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 1005 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 1006 1007 if (!(rate->flags & IEEE80211_TX_RC_MCS)) 1008 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 1009 1010 tx_count = rate->count; 1011 } 1012 1013 /* use maximum tx count for beacons and buffered multicast */ 1014 if (qid >= MT_TXQ_BEACON) 1015 tx_count = 0x1f; 1016 1017 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) | 1018 MT_TXD3_SN_VALID; 1019 1020 if (ieee80211_is_data_qos(hdr->frame_control)) 1021 seqno = le16_to_cpu(hdr->seq_ctrl); 1022 else if (ieee80211_is_back_req(hdr->frame_control)) 1023 seqno = le16_to_cpu(bar->start_seq_num); 1024 else 1025 val &= ~MT_TXD3_SN_VALID; 1026 1027 val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4); 1028 1029 txwi[3] = cpu_to_le32(val); 1030 1031 if (key) { 1032 u64 pn = atomic64_inc_return(&key->tx_pn); 1033 1034 txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID); 1035 txwi[4] = cpu_to_le32(pn & GENMASK(31, 0)); 1036 txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32)); 1037 } 1038 1039 txwi[7] = 0; 1040 1041 return 0; 1042 } 1043 1044 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1045 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1046 struct ieee80211_sta *sta, 1047 struct mt76_tx_info *tx_info) 1048 { 1049 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1050 struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid); 1051 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1052 struct ieee80211_key_conf *key = info->control.hw_key; 1053 int pid; 1054 1055 if (!wcid) 1056 wcid = &dev->global_sta.wcid; 1057 1058 if (sta) { 1059 msta = (struct mt7603_sta *)sta->drv_priv; 1060 1061 if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER | 1062 IEEE80211_TX_CTL_CLEAR_PS_FILT)) || 1063 (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) 1064 mt7603_wtbl_set_ps(dev, msta, false); 1065 1066 mt76_tx_check_agg_ssn(sta, tx_info->skb); 1067 } 1068 1069 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1070 1071 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) { 1072 spin_lock_bh(&dev->mt76.lock); 1073 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0], 1074 msta->rates); 1075 msta->rate_probe = true; 1076 spin_unlock_bh(&dev->mt76.lock); 1077 } 1078 1079 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid, 1080 sta, pid, key); 1081 1082 return 0; 1083 } 1084 1085 static bool 1086 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta, 1087 struct ieee80211_tx_info *info, __le32 *txs_data) 1088 { 1089 struct ieee80211_supported_band *sband; 1090 struct mt7603_rate_set *rs; 1091 int first_idx = 0, last_idx; 1092 u32 rate_set_tsf; 1093 u32 final_rate; 1094 u32 final_rate_flags; 1095 bool rs_idx; 1096 bool ack_timeout; 1097 bool fixed_rate; 1098 bool probe; 1099 bool ampdu; 1100 bool cck = false; 1101 int count; 1102 u32 txs; 1103 int idx; 1104 int i; 1105 1106 fixed_rate = info->status.rates[0].count; 1107 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1108 1109 txs = le32_to_cpu(txs_data[4]); 1110 ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU); 1111 count = FIELD_GET(MT_TXS4_TX_COUNT, txs); 1112 last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs); 1113 1114 txs = le32_to_cpu(txs_data[0]); 1115 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1116 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1117 1118 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1119 return false; 1120 1121 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1122 return false; 1123 1124 if (!ack_timeout) 1125 info->flags |= IEEE80211_TX_STAT_ACK; 1126 1127 info->status.ampdu_len = 1; 1128 info->status.ampdu_ack_len = !!(info->flags & 1129 IEEE80211_TX_STAT_ACK); 1130 1131 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1132 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1133 1134 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY); 1135 1136 if (fixed_rate && !probe) { 1137 info->status.rates[0].count = count; 1138 i = 0; 1139 goto out; 1140 } 1141 1142 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1143 rs_idx = !((u32)(le32_get_bits(txs_data[1], MT_TXS1_F0_TIMESTAMP) - 1144 rate_set_tsf) < 1000000); 1145 rs_idx ^= rate_set_tsf & BIT(0); 1146 rs = &sta->rateset[rs_idx]; 1147 1148 if (!first_idx && rs->probe_rate.idx >= 0) { 1149 info->status.rates[0] = rs->probe_rate; 1150 1151 spin_lock_bh(&dev->mt76.lock); 1152 if (sta->rate_probe) { 1153 mt7603_wtbl_set_rates(dev, sta, NULL, 1154 sta->rates); 1155 sta->rate_probe = false; 1156 } 1157 spin_unlock_bh(&dev->mt76.lock); 1158 } else { 1159 info->status.rates[0] = rs->rates[first_idx / 2]; 1160 } 1161 info->status.rates[0].count = 0; 1162 1163 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1164 struct ieee80211_tx_rate *cur_rate; 1165 int cur_count; 1166 1167 cur_rate = &rs->rates[idx / 2]; 1168 cur_count = min_t(int, MT7603_RATE_RETRY, count); 1169 count -= cur_count; 1170 1171 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1172 cur_rate->flags != info->status.rates[i].flags)) { 1173 i++; 1174 if (i == ARRAY_SIZE(info->status.rates)) { 1175 i--; 1176 break; 1177 } 1178 1179 info->status.rates[i] = *cur_rate; 1180 info->status.rates[i].count = 0; 1181 } 1182 1183 info->status.rates[i].count += cur_count; 1184 } 1185 1186 out: 1187 final_rate_flags = info->status.rates[i].flags; 1188 1189 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1190 case MT_PHY_TYPE_CCK: 1191 cck = true; 1192 fallthrough; 1193 case MT_PHY_TYPE_OFDM: 1194 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) 1195 sband = &dev->mphy.sband_5g.sband; 1196 else 1197 sband = &dev->mphy.sband_2g.sband; 1198 final_rate &= GENMASK(5, 0); 1199 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1200 cck); 1201 final_rate_flags = 0; 1202 break; 1203 case MT_PHY_TYPE_HT_GF: 1204 case MT_PHY_TYPE_HT: 1205 final_rate_flags |= IEEE80211_TX_RC_MCS; 1206 final_rate &= GENMASK(5, 0); 1207 if (final_rate > 15) 1208 return false; 1209 break; 1210 default: 1211 return false; 1212 } 1213 1214 info->status.rates[i].idx = final_rate; 1215 info->status.rates[i].flags = final_rate_flags; 1216 1217 return true; 1218 } 1219 1220 static bool 1221 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid, 1222 __le32 *txs_data) 1223 { 1224 struct mt76_dev *mdev = &dev->mt76; 1225 struct sk_buff_head list; 1226 struct sk_buff *skb; 1227 1228 if (pid < MT_PACKET_ID_FIRST) 1229 return false; 1230 1231 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1232 1233 mt76_tx_status_lock(mdev, &list); 1234 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1235 if (skb) { 1236 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1237 1238 if (!mt7603_fill_txs(dev, sta, info, txs_data)) { 1239 info->status.rates[0].count = 0; 1240 info->status.rates[0].idx = -1; 1241 } 1242 1243 mt76_tx_status_skb_done(mdev, skb, &list); 1244 } 1245 mt76_tx_status_unlock(mdev, &list); 1246 1247 return !!skb; 1248 } 1249 1250 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data) 1251 { 1252 struct ieee80211_tx_info info = {}; 1253 struct ieee80211_sta *sta = NULL; 1254 struct mt7603_sta *msta = NULL; 1255 struct mt76_wcid *wcid; 1256 __le32 *txs_data = data; 1257 u8 wcidx; 1258 u8 pid; 1259 1260 pid = le32_get_bits(txs_data[4], MT_TXS4_PID); 1261 wcidx = le32_get_bits(txs_data[3], MT_TXS3_WCID); 1262 1263 if (pid == MT_PACKET_ID_NO_ACK) 1264 return; 1265 1266 rcu_read_lock(); 1267 1268 wcid = mt76_wcid_ptr(dev, wcidx); 1269 if (!wcid) 1270 goto out; 1271 1272 msta = container_of(wcid, struct mt7603_sta, wcid); 1273 sta = wcid_to_sta(wcid); 1274 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1275 1276 if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data)) 1277 goto out; 1278 1279 if (wcidx >= MT7603_WTBL_STA || !sta) 1280 goto out; 1281 1282 if (mt7603_fill_txs(dev, msta, &info, txs_data)) { 1283 spin_lock_bh(&dev->mt76.rx_lock); 1284 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info); 1285 spin_unlock_bh(&dev->mt76.rx_lock); 1286 } 1287 1288 out: 1289 rcu_read_unlock(); 1290 } 1291 1292 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 1293 { 1294 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1295 struct sk_buff *skb = e->skb; 1296 1297 if (!e->txwi) { 1298 dev_kfree_skb_any(skb); 1299 return; 1300 } 1301 1302 dev->tx_hang_check = 0; 1303 mt76_tx_complete_skb(mdev, e->wcid, skb); 1304 } 1305 1306 static bool 1307 wait_for_wpdma(struct mt7603_dev *dev) 1308 { 1309 return mt76_poll(dev, MT_WPDMA_GLO_CFG, 1310 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 1311 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 1312 0, 1000); 1313 } 1314 1315 static void mt7603_pse_reset(struct mt7603_dev *dev) 1316 { 1317 /* Clear previous reset result */ 1318 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) 1319 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S); 1320 1321 /* Reset PSE */ 1322 mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1323 1324 if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET, 1325 MT_MCU_DEBUG_RESET_PSE_S, 1326 MT_MCU_DEBUG_RESET_PSE_S, 500)) { 1327 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++; 1328 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1329 } else { 1330 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1331 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES); 1332 } 1333 1334 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3) 1335 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1336 } 1337 1338 void mt7603_mac_dma_start(struct mt7603_dev *dev) 1339 { 1340 mt7603_mac_start(dev); 1341 1342 wait_for_wpdma(dev); 1343 usleep_range(50, 100); 1344 1345 mt76_set(dev, MT_WPDMA_GLO_CFG, 1346 (MT_WPDMA_GLO_CFG_TX_DMA_EN | 1347 MT_WPDMA_GLO_CFG_RX_DMA_EN | 1348 FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) | 1349 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE)); 1350 1351 mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL); 1352 } 1353 1354 void mt7603_mac_start(struct mt7603_dev *dev) 1355 { 1356 mt76_clear(dev, MT_ARB_SCR, 1357 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1358 mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0); 1359 mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1360 } 1361 1362 void mt7603_mac_stop(struct mt7603_dev *dev) 1363 { 1364 mt76_set(dev, MT_ARB_SCR, 1365 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1366 mt76_wr(dev, MT_WF_ARB_TX_START_0, 0); 1367 mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1368 } 1369 1370 void mt7603_pse_client_reset(struct mt7603_dev *dev) 1371 { 1372 u32 addr; 1373 1374 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + 1375 MT_CLIENT_RESET_TX); 1376 1377 /* Clear previous reset state */ 1378 mt76_clear(dev, addr, 1379 MT_CLIENT_RESET_TX_R_E_1 | 1380 MT_CLIENT_RESET_TX_R_E_2 | 1381 MT_CLIENT_RESET_TX_R_E_1_S | 1382 MT_CLIENT_RESET_TX_R_E_2_S); 1383 1384 /* Start PSE client TX abort */ 1385 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF); 1386 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1); 1387 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S, 1388 MT_CLIENT_RESET_TX_R_E_1_S, 500); 1389 1390 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2); 1391 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 1392 1393 /* Wait for PSE client to clear TX FIFO */ 1394 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S, 1395 MT_CLIENT_RESET_TX_R_E_2_S, 500); 1396 1397 /* Clear PSE client TX abort state */ 1398 mt76_clear(dev, addr, 1399 MT_CLIENT_RESET_TX_R_E_1 | 1400 MT_CLIENT_RESET_TX_R_E_2); 1401 } 1402 1403 static void mt7603_dma_sched_reset(struct mt7603_dev *dev) 1404 { 1405 if (!is_mt7628(dev)) 1406 return; 1407 1408 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET); 1409 mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET); 1410 } 1411 1412 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev) 1413 { 1414 int beacon_int = dev->mt76.beacon_int; 1415 u32 mask = dev->mt76.mmio.irqmask; 1416 int i; 1417 1418 ieee80211_stop_queues(dev->mt76.hw); 1419 set_bit(MT76_RESET, &dev->mphy.state); 1420 1421 /* lock/unlock all queues to ensure that no tx is pending */ 1422 mt76_txq_schedule_all(&dev->mphy); 1423 1424 mt76_worker_disable(&dev->mt76.tx_worker); 1425 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 1426 napi_disable(&dev->mt76.napi[0]); 1427 napi_disable(&dev->mt76.napi[1]); 1428 napi_disable(&dev->mt76.tx_napi); 1429 1430 mutex_lock(&dev->mt76.mutex); 1431 1432 mt7603_beacon_set_timer(dev, -1, 0); 1433 1434 mt7603_mac_stop(dev); 1435 1436 mt76_clear(dev, MT_WPDMA_GLO_CFG, 1437 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN | 1438 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 1439 usleep_range(1000, 2000); 1440 1441 mt7603_irq_disable(dev, mask); 1442 1443 mt7603_pse_client_reset(dev); 1444 1445 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true); 1446 for (i = 0; i < __MT_TXQ_MAX; i++) 1447 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 1448 1449 mt7603_dma_sched_reset(dev); 1450 1451 mt76_tx_status_check(&dev->mt76, true); 1452 1453 mt76_for_each_q_rx(&dev->mt76, i) { 1454 mt76_queue_rx_reset(dev, i); 1455 } 1456 1457 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] || 1458 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY) 1459 mt7603_pse_reset(dev); 1460 1461 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { 1462 mt7603_mac_dma_start(dev); 1463 1464 mt7603_irq_enable(dev, mask); 1465 1466 clear_bit(MT76_RESET, &dev->mphy.state); 1467 } 1468 1469 mutex_unlock(&dev->mt76.mutex); 1470 1471 mt76_worker_enable(&dev->mt76.tx_worker); 1472 1473 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 1474 mt7603_beacon_set_timer(dev, -1, beacon_int); 1475 1476 napi_enable(&dev->mt76.tx_napi); 1477 napi_enable(&dev->mt76.napi[0]); 1478 napi_enable(&dev->mt76.napi[1]); 1479 1480 local_bh_disable(); 1481 napi_schedule(&dev->mt76.tx_napi); 1482 napi_schedule(&dev->mt76.napi[0]); 1483 napi_schedule(&dev->mt76.napi[1]); 1484 local_bh_enable(); 1485 1486 ieee80211_wake_queues(dev->mt76.hw); 1487 mt76_txq_schedule_all(&dev->mphy); 1488 } 1489 1490 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index) 1491 { 1492 u32 val; 1493 1494 mt76_wr(dev, MT_WPDMA_DEBUG, 1495 FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) | 1496 MT_WPDMA_DEBUG_SEL); 1497 1498 val = mt76_rr(dev, MT_WPDMA_DEBUG); 1499 return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val); 1500 } 1501 1502 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev) 1503 { 1504 if (is_mt7628(dev)) 1505 return mt7603_dma_debug(dev, 9) & BIT(9); 1506 1507 return mt7603_dma_debug(dev, 2) & BIT(8); 1508 } 1509 1510 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev) 1511 { 1512 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY)) 1513 return false; 1514 1515 return mt7603_rx_fifo_busy(dev); 1516 } 1517 1518 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev) 1519 { 1520 u32 val; 1521 1522 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY)) 1523 return false; 1524 1525 val = mt7603_dma_debug(dev, 9); 1526 return (val & BIT(8)) && (val & 0xf) != 0xf; 1527 } 1528 1529 static bool mt7603_tx_hang(struct mt7603_dev *dev) 1530 { 1531 struct mt76_queue *q; 1532 u32 dma_idx, prev_dma_idx; 1533 int i; 1534 1535 for (i = 0; i < 4; i++) { 1536 q = dev->mphy.q_tx[i]; 1537 1538 if (!q->queued) 1539 continue; 1540 1541 prev_dma_idx = dev->tx_dma_idx[i]; 1542 dma_idx = readl(&q->regs->dma_idx); 1543 dev->tx_dma_idx[i] = dma_idx; 1544 1545 if (dma_idx == prev_dma_idx && 1546 dma_idx != readl(&q->regs->cpu_idx)) 1547 break; 1548 } 1549 1550 return i < 4; 1551 } 1552 1553 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev) 1554 { 1555 u32 addr, val; 1556 1557 if (mt7603_rx_fifo_busy(dev)) 1558 goto out; 1559 1560 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS); 1561 mt76_wr(dev, addr, 3); 1562 val = mt76_rr(dev, addr) >> 16; 1563 1564 if (!(val & BIT(0))) 1565 return false; 1566 1567 if (is_mt7628(dev)) 1568 val &= 0xa000; 1569 else 1570 val &= 0x8000; 1571 if (!val) 1572 return false; 1573 1574 out: 1575 if (mt76_rr(dev, MT_INT_SOURCE_CSR) & 1576 (MT_INT_RX_DONE(0) | MT_INT_RX_DONE(1))) 1577 return false; 1578 1579 return true; 1580 } 1581 1582 static bool 1583 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter, 1584 enum mt7603_reset_cause cause, 1585 bool (*check)(struct mt7603_dev *dev)) 1586 { 1587 if (dev->reset_test == cause + 1) { 1588 dev->reset_test = 0; 1589 goto trigger; 1590 } 1591 1592 if (check) { 1593 if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) { 1594 *counter = 0; 1595 return false; 1596 } 1597 1598 (*counter)++; 1599 } 1600 1601 if (*counter < MT7603_WATCHDOG_TIMEOUT) 1602 return false; 1603 trigger: 1604 dev->cur_reset_cause = cause; 1605 dev->reset_cause[cause]++; 1606 return true; 1607 } 1608 1609 void mt7603_update_channel(struct mt76_phy *mphy) 1610 { 1611 struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76); 1612 struct mt76_channel_state *state; 1613 1614 state = mphy->chan_state; 1615 state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA); 1616 } 1617 1618 void 1619 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val) 1620 { 1621 u32 rxtd_6 = 0xd7c80000; 1622 1623 if (val == dev->ed_strict_mode) 1624 return; 1625 1626 dev->ed_strict_mode = val; 1627 1628 /* Ensure that ED/CCA does not trigger if disabled */ 1629 if (!dev->ed_monitor) 1630 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34); 1631 else 1632 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d); 1633 1634 if (dev->ed_monitor && !dev->ed_strict_mode) 1635 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f); 1636 else 1637 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10); 1638 1639 mt76_wr(dev, MT_RXTD(6), rxtd_6); 1640 1641 mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN, 1642 dev->ed_monitor && !dev->ed_strict_mode); 1643 } 1644 1645 static void 1646 mt7603_edcca_check(struct mt7603_dev *dev) 1647 { 1648 u32 val = mt76_rr(dev, MT_AGC(41)); 1649 ktime_t cur_time; 1650 int rssi0, rssi1; 1651 u32 active; 1652 u32 ed_busy; 1653 1654 if (!dev->ed_monitor) 1655 return; 1656 1657 rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val); 1658 if (rssi0 > 128) 1659 rssi0 -= 256; 1660 1661 if (dev->mphy.antenna_mask & BIT(1)) { 1662 rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val); 1663 if (rssi1 > 128) 1664 rssi1 -= 256; 1665 } else { 1666 rssi1 = rssi0; 1667 } 1668 1669 if (max(rssi0, rssi1) >= -40 && 1670 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH) 1671 dev->ed_strong_signal++; 1672 else if (dev->ed_strong_signal > 0) 1673 dev->ed_strong_signal--; 1674 1675 cur_time = ktime_get_boottime(); 1676 ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK; 1677 1678 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 1679 dev->ed_time = cur_time; 1680 1681 if (!active) 1682 return; 1683 1684 if (100 * ed_busy / active > 90) { 1685 if (dev->ed_trigger < 0) 1686 dev->ed_trigger = 0; 1687 dev->ed_trigger++; 1688 } else { 1689 if (dev->ed_trigger > 0) 1690 dev->ed_trigger = 0; 1691 dev->ed_trigger--; 1692 } 1693 1694 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH || 1695 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) { 1696 mt7603_edcca_set_strict(dev, true); 1697 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) { 1698 mt7603_edcca_set_strict(dev, false); 1699 } 1700 1701 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH) 1702 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH; 1703 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) 1704 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH; 1705 } 1706 1707 void mt7603_cca_stats_reset(struct mt7603_dev *dev) 1708 { 1709 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1710 mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1711 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN); 1712 } 1713 1714 static void 1715 mt7603_adjust_sensitivity(struct mt7603_dev *dev) 1716 { 1717 u32 agc0 = dev->agc0, agc3 = dev->agc3; 1718 u32 adj; 1719 1720 if (!dev->sensitivity || dev->sensitivity < -100) { 1721 dev->sensitivity = 0; 1722 } else if (dev->sensitivity <= -84) { 1723 adj = 7 + (dev->sensitivity + 92) / 2; 1724 1725 agc0 = 0x56f0076f; 1726 agc0 |= adj << 12; 1727 agc0 |= adj << 16; 1728 agc3 = 0x81d0d5e3; 1729 } else if (dev->sensitivity <= -72) { 1730 adj = 7 + (dev->sensitivity + 80) / 2; 1731 1732 agc0 = 0x6af0006f; 1733 agc0 |= adj << 8; 1734 agc0 |= adj << 12; 1735 agc0 |= adj << 16; 1736 1737 agc3 = 0x8181d5e3; 1738 } else { 1739 if (dev->sensitivity > -54) 1740 dev->sensitivity = -54; 1741 1742 adj = 7 + (dev->sensitivity + 80) / 2; 1743 1744 agc0 = 0x7ff0000f; 1745 agc0 |= adj << 4; 1746 agc0 |= adj << 8; 1747 agc0 |= adj << 12; 1748 agc0 |= adj << 16; 1749 1750 agc3 = 0x818181e3; 1751 } 1752 1753 mt76_wr(dev, MT_AGC(0), agc0); 1754 mt76_wr(dev, MT_AGC1(0), agc0); 1755 1756 mt76_wr(dev, MT_AGC(3), agc3); 1757 mt76_wr(dev, MT_AGC1(3), agc3); 1758 } 1759 1760 static void 1761 mt7603_false_cca_check(struct mt7603_dev *dev) 1762 { 1763 int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm; 1764 int false_cca; 1765 int min_signal; 1766 u32 val; 1767 1768 if (!dev->dynamic_sensitivity) 1769 return; 1770 1771 val = mt76_rr(dev, MT_PHYCTRL_STAT_PD); 1772 pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val); 1773 pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val); 1774 1775 val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY); 1776 mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val); 1777 mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val); 1778 1779 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1780 dev->false_cca_cck = pd_cck - mdrdy_cck; 1781 1782 mt7603_cca_stats_reset(dev); 1783 1784 min_signal = mt76_get_min_avg_rssi(&dev->mt76, 0); 1785 if (!min_signal) { 1786 dev->sensitivity = 0; 1787 dev->last_cca_adj = jiffies; 1788 goto out; 1789 } 1790 1791 min_signal -= 15; 1792 1793 false_cca = dev->false_cca_ofdm + dev->false_cca_cck; 1794 if (false_cca > 600 && 1795 dev->sensitivity < -100 + dev->sensitivity_limit) { 1796 if (!dev->sensitivity) 1797 dev->sensitivity = -92; 1798 else 1799 dev->sensitivity += 2; 1800 dev->last_cca_adj = jiffies; 1801 } else if (false_cca < 100 || 1802 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) { 1803 dev->last_cca_adj = jiffies; 1804 if (!dev->sensitivity) 1805 goto out; 1806 1807 dev->sensitivity -= 2; 1808 } 1809 1810 if (dev->sensitivity && dev->sensitivity > min_signal) { 1811 dev->sensitivity = min_signal; 1812 dev->last_cca_adj = jiffies; 1813 } 1814 1815 out: 1816 mt7603_adjust_sensitivity(dev); 1817 } 1818 1819 void mt7603_mac_work(struct work_struct *work) 1820 { 1821 struct mt7603_dev *dev = container_of(work, struct mt7603_dev, 1822 mphy.mac_work.work); 1823 bool reset = false; 1824 int i, idx; 1825 1826 mt76_tx_status_check(&dev->mt76, false); 1827 1828 mutex_lock(&dev->mt76.mutex); 1829 1830 dev->mphy.mac_work_count++; 1831 mt76_update_survey(&dev->mphy); 1832 mt7603_edcca_check(dev); 1833 1834 for (i = 0, idx = 0; i < 2; i++) { 1835 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 1836 1837 dev->mphy.aggr_stats[idx++] += val & 0xffff; 1838 dev->mphy.aggr_stats[idx++] += val >> 16; 1839 } 1840 1841 if (dev->mphy.mac_work_count == 10) 1842 mt7603_false_cca_check(dev); 1843 1844 if (mt7603_watchdog_check(dev, &dev->rx_pse_check, 1845 RESET_CAUSE_RX_PSE_BUSY, 1846 mt7603_rx_pse_busy) || 1847 mt7603_watchdog_check(dev, &dev->beacon_check, 1848 RESET_CAUSE_BEACON_STUCK, 1849 NULL) || 1850 mt7603_watchdog_check(dev, &dev->tx_hang_check, 1851 RESET_CAUSE_TX_HANG, 1852 mt7603_tx_hang) || 1853 mt7603_watchdog_check(dev, &dev->tx_dma_check, 1854 RESET_CAUSE_TX_BUSY, 1855 mt7603_tx_dma_busy) || 1856 mt7603_watchdog_check(dev, &dev->rx_dma_check, 1857 RESET_CAUSE_RX_BUSY, 1858 mt7603_rx_dma_busy) || 1859 mt7603_watchdog_check(dev, &dev->mcu_hang, 1860 RESET_CAUSE_MCU_HANG, 1861 NULL) || 1862 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { 1863 dev->beacon_check = 0; 1864 dev->tx_dma_check = 0; 1865 dev->tx_hang_check = 0; 1866 dev->rx_dma_check = 0; 1867 dev->rx_pse_check = 0; 1868 dev->mcu_hang = 0; 1869 dev->rx_dma_idx = ~0; 1870 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx)); 1871 reset = true; 1872 dev->mphy.mac_work_count = 0; 1873 } 1874 1875 if (dev->mphy.mac_work_count >= 10) 1876 dev->mphy.mac_work_count = 0; 1877 1878 mutex_unlock(&dev->mt76.mutex); 1879 1880 if (reset) 1881 mt7603_mac_watchdog_reset(dev); 1882 1883 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1884 msecs_to_jiffies(MT7603_WATCHDOG_TIME)); 1885 } 1886