1 /* SPDX-License-Identifier: ISC */ 2 3 #include "mt7603.h" 4 #include "mac.h" 5 #include "../dma.h" 6 7 static int 8 mt7603_init_tx_queue(struct mt7603_dev *dev, struct mt76_queue *q, 9 int idx, int n_desc) 10 { 11 int ret; 12 13 q->hw_idx = idx; 14 q->regs = dev->mt76.mmio.regs + MT_TX_RING_BASE + idx * MT_RING_SIZE; 15 q->ndesc = n_desc; 16 17 ret = mt76_queue_alloc(dev, q); 18 if (ret) 19 return ret; 20 21 mt7603_irq_enable(dev, MT_INT_TX_DONE(idx)); 22 23 return 0; 24 } 25 26 static void 27 mt7603_rx_loopback_skb(struct mt7603_dev *dev, struct sk_buff *skb) 28 { 29 __le32 *txd = (__le32 *)skb->data; 30 struct mt7603_sta *msta; 31 struct mt76_wcid *wcid; 32 int idx; 33 u32 val; 34 35 if (skb->len < sizeof(MT_TXD_SIZE) + sizeof(struct ieee80211_hdr)) 36 goto free; 37 38 val = le32_to_cpu(txd[1]); 39 idx = FIELD_GET(MT_TXD1_WLAN_IDX, val); 40 skb->priority = FIELD_GET(MT_TXD1_TID, val); 41 42 if (idx >= MT7603_WTBL_STA - 1) 43 goto free; 44 45 wcid = rcu_dereference(dev->mt76.wcid[idx]); 46 if (!wcid) 47 goto free; 48 49 msta = container_of(wcid, struct mt7603_sta, wcid); 50 val = le32_to_cpu(txd[0]); 51 skb_set_queue_mapping(skb, FIELD_GET(MT_TXD0_Q_IDX, val)); 52 53 spin_lock_bh(&dev->ps_lock); 54 __skb_queue_tail(&msta->psq, skb); 55 if (skb_queue_len(&msta->psq) >= 64) { 56 skb = __skb_dequeue(&msta->psq); 57 dev_kfree_skb(skb); 58 } 59 spin_unlock_bh(&dev->ps_lock); 60 return; 61 62 free: 63 dev_kfree_skb(skb); 64 } 65 66 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 67 struct sk_buff *skb) 68 { 69 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 70 __le32 *rxd = (__le32 *)skb->data; 71 __le32 *end = (__le32 *)&skb->data[skb->len]; 72 enum rx_pkt_type type; 73 74 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 75 76 if (q == MT_RXQ_MCU) { 77 if (type == PKT_TYPE_RX_EVENT) 78 mt76_mcu_rx_event(&dev->mt76, skb); 79 else 80 mt7603_rx_loopback_skb(dev, skb); 81 return; 82 } 83 84 switch (type) { 85 case PKT_TYPE_TXS: 86 for (rxd++; rxd + 5 <= end; rxd += 5) 87 mt7603_mac_add_txs(dev, rxd); 88 dev_kfree_skb(skb); 89 break; 90 case PKT_TYPE_RX_EVENT: 91 mt76_mcu_rx_event(&dev->mt76, skb); 92 return; 93 case PKT_TYPE_NORMAL: 94 if (mt7603_mac_fill_rx(dev, skb) == 0) { 95 mt76_rx(&dev->mt76, q, skb); 96 return; 97 } 98 /* fall through */ 99 default: 100 dev_kfree_skb(skb); 101 break; 102 } 103 } 104 105 static int 106 mt7603_init_rx_queue(struct mt7603_dev *dev, struct mt76_queue *q, 107 int idx, int n_desc, int bufsize) 108 { 109 int ret; 110 111 q->regs = dev->mt76.mmio.regs + MT_RX_RING_BASE + idx * MT_RING_SIZE; 112 q->ndesc = n_desc; 113 q->buf_size = bufsize; 114 115 ret = mt76_queue_alloc(dev, q); 116 if (ret) 117 return ret; 118 119 mt7603_irq_enable(dev, MT_INT_RX_DONE(idx)); 120 121 return 0; 122 } 123 124 static void 125 mt7603_tx_tasklet(unsigned long data) 126 { 127 struct mt7603_dev *dev = (struct mt7603_dev *)data; 128 int i; 129 130 dev->tx_dma_check = 0; 131 for (i = MT_TXQ_MCU; i >= 0; i--) 132 mt76_queue_tx_cleanup(dev, i, false); 133 134 mt7603_irq_enable(dev, MT_INT_TX_DONE_ALL); 135 } 136 137 int mt7603_dma_init(struct mt7603_dev *dev) 138 { 139 static const u8 wmm_queue_map[] = { 140 [IEEE80211_AC_BK] = 0, 141 [IEEE80211_AC_BE] = 1, 142 [IEEE80211_AC_VI] = 2, 143 [IEEE80211_AC_VO] = 3, 144 }; 145 int ret; 146 int i; 147 148 mt76_dma_attach(&dev->mt76); 149 150 init_waitqueue_head(&dev->mt76.mmio.mcu.wait); 151 skb_queue_head_init(&dev->mt76.mmio.mcu.res_q); 152 153 tasklet_init(&dev->tx_tasklet, mt7603_tx_tasklet, (unsigned long)dev); 154 155 mt76_clear(dev, MT_WPDMA_GLO_CFG, 156 MT_WPDMA_GLO_CFG_TX_DMA_EN | 157 MT_WPDMA_GLO_CFG_RX_DMA_EN | 158 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE | 159 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 160 161 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); 162 mt7603_pse_client_reset(dev); 163 164 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { 165 ret = mt7603_init_tx_queue(dev, &dev->mt76.q_tx[i], 166 wmm_queue_map[i], 167 MT_TX_RING_SIZE); 168 if (ret) 169 return ret; 170 } 171 172 ret = mt7603_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD], 173 MT_TX_HW_QUEUE_MGMT, MT_TX_RING_SIZE); 174 if (ret) 175 return ret; 176 177 ret = mt7603_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU], 178 MT_TX_HW_QUEUE_MCU, MT_MCU_RING_SIZE); 179 if (ret) 180 return ret; 181 182 ret = mt7603_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_BEACON], 183 MT_TX_HW_QUEUE_BCN, MT_MCU_RING_SIZE); 184 if (ret) 185 return ret; 186 187 ret = mt7603_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_CAB], 188 MT_TX_HW_QUEUE_BMC, MT_MCU_RING_SIZE); 189 if (ret) 190 return ret; 191 192 ret = mt7603_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, 193 MT_MCU_RING_SIZE, MT_RX_BUF_SIZE); 194 if (ret) 195 return ret; 196 197 ret = mt7603_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 198 MT7603_RX_RING_SIZE, MT_RX_BUF_SIZE); 199 if (ret) 200 return ret; 201 202 mt76_wr(dev, MT_DELAY_INT_CFG, 0); 203 return mt76_init_queues(dev); 204 } 205 206 void mt7603_dma_cleanup(struct mt7603_dev *dev) 207 { 208 mt76_clear(dev, MT_WPDMA_GLO_CFG, 209 MT_WPDMA_GLO_CFG_TX_DMA_EN | 210 MT_WPDMA_GLO_CFG_RX_DMA_EN | 211 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 212 213 tasklet_kill(&dev->tx_tasklet); 214 mt76_dma_cleanup(&dev->mt76); 215 } 216