1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include <net/page_pool/helpers.h> 19 #include "util.h" 20 #include "testmode.h" 21 22 #define MT_MCU_RING_SIZE 32 23 #define MT_RX_BUF_SIZE 2048 24 #define MT_SKB_HEAD_LEN 256 25 26 #define MT_MAX_NON_AQL_PKT 16 27 #define MT_TXQ_FREE_THR 32 28 29 #define MT76_TOKEN_FREE_THR 64 30 31 #define MT_QFLAG_WED_RING GENMASK(1, 0) 32 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 33 #define MT_QFLAG_WED BIT(4) 34 35 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 36 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 37 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 38 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 39 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 40 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 41 42 struct mt76_dev; 43 struct mt76_phy; 44 struct mt76_wcid; 45 struct mt76s_intr; 46 47 struct mt76_reg_pair { 48 u32 reg; 49 u32 value; 50 }; 51 52 enum mt76_bus_type { 53 MT76_BUS_MMIO, 54 MT76_BUS_USB, 55 MT76_BUS_SDIO, 56 }; 57 58 enum mt76_wed_type { 59 MT76_WED_Q_TX, 60 MT76_WED_Q_TXFREE, 61 MT76_WED_Q_RX, 62 }; 63 64 struct mt76_bus_ops { 65 u32 (*rr)(struct mt76_dev *dev, u32 offset); 66 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 67 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 68 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 69 int len); 70 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 71 int len); 72 int (*wr_rp)(struct mt76_dev *dev, u32 base, 73 const struct mt76_reg_pair *rp, int len); 74 int (*rd_rp)(struct mt76_dev *dev, u32 base, 75 struct mt76_reg_pair *rp, int len); 76 enum mt76_bus_type type; 77 }; 78 79 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 80 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 81 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 82 83 enum mt76_txq_id { 84 MT_TXQ_VO = IEEE80211_AC_VO, 85 MT_TXQ_VI = IEEE80211_AC_VI, 86 MT_TXQ_BE = IEEE80211_AC_BE, 87 MT_TXQ_BK = IEEE80211_AC_BK, 88 MT_TXQ_PSD, 89 MT_TXQ_BEACON, 90 MT_TXQ_CAB, 91 __MT_TXQ_MAX 92 }; 93 94 enum mt76_mcuq_id { 95 MT_MCUQ_WM, 96 MT_MCUQ_WA, 97 MT_MCUQ_FWDL, 98 __MT_MCUQ_MAX 99 }; 100 101 enum mt76_rxq_id { 102 MT_RXQ_MAIN, 103 MT_RXQ_MCU, 104 MT_RXQ_MCU_WA, 105 MT_RXQ_BAND1, 106 MT_RXQ_BAND1_WA, 107 MT_RXQ_MAIN_WA, 108 MT_RXQ_BAND2, 109 MT_RXQ_BAND2_WA, 110 __MT_RXQ_MAX 111 }; 112 113 enum mt76_band_id { 114 MT_BAND0, 115 MT_BAND1, 116 MT_BAND2, 117 __MT_MAX_BAND 118 }; 119 120 enum mt76_cipher_type { 121 MT_CIPHER_NONE, 122 MT_CIPHER_WEP40, 123 MT_CIPHER_TKIP, 124 MT_CIPHER_TKIP_NO_MIC, 125 MT_CIPHER_AES_CCMP, 126 MT_CIPHER_WEP104, 127 MT_CIPHER_BIP_CMAC_128, 128 MT_CIPHER_WEP128, 129 MT_CIPHER_WAPI, 130 MT_CIPHER_CCMP_CCX, 131 MT_CIPHER_CCMP_256, 132 MT_CIPHER_GCMP, 133 MT_CIPHER_GCMP_256, 134 }; 135 136 enum mt76_dfs_state { 137 MT_DFS_STATE_UNKNOWN, 138 MT_DFS_STATE_DISABLED, 139 MT_DFS_STATE_CAC, 140 MT_DFS_STATE_ACTIVE, 141 }; 142 143 struct mt76_queue_buf { 144 dma_addr_t addr; 145 u16 len; 146 bool skip_unmap; 147 }; 148 149 struct mt76_tx_info { 150 struct mt76_queue_buf buf[32]; 151 struct sk_buff *skb; 152 int nbuf; 153 u32 info; 154 }; 155 156 struct mt76_queue_entry { 157 union { 158 void *buf; 159 struct sk_buff *skb; 160 }; 161 union { 162 struct mt76_txwi_cache *txwi; 163 struct urb *urb; 164 int buf_sz; 165 }; 166 u32 dma_addr[2]; 167 u16 dma_len[2]; 168 u16 wcid; 169 bool skip_buf0:1; 170 bool skip_buf1:1; 171 bool done:1; 172 }; 173 174 struct mt76_queue_regs { 175 u32 desc_base; 176 u32 ring_size; 177 u32 cpu_idx; 178 u32 dma_idx; 179 } __packed __aligned(4); 180 181 struct mt76_queue { 182 struct mt76_queue_regs __iomem *regs; 183 184 spinlock_t lock; 185 spinlock_t cleanup_lock; 186 struct mt76_queue_entry *entry; 187 struct mt76_desc *desc; 188 189 u16 first; 190 u16 head; 191 u16 tail; 192 int ndesc; 193 int queued; 194 int buf_size; 195 bool stopped; 196 bool blocked; 197 198 u8 buf_offset; 199 u8 hw_idx; 200 u8 flags; 201 202 u32 wed_regs; 203 204 dma_addr_t desc_dma; 205 struct sk_buff *rx_head; 206 struct page_pool *page_pool; 207 }; 208 209 struct mt76_mcu_ops { 210 u32 headroom; 211 u32 tailroom; 212 213 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 214 int len, bool wait_resp); 215 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 216 int cmd, int *seq); 217 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 218 struct sk_buff *skb, int seq); 219 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 220 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 221 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 222 const struct mt76_reg_pair *rp, int len); 223 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 224 struct mt76_reg_pair *rp, int len); 225 int (*mcu_restart)(struct mt76_dev *dev); 226 }; 227 228 struct mt76_queue_ops { 229 int (*init)(struct mt76_dev *dev, 230 int (*poll)(struct napi_struct *napi, int budget)); 231 232 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 233 int idx, int n_desc, int bufsize, 234 u32 ring_base); 235 236 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 237 enum mt76_txq_id qid, struct sk_buff *skb, 238 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 239 240 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 241 struct sk_buff *skb, u32 tx_info); 242 243 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 244 int *len, u32 *info, bool *more); 245 246 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 247 248 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 249 bool flush); 250 251 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 252 253 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 254 255 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 256 }; 257 258 enum mt76_phy_type { 259 MT_PHY_TYPE_CCK, 260 MT_PHY_TYPE_OFDM, 261 MT_PHY_TYPE_HT, 262 MT_PHY_TYPE_HT_GF, 263 MT_PHY_TYPE_VHT, 264 MT_PHY_TYPE_HE_SU = 8, 265 MT_PHY_TYPE_HE_EXT_SU, 266 MT_PHY_TYPE_HE_TB, 267 MT_PHY_TYPE_HE_MU, 268 MT_PHY_TYPE_EHT_SU = 13, 269 MT_PHY_TYPE_EHT_TRIG, 270 MT_PHY_TYPE_EHT_MU, 271 __MT_PHY_TYPE_MAX, 272 }; 273 274 struct mt76_sta_stats { 275 u64 tx_mode[__MT_PHY_TYPE_MAX]; 276 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 277 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 278 u64 tx_mcs[16]; /* mcs idx */ 279 u64 tx_bytes; 280 /* WED TX */ 281 u32 tx_packets; /* unit: MSDU */ 282 u32 tx_retries; 283 u32 tx_failed; 284 /* WED RX */ 285 u64 rx_bytes; 286 u32 rx_packets; 287 u32 rx_errors; 288 u32 rx_drops; 289 }; 290 291 enum mt76_wcid_flags { 292 MT_WCID_FLAG_CHECK_PS, 293 MT_WCID_FLAG_PS, 294 MT_WCID_FLAG_4ADDR, 295 MT_WCID_FLAG_HDR_TRANS, 296 }; 297 298 #define MT76_N_WCIDS 1088 299 300 /* stored in ieee80211_tx_info::hw_queue */ 301 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 302 303 DECLARE_EWMA(signal, 10, 8); 304 305 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 306 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 307 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 308 #define MT_WCID_TX_INFO_SET BIT(31) 309 310 struct mt76_wcid { 311 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 312 313 atomic_t non_aql_packets; 314 unsigned long flags; 315 316 struct ewma_signal rssi; 317 int inactive_count; 318 319 struct rate_info rate; 320 unsigned long ampdu_state; 321 322 u16 idx; 323 u8 hw_key_idx; 324 u8 hw_key_idx2; 325 326 u8 sta:1; 327 u8 amsdu:1; 328 u8 phy_idx:2; 329 330 u8 rx_check_pn; 331 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 332 u16 cipher; 333 334 u32 tx_info; 335 bool sw_iv; 336 337 struct list_head tx_list; 338 struct sk_buff_head tx_pending; 339 340 struct list_head list; 341 struct idr pktid; 342 343 struct mt76_sta_stats stats; 344 345 struct list_head poll_list; 346 }; 347 348 struct mt76_txq { 349 u16 wcid; 350 351 u16 agg_ssn; 352 bool send_bar; 353 bool aggr; 354 }; 355 356 struct mt76_txwi_cache { 357 struct list_head list; 358 dma_addr_t dma_addr; 359 360 union { 361 struct sk_buff *skb; 362 void *ptr; 363 }; 364 }; 365 366 struct mt76_rx_tid { 367 struct rcu_head rcu_head; 368 369 struct mt76_dev *dev; 370 371 spinlock_t lock; 372 struct delayed_work reorder_work; 373 374 u16 head; 375 u16 size; 376 u16 nframes; 377 378 u8 num; 379 380 u8 started:1, stopped:1, timer_pending:1; 381 382 struct sk_buff *reorder_buf[] __counted_by(size); 383 }; 384 385 #define MT_TX_CB_DMA_DONE BIT(0) 386 #define MT_TX_CB_TXS_DONE BIT(1) 387 #define MT_TX_CB_TXS_FAILED BIT(2) 388 389 #define MT_PACKET_ID_MASK GENMASK(6, 0) 390 #define MT_PACKET_ID_NO_ACK 0 391 #define MT_PACKET_ID_NO_SKB 1 392 #define MT_PACKET_ID_WED 2 393 #define MT_PACKET_ID_FIRST 3 394 #define MT_PACKET_ID_HAS_RATE BIT(7) 395 /* This is timer for when to give up when waiting for TXS callback, 396 * with starting time being the time at which the DMA_DONE callback 397 * was seen (so, we know packet was processed then, it should not take 398 * long after that for firmware to send the TXS callback if it is going 399 * to do so.) 400 */ 401 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 402 403 struct mt76_tx_cb { 404 unsigned long jiffies; 405 u16 wcid; 406 u8 pktid; 407 u8 flags; 408 }; 409 410 enum { 411 MT76_STATE_INITIALIZED, 412 MT76_STATE_REGISTERED, 413 MT76_STATE_RUNNING, 414 MT76_STATE_MCU_RUNNING, 415 MT76_SCANNING, 416 MT76_HW_SCANNING, 417 MT76_HW_SCHED_SCANNING, 418 MT76_RESTART, 419 MT76_RESET, 420 MT76_MCU_RESET, 421 MT76_REMOVED, 422 MT76_READING_STATS, 423 MT76_STATE_POWER_OFF, 424 MT76_STATE_SUSPEND, 425 MT76_STATE_ROC, 426 MT76_STATE_PM, 427 MT76_STATE_WED_RESET, 428 }; 429 430 struct mt76_hw_cap { 431 bool has_2ghz; 432 bool has_5ghz; 433 bool has_6ghz; 434 }; 435 436 #define MT_DRV_TXWI_NO_FREE BIT(0) 437 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 438 #define MT_DRV_SW_RX_AIRTIME BIT(2) 439 #define MT_DRV_RX_DMA_HDR BIT(3) 440 #define MT_DRV_HW_MGMT_TXQ BIT(4) 441 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 442 443 struct mt76_driver_ops { 444 u32 drv_flags; 445 u32 survey_flags; 446 u16 txwi_size; 447 u16 token_size; 448 u8 mcs_rates; 449 450 void (*update_survey)(struct mt76_phy *phy); 451 452 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 453 enum mt76_txq_id qid, struct mt76_wcid *wcid, 454 struct ieee80211_sta *sta, 455 struct mt76_tx_info *tx_info); 456 457 void (*tx_complete_skb)(struct mt76_dev *dev, 458 struct mt76_queue_entry *e); 459 460 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 461 462 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 463 464 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 465 struct sk_buff *skb, u32 *info); 466 467 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 468 469 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 470 bool ps); 471 472 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 473 struct ieee80211_sta *sta); 474 475 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 476 struct ieee80211_sta *sta); 477 478 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 479 struct ieee80211_sta *sta); 480 }; 481 482 struct mt76_channel_state { 483 u64 cc_active; 484 u64 cc_busy; 485 u64 cc_rx; 486 u64 cc_bss_rx; 487 u64 cc_tx; 488 489 s8 noise; 490 }; 491 492 struct mt76_sband { 493 struct ieee80211_supported_band sband; 494 struct mt76_channel_state *chan; 495 }; 496 497 /* addr req mask */ 498 #define MT_VEND_TYPE_EEPROM BIT(31) 499 #define MT_VEND_TYPE_CFG BIT(30) 500 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 501 502 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 503 enum mt_vendor_req { 504 MT_VEND_DEV_MODE = 0x1, 505 MT_VEND_WRITE = 0x2, 506 MT_VEND_POWER_ON = 0x4, 507 MT_VEND_MULTI_WRITE = 0x6, 508 MT_VEND_MULTI_READ = 0x7, 509 MT_VEND_READ_EEPROM = 0x9, 510 MT_VEND_WRITE_FCE = 0x42, 511 MT_VEND_WRITE_CFG = 0x46, 512 MT_VEND_READ_CFG = 0x47, 513 MT_VEND_READ_EXT = 0x63, 514 MT_VEND_WRITE_EXT = 0x66, 515 MT_VEND_FEATURE_SET = 0x91, 516 }; 517 518 enum mt76u_in_ep { 519 MT_EP_IN_PKT_RX, 520 MT_EP_IN_CMD_RESP, 521 __MT_EP_IN_MAX, 522 }; 523 524 enum mt76u_out_ep { 525 MT_EP_OUT_INBAND_CMD, 526 MT_EP_OUT_AC_BE, 527 MT_EP_OUT_AC_BK, 528 MT_EP_OUT_AC_VI, 529 MT_EP_OUT_AC_VO, 530 MT_EP_OUT_HCCA, 531 __MT_EP_OUT_MAX, 532 }; 533 534 struct mt76_mcu { 535 struct mutex mutex; 536 u32 msg_seq; 537 int timeout; 538 539 struct sk_buff_head res_q; 540 wait_queue_head_t wait; 541 }; 542 543 #define MT_TX_SG_MAX_SIZE 8 544 #define MT_RX_SG_MAX_SIZE 4 545 #define MT_NUM_TX_ENTRIES 256 546 #define MT_NUM_RX_ENTRIES 128 547 #define MCU_RESP_URB_SIZE 1024 548 struct mt76_usb { 549 struct mutex usb_ctrl_mtx; 550 u8 *data; 551 u16 data_len; 552 553 struct mt76_worker status_worker; 554 struct mt76_worker rx_worker; 555 556 struct work_struct stat_work; 557 558 u8 out_ep[__MT_EP_OUT_MAX]; 559 u8 in_ep[__MT_EP_IN_MAX]; 560 bool sg_en; 561 562 struct mt76u_mcu { 563 u8 *data; 564 /* multiple reads */ 565 struct mt76_reg_pair *rp; 566 int rp_len; 567 u32 base; 568 } mcu; 569 }; 570 571 #define MT76S_XMIT_BUF_SZ 0x3fe00 572 #define MT76S_NUM_TX_ENTRIES 256 573 #define MT76S_NUM_RX_ENTRIES 512 574 struct mt76_sdio { 575 struct mt76_worker txrx_worker; 576 struct mt76_worker status_worker; 577 struct mt76_worker net_worker; 578 579 struct work_struct stat_work; 580 581 u8 *xmit_buf; 582 u32 xmit_buf_sz; 583 584 struct sdio_func *func; 585 void *intr_data; 586 u8 hw_ver; 587 wait_queue_head_t wait; 588 589 struct { 590 int pse_data_quota; 591 int ple_data_quota; 592 int pse_mcu_quota; 593 int pse_page_size; 594 int deficit; 595 } sched; 596 597 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 598 }; 599 600 struct mt76_mmio { 601 void __iomem *regs; 602 spinlock_t irq_lock; 603 u32 irqmask; 604 605 struct mtk_wed_device wed; 606 struct completion wed_reset; 607 struct completion wed_reset_complete; 608 }; 609 610 struct mt76_rx_status { 611 union { 612 struct mt76_wcid *wcid; 613 u16 wcid_idx; 614 }; 615 616 u32 reorder_time; 617 618 u32 ampdu_ref; 619 u32 timestamp; 620 621 u8 iv[6]; 622 623 u8 phy_idx:2; 624 u8 aggr:1; 625 u8 qos_ctl; 626 u16 seqno; 627 628 u16 freq; 629 u32 flag; 630 u8 enc_flags; 631 u8 encoding:3, bw:4; 632 union { 633 struct { 634 u8 he_ru:3; 635 u8 he_gi:2; 636 u8 he_dcm:1; 637 }; 638 struct { 639 u8 ru:4; 640 u8 gi:2; 641 } eht; 642 }; 643 644 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 645 u8 rate_idx; 646 u8 nss:5, band:3; 647 s8 signal; 648 u8 chains; 649 s8 chain_signal[IEEE80211_MAX_CHAINS]; 650 }; 651 652 struct mt76_freq_range_power { 653 const struct cfg80211_sar_freq_ranges *range; 654 s8 power; 655 }; 656 657 struct mt76_testmode_ops { 658 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 659 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 660 enum mt76_testmode_state new_state); 661 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 662 }; 663 664 struct mt76_testmode_data { 665 enum mt76_testmode_state state; 666 667 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 668 struct sk_buff *tx_skb; 669 670 u32 tx_count; 671 u16 tx_mpdu_len; 672 673 u8 tx_rate_mode; 674 u8 tx_rate_idx; 675 u8 tx_rate_nss; 676 u8 tx_rate_sgi; 677 u8 tx_rate_ldpc; 678 u8 tx_rate_stbc; 679 u8 tx_ltf; 680 681 u8 tx_antenna_mask; 682 u8 tx_spe_idx; 683 684 u8 tx_duty_cycle; 685 u32 tx_time; 686 u32 tx_ipg; 687 688 u32 freq_offset; 689 690 u8 tx_power[4]; 691 u8 tx_power_control; 692 693 u8 addr[3][ETH_ALEN]; 694 695 u32 tx_pending; 696 u32 tx_queued; 697 u16 tx_queued_limit; 698 u32 tx_done; 699 struct { 700 u64 packets[__MT_RXQ_MAX]; 701 u64 fcs_error[__MT_RXQ_MAX]; 702 } rx_stats; 703 }; 704 705 struct mt76_vif { 706 u8 idx; 707 u8 omac_idx; 708 u8 band_idx; 709 u8 wmm_idx; 710 u8 scan_seq_num; 711 u8 cipher; 712 u8 basic_rates_idx; 713 u8 mcast_rates_idx; 714 u8 beacon_rates_idx; 715 struct ieee80211_chanctx_conf *ctx; 716 }; 717 718 struct mt76_phy { 719 struct ieee80211_hw *hw; 720 struct mt76_dev *dev; 721 void *priv; 722 723 unsigned long state; 724 u8 band_idx; 725 726 spinlock_t tx_lock; 727 struct list_head tx_list; 728 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 729 730 struct cfg80211_chan_def chandef; 731 struct ieee80211_channel *main_chan; 732 733 struct mt76_channel_state *chan_state; 734 enum mt76_dfs_state dfs_state; 735 ktime_t survey_time; 736 737 u32 aggr_stats[32]; 738 739 struct mt76_hw_cap cap; 740 struct mt76_sband sband_2g; 741 struct mt76_sband sband_5g; 742 struct mt76_sband sband_6g; 743 744 u8 macaddr[ETH_ALEN]; 745 746 int txpower_cur; 747 u8 antenna_mask; 748 u16 chainmask; 749 750 #ifdef CONFIG_NL80211_TESTMODE 751 struct mt76_testmode_data test; 752 #endif 753 754 struct delayed_work mac_work; 755 u8 mac_work_count; 756 757 struct { 758 struct sk_buff *head; 759 struct sk_buff **tail; 760 u16 seqno; 761 } rx_amsdu[__MT_RXQ_MAX]; 762 763 struct mt76_freq_range_power *frp; 764 765 struct { 766 struct led_classdev cdev; 767 char name[32]; 768 bool al; 769 u8 pin; 770 } leds; 771 }; 772 773 struct mt76_dev { 774 struct mt76_phy phy; /* must be first */ 775 struct mt76_phy *phys[__MT_MAX_BAND]; 776 777 struct ieee80211_hw *hw; 778 779 spinlock_t wed_lock; 780 spinlock_t lock; 781 spinlock_t cc_lock; 782 783 u32 cur_cc_bss_rx; 784 785 struct mt76_rx_status rx_ampdu_status; 786 u32 rx_ampdu_len; 787 u32 rx_ampdu_ref; 788 789 struct mutex mutex; 790 791 const struct mt76_bus_ops *bus; 792 const struct mt76_driver_ops *drv; 793 const struct mt76_mcu_ops *mcu_ops; 794 struct device *dev; 795 struct device *dma_dev; 796 797 struct mt76_mcu mcu; 798 799 struct net_device napi_dev; 800 struct net_device tx_napi_dev; 801 spinlock_t rx_lock; 802 struct napi_struct napi[__MT_RXQ_MAX]; 803 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 804 struct tasklet_struct irq_tasklet; 805 806 struct list_head txwi_cache; 807 struct list_head rxwi_cache; 808 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 809 struct mt76_queue q_rx[__MT_RXQ_MAX]; 810 const struct mt76_queue_ops *queue_ops; 811 int tx_dma_idx[4]; 812 813 struct mt76_worker tx_worker; 814 struct napi_struct tx_napi; 815 816 spinlock_t token_lock; 817 struct idr token; 818 u16 wed_token_count; 819 u16 token_count; 820 u16 token_size; 821 822 spinlock_t rx_token_lock; 823 struct idr rx_token; 824 u16 rx_token_size; 825 826 wait_queue_head_t tx_wait; 827 /* spinclock used to protect wcid pktid linked list */ 828 spinlock_t status_lock; 829 830 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 831 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 832 833 u64 vif_mask; 834 835 struct mt76_wcid global_wcid; 836 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 837 struct list_head wcid_list; 838 839 struct list_head sta_poll_list; 840 spinlock_t sta_poll_lock; 841 842 u32 rev; 843 844 struct tasklet_struct pre_tbtt_tasklet; 845 int beacon_int; 846 u8 beacon_mask; 847 848 struct debugfs_blob_wrapper eeprom; 849 struct debugfs_blob_wrapper otp; 850 851 char alpha2[3]; 852 enum nl80211_dfs_regions region; 853 854 u32 debugfs_reg; 855 856 u8 csa_complete; 857 858 u32 rxfilter; 859 860 #ifdef CONFIG_NL80211_TESTMODE 861 const struct mt76_testmode_ops *test_ops; 862 struct { 863 const char *name; 864 u32 offset; 865 } test_mtd; 866 #endif 867 struct workqueue_struct *wq; 868 869 union { 870 struct mt76_mmio mmio; 871 struct mt76_usb usb; 872 struct mt76_sdio sdio; 873 }; 874 }; 875 876 /* per-phy stats. */ 877 struct mt76_mib_stats { 878 u32 ack_fail_cnt; 879 u32 fcs_err_cnt; 880 u32 rts_cnt; 881 u32 rts_retries_cnt; 882 u32 ba_miss_cnt; 883 u32 tx_bf_cnt; 884 u32 tx_mu_bf_cnt; 885 u32 tx_mu_mpdu_cnt; 886 u32 tx_mu_acked_mpdu_cnt; 887 u32 tx_su_acked_mpdu_cnt; 888 u32 tx_bf_ibf_ppdu_cnt; 889 u32 tx_bf_ebf_ppdu_cnt; 890 891 u32 tx_bf_rx_fb_all_cnt; 892 u32 tx_bf_rx_fb_eht_cnt; 893 u32 tx_bf_rx_fb_he_cnt; 894 u32 tx_bf_rx_fb_vht_cnt; 895 u32 tx_bf_rx_fb_ht_cnt; 896 897 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 898 u32 tx_bf_rx_fb_nc_cnt; 899 u32 tx_bf_rx_fb_nr_cnt; 900 u32 tx_bf_fb_cpl_cnt; 901 u32 tx_bf_fb_trig_cnt; 902 903 u32 tx_ampdu_cnt; 904 u32 tx_stop_q_empty_cnt; 905 u32 tx_mpdu_attempts_cnt; 906 u32 tx_mpdu_success_cnt; 907 u32 tx_pkt_ebf_cnt; 908 u32 tx_pkt_ibf_cnt; 909 910 u32 tx_rwp_fail_cnt; 911 u32 tx_rwp_need_cnt; 912 913 /* rx stats */ 914 u32 rx_fifo_full_cnt; 915 u32 channel_idle_cnt; 916 u32 primary_cca_busy_time; 917 u32 secondary_cca_busy_time; 918 u32 primary_energy_detect_time; 919 u32 cck_mdrdy_time; 920 u32 ofdm_mdrdy_time; 921 u32 green_mdrdy_time; 922 u32 rx_vector_mismatch_cnt; 923 u32 rx_delimiter_fail_cnt; 924 u32 rx_mrdy_cnt; 925 u32 rx_len_mismatch_cnt; 926 u32 rx_mpdu_cnt; 927 u32 rx_ampdu_cnt; 928 u32 rx_ampdu_bytes_cnt; 929 u32 rx_ampdu_valid_subframe_cnt; 930 u32 rx_ampdu_valid_subframe_bytes_cnt; 931 u32 rx_pfdrop_cnt; 932 u32 rx_vec_queue_overflow_drop_cnt; 933 u32 rx_ba_cnt; 934 935 u32 tx_amsdu[8]; 936 u32 tx_amsdu_cnt; 937 938 /* mcu_muru_stats */ 939 u32 dl_cck_cnt; 940 u32 dl_ofdm_cnt; 941 u32 dl_htmix_cnt; 942 u32 dl_htgf_cnt; 943 u32 dl_vht_su_cnt; 944 u32 dl_vht_2mu_cnt; 945 u32 dl_vht_3mu_cnt; 946 u32 dl_vht_4mu_cnt; 947 u32 dl_he_su_cnt; 948 u32 dl_he_ext_su_cnt; 949 u32 dl_he_2ru_cnt; 950 u32 dl_he_2mu_cnt; 951 u32 dl_he_3ru_cnt; 952 u32 dl_he_3mu_cnt; 953 u32 dl_he_4ru_cnt; 954 u32 dl_he_4mu_cnt; 955 u32 dl_he_5to8ru_cnt; 956 u32 dl_he_9to16ru_cnt; 957 u32 dl_he_gtr16ru_cnt; 958 959 u32 ul_hetrig_su_cnt; 960 u32 ul_hetrig_2ru_cnt; 961 u32 ul_hetrig_3ru_cnt; 962 u32 ul_hetrig_4ru_cnt; 963 u32 ul_hetrig_5to8ru_cnt; 964 u32 ul_hetrig_9to16ru_cnt; 965 u32 ul_hetrig_gtr16ru_cnt; 966 u32 ul_hetrig_2mu_cnt; 967 u32 ul_hetrig_3mu_cnt; 968 u32 ul_hetrig_4mu_cnt; 969 }; 970 971 struct mt76_power_limits { 972 s8 cck[4]; 973 s8 ofdm[8]; 974 s8 mcs[4][10]; 975 s8 ru[7][12]; 976 s8 eht[16][16]; 977 }; 978 979 struct mt76_ethtool_worker_info { 980 u64 *data; 981 int idx; 982 int initial_stat_idx; 983 int worker_stat_count; 984 int sta_count; 985 }; 986 987 #define CCK_RATE(_idx, _rate) { \ 988 .bitrate = _rate, \ 989 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 990 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 991 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 992 } 993 994 #define OFDM_RATE(_idx, _rate) { \ 995 .bitrate = _rate, \ 996 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 997 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 998 } 999 1000 extern struct ieee80211_rate mt76_rates[12]; 1001 1002 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1003 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1004 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1005 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1006 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1007 1008 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1009 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1010 1011 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1012 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1013 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1014 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1015 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1016 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1017 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1018 1019 1020 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1021 1022 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1023 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1024 1025 #define mt76_get_field(_dev, _reg, _field) \ 1026 FIELD_GET(_field, mt76_rr(dev, _reg)) 1027 1028 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1029 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1030 1031 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1032 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1033 1034 #define mt76_hw(dev) (dev)->mphy.hw 1035 1036 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1037 int timeout); 1038 1039 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1040 1041 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1042 int timeout, int kick); 1043 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1044 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1045 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1046 1047 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1048 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1049 1050 static inline u16 mt76_chip(struct mt76_dev *dev) 1051 { 1052 return dev->rev >> 16; 1053 } 1054 1055 static inline u16 mt76_rev(struct mt76_dev *dev) 1056 { 1057 return dev->rev & 0xffff; 1058 } 1059 1060 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1061 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1062 1063 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1064 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1065 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1066 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 1067 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1068 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1069 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1070 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1071 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1072 1073 #define mt76_for_each_q_rx(dev, i) \ 1074 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1075 if ((dev)->q_rx[i].ndesc) 1076 1077 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1078 const struct ieee80211_ops *ops, 1079 const struct mt76_driver_ops *drv_ops); 1080 int mt76_register_device(struct mt76_dev *dev, bool vht, 1081 struct ieee80211_rate *rates, int n_rates); 1082 void mt76_unregister_device(struct mt76_dev *dev); 1083 void mt76_free_device(struct mt76_dev *dev); 1084 void mt76_unregister_phy(struct mt76_phy *phy); 1085 1086 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1087 const struct ieee80211_ops *ops, 1088 u8 band_idx); 1089 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1090 struct ieee80211_rate *rates, int n_rates); 1091 1092 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1093 const struct file_operations *ops); 1094 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1095 { 1096 return mt76_register_debugfs_fops(&dev->phy, NULL); 1097 } 1098 1099 int mt76_queues_read(struct seq_file *s, void *data); 1100 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1101 s8 *val, int len); 1102 1103 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1104 void mt76_eeprom_override(struct mt76_phy *phy); 1105 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 1106 1107 struct mt76_queue * 1108 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1109 int ring_base, u32 flags); 1110 u16 mt76_calculate_default_rate(struct mt76_phy *phy, 1111 struct ieee80211_vif *vif, int rateidx); 1112 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1113 int n_desc, int ring_base, u32 flags) 1114 { 1115 struct mt76_queue *q; 1116 1117 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 1118 if (IS_ERR(q)) 1119 return PTR_ERR(q); 1120 1121 phy->q_tx[qid] = q; 1122 1123 return 0; 1124 } 1125 1126 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1127 int n_desc, int ring_base) 1128 { 1129 struct mt76_queue *q; 1130 1131 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1132 if (IS_ERR(q)) 1133 return PTR_ERR(q); 1134 1135 dev->q_mcu[qid] = q; 1136 1137 return 0; 1138 } 1139 1140 static inline struct mt76_phy * 1141 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1142 { 1143 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1144 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1145 return dev->phys[phy_idx]; 1146 1147 return &dev->phy; 1148 } 1149 1150 static inline struct ieee80211_hw * 1151 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1152 { 1153 return mt76_dev_phy(dev, phy_idx)->hw; 1154 } 1155 1156 static inline u8 * 1157 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1158 { 1159 return (u8 *)t - dev->drv->txwi_size; 1160 } 1161 1162 /* increment with wrap-around */ 1163 static inline int mt76_incr(int val, int size) 1164 { 1165 return (val + 1) & (size - 1); 1166 } 1167 1168 /* decrement with wrap-around */ 1169 static inline int mt76_decr(int val, int size) 1170 { 1171 return (val - 1) & (size - 1); 1172 } 1173 1174 u8 mt76_ac_to_hwq(u8 ac); 1175 1176 static inline struct ieee80211_txq * 1177 mtxq_to_txq(struct mt76_txq *mtxq) 1178 { 1179 void *ptr = mtxq; 1180 1181 return container_of(ptr, struct ieee80211_txq, drv_priv); 1182 } 1183 1184 static inline struct ieee80211_sta * 1185 wcid_to_sta(struct mt76_wcid *wcid) 1186 { 1187 void *ptr = wcid; 1188 1189 if (!wcid || !wcid->sta) 1190 return NULL; 1191 1192 return container_of(ptr, struct ieee80211_sta, drv_priv); 1193 } 1194 1195 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1196 { 1197 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1198 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1199 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1200 } 1201 1202 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1203 { 1204 struct mt76_rx_status mstat; 1205 u8 *data = skb->data; 1206 1207 /* Alignment concerns */ 1208 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1209 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1210 1211 mstat = *((struct mt76_rx_status *)skb->cb); 1212 1213 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1214 data += sizeof(struct ieee80211_radiotap_he); 1215 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1216 data += sizeof(struct ieee80211_radiotap_he_mu); 1217 1218 return data; 1219 } 1220 1221 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1222 { 1223 int len = ieee80211_get_hdrlen_from_skb(skb); 1224 1225 if (len % 4 == 0) 1226 return; 1227 1228 skb_push(skb, 2); 1229 memmove(skb->data, skb->data + 2, len); 1230 1231 skb->data[len] = 0; 1232 skb->data[len + 1] = 0; 1233 } 1234 1235 static inline bool mt76_is_skb_pktid(u8 pktid) 1236 { 1237 if (pktid & MT_PACKET_ID_HAS_RATE) 1238 return false; 1239 1240 return pktid >= MT_PACKET_ID_FIRST; 1241 } 1242 1243 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1244 { 1245 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1246 u8 idx = nss - 1; 1247 1248 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1249 } 1250 1251 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1252 { 1253 #ifdef CONFIG_NL80211_TESTMODE 1254 return phy->test.state != MT76_TM_STATE_OFF; 1255 #else 1256 return false; 1257 #endif 1258 } 1259 1260 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1261 struct sk_buff *skb, 1262 struct ieee80211_hw **hw) 1263 { 1264 #ifdef CONFIG_NL80211_TESTMODE 1265 int i; 1266 1267 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1268 struct mt76_phy *phy = dev->phys[i]; 1269 1270 if (phy && skb == phy->test.tx_skb) { 1271 *hw = dev->phys[i]->hw; 1272 return true; 1273 } 1274 } 1275 return false; 1276 #else 1277 return false; 1278 #endif 1279 } 1280 1281 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1282 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1283 struct mt76_wcid *wcid, struct sk_buff *skb); 1284 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1285 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1286 bool send_bar); 1287 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1288 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1289 void mt76_txq_schedule_all(struct mt76_phy *phy); 1290 void mt76_tx_worker_run(struct mt76_dev *dev); 1291 void mt76_tx_worker(struct mt76_worker *w); 1292 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1293 struct ieee80211_sta *sta, 1294 u16 tids, int nframes, 1295 enum ieee80211_frame_release_type reason, 1296 bool more_data); 1297 bool mt76_has_tx_pending(struct mt76_phy *phy); 1298 void mt76_set_channel(struct mt76_phy *phy); 1299 void mt76_update_survey(struct mt76_phy *phy); 1300 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1301 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1302 struct survey_info *survey); 1303 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1304 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1305 1306 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1307 u16 ssn, u16 size); 1308 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1309 1310 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1311 struct ieee80211_key_conf *key); 1312 1313 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1314 __acquires(&dev->status_lock); 1315 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1316 __releases(&dev->status_lock); 1317 1318 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1319 struct sk_buff *skb); 1320 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1321 struct mt76_wcid *wcid, int pktid, 1322 struct sk_buff_head *list); 1323 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1324 struct sk_buff_head *list); 1325 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1326 struct list_head *free_list); 1327 static inline void 1328 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1329 { 1330 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1331 } 1332 1333 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1334 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1335 struct ieee80211_sta *sta, 1336 enum ieee80211_sta_state old_state, 1337 enum ieee80211_sta_state new_state); 1338 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1339 struct ieee80211_sta *sta); 1340 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1341 struct ieee80211_sta *sta); 1342 1343 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1344 1345 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1346 int *dbm); 1347 int mt76_init_sar_power(struct ieee80211_hw *hw, 1348 const struct cfg80211_sar_specs *sar); 1349 int mt76_get_sar_power(struct mt76_phy *phy, 1350 struct ieee80211_channel *chan, 1351 int power); 1352 1353 void mt76_csa_check(struct mt76_dev *dev); 1354 void mt76_csa_finish(struct mt76_dev *dev); 1355 1356 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1357 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1358 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1359 int mt76_get_rate(struct mt76_dev *dev, 1360 struct ieee80211_supported_band *sband, 1361 int idx, bool cck); 1362 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1363 const u8 *mac); 1364 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1365 struct ieee80211_vif *vif); 1366 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1367 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1368 void *data, int len); 1369 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1370 struct netlink_callback *cb, void *data, int len); 1371 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1372 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1373 1374 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1375 { 1376 #ifdef CONFIG_NL80211_TESTMODE 1377 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1378 1379 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1380 state = MT76_TM_STATE_OFF; 1381 1382 mt76_testmode_set_state(phy, state); 1383 #endif 1384 } 1385 1386 1387 /* internal */ 1388 static inline struct ieee80211_hw * 1389 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1390 { 1391 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1392 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1393 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1394 1395 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1396 1397 return hw; 1398 } 1399 1400 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1401 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1402 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1403 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1404 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1405 struct napi_struct *napi); 1406 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1407 struct napi_struct *napi); 1408 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1409 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1410 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1411 struct mt76_queue_entry *e); 1412 1413 /* usb */ 1414 static inline bool mt76u_urb_error(struct urb *urb) 1415 { 1416 return urb->status && 1417 urb->status != -ECONNRESET && 1418 urb->status != -ESHUTDOWN && 1419 urb->status != -ENOENT; 1420 } 1421 1422 /* Map hardware queues to usb endpoints */ 1423 static inline u8 q2ep(u8 qid) 1424 { 1425 /* TODO: take management packets to queue 5 */ 1426 return qid + 1; 1427 } 1428 1429 static inline int 1430 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1431 int timeout, int ep) 1432 { 1433 struct usb_interface *uintf = to_usb_interface(dev->dev); 1434 struct usb_device *udev = interface_to_usbdev(uintf); 1435 struct mt76_usb *usb = &dev->usb; 1436 unsigned int pipe; 1437 1438 if (actual_len) 1439 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1440 else 1441 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1442 1443 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1444 } 1445 1446 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1447 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1448 struct mt76_sta_stats *stats, bool eht); 1449 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1450 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1451 u16 val, u16 offset, void *buf, size_t len); 1452 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1453 u8 req_type, u16 val, u16 offset, 1454 void *buf, size_t len); 1455 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1456 const u16 offset, const u32 val); 1457 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1458 void *data, int len); 1459 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1460 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1461 u32 addr, u32 val); 1462 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1463 struct mt76_bus_ops *ops); 1464 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1465 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1466 int mt76u_alloc_queues(struct mt76_dev *dev); 1467 void mt76u_stop_tx(struct mt76_dev *dev); 1468 void mt76u_stop_rx(struct mt76_dev *dev); 1469 int mt76u_resume_rx(struct mt76_dev *dev); 1470 void mt76u_queues_deinit(struct mt76_dev *dev); 1471 1472 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1473 const struct mt76_bus_ops *bus_ops); 1474 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1475 int mt76s_alloc_tx(struct mt76_dev *dev); 1476 void mt76s_deinit(struct mt76_dev *dev); 1477 void mt76s_sdio_irq(struct sdio_func *func); 1478 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1479 bool mt76s_txqs_empty(struct mt76_dev *dev); 1480 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1481 int hw_ver); 1482 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1483 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1484 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1485 u32 mt76s_read_pcr(struct mt76_dev *dev); 1486 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1487 const void *data, int len); 1488 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1489 void *data, int len); 1490 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1491 const struct mt76_reg_pair *data, 1492 int len); 1493 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1494 struct mt76_reg_pair *data, int len); 1495 1496 struct sk_buff * 1497 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1498 int len, int data_len, gfp_t gfp); 1499 static inline struct sk_buff * 1500 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1501 int data_len) 1502 { 1503 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1504 } 1505 1506 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1507 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1508 unsigned long expires); 1509 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1510 int len, bool wait_resp, struct sk_buff **ret); 1511 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1512 int cmd, bool wait_resp, struct sk_buff **ret); 1513 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1514 int len, int max_len); 1515 static inline int 1516 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1517 int len) 1518 { 1519 int max_len = 4096 - dev->mcu_ops->headroom; 1520 1521 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1522 } 1523 1524 static inline int 1525 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1526 bool wait_resp) 1527 { 1528 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1529 } 1530 1531 static inline int 1532 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1533 bool wait_resp) 1534 { 1535 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1536 } 1537 1538 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1539 1540 struct device_node * 1541 mt76_find_power_limits_node(struct mt76_dev *dev); 1542 struct device_node * 1543 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan); 1544 1545 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1546 struct ieee80211_channel *chan, 1547 struct mt76_power_limits *dest, 1548 s8 target_power); 1549 1550 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1551 { 1552 return (q->flags & MT_QFLAG_WED) && 1553 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1554 } 1555 1556 struct mt76_txwi_cache * 1557 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1558 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1559 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1560 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1561 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1562 struct mt76_txwi_cache *r, dma_addr_t phys); 1563 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1564 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1565 { 1566 struct page *page = virt_to_head_page(buf); 1567 1568 page_pool_put_full_page(page->pp, page, allow_direct); 1569 } 1570 1571 static inline void * 1572 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1573 { 1574 struct page *page; 1575 1576 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1577 if (!page) 1578 return NULL; 1579 1580 return page_address(page) + *offset; 1581 } 1582 1583 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1584 { 1585 spin_lock_bh(&dev->token_lock); 1586 __mt76_set_tx_blocked(dev, blocked); 1587 spin_unlock_bh(&dev->token_lock); 1588 } 1589 1590 static inline int 1591 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1592 { 1593 int token; 1594 1595 spin_lock_bh(&dev->token_lock); 1596 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1597 spin_unlock_bh(&dev->token_lock); 1598 1599 return token; 1600 } 1601 1602 static inline struct mt76_txwi_cache * 1603 mt76_token_put(struct mt76_dev *dev, int token) 1604 { 1605 struct mt76_txwi_cache *txwi; 1606 1607 spin_lock_bh(&dev->token_lock); 1608 txwi = idr_remove(&dev->token, token); 1609 spin_unlock_bh(&dev->token_lock); 1610 1611 return txwi; 1612 } 1613 1614 void mt76_wcid_init(struct mt76_wcid *wcid); 1615 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid); 1616 1617 #endif 1618