1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 #include "testmode.h" 19 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 128 23 24 #define MT_MAX_NON_AQL_PKT 16 25 #define MT_TXQ_FREE_THR 32 26 27 struct mt76_dev; 28 struct mt76_phy; 29 struct mt76_wcid; 30 31 struct mt76_reg_pair { 32 u32 reg; 33 u32 value; 34 }; 35 36 enum mt76_bus_type { 37 MT76_BUS_MMIO, 38 MT76_BUS_USB, 39 MT76_BUS_SDIO, 40 }; 41 42 struct mt76_bus_ops { 43 u32 (*rr)(struct mt76_dev *dev, u32 offset); 44 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 45 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 46 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 47 int len); 48 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 49 int len); 50 int (*wr_rp)(struct mt76_dev *dev, u32 base, 51 const struct mt76_reg_pair *rp, int len); 52 int (*rd_rp)(struct mt76_dev *dev, u32 base, 53 struct mt76_reg_pair *rp, int len); 54 enum mt76_bus_type type; 55 }; 56 57 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 58 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 59 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 60 61 enum mt76_txq_id { 62 MT_TXQ_VO = IEEE80211_AC_VO, 63 MT_TXQ_VI = IEEE80211_AC_VI, 64 MT_TXQ_BE = IEEE80211_AC_BE, 65 MT_TXQ_BK = IEEE80211_AC_BK, 66 MT_TXQ_PSD, 67 MT_TXQ_BEACON, 68 MT_TXQ_CAB, 69 __MT_TXQ_MAX 70 }; 71 72 enum mt76_mcuq_id { 73 MT_MCUQ_WM, 74 MT_MCUQ_WA, 75 MT_MCUQ_FWDL, 76 __MT_MCUQ_MAX 77 }; 78 79 enum mt76_rxq_id { 80 MT_RXQ_MAIN, 81 MT_RXQ_MCU, 82 MT_RXQ_MCU_WA, 83 MT_RXQ_EXT, 84 __MT_RXQ_MAX 85 }; 86 87 struct mt76_queue_buf { 88 dma_addr_t addr; 89 u16 len; 90 bool skip_unmap; 91 }; 92 93 struct mt76_tx_info { 94 struct mt76_queue_buf buf[32]; 95 struct sk_buff *skb; 96 int nbuf; 97 u32 info; 98 }; 99 100 struct mt76_queue_entry { 101 union { 102 void *buf; 103 struct sk_buff *skb; 104 }; 105 union { 106 struct mt76_txwi_cache *txwi; 107 struct urb *urb; 108 int buf_sz; 109 }; 110 u32 dma_addr[2]; 111 u16 dma_len[2]; 112 u16 wcid; 113 bool skip_buf0:1; 114 bool skip_buf1:1; 115 bool done:1; 116 }; 117 118 struct mt76_queue_regs { 119 u32 desc_base; 120 u32 ring_size; 121 u32 cpu_idx; 122 u32 dma_idx; 123 } __packed __aligned(4); 124 125 struct mt76_queue { 126 struct mt76_queue_regs __iomem *regs; 127 128 spinlock_t lock; 129 spinlock_t cleanup_lock; 130 struct mt76_queue_entry *entry; 131 struct mt76_desc *desc; 132 133 u16 first; 134 u16 head; 135 u16 tail; 136 int ndesc; 137 int queued; 138 int buf_size; 139 bool stopped; 140 bool blocked; 141 142 u8 buf_offset; 143 u8 hw_idx; 144 u8 qid; 145 146 dma_addr_t desc_dma; 147 struct sk_buff *rx_head; 148 struct page_frag_cache rx_page; 149 }; 150 151 struct mt76_mcu_ops { 152 u32 headroom; 153 u32 tailroom; 154 155 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 156 int len, bool wait_resp); 157 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 158 int cmd, int *seq); 159 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 160 struct sk_buff *skb, int seq); 161 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 162 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 163 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 164 const struct mt76_reg_pair *rp, int len); 165 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 166 struct mt76_reg_pair *rp, int len); 167 int (*mcu_restart)(struct mt76_dev *dev); 168 }; 169 170 struct mt76_queue_ops { 171 int (*init)(struct mt76_dev *dev); 172 173 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 174 int idx, int n_desc, int bufsize, 175 u32 ring_base); 176 177 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 178 struct sk_buff *skb, struct mt76_wcid *wcid, 179 struct ieee80211_sta *sta); 180 181 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 182 struct sk_buff *skb, u32 tx_info); 183 184 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 185 int *len, u32 *info, bool *more); 186 187 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 188 189 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 190 bool flush); 191 192 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 193 }; 194 195 enum mt76_wcid_flags { 196 MT_WCID_FLAG_CHECK_PS, 197 MT_WCID_FLAG_PS, 198 MT_WCID_FLAG_4ADDR, 199 }; 200 201 #define MT76_N_WCIDS 288 202 203 /* stored in ieee80211_tx_info::hw_queue */ 204 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 205 206 DECLARE_EWMA(signal, 10, 8); 207 208 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 209 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 210 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 211 #define MT_WCID_TX_INFO_SET BIT(31) 212 213 struct mt76_wcid { 214 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 215 216 atomic_t non_aql_packets; 217 unsigned long flags; 218 219 struct ewma_signal rssi; 220 int inactive_count; 221 222 u16 idx; 223 u8 hw_key_idx; 224 225 u8 sta:1; 226 u8 ext_phy:1; 227 u8 amsdu:1; 228 229 u8 rx_check_pn; 230 u8 rx_key_pn[IEEE80211_NUM_TIDS][6]; 231 u16 cipher; 232 233 u32 tx_info; 234 bool sw_iv; 235 236 u8 packet_id; 237 }; 238 239 struct mt76_txq { 240 struct mt76_wcid *wcid; 241 242 u16 agg_ssn; 243 bool send_bar; 244 bool aggr; 245 }; 246 247 struct mt76_txwi_cache { 248 struct list_head list; 249 dma_addr_t dma_addr; 250 251 struct sk_buff *skb; 252 }; 253 254 struct mt76_rx_tid { 255 struct rcu_head rcu_head; 256 257 struct mt76_dev *dev; 258 259 spinlock_t lock; 260 struct delayed_work reorder_work; 261 262 u16 head; 263 u16 size; 264 u16 nframes; 265 266 u8 num; 267 268 u8 started:1, stopped:1, timer_pending:1; 269 270 struct sk_buff *reorder_buf[]; 271 }; 272 273 #define MT_TX_CB_DMA_DONE BIT(0) 274 #define MT_TX_CB_TXS_DONE BIT(1) 275 #define MT_TX_CB_TXS_FAILED BIT(2) 276 277 #define MT_PACKET_ID_MASK GENMASK(6, 0) 278 #define MT_PACKET_ID_NO_ACK 0 279 #define MT_PACKET_ID_NO_SKB 1 280 #define MT_PACKET_ID_FIRST 2 281 #define MT_PACKET_ID_HAS_RATE BIT(7) 282 283 #define MT_TX_STATUS_SKB_TIMEOUT HZ 284 285 struct mt76_tx_cb { 286 unsigned long jiffies; 287 u16 wcid; 288 u8 pktid; 289 u8 flags; 290 }; 291 292 enum { 293 MT76_STATE_INITIALIZED, 294 MT76_STATE_RUNNING, 295 MT76_STATE_MCU_RUNNING, 296 MT76_SCANNING, 297 MT76_HW_SCANNING, 298 MT76_HW_SCHED_SCANNING, 299 MT76_RESTART, 300 MT76_RESET, 301 MT76_MCU_RESET, 302 MT76_REMOVED, 303 MT76_READING_STATS, 304 MT76_STATE_POWER_OFF, 305 MT76_STATE_SUSPEND, 306 MT76_STATE_ROC, 307 MT76_STATE_PM, 308 }; 309 310 struct mt76_hw_cap { 311 bool has_2ghz; 312 bool has_5ghz; 313 }; 314 315 #define MT_DRV_TXWI_NO_FREE BIT(0) 316 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 317 #define MT_DRV_SW_RX_AIRTIME BIT(2) 318 #define MT_DRV_RX_DMA_HDR BIT(3) 319 #define MT_DRV_HW_MGMT_TXQ BIT(4) 320 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 321 322 struct mt76_driver_ops { 323 u32 drv_flags; 324 u32 survey_flags; 325 u16 txwi_size; 326 327 void (*update_survey)(struct mt76_dev *dev); 328 329 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 330 enum mt76_txq_id qid, struct mt76_wcid *wcid, 331 struct ieee80211_sta *sta, 332 struct mt76_tx_info *tx_info); 333 334 void (*tx_complete_skb)(struct mt76_dev *dev, 335 struct mt76_queue_entry *e); 336 337 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 338 339 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 340 struct sk_buff *skb); 341 342 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 343 344 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 345 bool ps); 346 347 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 348 struct ieee80211_sta *sta); 349 350 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 351 struct ieee80211_sta *sta); 352 353 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 354 struct ieee80211_sta *sta); 355 }; 356 357 struct mt76_channel_state { 358 u64 cc_active; 359 u64 cc_busy; 360 u64 cc_rx; 361 u64 cc_bss_rx; 362 u64 cc_tx; 363 364 s8 noise; 365 }; 366 367 struct mt76_sband { 368 struct ieee80211_supported_band sband; 369 struct mt76_channel_state *chan; 370 }; 371 372 struct mt76_rate_power { 373 union { 374 struct { 375 s8 cck[4]; 376 s8 ofdm[8]; 377 s8 stbc[10]; 378 s8 ht[16]; 379 s8 vht[10]; 380 }; 381 s8 all[48]; 382 }; 383 }; 384 385 /* addr req mask */ 386 #define MT_VEND_TYPE_EEPROM BIT(31) 387 #define MT_VEND_TYPE_CFG BIT(30) 388 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 389 390 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 391 enum mt_vendor_req { 392 MT_VEND_DEV_MODE = 0x1, 393 MT_VEND_WRITE = 0x2, 394 MT_VEND_POWER_ON = 0x4, 395 MT_VEND_MULTI_WRITE = 0x6, 396 MT_VEND_MULTI_READ = 0x7, 397 MT_VEND_READ_EEPROM = 0x9, 398 MT_VEND_WRITE_FCE = 0x42, 399 MT_VEND_WRITE_CFG = 0x46, 400 MT_VEND_READ_CFG = 0x47, 401 MT_VEND_READ_EXT = 0x63, 402 MT_VEND_WRITE_EXT = 0x66, 403 MT_VEND_FEATURE_SET = 0x91, 404 }; 405 406 enum mt76u_in_ep { 407 MT_EP_IN_PKT_RX, 408 MT_EP_IN_CMD_RESP, 409 __MT_EP_IN_MAX, 410 }; 411 412 enum mt76u_out_ep { 413 MT_EP_OUT_INBAND_CMD, 414 MT_EP_OUT_AC_BE, 415 MT_EP_OUT_AC_BK, 416 MT_EP_OUT_AC_VI, 417 MT_EP_OUT_AC_VO, 418 MT_EP_OUT_HCCA, 419 __MT_EP_OUT_MAX, 420 }; 421 422 struct mt76_mcu { 423 struct mutex mutex; 424 u32 msg_seq; 425 int timeout; 426 427 struct sk_buff_head res_q; 428 wait_queue_head_t wait; 429 }; 430 431 #define MT_TX_SG_MAX_SIZE 8 432 #define MT_RX_SG_MAX_SIZE 4 433 #define MT_NUM_TX_ENTRIES 256 434 #define MT_NUM_RX_ENTRIES 128 435 #define MCU_RESP_URB_SIZE 1024 436 struct mt76_usb { 437 struct mutex usb_ctrl_mtx; 438 u8 *data; 439 u16 data_len; 440 441 struct mt76_worker status_worker; 442 struct mt76_worker rx_worker; 443 444 struct work_struct stat_work; 445 446 u8 out_ep[__MT_EP_OUT_MAX]; 447 u8 in_ep[__MT_EP_IN_MAX]; 448 bool sg_en; 449 450 struct mt76u_mcu { 451 u8 *data; 452 /* multiple reads */ 453 struct mt76_reg_pair *rp; 454 int rp_len; 455 u32 base; 456 bool burst; 457 } mcu; 458 }; 459 460 #define MT76S_XMIT_BUF_SZ (16 * PAGE_SIZE) 461 struct mt76_sdio { 462 struct mt76_worker txrx_worker; 463 struct mt76_worker status_worker; 464 struct mt76_worker net_worker; 465 466 struct work_struct stat_work; 467 468 u8 *xmit_buf[IEEE80211_NUM_ACS + 2]; 469 470 struct sdio_func *func; 471 void *intr_data; 472 473 struct { 474 int pse_data_quota; 475 int ple_data_quota; 476 int pse_mcu_quota; 477 int deficit; 478 } sched; 479 }; 480 481 struct mt76_mmio { 482 void __iomem *regs; 483 spinlock_t irq_lock; 484 u32 irqmask; 485 }; 486 487 struct mt76_rx_status { 488 union { 489 struct mt76_wcid *wcid; 490 u16 wcid_idx; 491 }; 492 493 unsigned long reorder_time; 494 495 u32 ampdu_ref; 496 497 u8 iv[6]; 498 499 u8 ext_phy:1; 500 u8 aggr:1; 501 u8 tid; 502 u16 seqno; 503 504 u16 freq; 505 u32 flag; 506 u8 enc_flags; 507 u8 encoding:2, bw:3, he_ru:3; 508 u8 he_gi:2, he_dcm:1; 509 u8 rate_idx; 510 u8 nss; 511 u8 band; 512 s8 signal; 513 u8 chains; 514 s8 chain_signal[IEEE80211_MAX_CHAINS]; 515 }; 516 517 struct mt76_testmode_ops { 518 int (*set_state)(struct mt76_dev *dev, enum mt76_testmode_state state); 519 int (*set_params)(struct mt76_dev *dev, struct nlattr **tb, 520 enum mt76_testmode_state new_state); 521 int (*dump_stats)(struct mt76_dev *dev, struct sk_buff *msg); 522 }; 523 524 struct mt76_testmode_data { 525 enum mt76_testmode_state state; 526 527 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 528 struct sk_buff *tx_skb; 529 530 u32 tx_count; 531 u16 tx_msdu_len; 532 533 u8 tx_rate_mode; 534 u8 tx_rate_idx; 535 u8 tx_rate_nss; 536 u8 tx_rate_sgi; 537 u8 tx_rate_ldpc; 538 u8 tx_rate_stbc; 539 u8 tx_ltf; 540 541 u8 tx_antenna_mask; 542 543 u32 freq_offset; 544 545 u8 tx_power[4]; 546 u8 tx_power_control; 547 548 const char *mtd_name; 549 u32 mtd_offset; 550 551 u32 tx_pending; 552 u32 tx_queued; 553 u32 tx_done; 554 struct { 555 u64 packets[__MT_RXQ_MAX]; 556 u64 fcs_error[__MT_RXQ_MAX]; 557 } rx_stats; 558 }; 559 560 struct mt76_phy { 561 struct ieee80211_hw *hw; 562 struct mt76_dev *dev; 563 void *priv; 564 565 unsigned long state; 566 567 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 568 569 struct cfg80211_chan_def chandef; 570 struct ieee80211_channel *main_chan; 571 572 struct mt76_channel_state *chan_state; 573 ktime_t survey_time; 574 575 struct mt76_hw_cap cap; 576 struct mt76_sband sband_2g; 577 struct mt76_sband sband_5g; 578 579 u8 macaddr[ETH_ALEN]; 580 581 u32 vif_mask; 582 583 int txpower_cur; 584 u8 antenna_mask; 585 }; 586 587 struct mt76_dev { 588 struct mt76_phy phy; /* must be first */ 589 590 struct mt76_phy *phy2; 591 592 struct ieee80211_hw *hw; 593 594 spinlock_t lock; 595 spinlock_t cc_lock; 596 597 u32 cur_cc_bss_rx; 598 599 struct mt76_rx_status rx_ampdu_status; 600 u32 rx_ampdu_len; 601 u32 rx_ampdu_ref; 602 603 struct mutex mutex; 604 605 const struct mt76_bus_ops *bus; 606 const struct mt76_driver_ops *drv; 607 const struct mt76_mcu_ops *mcu_ops; 608 struct device *dev; 609 610 struct mt76_mcu mcu; 611 612 struct net_device napi_dev; 613 spinlock_t rx_lock; 614 struct napi_struct napi[__MT_RXQ_MAX]; 615 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 616 617 struct list_head txwi_cache; 618 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 619 struct mt76_queue q_rx[__MT_RXQ_MAX]; 620 const struct mt76_queue_ops *queue_ops; 621 int tx_dma_idx[4]; 622 623 struct mt76_worker tx_worker; 624 struct napi_struct tx_napi; 625 struct delayed_work mac_work; 626 627 wait_queue_head_t tx_wait; 628 struct sk_buff_head status_list; 629 630 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 631 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 632 633 struct mt76_wcid global_wcid; 634 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 635 636 u32 rev; 637 638 u32 aggr_stats[32]; 639 640 struct tasklet_struct pre_tbtt_tasklet; 641 int beacon_int; 642 u8 beacon_mask; 643 644 struct debugfs_blob_wrapper eeprom; 645 struct debugfs_blob_wrapper otp; 646 647 struct mt76_rate_power rate_power; 648 649 enum nl80211_dfs_regions region; 650 651 u32 debugfs_reg; 652 653 struct led_classdev led_cdev; 654 char led_name[32]; 655 bool led_al; 656 u8 led_pin; 657 658 u8 csa_complete; 659 660 u32 rxfilter; 661 662 #ifdef CONFIG_NL80211_TESTMODE 663 const struct mt76_testmode_ops *test_ops; 664 struct mt76_testmode_data test; 665 #endif 666 667 struct workqueue_struct *wq; 668 669 union { 670 struct mt76_mmio mmio; 671 struct mt76_usb usb; 672 struct mt76_sdio sdio; 673 }; 674 }; 675 676 enum mt76_phy_type { 677 MT_PHY_TYPE_CCK, 678 MT_PHY_TYPE_OFDM, 679 MT_PHY_TYPE_HT, 680 MT_PHY_TYPE_HT_GF, 681 MT_PHY_TYPE_VHT, 682 MT_PHY_TYPE_HE_SU = 8, 683 MT_PHY_TYPE_HE_EXT_SU, 684 MT_PHY_TYPE_HE_TB, 685 MT_PHY_TYPE_HE_MU, 686 }; 687 688 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 689 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 690 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 691 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 692 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 693 694 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 695 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 696 697 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 698 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 699 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 700 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 701 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 702 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 703 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 704 705 706 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 707 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 708 709 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 710 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 711 712 #define mt76_get_field(_dev, _reg, _field) \ 713 FIELD_GET(_field, mt76_rr(dev, _reg)) 714 715 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 716 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 717 718 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 719 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 720 721 #define mt76_hw(dev) (dev)->mphy.hw 722 723 static inline struct ieee80211_hw * 724 mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) 725 { 726 if (wcid <= MT76_N_WCIDS && 727 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 728 return dev->phy2->hw; 729 730 return dev->phy.hw; 731 } 732 733 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 734 int timeout); 735 736 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 737 738 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 739 int timeout); 740 741 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 742 743 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 744 void mt76_pci_disable_aspm(struct pci_dev *pdev); 745 746 static inline u16 mt76_chip(struct mt76_dev *dev) 747 { 748 return dev->rev >> 16; 749 } 750 751 static inline u16 mt76_rev(struct mt76_dev *dev) 752 { 753 return dev->rev & 0xffff; 754 } 755 756 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 757 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 758 759 #define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76)) 760 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 761 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 762 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 763 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 764 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 765 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 766 767 #define mt76_for_each_q_rx(dev, i) \ 768 for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \ 769 (dev)->q_rx[i].ndesc; i++) 770 771 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 772 const struct ieee80211_ops *ops, 773 const struct mt76_driver_ops *drv_ops); 774 int mt76_register_device(struct mt76_dev *dev, bool vht, 775 struct ieee80211_rate *rates, int n_rates); 776 void mt76_unregister_device(struct mt76_dev *dev); 777 void mt76_free_device(struct mt76_dev *dev); 778 void mt76_unregister_phy(struct mt76_phy *phy); 779 780 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 781 const struct ieee80211_ops *ops); 782 int mt76_register_phy(struct mt76_phy *phy, bool vht, 783 struct ieee80211_rate *rates, int n_rates); 784 785 struct dentry *mt76_register_debugfs(struct mt76_dev *dev); 786 int mt76_queues_read(struct seq_file *s, void *data); 787 void mt76_seq_puts_array(struct seq_file *file, const char *str, 788 s8 *val, int len); 789 790 int mt76_eeprom_init(struct mt76_dev *dev, int len); 791 void mt76_eeprom_override(struct mt76_phy *phy); 792 793 struct mt76_queue * 794 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 795 int ring_base); 796 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 797 int n_desc, int ring_base) 798 { 799 struct mt76_queue *q; 800 801 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base); 802 if (IS_ERR(q)) 803 return PTR_ERR(q); 804 805 q->qid = qid; 806 phy->q_tx[qid] = q; 807 808 return 0; 809 } 810 811 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 812 int n_desc, int ring_base) 813 { 814 struct mt76_queue *q; 815 816 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base); 817 if (IS_ERR(q)) 818 return PTR_ERR(q); 819 820 q->qid = __MT_TXQ_MAX + qid; 821 dev->q_mcu[qid] = q; 822 823 return 0; 824 } 825 826 static inline struct mt76_phy * 827 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 828 { 829 if (phy_ext && dev->phy2) 830 return dev->phy2; 831 return &dev->phy; 832 } 833 834 static inline struct ieee80211_hw * 835 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 836 { 837 return mt76_dev_phy(dev, phy_ext)->hw; 838 } 839 840 static inline u8 * 841 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 842 { 843 return (u8 *)t - dev->drv->txwi_size; 844 } 845 846 /* increment with wrap-around */ 847 static inline int mt76_incr(int val, int size) 848 { 849 return (val + 1) & (size - 1); 850 } 851 852 /* decrement with wrap-around */ 853 static inline int mt76_decr(int val, int size) 854 { 855 return (val - 1) & (size - 1); 856 } 857 858 u8 mt76_ac_to_hwq(u8 ac); 859 860 static inline struct ieee80211_txq * 861 mtxq_to_txq(struct mt76_txq *mtxq) 862 { 863 void *ptr = mtxq; 864 865 return container_of(ptr, struct ieee80211_txq, drv_priv); 866 } 867 868 static inline struct ieee80211_sta * 869 wcid_to_sta(struct mt76_wcid *wcid) 870 { 871 void *ptr = wcid; 872 873 if (!wcid || !wcid->sta) 874 return NULL; 875 876 return container_of(ptr, struct ieee80211_sta, drv_priv); 877 } 878 879 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 880 { 881 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 882 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 883 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 884 } 885 886 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 887 { 888 struct mt76_rx_status mstat; 889 u8 *data = skb->data; 890 891 /* Alignment concerns */ 892 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 893 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 894 895 mstat = *((struct mt76_rx_status *)skb->cb); 896 897 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 898 data += sizeof(struct ieee80211_radiotap_he); 899 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 900 data += sizeof(struct ieee80211_radiotap_he_mu); 901 902 return data; 903 } 904 905 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 906 { 907 int len = ieee80211_get_hdrlen_from_skb(skb); 908 909 if (len % 4 == 0) 910 return; 911 912 skb_push(skb, 2); 913 memmove(skb->data, skb->data + 2, len); 914 915 skb->data[len] = 0; 916 skb->data[len + 1] = 0; 917 } 918 919 static inline bool mt76_is_skb_pktid(u8 pktid) 920 { 921 if (pktid & MT_PACKET_ID_HAS_RATE) 922 return false; 923 924 return pktid >= MT_PACKET_ID_FIRST; 925 } 926 927 static inline u8 mt76_tx_power_nss_delta(u8 nss) 928 { 929 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 930 931 return nss_delta[nss - 1]; 932 } 933 934 static inline bool mt76_testmode_enabled(struct mt76_dev *dev) 935 { 936 #ifdef CONFIG_NL80211_TESTMODE 937 return dev->test.state != MT76_TM_STATE_OFF; 938 #else 939 return false; 940 #endif 941 } 942 943 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 944 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 945 struct mt76_wcid *wcid, struct sk_buff *skb); 946 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 947 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 948 bool send_bar); 949 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 950 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 951 void mt76_txq_schedule_all(struct mt76_phy *phy); 952 void mt76_tx_worker(struct mt76_worker *w); 953 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 954 struct ieee80211_sta *sta, 955 u16 tids, int nframes, 956 enum ieee80211_frame_release_type reason, 957 bool more_data); 958 bool mt76_has_tx_pending(struct mt76_phy *phy); 959 void mt76_set_channel(struct mt76_phy *phy); 960 void mt76_update_survey(struct mt76_dev *dev); 961 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 962 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 963 struct survey_info *survey); 964 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 965 966 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 967 u16 ssn, u16 size); 968 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 969 970 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 971 struct ieee80211_key_conf *key); 972 973 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 974 __acquires(&dev->status_list.lock); 975 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 976 __releases(&dev->status_list.lock); 977 978 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 979 struct sk_buff *skb); 980 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 981 struct mt76_wcid *wcid, int pktid, 982 struct sk_buff_head *list); 983 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 984 struct sk_buff_head *list); 985 void mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb); 986 void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, 987 bool flush); 988 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 989 struct ieee80211_sta *sta, 990 enum ieee80211_sta_state old_state, 991 enum ieee80211_sta_state new_state); 992 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 993 struct ieee80211_sta *sta); 994 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 995 struct ieee80211_sta *sta); 996 997 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 998 999 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1000 int *dbm); 1001 1002 void mt76_csa_check(struct mt76_dev *dev); 1003 void mt76_csa_finish(struct mt76_dev *dev); 1004 1005 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1006 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1007 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1008 int mt76_get_rate(struct mt76_dev *dev, 1009 struct ieee80211_supported_band *sband, 1010 int idx, bool cck); 1011 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1012 const u8 *mac); 1013 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1014 struct ieee80211_vif *vif); 1015 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1016 void *data, int len); 1017 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1018 struct netlink_callback *cb, void *data, int len); 1019 int mt76_testmode_set_state(struct mt76_dev *dev, enum mt76_testmode_state state); 1020 1021 static inline void mt76_testmode_reset(struct mt76_dev *dev, bool disable) 1022 { 1023 #ifdef CONFIG_NL80211_TESTMODE 1024 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1025 1026 if (disable || dev->test.state == MT76_TM_STATE_OFF) 1027 state = MT76_TM_STATE_OFF; 1028 1029 mt76_testmode_set_state(dev, state); 1030 #endif 1031 } 1032 1033 1034 /* internal */ 1035 static inline struct ieee80211_hw * 1036 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1037 { 1038 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1039 struct ieee80211_hw *hw = dev->phy.hw; 1040 1041 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 1042 hw = dev->phy2->hw; 1043 1044 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 1045 1046 return hw; 1047 } 1048 1049 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1050 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1051 struct napi_struct *napi); 1052 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1053 struct napi_struct *napi); 1054 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1055 void mt76_testmode_tx_pending(struct mt76_dev *dev); 1056 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1057 struct mt76_queue_entry *e); 1058 1059 /* usb */ 1060 static inline bool mt76u_urb_error(struct urb *urb) 1061 { 1062 return urb->status && 1063 urb->status != -ECONNRESET && 1064 urb->status != -ESHUTDOWN && 1065 urb->status != -ENOENT; 1066 } 1067 1068 /* Map hardware queues to usb endpoints */ 1069 static inline u8 q2ep(u8 qid) 1070 { 1071 /* TODO: take management packets to queue 5 */ 1072 return qid + 1; 1073 } 1074 1075 static inline int 1076 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1077 int timeout, int ep) 1078 { 1079 struct usb_interface *uintf = to_usb_interface(dev->dev); 1080 struct usb_device *udev = interface_to_usbdev(uintf); 1081 struct mt76_usb *usb = &dev->usb; 1082 unsigned int pipe; 1083 1084 if (actual_len) 1085 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1086 else 1087 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1088 1089 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1090 } 1091 1092 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1093 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1094 u8 req_type, u16 val, u16 offset, 1095 void *buf, size_t len); 1096 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1097 const u16 offset, const u32 val); 1098 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1099 bool ext); 1100 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1101 int mt76u_alloc_queues(struct mt76_dev *dev); 1102 void mt76u_stop_tx(struct mt76_dev *dev); 1103 void mt76u_stop_rx(struct mt76_dev *dev); 1104 int mt76u_resume_rx(struct mt76_dev *dev); 1105 void mt76u_queues_deinit(struct mt76_dev *dev); 1106 1107 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1108 const struct mt76_bus_ops *bus_ops); 1109 int mt76s_alloc_queues(struct mt76_dev *dev); 1110 void mt76s_deinit(struct mt76_dev *dev); 1111 1112 struct sk_buff * 1113 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1114 int data_len); 1115 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1116 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1117 unsigned long expires); 1118 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1119 int len, bool wait_resp, struct sk_buff **ret); 1120 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1121 int cmd, bool wait_resp, struct sk_buff **ret); 1122 int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1123 int len); 1124 static inline int 1125 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1126 bool wait_resp) 1127 { 1128 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1129 } 1130 1131 static inline int 1132 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1133 bool wait_resp) 1134 { 1135 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1136 } 1137 1138 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1139 1140 #endif 1141