1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include <net/page_pool/helpers.h> 19 #include "util.h" 20 #include "testmode.h" 21 22 #define MT_MCU_RING_SIZE 32 23 #define MT_RX_BUF_SIZE 2048 24 #define MT_SKB_HEAD_LEN 256 25 26 #define MT_MAX_NON_AQL_PKT 16 27 #define MT_TXQ_FREE_THR 32 28 29 #define MT76_TOKEN_FREE_THR 64 30 31 #define MT_QFLAG_WED_RING GENMASK(1, 0) 32 #define MT_QFLAG_WED_TYPE GENMASK(4, 2) 33 #define MT_QFLAG_WED BIT(5) 34 #define MT_QFLAG_WED_RRO BIT(6) 35 #define MT_QFLAG_WED_RRO_EN BIT(7) 36 37 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 38 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 39 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 40 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n)) 41 42 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 43 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 44 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 45 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 46 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 47 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 48 49 struct mt76_dev; 50 struct mt76_phy; 51 struct mt76_wcid; 52 struct mt76s_intr; 53 54 struct mt76_reg_pair { 55 u32 reg; 56 u32 value; 57 }; 58 59 enum mt76_bus_type { 60 MT76_BUS_MMIO, 61 MT76_BUS_USB, 62 MT76_BUS_SDIO, 63 }; 64 65 enum mt76_wed_type { 66 MT76_WED_Q_TX, 67 MT76_WED_Q_TXFREE, 68 MT76_WED_Q_RX, 69 MT76_WED_RRO_Q_DATA, 70 MT76_WED_RRO_Q_MSDU_PG, 71 MT76_WED_RRO_Q_IND, 72 }; 73 74 struct mt76_bus_ops { 75 u32 (*rr)(struct mt76_dev *dev, u32 offset); 76 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 77 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 78 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 79 int len); 80 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 81 int len); 82 int (*wr_rp)(struct mt76_dev *dev, u32 base, 83 const struct mt76_reg_pair *rp, int len); 84 int (*rd_rp)(struct mt76_dev *dev, u32 base, 85 struct mt76_reg_pair *rp, int len); 86 enum mt76_bus_type type; 87 }; 88 89 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 90 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 91 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 92 93 enum mt76_txq_id { 94 MT_TXQ_VO = IEEE80211_AC_VO, 95 MT_TXQ_VI = IEEE80211_AC_VI, 96 MT_TXQ_BE = IEEE80211_AC_BE, 97 MT_TXQ_BK = IEEE80211_AC_BK, 98 MT_TXQ_PSD, 99 MT_TXQ_BEACON, 100 MT_TXQ_CAB, 101 __MT_TXQ_MAX 102 }; 103 104 enum mt76_mcuq_id { 105 MT_MCUQ_WM, 106 MT_MCUQ_WA, 107 MT_MCUQ_FWDL, 108 __MT_MCUQ_MAX 109 }; 110 111 enum mt76_rxq_id { 112 MT_RXQ_MAIN, 113 MT_RXQ_MCU, 114 MT_RXQ_MCU_WA, 115 MT_RXQ_BAND1, 116 MT_RXQ_BAND1_WA, 117 MT_RXQ_MAIN_WA, 118 MT_RXQ_BAND2, 119 MT_RXQ_BAND2_WA, 120 MT_RXQ_RRO_BAND0, 121 MT_RXQ_RRO_BAND1, 122 MT_RXQ_RRO_BAND2, 123 MT_RXQ_MSDU_PAGE_BAND0, 124 MT_RXQ_MSDU_PAGE_BAND1, 125 MT_RXQ_MSDU_PAGE_BAND2, 126 MT_RXQ_TXFREE_BAND0, 127 MT_RXQ_TXFREE_BAND1, 128 MT_RXQ_TXFREE_BAND2, 129 MT_RXQ_RRO_IND, 130 __MT_RXQ_MAX 131 }; 132 133 enum mt76_band_id { 134 MT_BAND0, 135 MT_BAND1, 136 MT_BAND2, 137 __MT_MAX_BAND 138 }; 139 140 enum mt76_cipher_type { 141 MT_CIPHER_NONE, 142 MT_CIPHER_WEP40, 143 MT_CIPHER_TKIP, 144 MT_CIPHER_TKIP_NO_MIC, 145 MT_CIPHER_AES_CCMP, 146 MT_CIPHER_WEP104, 147 MT_CIPHER_BIP_CMAC_128, 148 MT_CIPHER_WEP128, 149 MT_CIPHER_WAPI, 150 MT_CIPHER_CCMP_CCX, 151 MT_CIPHER_CCMP_256, 152 MT_CIPHER_GCMP, 153 MT_CIPHER_GCMP_256, 154 }; 155 156 enum mt76_dfs_state { 157 MT_DFS_STATE_UNKNOWN, 158 MT_DFS_STATE_DISABLED, 159 MT_DFS_STATE_CAC, 160 MT_DFS_STATE_ACTIVE, 161 }; 162 163 struct mt76_queue_buf { 164 dma_addr_t addr; 165 u16 len; 166 bool skip_unmap; 167 }; 168 169 struct mt76_tx_info { 170 struct mt76_queue_buf buf[32]; 171 struct sk_buff *skb; 172 int nbuf; 173 u32 info; 174 }; 175 176 struct mt76_queue_entry { 177 union { 178 void *buf; 179 struct sk_buff *skb; 180 }; 181 union { 182 struct mt76_txwi_cache *txwi; 183 struct urb *urb; 184 int buf_sz; 185 }; 186 dma_addr_t dma_addr[2]; 187 u16 dma_len[2]; 188 u16 wcid; 189 bool skip_buf0:1; 190 bool skip_buf1:1; 191 bool done:1; 192 }; 193 194 struct mt76_queue_regs { 195 u32 desc_base; 196 u32 ring_size; 197 u32 cpu_idx; 198 u32 dma_idx; 199 } __packed __aligned(4); 200 201 struct mt76_queue { 202 struct mt76_queue_regs __iomem *regs; 203 204 spinlock_t lock; 205 spinlock_t cleanup_lock; 206 struct mt76_queue_entry *entry; 207 struct mt76_rro_desc *rro_desc; 208 struct mt76_desc *desc; 209 210 u16 first; 211 u16 head; 212 u16 tail; 213 u8 hw_idx; 214 u8 ep; 215 int ndesc; 216 int queued; 217 int buf_size; 218 bool stopped; 219 bool blocked; 220 221 u8 buf_offset; 222 u16 flags; 223 224 struct mtk_wed_device *wed; 225 u32 wed_regs; 226 227 dma_addr_t desc_dma; 228 struct sk_buff *rx_head; 229 struct page_pool *page_pool; 230 }; 231 232 struct mt76_mcu_ops { 233 u32 headroom; 234 u32 tailroom; 235 236 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 237 int len, bool wait_resp); 238 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 239 int cmd, int *seq); 240 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 241 struct sk_buff *skb, int seq); 242 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 243 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 244 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 245 const struct mt76_reg_pair *rp, int len); 246 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 247 struct mt76_reg_pair *rp, int len); 248 int (*mcu_restart)(struct mt76_dev *dev); 249 }; 250 251 struct mt76_queue_ops { 252 int (*init)(struct mt76_dev *dev, 253 int (*poll)(struct napi_struct *napi, int budget)); 254 255 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 256 int idx, int n_desc, int bufsize, 257 u32 ring_base); 258 259 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q, 260 enum mt76_txq_id qid, struct sk_buff *skb, 261 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 262 263 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 264 struct sk_buff *skb, u32 tx_info); 265 266 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 267 int *len, u32 *info, bool *more); 268 269 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 270 271 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 272 bool flush); 273 274 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 275 276 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 277 278 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 279 }; 280 281 enum mt76_phy_type { 282 MT_PHY_TYPE_CCK, 283 MT_PHY_TYPE_OFDM, 284 MT_PHY_TYPE_HT, 285 MT_PHY_TYPE_HT_GF, 286 MT_PHY_TYPE_VHT, 287 MT_PHY_TYPE_HE_SU = 8, 288 MT_PHY_TYPE_HE_EXT_SU, 289 MT_PHY_TYPE_HE_TB, 290 MT_PHY_TYPE_HE_MU, 291 MT_PHY_TYPE_EHT_SU = 13, 292 MT_PHY_TYPE_EHT_TRIG, 293 MT_PHY_TYPE_EHT_MU, 294 __MT_PHY_TYPE_MAX, 295 }; 296 297 struct mt76_sta_stats { 298 u64 tx_mode[__MT_PHY_TYPE_MAX]; 299 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 300 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 301 u64 tx_mcs[16]; /* mcs idx */ 302 u64 tx_bytes; 303 /* WED TX */ 304 u32 tx_packets; /* unit: MSDU */ 305 u32 tx_retries; 306 u32 tx_failed; 307 /* WED RX */ 308 u64 rx_bytes; 309 u32 rx_packets; 310 u32 rx_errors; 311 u32 rx_drops; 312 }; 313 314 enum mt76_wcid_flags { 315 MT_WCID_FLAG_CHECK_PS, 316 MT_WCID_FLAG_PS, 317 MT_WCID_FLAG_4ADDR, 318 MT_WCID_FLAG_HDR_TRANS, 319 }; 320 321 #define MT76_N_WCIDS 1088 322 323 /* stored in ieee80211_tx_info::hw_queue */ 324 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 325 326 DECLARE_EWMA(signal, 10, 8); 327 328 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 329 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 330 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 331 #define MT_WCID_TX_INFO_SET BIT(31) 332 333 struct mt76_wcid { 334 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 335 336 atomic_t non_aql_packets; 337 unsigned long flags; 338 339 struct ewma_signal rssi; 340 int inactive_count; 341 342 struct rate_info rate; 343 unsigned long ampdu_state; 344 345 u16 idx; 346 u8 hw_key_idx; 347 u8 hw_key_idx2; 348 349 u8 sta:1; 350 u8 amsdu:1; 351 u8 phy_idx:2; 352 u8 link_id:4; 353 bool link_valid; 354 355 u8 rx_check_pn; 356 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 357 u16 cipher; 358 359 u32 tx_info; 360 bool sw_iv; 361 362 struct list_head tx_list; 363 struct sk_buff_head tx_pending; 364 365 struct list_head list; 366 struct idr pktid; 367 368 struct mt76_sta_stats stats; 369 370 struct list_head poll_list; 371 372 struct mt76_wcid *def_wcid; 373 }; 374 375 struct mt76_txq { 376 u16 wcid; 377 378 u16 agg_ssn; 379 bool send_bar; 380 bool aggr; 381 }; 382 383 struct mt76_wed_rro_ind { 384 u32 se_id : 12; 385 u32 rsv : 4; 386 u32 start_sn : 12; 387 u32 ind_reason : 4; 388 u32 ind_cnt : 13; 389 u32 win_sz : 3; 390 u32 rsv2 : 13; 391 u32 magic_cnt : 3; 392 }; 393 394 struct mt76_txwi_cache { 395 struct list_head list; 396 dma_addr_t dma_addr; 397 398 union { 399 struct sk_buff *skb; 400 void *ptr; 401 }; 402 }; 403 404 struct mt76_rx_tid { 405 struct rcu_head rcu_head; 406 407 struct mt76_dev *dev; 408 409 spinlock_t lock; 410 struct delayed_work reorder_work; 411 412 u16 id; 413 u16 head; 414 u16 size; 415 u16 nframes; 416 417 u8 num; 418 419 u8 started:1, stopped:1, timer_pending:1; 420 421 struct sk_buff *reorder_buf[] __counted_by(size); 422 }; 423 424 #define MT_TX_CB_DMA_DONE BIT(0) 425 #define MT_TX_CB_TXS_DONE BIT(1) 426 #define MT_TX_CB_TXS_FAILED BIT(2) 427 428 #define MT_PACKET_ID_MASK GENMASK(6, 0) 429 #define MT_PACKET_ID_NO_ACK 0 430 #define MT_PACKET_ID_NO_SKB 1 431 #define MT_PACKET_ID_WED 2 432 #define MT_PACKET_ID_FIRST 3 433 #define MT_PACKET_ID_HAS_RATE BIT(7) 434 /* This is timer for when to give up when waiting for TXS callback, 435 * with starting time being the time at which the DMA_DONE callback 436 * was seen (so, we know packet was processed then, it should not take 437 * long after that for firmware to send the TXS callback if it is going 438 * to do so.) 439 */ 440 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 441 442 struct mt76_tx_cb { 443 unsigned long jiffies; 444 u16 wcid; 445 u8 pktid; 446 u8 flags; 447 }; 448 449 enum { 450 MT76_STATE_INITIALIZED, 451 MT76_STATE_REGISTERED, 452 MT76_STATE_RUNNING, 453 MT76_STATE_MCU_RUNNING, 454 MT76_SCANNING, 455 MT76_HW_SCANNING, 456 MT76_HW_SCHED_SCANNING, 457 MT76_RESTART, 458 MT76_RESET, 459 MT76_MCU_RESET, 460 MT76_REMOVED, 461 MT76_READING_STATS, 462 MT76_STATE_POWER_OFF, 463 MT76_STATE_SUSPEND, 464 MT76_STATE_ROC, 465 MT76_STATE_PM, 466 MT76_STATE_WED_RESET, 467 }; 468 469 struct mt76_hw_cap { 470 bool has_2ghz; 471 bool has_5ghz; 472 bool has_6ghz; 473 }; 474 475 #define MT_DRV_TXWI_NO_FREE BIT(0) 476 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 477 #define MT_DRV_SW_RX_AIRTIME BIT(2) 478 #define MT_DRV_RX_DMA_HDR BIT(3) 479 #define MT_DRV_HW_MGMT_TXQ BIT(4) 480 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 481 482 struct mt76_driver_ops { 483 u32 drv_flags; 484 u32 survey_flags; 485 u16 txwi_size; 486 u16 token_size; 487 u8 mcs_rates; 488 489 void (*update_survey)(struct mt76_phy *phy); 490 491 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 492 enum mt76_txq_id qid, struct mt76_wcid *wcid, 493 struct ieee80211_sta *sta, 494 struct mt76_tx_info *tx_info); 495 496 void (*tx_complete_skb)(struct mt76_dev *dev, 497 struct mt76_queue_entry *e); 498 499 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 500 501 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 502 503 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 504 struct sk_buff *skb, u32 *info); 505 506 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 507 508 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 509 bool ps); 510 511 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 512 struct ieee80211_sta *sta); 513 514 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 515 struct ieee80211_sta *sta); 516 517 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 518 struct ieee80211_sta *sta); 519 }; 520 521 struct mt76_channel_state { 522 u64 cc_active; 523 u64 cc_busy; 524 u64 cc_rx; 525 u64 cc_bss_rx; 526 u64 cc_tx; 527 528 s8 noise; 529 }; 530 531 struct mt76_sband { 532 struct ieee80211_supported_band sband; 533 struct mt76_channel_state *chan; 534 }; 535 536 /* addr req mask */ 537 #define MT_VEND_TYPE_EEPROM BIT(31) 538 #define MT_VEND_TYPE_CFG BIT(30) 539 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 540 541 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 542 enum mt_vendor_req { 543 MT_VEND_DEV_MODE = 0x1, 544 MT_VEND_WRITE = 0x2, 545 MT_VEND_POWER_ON = 0x4, 546 MT_VEND_MULTI_WRITE = 0x6, 547 MT_VEND_MULTI_READ = 0x7, 548 MT_VEND_READ_EEPROM = 0x9, 549 MT_VEND_WRITE_FCE = 0x42, 550 MT_VEND_WRITE_CFG = 0x46, 551 MT_VEND_READ_CFG = 0x47, 552 MT_VEND_READ_EXT = 0x63, 553 MT_VEND_WRITE_EXT = 0x66, 554 MT_VEND_FEATURE_SET = 0x91, 555 }; 556 557 enum mt76u_in_ep { 558 MT_EP_IN_PKT_RX, 559 MT_EP_IN_CMD_RESP, 560 __MT_EP_IN_MAX, 561 }; 562 563 enum mt76u_out_ep { 564 MT_EP_OUT_INBAND_CMD, 565 MT_EP_OUT_AC_BE, 566 MT_EP_OUT_AC_BK, 567 MT_EP_OUT_AC_VI, 568 MT_EP_OUT_AC_VO, 569 MT_EP_OUT_HCCA, 570 __MT_EP_OUT_MAX, 571 }; 572 573 struct mt76_mcu { 574 struct mutex mutex; 575 u32 msg_seq; 576 int timeout; 577 578 struct sk_buff_head res_q; 579 wait_queue_head_t wait; 580 }; 581 582 #define MT_TX_SG_MAX_SIZE 8 583 #define MT_RX_SG_MAX_SIZE 4 584 #define MT_NUM_TX_ENTRIES 256 585 #define MT_NUM_RX_ENTRIES 128 586 #define MCU_RESP_URB_SIZE 1024 587 struct mt76_usb { 588 struct mutex usb_ctrl_mtx; 589 u8 *data; 590 u16 data_len; 591 592 struct mt76_worker status_worker; 593 struct mt76_worker rx_worker; 594 595 struct work_struct stat_work; 596 597 u8 out_ep[__MT_EP_OUT_MAX]; 598 u8 in_ep[__MT_EP_IN_MAX]; 599 bool sg_en; 600 601 struct mt76u_mcu { 602 u8 *data; 603 /* multiple reads */ 604 struct mt76_reg_pair *rp; 605 int rp_len; 606 u32 base; 607 } mcu; 608 }; 609 610 #define MT76S_XMIT_BUF_SZ 0x3fe00 611 #define MT76S_NUM_TX_ENTRIES 256 612 #define MT76S_NUM_RX_ENTRIES 512 613 struct mt76_sdio { 614 struct mt76_worker txrx_worker; 615 struct mt76_worker status_worker; 616 struct mt76_worker net_worker; 617 struct mt76_worker stat_worker; 618 619 u8 *xmit_buf; 620 u32 xmit_buf_sz; 621 622 struct sdio_func *func; 623 void *intr_data; 624 u8 hw_ver; 625 wait_queue_head_t wait; 626 627 struct { 628 int pse_data_quota; 629 int ple_data_quota; 630 int pse_mcu_quota; 631 int pse_page_size; 632 int deficit; 633 } sched; 634 635 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 636 }; 637 638 struct mt76_mmio { 639 void __iomem *regs; 640 spinlock_t irq_lock; 641 u32 irqmask; 642 643 struct mtk_wed_device wed; 644 struct mtk_wed_device wed_hif2; 645 struct completion wed_reset; 646 struct completion wed_reset_complete; 647 }; 648 649 struct mt76_rx_status { 650 union { 651 struct mt76_wcid *wcid; 652 u16 wcid_idx; 653 }; 654 655 u32 reorder_time; 656 657 u32 ampdu_ref; 658 u32 timestamp; 659 660 u8 iv[6]; 661 662 u8 phy_idx:2; 663 u8 aggr:1; 664 u8 qos_ctl; 665 u16 seqno; 666 667 u16 freq; 668 u32 flag; 669 u8 enc_flags; 670 u8 encoding:3, bw:4; 671 union { 672 struct { 673 u8 he_ru:3; 674 u8 he_gi:2; 675 u8 he_dcm:1; 676 }; 677 struct { 678 u8 ru:4; 679 u8 gi:2; 680 } eht; 681 }; 682 683 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 684 u8 rate_idx; 685 u8 nss:5, band:3; 686 s8 signal; 687 u8 chains; 688 s8 chain_signal[IEEE80211_MAX_CHAINS]; 689 }; 690 691 struct mt76_freq_range_power { 692 const struct cfg80211_sar_freq_ranges *range; 693 s8 power; 694 }; 695 696 struct mt76_testmode_ops { 697 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 698 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 699 enum mt76_testmode_state new_state); 700 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 701 }; 702 703 struct mt76_testmode_data { 704 enum mt76_testmode_state state; 705 706 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 707 struct sk_buff *tx_skb; 708 709 u32 tx_count; 710 u16 tx_mpdu_len; 711 712 u8 tx_rate_mode; 713 u8 tx_rate_idx; 714 u8 tx_rate_nss; 715 u8 tx_rate_sgi; 716 u8 tx_rate_ldpc; 717 u8 tx_rate_stbc; 718 u8 tx_ltf; 719 720 u8 tx_antenna_mask; 721 u8 tx_spe_idx; 722 723 u8 tx_duty_cycle; 724 u32 tx_time; 725 u32 tx_ipg; 726 727 u32 freq_offset; 728 729 u8 tx_power[4]; 730 u8 tx_power_control; 731 732 u8 addr[3][ETH_ALEN]; 733 734 u32 tx_pending; 735 u32 tx_queued; 736 u16 tx_queued_limit; 737 u32 tx_done; 738 struct { 739 u64 packets[__MT_RXQ_MAX]; 740 u64 fcs_error[__MT_RXQ_MAX]; 741 } rx_stats; 742 }; 743 744 struct mt76_vif { 745 u8 idx; 746 u8 omac_idx; 747 u8 band_idx; 748 u8 wmm_idx; 749 u8 scan_seq_num; 750 u8 cipher; 751 u8 basic_rates_idx; 752 u8 mcast_rates_idx; 753 u8 beacon_rates_idx; 754 struct ieee80211_chanctx_conf *ctx; 755 }; 756 757 struct mt76_phy { 758 struct ieee80211_hw *hw; 759 struct mt76_dev *dev; 760 void *priv; 761 762 unsigned long state; 763 u8 band_idx; 764 765 spinlock_t tx_lock; 766 struct list_head tx_list; 767 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 768 769 struct cfg80211_chan_def chandef; 770 struct ieee80211_channel *main_chan; 771 772 struct mt76_channel_state *chan_state; 773 enum mt76_dfs_state dfs_state; 774 ktime_t survey_time; 775 776 u32 aggr_stats[32]; 777 778 struct mt76_hw_cap cap; 779 struct mt76_sband sband_2g; 780 struct mt76_sband sband_5g; 781 struct mt76_sband sband_6g; 782 783 u8 macaddr[ETH_ALEN]; 784 785 int txpower_cur; 786 u8 antenna_mask; 787 u16 chainmask; 788 789 #ifdef CONFIG_NL80211_TESTMODE 790 struct mt76_testmode_data test; 791 #endif 792 793 struct delayed_work mac_work; 794 u8 mac_work_count; 795 796 struct { 797 struct sk_buff *head; 798 struct sk_buff **tail; 799 u16 seqno; 800 } rx_amsdu[__MT_RXQ_MAX]; 801 802 struct mt76_freq_range_power *frp; 803 804 struct { 805 struct led_classdev cdev; 806 char name[32]; 807 bool al; 808 u8 pin; 809 } leds; 810 }; 811 812 struct mt76_dev { 813 struct mt76_phy phy; /* must be first */ 814 struct mt76_phy *phys[__MT_MAX_BAND]; 815 816 struct ieee80211_hw *hw; 817 818 spinlock_t wed_lock; 819 spinlock_t lock; 820 spinlock_t cc_lock; 821 822 u32 cur_cc_bss_rx; 823 824 struct mt76_rx_status rx_ampdu_status; 825 u32 rx_ampdu_len; 826 u32 rx_ampdu_ref; 827 828 struct mutex mutex; 829 830 const struct mt76_bus_ops *bus; 831 const struct mt76_driver_ops *drv; 832 const struct mt76_mcu_ops *mcu_ops; 833 struct device *dev; 834 struct device *dma_dev; 835 836 struct mt76_mcu mcu; 837 838 struct net_device *napi_dev; 839 struct net_device *tx_napi_dev; 840 spinlock_t rx_lock; 841 struct napi_struct napi[__MT_RXQ_MAX]; 842 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 843 struct tasklet_struct irq_tasklet; 844 845 struct list_head txwi_cache; 846 struct list_head rxwi_cache; 847 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 848 struct mt76_queue q_rx[__MT_RXQ_MAX]; 849 const struct mt76_queue_ops *queue_ops; 850 int tx_dma_idx[4]; 851 852 struct mt76_worker tx_worker; 853 struct napi_struct tx_napi; 854 855 spinlock_t token_lock; 856 struct idr token; 857 u16 wed_token_count; 858 u16 token_count; 859 u16 token_size; 860 861 spinlock_t rx_token_lock; 862 struct idr rx_token; 863 u16 rx_token_size; 864 865 wait_queue_head_t tx_wait; 866 /* spinclock used to protect wcid pktid linked list */ 867 spinlock_t status_lock; 868 869 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 870 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 871 872 u64 vif_mask; 873 874 struct mt76_wcid global_wcid; 875 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 876 struct list_head wcid_list; 877 878 struct list_head sta_poll_list; 879 spinlock_t sta_poll_lock; 880 881 u32 rev; 882 883 struct tasklet_struct pre_tbtt_tasklet; 884 int beacon_int; 885 u8 beacon_mask; 886 887 struct debugfs_blob_wrapper eeprom; 888 struct debugfs_blob_wrapper otp; 889 890 char alpha2[3]; 891 enum nl80211_dfs_regions region; 892 893 u32 debugfs_reg; 894 895 u8 csa_complete; 896 897 u32 rxfilter; 898 899 #ifdef CONFIG_NL80211_TESTMODE 900 const struct mt76_testmode_ops *test_ops; 901 struct { 902 const char *name; 903 u32 offset; 904 } test_mtd; 905 #endif 906 struct workqueue_struct *wq; 907 908 union { 909 struct mt76_mmio mmio; 910 struct mt76_usb usb; 911 struct mt76_sdio sdio; 912 }; 913 }; 914 915 /* per-phy stats. */ 916 struct mt76_mib_stats { 917 u32 ack_fail_cnt; 918 u32 fcs_err_cnt; 919 u32 rts_cnt; 920 u32 rts_retries_cnt; 921 u32 ba_miss_cnt; 922 u32 tx_bf_cnt; 923 u32 tx_mu_bf_cnt; 924 u32 tx_mu_mpdu_cnt; 925 u32 tx_mu_acked_mpdu_cnt; 926 u32 tx_su_acked_mpdu_cnt; 927 u32 tx_bf_ibf_ppdu_cnt; 928 u32 tx_bf_ebf_ppdu_cnt; 929 930 u32 tx_bf_rx_fb_all_cnt; 931 u32 tx_bf_rx_fb_eht_cnt; 932 u32 tx_bf_rx_fb_he_cnt; 933 u32 tx_bf_rx_fb_vht_cnt; 934 u32 tx_bf_rx_fb_ht_cnt; 935 936 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 937 u32 tx_bf_rx_fb_nc_cnt; 938 u32 tx_bf_rx_fb_nr_cnt; 939 u32 tx_bf_fb_cpl_cnt; 940 u32 tx_bf_fb_trig_cnt; 941 942 u32 tx_ampdu_cnt; 943 u32 tx_stop_q_empty_cnt; 944 u32 tx_mpdu_attempts_cnt; 945 u32 tx_mpdu_success_cnt; 946 u32 tx_pkt_ebf_cnt; 947 u32 tx_pkt_ibf_cnt; 948 949 u32 tx_rwp_fail_cnt; 950 u32 tx_rwp_need_cnt; 951 952 /* rx stats */ 953 u32 rx_fifo_full_cnt; 954 u32 channel_idle_cnt; 955 u32 primary_cca_busy_time; 956 u32 secondary_cca_busy_time; 957 u32 primary_energy_detect_time; 958 u32 cck_mdrdy_time; 959 u32 ofdm_mdrdy_time; 960 u32 green_mdrdy_time; 961 u32 rx_vector_mismatch_cnt; 962 u32 rx_delimiter_fail_cnt; 963 u32 rx_mrdy_cnt; 964 u32 rx_len_mismatch_cnt; 965 u32 rx_mpdu_cnt; 966 u32 rx_ampdu_cnt; 967 u32 rx_ampdu_bytes_cnt; 968 u32 rx_ampdu_valid_subframe_cnt; 969 u32 rx_ampdu_valid_subframe_bytes_cnt; 970 u32 rx_pfdrop_cnt; 971 u32 rx_vec_queue_overflow_drop_cnt; 972 u32 rx_ba_cnt; 973 974 u32 tx_amsdu[8]; 975 u32 tx_amsdu_cnt; 976 977 /* mcu_muru_stats */ 978 u32 dl_cck_cnt; 979 u32 dl_ofdm_cnt; 980 u32 dl_htmix_cnt; 981 u32 dl_htgf_cnt; 982 u32 dl_vht_su_cnt; 983 u32 dl_vht_2mu_cnt; 984 u32 dl_vht_3mu_cnt; 985 u32 dl_vht_4mu_cnt; 986 u32 dl_he_su_cnt; 987 u32 dl_he_ext_su_cnt; 988 u32 dl_he_2ru_cnt; 989 u32 dl_he_2mu_cnt; 990 u32 dl_he_3ru_cnt; 991 u32 dl_he_3mu_cnt; 992 u32 dl_he_4ru_cnt; 993 u32 dl_he_4mu_cnt; 994 u32 dl_he_5to8ru_cnt; 995 u32 dl_he_9to16ru_cnt; 996 u32 dl_he_gtr16ru_cnt; 997 998 u32 ul_hetrig_su_cnt; 999 u32 ul_hetrig_2ru_cnt; 1000 u32 ul_hetrig_3ru_cnt; 1001 u32 ul_hetrig_4ru_cnt; 1002 u32 ul_hetrig_5to8ru_cnt; 1003 u32 ul_hetrig_9to16ru_cnt; 1004 u32 ul_hetrig_gtr16ru_cnt; 1005 u32 ul_hetrig_2mu_cnt; 1006 u32 ul_hetrig_3mu_cnt; 1007 u32 ul_hetrig_4mu_cnt; 1008 }; 1009 1010 struct mt76_power_limits { 1011 s8 cck[4]; 1012 s8 ofdm[8]; 1013 s8 mcs[4][10]; 1014 s8 ru[7][12]; 1015 s8 eht[16][16]; 1016 }; 1017 1018 struct mt76_ethtool_worker_info { 1019 u64 *data; 1020 int idx; 1021 int initial_stat_idx; 1022 int worker_stat_count; 1023 int sta_count; 1024 }; 1025 1026 #define CCK_RATE(_idx, _rate) { \ 1027 .bitrate = _rate, \ 1028 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 1029 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 1030 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 1031 } 1032 1033 #define OFDM_RATE(_idx, _rate) { \ 1034 .bitrate = _rate, \ 1035 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1036 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1037 } 1038 1039 extern struct ieee80211_rate mt76_rates[12]; 1040 1041 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1042 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1043 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1044 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1045 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1046 1047 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1048 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1049 1050 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1051 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1052 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1053 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1054 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1055 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1056 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1057 1058 1059 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1060 1061 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1062 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1063 1064 #define mt76_get_field(_dev, _reg, _field) \ 1065 FIELD_GET(_field, mt76_rr(dev, _reg)) 1066 1067 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1068 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1069 1070 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1071 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1072 1073 #define mt76_hw(dev) (dev)->mphy.hw 1074 1075 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1076 int timeout); 1077 1078 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1079 1080 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1081 int timeout, int kick); 1082 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1083 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1084 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1085 1086 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1087 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1088 bool mt76_pci_aspm_supported(struct pci_dev *pdev); 1089 1090 static inline u16 mt76_chip(struct mt76_dev *dev) 1091 { 1092 return dev->rev >> 16; 1093 } 1094 1095 static inline u16 mt76_rev(struct mt76_dev *dev) 1096 { 1097 return dev->rev & 0xffff; 1098 } 1099 1100 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed); 1101 void mt76_wed_offload_disable(struct mtk_wed_device *wed); 1102 void mt76_wed_reset_complete(struct mtk_wed_device *wed); 1103 void mt76_wed_dma_reset(struct mt76_dev *dev); 1104 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1105 struct net_device *netdev, enum tc_setup_type type, 1106 void *type_data); 1107 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1108 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size); 1109 int mt76_wed_offload_enable(struct mtk_wed_device *wed); 1110 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); 1111 #else 1112 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size) 1113 { 1114 return 0; 1115 } 1116 1117 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed) 1118 { 1119 return 0; 1120 } 1121 1122 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, 1123 bool reset) 1124 { 1125 return 0; 1126 } 1127 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1128 1129 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1130 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1131 1132 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1133 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1134 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1135 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__) 1136 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1137 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1138 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1139 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1140 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1141 1142 #define mt76_for_each_q_rx(dev, i) \ 1143 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1144 if ((dev)->q_rx[i].ndesc) 1145 1146 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1147 const struct ieee80211_ops *ops, 1148 const struct mt76_driver_ops *drv_ops); 1149 int mt76_register_device(struct mt76_dev *dev, bool vht, 1150 struct ieee80211_rate *rates, int n_rates); 1151 void mt76_unregister_device(struct mt76_dev *dev); 1152 void mt76_free_device(struct mt76_dev *dev); 1153 void mt76_unregister_phy(struct mt76_phy *phy); 1154 1155 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1156 const struct ieee80211_ops *ops, 1157 u8 band_idx); 1158 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1159 struct ieee80211_rate *rates, int n_rates); 1160 1161 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1162 const struct file_operations *ops); 1163 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1164 { 1165 return mt76_register_debugfs_fops(&dev->phy, NULL); 1166 } 1167 1168 int mt76_queues_read(struct seq_file *s, void *data); 1169 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1170 s8 *val, int len); 1171 1172 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1173 void mt76_eeprom_override(struct mt76_phy *phy); 1174 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1175 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1176 const char *cell_name, int len); 1177 1178 struct mt76_queue * 1179 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1180 int ring_base, void *wed, u32 flags); 1181 u16 mt76_calculate_default_rate(struct mt76_phy *phy, 1182 struct ieee80211_vif *vif, int rateidx); 1183 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1184 int n_desc, int ring_base, void *wed, 1185 u32 flags) 1186 { 1187 struct mt76_queue *q; 1188 1189 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags); 1190 if (IS_ERR(q)) 1191 return PTR_ERR(q); 1192 1193 phy->q_tx[qid] = q; 1194 1195 return 0; 1196 } 1197 1198 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1199 int n_desc, int ring_base) 1200 { 1201 struct mt76_queue *q; 1202 1203 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0); 1204 if (IS_ERR(q)) 1205 return PTR_ERR(q); 1206 1207 dev->q_mcu[qid] = q; 1208 1209 return 0; 1210 } 1211 1212 static inline struct mt76_phy * 1213 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1214 { 1215 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1216 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1217 return dev->phys[phy_idx]; 1218 1219 return &dev->phy; 1220 } 1221 1222 static inline struct ieee80211_hw * 1223 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1224 { 1225 return mt76_dev_phy(dev, phy_idx)->hw; 1226 } 1227 1228 static inline u8 * 1229 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1230 { 1231 return (u8 *)t - dev->drv->txwi_size; 1232 } 1233 1234 /* increment with wrap-around */ 1235 static inline int mt76_incr(int val, int size) 1236 { 1237 return (val + 1) & (size - 1); 1238 } 1239 1240 /* decrement with wrap-around */ 1241 static inline int mt76_decr(int val, int size) 1242 { 1243 return (val - 1) & (size - 1); 1244 } 1245 1246 u8 mt76_ac_to_hwq(u8 ac); 1247 1248 static inline struct ieee80211_txq * 1249 mtxq_to_txq(struct mt76_txq *mtxq) 1250 { 1251 void *ptr = mtxq; 1252 1253 return container_of(ptr, struct ieee80211_txq, drv_priv); 1254 } 1255 1256 static inline struct ieee80211_sta * 1257 wcid_to_sta(struct mt76_wcid *wcid) 1258 { 1259 void *ptr = wcid; 1260 1261 if (!wcid || !wcid->sta) 1262 return NULL; 1263 1264 if (wcid->def_wcid) 1265 ptr = wcid->def_wcid; 1266 1267 return container_of(ptr, struct ieee80211_sta, drv_priv); 1268 } 1269 1270 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1271 { 1272 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1273 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1274 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1275 } 1276 1277 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1278 { 1279 struct mt76_rx_status mstat; 1280 u8 *data = skb->data; 1281 1282 /* Alignment concerns */ 1283 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1284 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1285 1286 mstat = *((struct mt76_rx_status *)skb->cb); 1287 1288 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1289 data += sizeof(struct ieee80211_radiotap_he); 1290 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1291 data += sizeof(struct ieee80211_radiotap_he_mu); 1292 1293 return data; 1294 } 1295 1296 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1297 { 1298 int len = ieee80211_get_hdrlen_from_skb(skb); 1299 1300 if (len % 4 == 0) 1301 return; 1302 1303 skb_push(skb, 2); 1304 memmove(skb->data, skb->data + 2, len); 1305 1306 skb->data[len] = 0; 1307 skb->data[len + 1] = 0; 1308 } 1309 1310 static inline bool mt76_is_skb_pktid(u8 pktid) 1311 { 1312 if (pktid & MT_PACKET_ID_HAS_RATE) 1313 return false; 1314 1315 return pktid >= MT_PACKET_ID_FIRST; 1316 } 1317 1318 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1319 { 1320 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1321 u8 idx = nss - 1; 1322 1323 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1324 } 1325 1326 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1327 { 1328 #ifdef CONFIG_NL80211_TESTMODE 1329 return phy->test.state != MT76_TM_STATE_OFF; 1330 #else 1331 return false; 1332 #endif 1333 } 1334 1335 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1336 struct sk_buff *skb, 1337 struct ieee80211_hw **hw) 1338 { 1339 #ifdef CONFIG_NL80211_TESTMODE 1340 int i; 1341 1342 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1343 struct mt76_phy *phy = dev->phys[i]; 1344 1345 if (phy && skb == phy->test.tx_skb) { 1346 *hw = dev->phys[i]->hw; 1347 return true; 1348 } 1349 } 1350 return false; 1351 #else 1352 return false; 1353 #endif 1354 } 1355 1356 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1357 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1358 struct mt76_wcid *wcid, struct sk_buff *skb); 1359 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1360 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1361 bool send_bar); 1362 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1363 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1364 void mt76_txq_schedule_all(struct mt76_phy *phy); 1365 void mt76_tx_worker_run(struct mt76_dev *dev); 1366 void mt76_tx_worker(struct mt76_worker *w); 1367 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1368 struct ieee80211_sta *sta, 1369 u16 tids, int nframes, 1370 enum ieee80211_frame_release_type reason, 1371 bool more_data); 1372 bool mt76_has_tx_pending(struct mt76_phy *phy); 1373 void mt76_set_channel(struct mt76_phy *phy); 1374 void mt76_update_survey(struct mt76_phy *phy); 1375 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1376 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1377 struct survey_info *survey); 1378 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1379 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1380 1381 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1382 u16 ssn, u16 size); 1383 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1384 1385 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1386 struct ieee80211_key_conf *key); 1387 1388 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1389 __acquires(&dev->status_lock); 1390 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1391 __releases(&dev->status_lock); 1392 1393 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1394 struct sk_buff *skb); 1395 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1396 struct mt76_wcid *wcid, int pktid, 1397 struct sk_buff_head *list); 1398 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1399 struct sk_buff_head *list); 1400 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1401 struct list_head *free_list); 1402 static inline void 1403 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1404 { 1405 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1406 } 1407 1408 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1409 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1410 struct ieee80211_sta *sta, 1411 enum ieee80211_sta_state old_state, 1412 enum ieee80211_sta_state new_state); 1413 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1414 struct ieee80211_sta *sta); 1415 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1416 struct ieee80211_sta *sta); 1417 1418 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1419 1420 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1421 int *dbm); 1422 int mt76_init_sar_power(struct ieee80211_hw *hw, 1423 const struct cfg80211_sar_specs *sar); 1424 int mt76_get_sar_power(struct mt76_phy *phy, 1425 struct ieee80211_channel *chan, 1426 int power); 1427 1428 void mt76_csa_check(struct mt76_dev *dev); 1429 void mt76_csa_finish(struct mt76_dev *dev); 1430 1431 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1432 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1433 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1434 int mt76_get_rate(struct mt76_dev *dev, 1435 struct ieee80211_supported_band *sband, 1436 int idx, bool cck); 1437 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1438 const u8 *mac); 1439 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1440 struct ieee80211_vif *vif); 1441 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1442 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1443 void *data, int len); 1444 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1445 struct netlink_callback *cb, void *data, int len); 1446 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1447 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1448 1449 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1450 { 1451 #ifdef CONFIG_NL80211_TESTMODE 1452 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1453 1454 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1455 state = MT76_TM_STATE_OFF; 1456 1457 mt76_testmode_set_state(phy, state); 1458 #endif 1459 } 1460 1461 1462 /* internal */ 1463 static inline struct ieee80211_hw * 1464 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1465 { 1466 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1467 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1468 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1469 1470 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1471 1472 return hw; 1473 } 1474 1475 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1476 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1477 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1478 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1479 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1480 struct napi_struct *napi); 1481 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1482 struct napi_struct *napi); 1483 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1484 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1485 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1486 struct mt76_queue_entry *e); 1487 1488 /* usb */ 1489 static inline bool mt76u_urb_error(struct urb *urb) 1490 { 1491 return urb->status && 1492 urb->status != -ECONNRESET && 1493 urb->status != -ESHUTDOWN && 1494 urb->status != -ENOENT; 1495 } 1496 1497 static inline int 1498 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1499 int timeout, int ep) 1500 { 1501 struct usb_interface *uintf = to_usb_interface(dev->dev); 1502 struct usb_device *udev = interface_to_usbdev(uintf); 1503 struct mt76_usb *usb = &dev->usb; 1504 unsigned int pipe; 1505 1506 if (actual_len) 1507 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1508 else 1509 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1510 1511 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1512 } 1513 1514 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1515 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1516 struct mt76_sta_stats *stats, bool eht); 1517 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1518 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1519 u16 val, u16 offset, void *buf, size_t len); 1520 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1521 u8 req_type, u16 val, u16 offset, 1522 void *buf, size_t len); 1523 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1524 const u16 offset, const u32 val); 1525 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1526 void *data, int len); 1527 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1528 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1529 u32 addr, u32 val); 1530 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1531 struct mt76_bus_ops *ops); 1532 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1533 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1534 int mt76u_alloc_queues(struct mt76_dev *dev); 1535 void mt76u_stop_tx(struct mt76_dev *dev); 1536 void mt76u_stop_rx(struct mt76_dev *dev); 1537 int mt76u_resume_rx(struct mt76_dev *dev); 1538 void mt76u_queues_deinit(struct mt76_dev *dev); 1539 1540 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1541 const struct mt76_bus_ops *bus_ops); 1542 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1543 int mt76s_alloc_tx(struct mt76_dev *dev); 1544 void mt76s_deinit(struct mt76_dev *dev); 1545 void mt76s_sdio_irq(struct sdio_func *func); 1546 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1547 bool mt76s_txqs_empty(struct mt76_dev *dev); 1548 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1549 int hw_ver); 1550 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1551 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1552 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1553 u32 mt76s_read_pcr(struct mt76_dev *dev); 1554 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1555 const void *data, int len); 1556 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1557 void *data, int len); 1558 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1559 const struct mt76_reg_pair *data, 1560 int len); 1561 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1562 struct mt76_reg_pair *data, int len); 1563 1564 struct sk_buff * 1565 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1566 int len, int data_len, gfp_t gfp); 1567 static inline struct sk_buff * 1568 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1569 int data_len) 1570 { 1571 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1572 } 1573 1574 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1575 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1576 unsigned long expires); 1577 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1578 int len, bool wait_resp, struct sk_buff **ret); 1579 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1580 int cmd, bool wait_resp, struct sk_buff **ret); 1581 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1582 int len, int max_len); 1583 static inline int 1584 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1585 int len) 1586 { 1587 int max_len = 4096 - dev->mcu_ops->headroom; 1588 1589 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1590 } 1591 1592 static inline int 1593 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1594 bool wait_resp) 1595 { 1596 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1597 } 1598 1599 static inline int 1600 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1601 bool wait_resp) 1602 { 1603 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1604 } 1605 1606 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1607 1608 struct device_node * 1609 mt76_find_power_limits_node(struct mt76_dev *dev); 1610 struct device_node * 1611 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan); 1612 1613 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1614 struct ieee80211_channel *chan, 1615 struct mt76_power_limits *dest, 1616 s8 target_power); 1617 1618 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q) 1619 { 1620 int i; 1621 1622 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 1623 if (q == &dev->q_rx[i]) 1624 return true; 1625 } 1626 1627 return false; 1628 } 1629 1630 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q) 1631 { 1632 return (q->flags & MT_QFLAG_WED) && 1633 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE; 1634 } 1635 1636 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q) 1637 { 1638 return q->flags & MT_QFLAG_WED_RRO; 1639 } 1640 1641 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q) 1642 { 1643 return mt76_queue_is_wed_rro(q) && 1644 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1645 } 1646 1647 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1648 { 1649 return mt76_queue_is_wed_rro(q) && 1650 (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA || 1651 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG); 1652 } 1653 1654 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1655 { 1656 if (!(q->flags & MT_QFLAG_WED)) 1657 return false; 1658 1659 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX || 1660 mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q); 1661 1662 } 1663 1664 struct mt76_txwi_cache * 1665 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1666 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1667 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1668 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1669 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1670 struct mt76_txwi_cache *r, dma_addr_t phys); 1671 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1672 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1673 { 1674 struct page *page = virt_to_head_page(buf); 1675 1676 page_pool_put_full_page(page->pp, page, allow_direct); 1677 } 1678 1679 static inline void * 1680 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1681 { 1682 struct page *page; 1683 1684 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1685 if (!page) 1686 return NULL; 1687 1688 return page_address(page) + *offset; 1689 } 1690 1691 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1692 { 1693 spin_lock_bh(&dev->token_lock); 1694 __mt76_set_tx_blocked(dev, blocked); 1695 spin_unlock_bh(&dev->token_lock); 1696 } 1697 1698 static inline int 1699 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1700 { 1701 int token; 1702 1703 spin_lock_bh(&dev->token_lock); 1704 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1705 spin_unlock_bh(&dev->token_lock); 1706 1707 return token; 1708 } 1709 1710 static inline struct mt76_txwi_cache * 1711 mt76_token_put(struct mt76_dev *dev, int token) 1712 { 1713 struct mt76_txwi_cache *txwi; 1714 1715 spin_lock_bh(&dev->token_lock); 1716 txwi = idr_remove(&dev->token, token); 1717 spin_unlock_bh(&dev->token_lock); 1718 1719 return txwi; 1720 } 1721 1722 void mt76_wcid_init(struct mt76_wcid *wcid); 1723 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid); 1724 1725 #endif 1726