1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 39 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 40 41 struct mt76_dev; 42 struct mt76_phy; 43 struct mt76_wcid; 44 struct mt76s_intr; 45 46 struct mt76_reg_pair { 47 u32 reg; 48 u32 value; 49 }; 50 51 enum mt76_bus_type { 52 MT76_BUS_MMIO, 53 MT76_BUS_USB, 54 MT76_BUS_SDIO, 55 }; 56 57 enum mt76_wed_type { 58 MT76_WED_Q_TX, 59 MT76_WED_Q_TXFREE, 60 MT76_WED_Q_RX, 61 }; 62 63 struct mt76_bus_ops { 64 u32 (*rr)(struct mt76_dev *dev, u32 offset); 65 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 66 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 67 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 68 int len); 69 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 70 int len); 71 int (*wr_rp)(struct mt76_dev *dev, u32 base, 72 const struct mt76_reg_pair *rp, int len); 73 int (*rd_rp)(struct mt76_dev *dev, u32 base, 74 struct mt76_reg_pair *rp, int len); 75 enum mt76_bus_type type; 76 }; 77 78 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 79 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 80 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 81 82 enum mt76_txq_id { 83 MT_TXQ_VO = IEEE80211_AC_VO, 84 MT_TXQ_VI = IEEE80211_AC_VI, 85 MT_TXQ_BE = IEEE80211_AC_BE, 86 MT_TXQ_BK = IEEE80211_AC_BK, 87 MT_TXQ_PSD, 88 MT_TXQ_BEACON, 89 MT_TXQ_CAB, 90 __MT_TXQ_MAX 91 }; 92 93 enum mt76_mcuq_id { 94 MT_MCUQ_WM, 95 MT_MCUQ_WA, 96 MT_MCUQ_FWDL, 97 __MT_MCUQ_MAX 98 }; 99 100 enum mt76_rxq_id { 101 MT_RXQ_MAIN, 102 MT_RXQ_MCU, 103 MT_RXQ_MCU_WA, 104 MT_RXQ_BAND1, 105 MT_RXQ_BAND1_WA, 106 MT_RXQ_MAIN_WA, 107 MT_RXQ_BAND2, 108 MT_RXQ_BAND2_WA, 109 __MT_RXQ_MAX 110 }; 111 112 enum mt76_band_id { 113 MT_BAND0, 114 MT_BAND1, 115 MT_BAND2, 116 __MT_MAX_BAND 117 }; 118 119 enum mt76_cipher_type { 120 MT_CIPHER_NONE, 121 MT_CIPHER_WEP40, 122 MT_CIPHER_TKIP, 123 MT_CIPHER_TKIP_NO_MIC, 124 MT_CIPHER_AES_CCMP, 125 MT_CIPHER_WEP104, 126 MT_CIPHER_BIP_CMAC_128, 127 MT_CIPHER_WEP128, 128 MT_CIPHER_WAPI, 129 MT_CIPHER_CCMP_CCX, 130 MT_CIPHER_CCMP_256, 131 MT_CIPHER_GCMP, 132 MT_CIPHER_GCMP_256, 133 }; 134 135 enum mt76_dfs_state { 136 MT_DFS_STATE_UNKNOWN, 137 MT_DFS_STATE_DISABLED, 138 MT_DFS_STATE_CAC, 139 MT_DFS_STATE_ACTIVE, 140 }; 141 142 struct mt76_queue_buf { 143 dma_addr_t addr; 144 u16 len; 145 bool skip_unmap; 146 }; 147 148 struct mt76_tx_info { 149 struct mt76_queue_buf buf[32]; 150 struct sk_buff *skb; 151 int nbuf; 152 u32 info; 153 }; 154 155 struct mt76_queue_entry { 156 union { 157 void *buf; 158 struct sk_buff *skb; 159 }; 160 union { 161 struct mt76_txwi_cache *txwi; 162 struct urb *urb; 163 int buf_sz; 164 }; 165 u32 dma_addr[2]; 166 u16 dma_len[2]; 167 u16 wcid; 168 bool skip_buf0:1; 169 bool skip_buf1:1; 170 bool done:1; 171 }; 172 173 struct mt76_queue_regs { 174 u32 desc_base; 175 u32 ring_size; 176 u32 cpu_idx; 177 u32 dma_idx; 178 } __packed __aligned(4); 179 180 struct mt76_queue { 181 struct mt76_queue_regs __iomem *regs; 182 183 spinlock_t lock; 184 spinlock_t cleanup_lock; 185 struct mt76_queue_entry *entry; 186 struct mt76_desc *desc; 187 188 u16 first; 189 u16 head; 190 u16 tail; 191 int ndesc; 192 int queued; 193 int buf_size; 194 bool stopped; 195 bool blocked; 196 197 u8 buf_offset; 198 u8 hw_idx; 199 u8 flags; 200 201 u32 wed_regs; 202 203 dma_addr_t desc_dma; 204 struct sk_buff *rx_head; 205 struct page_pool *page_pool; 206 }; 207 208 struct mt76_mcu_ops { 209 u32 headroom; 210 u32 tailroom; 211 212 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 213 int len, bool wait_resp); 214 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 215 int cmd, int *seq); 216 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 217 struct sk_buff *skb, int seq); 218 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 219 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 220 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 221 const struct mt76_reg_pair *rp, int len); 222 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 223 struct mt76_reg_pair *rp, int len); 224 int (*mcu_restart)(struct mt76_dev *dev); 225 }; 226 227 struct mt76_queue_ops { 228 int (*init)(struct mt76_dev *dev, 229 int (*poll)(struct napi_struct *napi, int budget)); 230 231 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 232 int idx, int n_desc, int bufsize, 233 u32 ring_base); 234 235 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 236 enum mt76_txq_id qid, struct sk_buff *skb, 237 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 238 239 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 240 struct sk_buff *skb, u32 tx_info); 241 242 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 243 int *len, u32 *info, bool *more); 244 245 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 246 247 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 248 bool flush); 249 250 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 253 254 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 255 }; 256 257 enum mt76_phy_type { 258 MT_PHY_TYPE_CCK, 259 MT_PHY_TYPE_OFDM, 260 MT_PHY_TYPE_HT, 261 MT_PHY_TYPE_HT_GF, 262 MT_PHY_TYPE_VHT, 263 MT_PHY_TYPE_HE_SU = 8, 264 MT_PHY_TYPE_HE_EXT_SU, 265 MT_PHY_TYPE_HE_TB, 266 MT_PHY_TYPE_HE_MU, 267 MT_PHY_TYPE_EHT_SU = 13, 268 MT_PHY_TYPE_EHT_TRIG, 269 MT_PHY_TYPE_EHT_MU, 270 __MT_PHY_TYPE_MAX, 271 }; 272 273 struct mt76_sta_stats { 274 u64 tx_mode[__MT_PHY_TYPE_MAX]; 275 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 276 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 277 u64 tx_mcs[16]; /* mcs idx */ 278 u64 tx_bytes; 279 /* WED TX */ 280 u32 tx_packets; 281 u32 tx_retries; 282 u32 tx_failed; 283 /* WED RX */ 284 u64 rx_bytes; 285 u32 rx_packets; 286 u32 rx_errors; 287 u32 rx_drops; 288 }; 289 290 enum mt76_wcid_flags { 291 MT_WCID_FLAG_CHECK_PS, 292 MT_WCID_FLAG_PS, 293 MT_WCID_FLAG_4ADDR, 294 MT_WCID_FLAG_HDR_TRANS, 295 }; 296 297 #define MT76_N_WCIDS 1088 298 299 /* stored in ieee80211_tx_info::hw_queue */ 300 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 301 302 DECLARE_EWMA(signal, 10, 8); 303 304 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 305 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 306 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 307 #define MT_WCID_TX_INFO_SET BIT(31) 308 309 struct mt76_wcid { 310 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 311 312 atomic_t non_aql_packets; 313 unsigned long flags; 314 315 struct ewma_signal rssi; 316 int inactive_count; 317 318 struct rate_info rate; 319 320 u16 idx; 321 u8 hw_key_idx; 322 u8 hw_key_idx2; 323 324 u8 sta:1; 325 u8 amsdu:1; 326 u8 phy_idx:2; 327 328 u8 rx_check_pn; 329 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 330 u16 cipher; 331 332 u32 tx_info; 333 bool sw_iv; 334 335 struct list_head list; 336 struct idr pktid; 337 338 struct mt76_sta_stats stats; 339 }; 340 341 struct mt76_txq { 342 u16 wcid; 343 344 u16 agg_ssn; 345 bool send_bar; 346 bool aggr; 347 }; 348 349 struct mt76_txwi_cache { 350 struct list_head list; 351 dma_addr_t dma_addr; 352 353 union { 354 struct sk_buff *skb; 355 void *ptr; 356 }; 357 }; 358 359 struct mt76_rx_tid { 360 struct rcu_head rcu_head; 361 362 struct mt76_dev *dev; 363 364 spinlock_t lock; 365 struct delayed_work reorder_work; 366 367 u16 head; 368 u16 size; 369 u16 nframes; 370 371 u8 num; 372 373 u8 started:1, stopped:1, timer_pending:1; 374 375 struct sk_buff *reorder_buf[]; 376 }; 377 378 #define MT_TX_CB_DMA_DONE BIT(0) 379 #define MT_TX_CB_TXS_DONE BIT(1) 380 #define MT_TX_CB_TXS_FAILED BIT(2) 381 382 #define MT_PACKET_ID_MASK GENMASK(6, 0) 383 #define MT_PACKET_ID_NO_ACK 0 384 #define MT_PACKET_ID_NO_SKB 1 385 #define MT_PACKET_ID_WED 2 386 #define MT_PACKET_ID_FIRST 3 387 #define MT_PACKET_ID_HAS_RATE BIT(7) 388 /* This is timer for when to give up when waiting for TXS callback, 389 * with starting time being the time at which the DMA_DONE callback 390 * was seen (so, we know packet was processed then, it should not take 391 * long after that for firmware to send the TXS callback if it is going 392 * to do so.) 393 */ 394 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 395 396 struct mt76_tx_cb { 397 unsigned long jiffies; 398 u16 wcid; 399 u8 pktid; 400 u8 flags; 401 }; 402 403 enum { 404 MT76_STATE_INITIALIZED, 405 MT76_STATE_RUNNING, 406 MT76_STATE_MCU_RUNNING, 407 MT76_SCANNING, 408 MT76_HW_SCANNING, 409 MT76_HW_SCHED_SCANNING, 410 MT76_RESTART, 411 MT76_RESET, 412 MT76_MCU_RESET, 413 MT76_REMOVED, 414 MT76_READING_STATS, 415 MT76_STATE_POWER_OFF, 416 MT76_STATE_SUSPEND, 417 MT76_STATE_ROC, 418 MT76_STATE_PM, 419 MT76_STATE_WED_RESET, 420 }; 421 422 struct mt76_hw_cap { 423 bool has_2ghz; 424 bool has_5ghz; 425 bool has_6ghz; 426 }; 427 428 #define MT_DRV_TXWI_NO_FREE BIT(0) 429 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 430 #define MT_DRV_SW_RX_AIRTIME BIT(2) 431 #define MT_DRV_RX_DMA_HDR BIT(3) 432 #define MT_DRV_HW_MGMT_TXQ BIT(4) 433 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 434 435 struct mt76_driver_ops { 436 u32 drv_flags; 437 u32 survey_flags; 438 u16 txwi_size; 439 u16 token_size; 440 u8 mcs_rates; 441 442 void (*update_survey)(struct mt76_phy *phy); 443 444 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 445 enum mt76_txq_id qid, struct mt76_wcid *wcid, 446 struct ieee80211_sta *sta, 447 struct mt76_tx_info *tx_info); 448 449 void (*tx_complete_skb)(struct mt76_dev *dev, 450 struct mt76_queue_entry *e); 451 452 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 453 454 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 455 456 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 457 struct sk_buff *skb, u32 *info); 458 459 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 460 461 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 462 bool ps); 463 464 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 465 struct ieee80211_sta *sta); 466 467 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 468 struct ieee80211_sta *sta); 469 470 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 471 struct ieee80211_sta *sta); 472 }; 473 474 struct mt76_channel_state { 475 u64 cc_active; 476 u64 cc_busy; 477 u64 cc_rx; 478 u64 cc_bss_rx; 479 u64 cc_tx; 480 481 s8 noise; 482 }; 483 484 struct mt76_sband { 485 struct ieee80211_supported_band sband; 486 struct mt76_channel_state *chan; 487 }; 488 489 /* addr req mask */ 490 #define MT_VEND_TYPE_EEPROM BIT(31) 491 #define MT_VEND_TYPE_CFG BIT(30) 492 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 493 494 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 495 enum mt_vendor_req { 496 MT_VEND_DEV_MODE = 0x1, 497 MT_VEND_WRITE = 0x2, 498 MT_VEND_POWER_ON = 0x4, 499 MT_VEND_MULTI_WRITE = 0x6, 500 MT_VEND_MULTI_READ = 0x7, 501 MT_VEND_READ_EEPROM = 0x9, 502 MT_VEND_WRITE_FCE = 0x42, 503 MT_VEND_WRITE_CFG = 0x46, 504 MT_VEND_READ_CFG = 0x47, 505 MT_VEND_READ_EXT = 0x63, 506 MT_VEND_WRITE_EXT = 0x66, 507 MT_VEND_FEATURE_SET = 0x91, 508 }; 509 510 enum mt76u_in_ep { 511 MT_EP_IN_PKT_RX, 512 MT_EP_IN_CMD_RESP, 513 __MT_EP_IN_MAX, 514 }; 515 516 enum mt76u_out_ep { 517 MT_EP_OUT_INBAND_CMD, 518 MT_EP_OUT_AC_BE, 519 MT_EP_OUT_AC_BK, 520 MT_EP_OUT_AC_VI, 521 MT_EP_OUT_AC_VO, 522 MT_EP_OUT_HCCA, 523 __MT_EP_OUT_MAX, 524 }; 525 526 struct mt76_mcu { 527 struct mutex mutex; 528 u32 msg_seq; 529 int timeout; 530 531 struct sk_buff_head res_q; 532 wait_queue_head_t wait; 533 }; 534 535 #define MT_TX_SG_MAX_SIZE 8 536 #define MT_RX_SG_MAX_SIZE 4 537 #define MT_NUM_TX_ENTRIES 256 538 #define MT_NUM_RX_ENTRIES 128 539 #define MCU_RESP_URB_SIZE 1024 540 struct mt76_usb { 541 struct mutex usb_ctrl_mtx; 542 u8 *data; 543 u16 data_len; 544 545 struct mt76_worker status_worker; 546 struct mt76_worker rx_worker; 547 548 struct work_struct stat_work; 549 550 u8 out_ep[__MT_EP_OUT_MAX]; 551 u8 in_ep[__MT_EP_IN_MAX]; 552 bool sg_en; 553 554 struct mt76u_mcu { 555 u8 *data; 556 /* multiple reads */ 557 struct mt76_reg_pair *rp; 558 int rp_len; 559 u32 base; 560 } mcu; 561 }; 562 563 #define MT76S_XMIT_BUF_SZ 0x3fe00 564 #define MT76S_NUM_TX_ENTRIES 256 565 #define MT76S_NUM_RX_ENTRIES 512 566 struct mt76_sdio { 567 struct mt76_worker txrx_worker; 568 struct mt76_worker status_worker; 569 struct mt76_worker net_worker; 570 571 struct work_struct stat_work; 572 573 u8 *xmit_buf; 574 u32 xmit_buf_sz; 575 576 struct sdio_func *func; 577 void *intr_data; 578 u8 hw_ver; 579 wait_queue_head_t wait; 580 581 struct { 582 int pse_data_quota; 583 int ple_data_quota; 584 int pse_mcu_quota; 585 int pse_page_size; 586 int deficit; 587 } sched; 588 589 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 590 }; 591 592 struct mt76_mmio { 593 void __iomem *regs; 594 spinlock_t irq_lock; 595 u32 irqmask; 596 597 struct mtk_wed_device wed; 598 struct completion wed_reset; 599 struct completion wed_reset_complete; 600 }; 601 602 struct mt76_rx_status { 603 union { 604 struct mt76_wcid *wcid; 605 u16 wcid_idx; 606 }; 607 608 u32 reorder_time; 609 610 u32 ampdu_ref; 611 u32 timestamp; 612 613 u8 iv[6]; 614 615 u8 phy_idx:2; 616 u8 aggr:1; 617 u8 qos_ctl; 618 u16 seqno; 619 620 u16 freq; 621 u32 flag; 622 u8 enc_flags; 623 u8 encoding:2, bw:3, he_ru:3; 624 u8 he_gi:2, he_dcm:1; 625 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 626 u8 rate_idx; 627 u8 nss; 628 u8 band; 629 s8 signal; 630 u8 chains; 631 s8 chain_signal[IEEE80211_MAX_CHAINS]; 632 }; 633 634 struct mt76_freq_range_power { 635 const struct cfg80211_sar_freq_ranges *range; 636 s8 power; 637 }; 638 639 struct mt76_testmode_ops { 640 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 641 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 642 enum mt76_testmode_state new_state); 643 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 644 }; 645 646 struct mt76_testmode_data { 647 enum mt76_testmode_state state; 648 649 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 650 struct sk_buff *tx_skb; 651 652 u32 tx_count; 653 u16 tx_mpdu_len; 654 655 u8 tx_rate_mode; 656 u8 tx_rate_idx; 657 u8 tx_rate_nss; 658 u8 tx_rate_sgi; 659 u8 tx_rate_ldpc; 660 u8 tx_rate_stbc; 661 u8 tx_ltf; 662 663 u8 tx_antenna_mask; 664 u8 tx_spe_idx; 665 666 u8 tx_duty_cycle; 667 u32 tx_time; 668 u32 tx_ipg; 669 670 u32 freq_offset; 671 672 u8 tx_power[4]; 673 u8 tx_power_control; 674 675 u8 addr[3][ETH_ALEN]; 676 677 u32 tx_pending; 678 u32 tx_queued; 679 u16 tx_queued_limit; 680 u32 tx_done; 681 struct { 682 u64 packets[__MT_RXQ_MAX]; 683 u64 fcs_error[__MT_RXQ_MAX]; 684 } rx_stats; 685 }; 686 687 struct mt76_vif { 688 u8 idx; 689 u8 omac_idx; 690 u8 band_idx; 691 u8 wmm_idx; 692 u8 scan_seq_num; 693 u8 cipher; 694 }; 695 696 struct mt76_phy { 697 struct ieee80211_hw *hw; 698 struct mt76_dev *dev; 699 void *priv; 700 701 unsigned long state; 702 u8 band_idx; 703 704 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 705 706 struct cfg80211_chan_def chandef; 707 struct ieee80211_channel *main_chan; 708 709 struct mt76_channel_state *chan_state; 710 enum mt76_dfs_state dfs_state; 711 ktime_t survey_time; 712 713 u32 aggr_stats[32]; 714 715 struct mt76_hw_cap cap; 716 struct mt76_sband sband_2g; 717 struct mt76_sband sband_5g; 718 struct mt76_sband sband_6g; 719 720 u8 macaddr[ETH_ALEN]; 721 722 int txpower_cur; 723 u8 antenna_mask; 724 u16 chainmask; 725 726 #ifdef CONFIG_NL80211_TESTMODE 727 struct mt76_testmode_data test; 728 #endif 729 730 struct delayed_work mac_work; 731 u8 mac_work_count; 732 733 struct { 734 struct sk_buff *head; 735 struct sk_buff **tail; 736 u16 seqno; 737 } rx_amsdu[__MT_RXQ_MAX]; 738 739 struct mt76_freq_range_power *frp; 740 741 struct { 742 struct led_classdev cdev; 743 char name[32]; 744 bool al; 745 u8 pin; 746 } leds; 747 }; 748 749 struct mt76_dev { 750 struct mt76_phy phy; /* must be first */ 751 struct mt76_phy *phys[__MT_MAX_BAND]; 752 753 struct ieee80211_hw *hw; 754 755 spinlock_t wed_lock; 756 spinlock_t lock; 757 spinlock_t cc_lock; 758 759 u32 cur_cc_bss_rx; 760 761 struct mt76_rx_status rx_ampdu_status; 762 u32 rx_ampdu_len; 763 u32 rx_ampdu_ref; 764 765 struct mutex mutex; 766 767 const struct mt76_bus_ops *bus; 768 const struct mt76_driver_ops *drv; 769 const struct mt76_mcu_ops *mcu_ops; 770 struct device *dev; 771 struct device *dma_dev; 772 773 struct mt76_mcu mcu; 774 775 struct net_device napi_dev; 776 struct net_device tx_napi_dev; 777 spinlock_t rx_lock; 778 struct napi_struct napi[__MT_RXQ_MAX]; 779 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 780 781 struct list_head txwi_cache; 782 struct list_head rxwi_cache; 783 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 784 struct mt76_queue q_rx[__MT_RXQ_MAX]; 785 const struct mt76_queue_ops *queue_ops; 786 int tx_dma_idx[4]; 787 788 struct mt76_worker tx_worker; 789 struct napi_struct tx_napi; 790 791 spinlock_t token_lock; 792 struct idr token; 793 u16 wed_token_count; 794 u16 token_count; 795 u16 token_size; 796 797 spinlock_t rx_token_lock; 798 struct idr rx_token; 799 u16 rx_token_size; 800 801 wait_queue_head_t tx_wait; 802 /* spinclock used to protect wcid pktid linked list */ 803 spinlock_t status_lock; 804 805 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 806 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 807 808 u64 vif_mask; 809 810 struct mt76_wcid global_wcid; 811 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 812 struct list_head wcid_list; 813 814 u32 rev; 815 816 struct tasklet_struct pre_tbtt_tasklet; 817 int beacon_int; 818 u8 beacon_mask; 819 820 struct debugfs_blob_wrapper eeprom; 821 struct debugfs_blob_wrapper otp; 822 823 char alpha2[3]; 824 enum nl80211_dfs_regions region; 825 826 u32 debugfs_reg; 827 828 u8 csa_complete; 829 830 u32 rxfilter; 831 832 #ifdef CONFIG_NL80211_TESTMODE 833 const struct mt76_testmode_ops *test_ops; 834 struct { 835 const char *name; 836 u32 offset; 837 } test_mtd; 838 #endif 839 struct workqueue_struct *wq; 840 841 union { 842 struct mt76_mmio mmio; 843 struct mt76_usb usb; 844 struct mt76_sdio sdio; 845 }; 846 }; 847 848 struct mt76_power_limits { 849 s8 cck[4]; 850 s8 ofdm[8]; 851 s8 mcs[4][10]; 852 s8 ru[7][12]; 853 }; 854 855 struct mt76_ethtool_worker_info { 856 u64 *data; 857 int idx; 858 int initial_stat_idx; 859 int worker_stat_count; 860 int sta_count; 861 }; 862 863 #define CCK_RATE(_idx, _rate) { \ 864 .bitrate = _rate, \ 865 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 866 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 867 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 868 } 869 870 #define OFDM_RATE(_idx, _rate) { \ 871 .bitrate = _rate, \ 872 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 873 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 874 } 875 876 extern struct ieee80211_rate mt76_rates[12]; 877 878 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 879 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 880 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 881 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 882 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 883 884 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 885 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 886 887 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 888 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 889 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 890 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 891 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 892 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 893 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 894 895 896 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 897 898 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 899 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 900 901 #define mt76_get_field(_dev, _reg, _field) \ 902 FIELD_GET(_field, mt76_rr(dev, _reg)) 903 904 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 905 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 906 907 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 908 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 909 910 #define mt76_hw(dev) (dev)->mphy.hw 911 912 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 913 int timeout); 914 915 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 916 917 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 918 int timeout, int kick); 919 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 920 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 921 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 922 923 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 924 void mt76_pci_disable_aspm(struct pci_dev *pdev); 925 926 static inline u16 mt76_chip(struct mt76_dev *dev) 927 { 928 return dev->rev >> 16; 929 } 930 931 static inline u16 mt76_rev(struct mt76_dev *dev) 932 { 933 return dev->rev & 0xffff; 934 } 935 936 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 937 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 938 939 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 940 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 941 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 942 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 943 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 944 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 945 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 946 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 947 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 948 949 #define mt76_for_each_q_rx(dev, i) \ 950 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 951 if ((dev)->q_rx[i].ndesc) 952 953 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 954 const struct ieee80211_ops *ops, 955 const struct mt76_driver_ops *drv_ops); 956 int mt76_register_device(struct mt76_dev *dev, bool vht, 957 struct ieee80211_rate *rates, int n_rates); 958 void mt76_unregister_device(struct mt76_dev *dev); 959 void mt76_free_device(struct mt76_dev *dev); 960 void mt76_unregister_phy(struct mt76_phy *phy); 961 962 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 963 const struct ieee80211_ops *ops, 964 u8 band_idx); 965 int mt76_register_phy(struct mt76_phy *phy, bool vht, 966 struct ieee80211_rate *rates, int n_rates); 967 968 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 969 const struct file_operations *ops); 970 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 971 { 972 return mt76_register_debugfs_fops(&dev->phy, NULL); 973 } 974 975 int mt76_queues_read(struct seq_file *s, void *data); 976 void mt76_seq_puts_array(struct seq_file *file, const char *str, 977 s8 *val, int len); 978 979 int mt76_eeprom_init(struct mt76_dev *dev, int len); 980 void mt76_eeprom_override(struct mt76_phy *phy); 981 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 982 983 struct mt76_queue * 984 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 985 int ring_base, u32 flags); 986 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 987 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 988 int n_desc, int ring_base, u32 flags) 989 { 990 struct mt76_queue *q; 991 992 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 993 if (IS_ERR(q)) 994 return PTR_ERR(q); 995 996 phy->q_tx[qid] = q; 997 998 return 0; 999 } 1000 1001 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1002 int n_desc, int ring_base) 1003 { 1004 struct mt76_queue *q; 1005 1006 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1007 if (IS_ERR(q)) 1008 return PTR_ERR(q); 1009 1010 dev->q_mcu[qid] = q; 1011 1012 return 0; 1013 } 1014 1015 static inline struct mt76_phy * 1016 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1017 { 1018 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1019 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1020 return dev->phys[phy_idx]; 1021 1022 return &dev->phy; 1023 } 1024 1025 static inline struct ieee80211_hw * 1026 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1027 { 1028 return mt76_dev_phy(dev, phy_idx)->hw; 1029 } 1030 1031 static inline u8 * 1032 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1033 { 1034 return (u8 *)t - dev->drv->txwi_size; 1035 } 1036 1037 /* increment with wrap-around */ 1038 static inline int mt76_incr(int val, int size) 1039 { 1040 return (val + 1) & (size - 1); 1041 } 1042 1043 /* decrement with wrap-around */ 1044 static inline int mt76_decr(int val, int size) 1045 { 1046 return (val - 1) & (size - 1); 1047 } 1048 1049 u8 mt76_ac_to_hwq(u8 ac); 1050 1051 static inline struct ieee80211_txq * 1052 mtxq_to_txq(struct mt76_txq *mtxq) 1053 { 1054 void *ptr = mtxq; 1055 1056 return container_of(ptr, struct ieee80211_txq, drv_priv); 1057 } 1058 1059 static inline struct ieee80211_sta * 1060 wcid_to_sta(struct mt76_wcid *wcid) 1061 { 1062 void *ptr = wcid; 1063 1064 if (!wcid || !wcid->sta) 1065 return NULL; 1066 1067 return container_of(ptr, struct ieee80211_sta, drv_priv); 1068 } 1069 1070 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1071 { 1072 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1073 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1074 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1075 } 1076 1077 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1078 { 1079 struct mt76_rx_status mstat; 1080 u8 *data = skb->data; 1081 1082 /* Alignment concerns */ 1083 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1084 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1085 1086 mstat = *((struct mt76_rx_status *)skb->cb); 1087 1088 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1089 data += sizeof(struct ieee80211_radiotap_he); 1090 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1091 data += sizeof(struct ieee80211_radiotap_he_mu); 1092 1093 return data; 1094 } 1095 1096 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1097 { 1098 int len = ieee80211_get_hdrlen_from_skb(skb); 1099 1100 if (len % 4 == 0) 1101 return; 1102 1103 skb_push(skb, 2); 1104 memmove(skb->data, skb->data + 2, len); 1105 1106 skb->data[len] = 0; 1107 skb->data[len + 1] = 0; 1108 } 1109 1110 static inline bool mt76_is_skb_pktid(u8 pktid) 1111 { 1112 if (pktid & MT_PACKET_ID_HAS_RATE) 1113 return false; 1114 1115 return pktid >= MT_PACKET_ID_FIRST; 1116 } 1117 1118 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1119 { 1120 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1121 u8 idx = nss - 1; 1122 1123 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1124 } 1125 1126 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1127 { 1128 #ifdef CONFIG_NL80211_TESTMODE 1129 return phy->test.state != MT76_TM_STATE_OFF; 1130 #else 1131 return false; 1132 #endif 1133 } 1134 1135 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1136 struct sk_buff *skb, 1137 struct ieee80211_hw **hw) 1138 { 1139 #ifdef CONFIG_NL80211_TESTMODE 1140 int i; 1141 1142 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1143 struct mt76_phy *phy = dev->phys[i]; 1144 1145 if (phy && skb == phy->test.tx_skb) { 1146 *hw = dev->phys[i]->hw; 1147 return true; 1148 } 1149 } 1150 return false; 1151 #else 1152 return false; 1153 #endif 1154 } 1155 1156 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1157 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1158 struct mt76_wcid *wcid, struct sk_buff *skb); 1159 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1160 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1161 bool send_bar); 1162 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1163 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1164 void mt76_txq_schedule_all(struct mt76_phy *phy); 1165 void mt76_tx_worker_run(struct mt76_dev *dev); 1166 void mt76_tx_worker(struct mt76_worker *w); 1167 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1168 struct ieee80211_sta *sta, 1169 u16 tids, int nframes, 1170 enum ieee80211_frame_release_type reason, 1171 bool more_data); 1172 bool mt76_has_tx_pending(struct mt76_phy *phy); 1173 void mt76_set_channel(struct mt76_phy *phy); 1174 void mt76_update_survey(struct mt76_phy *phy); 1175 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1176 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1177 struct survey_info *survey); 1178 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1179 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1180 1181 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1182 u16 ssn, u16 size); 1183 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1184 1185 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1186 struct ieee80211_key_conf *key); 1187 1188 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1189 __acquires(&dev->status_lock); 1190 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1191 __releases(&dev->status_lock); 1192 1193 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1194 struct sk_buff *skb); 1195 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1196 struct mt76_wcid *wcid, int pktid, 1197 struct sk_buff_head *list); 1198 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1199 struct sk_buff_head *list); 1200 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1201 struct list_head *free_list); 1202 static inline void 1203 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1204 { 1205 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1206 } 1207 1208 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1209 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1210 struct ieee80211_sta *sta, 1211 enum ieee80211_sta_state old_state, 1212 enum ieee80211_sta_state new_state); 1213 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1214 struct ieee80211_sta *sta); 1215 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1216 struct ieee80211_sta *sta); 1217 1218 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1219 1220 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1221 int *dbm); 1222 int mt76_init_sar_power(struct ieee80211_hw *hw, 1223 const struct cfg80211_sar_specs *sar); 1224 int mt76_get_sar_power(struct mt76_phy *phy, 1225 struct ieee80211_channel *chan, 1226 int power); 1227 1228 void mt76_csa_check(struct mt76_dev *dev); 1229 void mt76_csa_finish(struct mt76_dev *dev); 1230 1231 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1232 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1233 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1234 int mt76_get_rate(struct mt76_dev *dev, 1235 struct ieee80211_supported_band *sband, 1236 int idx, bool cck); 1237 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1238 const u8 *mac); 1239 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1240 struct ieee80211_vif *vif); 1241 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1242 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1243 void *data, int len); 1244 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1245 struct netlink_callback *cb, void *data, int len); 1246 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1247 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1248 1249 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1250 { 1251 #ifdef CONFIG_NL80211_TESTMODE 1252 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1253 1254 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1255 state = MT76_TM_STATE_OFF; 1256 1257 mt76_testmode_set_state(phy, state); 1258 #endif 1259 } 1260 1261 1262 /* internal */ 1263 static inline struct ieee80211_hw * 1264 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1265 { 1266 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1267 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1268 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1269 1270 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1271 1272 return hw; 1273 } 1274 1275 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1276 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1277 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1278 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1279 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1280 struct napi_struct *napi); 1281 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1282 struct napi_struct *napi); 1283 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1284 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1285 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1286 struct mt76_queue_entry *e); 1287 1288 /* usb */ 1289 static inline bool mt76u_urb_error(struct urb *urb) 1290 { 1291 return urb->status && 1292 urb->status != -ECONNRESET && 1293 urb->status != -ESHUTDOWN && 1294 urb->status != -ENOENT; 1295 } 1296 1297 /* Map hardware queues to usb endpoints */ 1298 static inline u8 q2ep(u8 qid) 1299 { 1300 /* TODO: take management packets to queue 5 */ 1301 return qid + 1; 1302 } 1303 1304 static inline int 1305 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1306 int timeout, int ep) 1307 { 1308 struct usb_interface *uintf = to_usb_interface(dev->dev); 1309 struct usb_device *udev = interface_to_usbdev(uintf); 1310 struct mt76_usb *usb = &dev->usb; 1311 unsigned int pipe; 1312 1313 if (actual_len) 1314 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1315 else 1316 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1317 1318 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1319 } 1320 1321 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1322 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1323 struct mt76_sta_stats *stats, bool eht); 1324 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1325 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1326 u16 val, u16 offset, void *buf, size_t len); 1327 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1328 u8 req_type, u16 val, u16 offset, 1329 void *buf, size_t len); 1330 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1331 const u16 offset, const u32 val); 1332 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1333 void *data, int len); 1334 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1335 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1336 u32 addr, u32 val); 1337 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1338 struct mt76_bus_ops *ops); 1339 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1340 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1341 int mt76u_alloc_queues(struct mt76_dev *dev); 1342 void mt76u_stop_tx(struct mt76_dev *dev); 1343 void mt76u_stop_rx(struct mt76_dev *dev); 1344 int mt76u_resume_rx(struct mt76_dev *dev); 1345 void mt76u_queues_deinit(struct mt76_dev *dev); 1346 1347 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1348 const struct mt76_bus_ops *bus_ops); 1349 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1350 int mt76s_alloc_tx(struct mt76_dev *dev); 1351 void mt76s_deinit(struct mt76_dev *dev); 1352 void mt76s_sdio_irq(struct sdio_func *func); 1353 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1354 bool mt76s_txqs_empty(struct mt76_dev *dev); 1355 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1356 int hw_ver); 1357 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1358 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1359 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1360 u32 mt76s_read_pcr(struct mt76_dev *dev); 1361 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1362 const void *data, int len); 1363 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1364 void *data, int len); 1365 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1366 const struct mt76_reg_pair *data, 1367 int len); 1368 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1369 struct mt76_reg_pair *data, int len); 1370 1371 struct sk_buff * 1372 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1373 int len, int data_len, gfp_t gfp); 1374 static inline struct sk_buff * 1375 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1376 int data_len) 1377 { 1378 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1379 } 1380 1381 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1382 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1383 unsigned long expires); 1384 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1385 int len, bool wait_resp, struct sk_buff **ret); 1386 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1387 int cmd, bool wait_resp, struct sk_buff **ret); 1388 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1389 int len, int max_len); 1390 static inline int 1391 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1392 int len) 1393 { 1394 int max_len = 4096 - dev->mcu_ops->headroom; 1395 1396 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1397 } 1398 1399 static inline int 1400 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1401 bool wait_resp) 1402 { 1403 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1404 } 1405 1406 static inline int 1407 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1408 bool wait_resp) 1409 { 1410 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1411 } 1412 1413 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1414 1415 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1416 struct ieee80211_channel *chan, 1417 struct mt76_power_limits *dest, 1418 s8 target_power); 1419 1420 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1421 { 1422 return (q->flags & MT_QFLAG_WED) && 1423 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1424 } 1425 1426 struct mt76_txwi_cache * 1427 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1428 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1429 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1430 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1431 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1432 struct mt76_txwi_cache *r, dma_addr_t phys); 1433 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1434 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1435 { 1436 struct page *page = virt_to_head_page(buf); 1437 1438 page_pool_put_full_page(page->pp, page, allow_direct); 1439 } 1440 1441 static inline void * 1442 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1443 { 1444 struct page *page; 1445 1446 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1447 if (!page) 1448 return NULL; 1449 1450 return page_address(page) + *offset; 1451 } 1452 1453 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1454 { 1455 spin_lock_bh(&dev->token_lock); 1456 __mt76_set_tx_blocked(dev, blocked); 1457 spin_unlock_bh(&dev->token_lock); 1458 } 1459 1460 static inline int 1461 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1462 { 1463 int token; 1464 1465 spin_lock_bh(&dev->token_lock); 1466 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1467 spin_unlock_bh(&dev->token_lock); 1468 1469 return token; 1470 } 1471 1472 static inline struct mt76_txwi_cache * 1473 mt76_token_put(struct mt76_dev *dev, int token) 1474 { 1475 struct mt76_txwi_cache *txwi; 1476 1477 spin_lock_bh(&dev->token_lock); 1478 txwi = idr_remove(&dev->token, token); 1479 spin_unlock_bh(&dev->token_lock); 1480 1481 return txwi; 1482 } 1483 1484 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1485 { 1486 INIT_LIST_HEAD(&wcid->list); 1487 idr_init(&wcid->pktid); 1488 } 1489 1490 static inline void 1491 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1492 { 1493 struct sk_buff_head list; 1494 1495 mt76_tx_status_lock(dev, &list); 1496 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1497 mt76_tx_status_unlock(dev, &list); 1498 1499 idr_destroy(&wcid->pktid); 1500 } 1501 1502 #endif 1503