1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include <net/page_pool/helpers.h> 19 #include "util.h" 20 #include "testmode.h" 21 22 #define MT_MCU_RING_SIZE 32 23 #define MT_RX_BUF_SIZE 2048 24 #define MT_SKB_HEAD_LEN 256 25 26 #define MT_MAX_NON_AQL_PKT 16 27 #define MT_TXQ_FREE_THR 32 28 29 #define MT76_TOKEN_FREE_THR 64 30 31 #define MT_QFLAG_WED_RING GENMASK(1, 0) 32 #define MT_QFLAG_WED_TYPE GENMASK(4, 2) 33 #define MT_QFLAG_WED BIT(5) 34 #define MT_QFLAG_WED_RRO BIT(6) 35 #define MT_QFLAG_WED_RRO_EN BIT(7) 36 37 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 38 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 39 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 40 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n)) 41 42 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 43 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 44 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 45 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 46 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 47 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 48 49 struct mt76_dev; 50 struct mt76_phy; 51 struct mt76_wcid; 52 struct mt76s_intr; 53 struct mt76_chanctx; 54 struct mt76_vif_link; 55 56 struct mt76_reg_pair { 57 u32 reg; 58 u32 value; 59 }; 60 61 enum mt76_bus_type { 62 MT76_BUS_MMIO, 63 MT76_BUS_USB, 64 MT76_BUS_SDIO, 65 }; 66 67 enum mt76_wed_type { 68 MT76_WED_Q_TX, 69 MT76_WED_Q_TXFREE, 70 MT76_WED_Q_RX, 71 MT76_WED_RRO_Q_DATA, 72 MT76_WED_RRO_Q_MSDU_PG, 73 MT76_WED_RRO_Q_IND, 74 }; 75 76 struct mt76_bus_ops { 77 u32 (*rr)(struct mt76_dev *dev, u32 offset); 78 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 79 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 80 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 81 int len); 82 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 83 int len); 84 int (*wr_rp)(struct mt76_dev *dev, u32 base, 85 const struct mt76_reg_pair *rp, int len); 86 int (*rd_rp)(struct mt76_dev *dev, u32 base, 87 struct mt76_reg_pair *rp, int len); 88 enum mt76_bus_type type; 89 }; 90 91 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 92 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 93 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 94 95 enum mt76_txq_id { 96 MT_TXQ_VO = IEEE80211_AC_VO, 97 MT_TXQ_VI = IEEE80211_AC_VI, 98 MT_TXQ_BE = IEEE80211_AC_BE, 99 MT_TXQ_BK = IEEE80211_AC_BK, 100 MT_TXQ_PSD, 101 MT_TXQ_BEACON, 102 MT_TXQ_CAB, 103 __MT_TXQ_MAX 104 }; 105 106 enum mt76_mcuq_id { 107 MT_MCUQ_WM, 108 MT_MCUQ_WA, 109 MT_MCUQ_FWDL, 110 __MT_MCUQ_MAX 111 }; 112 113 enum mt76_rxq_id { 114 MT_RXQ_MAIN, 115 MT_RXQ_MCU, 116 MT_RXQ_MCU_WA, 117 MT_RXQ_BAND1, 118 MT_RXQ_BAND1_WA, 119 MT_RXQ_MAIN_WA, 120 MT_RXQ_BAND2, 121 MT_RXQ_BAND2_WA, 122 MT_RXQ_RRO_BAND0, 123 MT_RXQ_RRO_BAND1, 124 MT_RXQ_RRO_BAND2, 125 MT_RXQ_MSDU_PAGE_BAND0, 126 MT_RXQ_MSDU_PAGE_BAND1, 127 MT_RXQ_MSDU_PAGE_BAND2, 128 MT_RXQ_TXFREE_BAND0, 129 MT_RXQ_TXFREE_BAND1, 130 MT_RXQ_TXFREE_BAND2, 131 MT_RXQ_RRO_IND, 132 __MT_RXQ_MAX 133 }; 134 135 enum mt76_band_id { 136 MT_BAND0, 137 MT_BAND1, 138 MT_BAND2, 139 __MT_MAX_BAND 140 }; 141 142 enum mt76_cipher_type { 143 MT_CIPHER_NONE, 144 MT_CIPHER_WEP40, 145 MT_CIPHER_TKIP, 146 MT_CIPHER_TKIP_NO_MIC, 147 MT_CIPHER_AES_CCMP, 148 MT_CIPHER_WEP104, 149 MT_CIPHER_BIP_CMAC_128, 150 MT_CIPHER_WEP128, 151 MT_CIPHER_WAPI, 152 MT_CIPHER_CCMP_CCX, 153 MT_CIPHER_CCMP_256, 154 MT_CIPHER_GCMP, 155 MT_CIPHER_GCMP_256, 156 }; 157 158 enum mt76_dfs_state { 159 MT_DFS_STATE_UNKNOWN, 160 MT_DFS_STATE_DISABLED, 161 MT_DFS_STATE_CAC, 162 MT_DFS_STATE_ACTIVE, 163 }; 164 165 struct mt76_queue_buf { 166 dma_addr_t addr; 167 u16 len:15, 168 skip_unmap:1; 169 }; 170 171 struct mt76_tx_info { 172 struct mt76_queue_buf buf[32]; 173 struct sk_buff *skb; 174 int nbuf; 175 u32 info; 176 }; 177 178 struct mt76_queue_entry { 179 union { 180 void *buf; 181 struct sk_buff *skb; 182 }; 183 union { 184 struct mt76_txwi_cache *txwi; 185 struct urb *urb; 186 int buf_sz; 187 }; 188 dma_addr_t dma_addr[2]; 189 u16 dma_len[2]; 190 u16 wcid; 191 bool skip_buf0:1; 192 bool skip_buf1:1; 193 bool done:1; 194 }; 195 196 struct mt76_queue_regs { 197 u32 desc_base; 198 u32 ring_size; 199 u32 cpu_idx; 200 u32 dma_idx; 201 } __packed __aligned(4); 202 203 struct mt76_queue { 204 struct mt76_queue_regs __iomem *regs; 205 206 spinlock_t lock; 207 spinlock_t cleanup_lock; 208 struct mt76_queue_entry *entry; 209 struct mt76_rro_desc *rro_desc; 210 struct mt76_desc *desc; 211 212 u16 first; 213 u16 head; 214 u16 tail; 215 u8 hw_idx; 216 u8 ep; 217 int ndesc; 218 int queued; 219 int buf_size; 220 bool stopped; 221 bool blocked; 222 223 u8 buf_offset; 224 u16 flags; 225 226 struct mtk_wed_device *wed; 227 u32 wed_regs; 228 229 dma_addr_t desc_dma; 230 struct sk_buff *rx_head; 231 struct page_pool *page_pool; 232 }; 233 234 struct mt76_mcu_ops { 235 unsigned int max_retry; 236 u32 headroom; 237 u32 tailroom; 238 239 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 240 int len, bool wait_resp); 241 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb, 242 int cmd, int *seq); 243 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 244 int cmd, int *seq); 245 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 246 struct sk_buff *skb, int seq); 247 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 248 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 249 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 250 const struct mt76_reg_pair *rp, int len); 251 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 252 struct mt76_reg_pair *rp, int len); 253 int (*mcu_restart)(struct mt76_dev *dev); 254 }; 255 256 struct mt76_queue_ops { 257 int (*init)(struct mt76_dev *dev, 258 int (*poll)(struct napi_struct *napi, int budget)); 259 260 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 261 int idx, int n_desc, int bufsize, 262 u32 ring_base); 263 264 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q, 265 enum mt76_txq_id qid, struct sk_buff *skb, 266 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 267 268 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 269 struct sk_buff *skb, u32 tx_info); 270 271 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 272 int *len, u32 *info, bool *more); 273 274 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 275 276 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 277 bool flush); 278 279 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 280 281 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 282 283 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 284 }; 285 286 enum mt76_phy_type { 287 MT_PHY_TYPE_CCK, 288 MT_PHY_TYPE_OFDM, 289 MT_PHY_TYPE_HT, 290 MT_PHY_TYPE_HT_GF, 291 MT_PHY_TYPE_VHT, 292 MT_PHY_TYPE_HE_SU = 8, 293 MT_PHY_TYPE_HE_EXT_SU, 294 MT_PHY_TYPE_HE_TB, 295 MT_PHY_TYPE_HE_MU, 296 MT_PHY_TYPE_EHT_SU = 13, 297 MT_PHY_TYPE_EHT_TRIG, 298 MT_PHY_TYPE_EHT_MU, 299 __MT_PHY_TYPE_MAX, 300 }; 301 302 struct mt76_sta_stats { 303 u64 tx_mode[__MT_PHY_TYPE_MAX]; 304 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 305 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 306 u64 tx_mcs[16]; /* mcs idx */ 307 u64 tx_bytes; 308 /* WED TX */ 309 u32 tx_packets; /* unit: MSDU */ 310 u32 tx_retries; 311 u32 tx_failed; 312 /* WED RX */ 313 u64 rx_bytes; 314 u32 rx_packets; 315 u32 rx_errors; 316 u32 rx_drops; 317 }; 318 319 enum mt76_wcid_flags { 320 MT_WCID_FLAG_CHECK_PS, 321 MT_WCID_FLAG_PS, 322 MT_WCID_FLAG_4ADDR, 323 MT_WCID_FLAG_HDR_TRANS, 324 }; 325 326 #define MT76_N_WCIDS 1088 327 328 /* stored in ieee80211_tx_info::hw_queue */ 329 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 330 331 DECLARE_EWMA(signal, 10, 8); 332 333 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 334 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 335 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 336 #define MT_WCID_TX_INFO_SET BIT(31) 337 338 struct mt76_wcid { 339 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 340 341 atomic_t non_aql_packets; 342 unsigned long flags; 343 344 struct ewma_signal rssi; 345 int inactive_count; 346 347 struct rate_info rate; 348 unsigned long ampdu_state; 349 350 u16 idx; 351 u8 hw_key_idx; 352 u8 hw_key_idx2; 353 354 u8 offchannel:1; 355 u8 sta:1; 356 u8 sta_disabled:1; 357 u8 amsdu:1; 358 u8 phy_idx:2; 359 u8 link_id:4; 360 bool link_valid; 361 362 u8 rx_check_pn; 363 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 364 u16 cipher; 365 366 u32 tx_info; 367 bool sw_iv; 368 369 struct list_head tx_list; 370 struct sk_buff_head tx_pending; 371 struct sk_buff_head tx_offchannel; 372 373 struct list_head list; 374 struct idr pktid; 375 376 struct mt76_sta_stats stats; 377 378 struct list_head poll_list; 379 380 struct mt76_wcid *def_wcid; 381 }; 382 383 struct mt76_txq { 384 u16 wcid; 385 386 u16 agg_ssn; 387 bool send_bar; 388 bool aggr; 389 }; 390 391 struct mt76_wed_rro_ind { 392 u32 se_id : 12; 393 u32 rsv : 4; 394 u32 start_sn : 12; 395 u32 ind_reason : 4; 396 u32 ind_cnt : 13; 397 u32 win_sz : 3; 398 u32 rsv2 : 13; 399 u32 magic_cnt : 3; 400 }; 401 402 struct mt76_txwi_cache { 403 struct list_head list; 404 dma_addr_t dma_addr; 405 406 union { 407 struct sk_buff *skb; 408 void *ptr; 409 }; 410 }; 411 412 struct mt76_rx_tid { 413 struct rcu_head rcu_head; 414 415 struct mt76_dev *dev; 416 417 spinlock_t lock; 418 struct delayed_work reorder_work; 419 420 u16 id; 421 u16 head; 422 u16 size; 423 u16 nframes; 424 425 u8 num; 426 427 u8 started:1, stopped:1, timer_pending:1; 428 429 struct sk_buff *reorder_buf[] __counted_by(size); 430 }; 431 432 #define MT_TX_CB_DMA_DONE BIT(0) 433 #define MT_TX_CB_TXS_DONE BIT(1) 434 #define MT_TX_CB_TXS_FAILED BIT(2) 435 436 #define MT_PACKET_ID_MASK GENMASK(6, 0) 437 #define MT_PACKET_ID_NO_ACK 0 438 #define MT_PACKET_ID_NO_SKB 1 439 #define MT_PACKET_ID_WED 2 440 #define MT_PACKET_ID_FIRST 3 441 #define MT_PACKET_ID_HAS_RATE BIT(7) 442 /* This is timer for when to give up when waiting for TXS callback, 443 * with starting time being the time at which the DMA_DONE callback 444 * was seen (so, we know packet was processed then, it should not take 445 * long after that for firmware to send the TXS callback if it is going 446 * to do so.) 447 */ 448 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 449 450 struct mt76_tx_cb { 451 unsigned long jiffies; 452 u16 wcid; 453 u8 pktid; 454 u8 flags; 455 }; 456 457 enum { 458 MT76_STATE_INITIALIZED, 459 MT76_STATE_REGISTERED, 460 MT76_STATE_RUNNING, 461 MT76_STATE_MCU_RUNNING, 462 MT76_SCANNING, 463 MT76_HW_SCANNING, 464 MT76_HW_SCHED_SCANNING, 465 MT76_RESTART, 466 MT76_RESET, 467 MT76_MCU_RESET, 468 MT76_REMOVED, 469 MT76_READING_STATS, 470 MT76_STATE_POWER_OFF, 471 MT76_STATE_SUSPEND, 472 MT76_STATE_ROC, 473 MT76_STATE_PM, 474 MT76_STATE_WED_RESET, 475 }; 476 477 enum mt76_sta_event { 478 MT76_STA_EVENT_ASSOC, 479 MT76_STA_EVENT_AUTHORIZE, 480 MT76_STA_EVENT_DISASSOC, 481 }; 482 483 struct mt76_hw_cap { 484 bool has_2ghz; 485 bool has_5ghz; 486 bool has_6ghz; 487 }; 488 489 #define MT_DRV_TXWI_NO_FREE BIT(0) 490 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 491 #define MT_DRV_SW_RX_AIRTIME BIT(2) 492 #define MT_DRV_RX_DMA_HDR BIT(3) 493 #define MT_DRV_HW_MGMT_TXQ BIT(4) 494 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 495 #define MT_DRV_IGNORE_TXS_FAILED BIT(6) 496 497 struct mt76_driver_ops { 498 u32 drv_flags; 499 u32 survey_flags; 500 u16 txwi_size; 501 u16 token_size; 502 u8 mcs_rates; 503 504 unsigned int link_data_size; 505 506 void (*update_survey)(struct mt76_phy *phy); 507 int (*set_channel)(struct mt76_phy *phy); 508 509 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 510 enum mt76_txq_id qid, struct mt76_wcid *wcid, 511 struct ieee80211_sta *sta, 512 struct mt76_tx_info *tx_info); 513 514 void (*tx_complete_skb)(struct mt76_dev *dev, 515 struct mt76_queue_entry *e); 516 517 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 518 519 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 520 521 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 522 struct sk_buff *skb, u32 *info); 523 524 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 525 526 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 527 bool ps); 528 529 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 530 struct ieee80211_sta *sta); 531 532 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif, 533 struct ieee80211_sta *sta, enum mt76_sta_event ev); 534 535 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 536 struct ieee80211_sta *sta); 537 538 int (*vif_link_add)(struct mt76_phy *phy, struct ieee80211_vif *vif, 539 struct ieee80211_bss_conf *link_conf, 540 struct mt76_vif_link *mlink); 541 542 void (*vif_link_remove)(struct mt76_phy *phy, 543 struct ieee80211_vif *vif, 544 struct ieee80211_bss_conf *link_conf, 545 struct mt76_vif_link *mlink); 546 }; 547 548 struct mt76_channel_state { 549 u64 cc_active; 550 u64 cc_busy; 551 u64 cc_rx; 552 u64 cc_bss_rx; 553 u64 cc_tx; 554 555 s8 noise; 556 }; 557 558 struct mt76_sband { 559 struct ieee80211_supported_band sband; 560 struct mt76_channel_state *chan; 561 }; 562 563 /* addr req mask */ 564 #define MT_VEND_TYPE_EEPROM BIT(31) 565 #define MT_VEND_TYPE_CFG BIT(30) 566 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 567 568 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 569 enum mt_vendor_req { 570 MT_VEND_DEV_MODE = 0x1, 571 MT_VEND_WRITE = 0x2, 572 MT_VEND_POWER_ON = 0x4, 573 MT_VEND_MULTI_WRITE = 0x6, 574 MT_VEND_MULTI_READ = 0x7, 575 MT_VEND_READ_EEPROM = 0x9, 576 MT_VEND_WRITE_FCE = 0x42, 577 MT_VEND_WRITE_CFG = 0x46, 578 MT_VEND_READ_CFG = 0x47, 579 MT_VEND_READ_EXT = 0x63, 580 MT_VEND_WRITE_EXT = 0x66, 581 MT_VEND_FEATURE_SET = 0x91, 582 }; 583 584 enum mt76u_in_ep { 585 MT_EP_IN_PKT_RX, 586 MT_EP_IN_CMD_RESP, 587 __MT_EP_IN_MAX, 588 }; 589 590 enum mt76u_out_ep { 591 MT_EP_OUT_INBAND_CMD, 592 MT_EP_OUT_AC_BE, 593 MT_EP_OUT_AC_BK, 594 MT_EP_OUT_AC_VI, 595 MT_EP_OUT_AC_VO, 596 MT_EP_OUT_HCCA, 597 __MT_EP_OUT_MAX, 598 }; 599 600 struct mt76_mcu { 601 struct mutex mutex; 602 u32 msg_seq; 603 int timeout; 604 605 struct sk_buff_head res_q; 606 wait_queue_head_t wait; 607 }; 608 609 #define MT_TX_SG_MAX_SIZE 8 610 #define MT_RX_SG_MAX_SIZE 4 611 #define MT_NUM_TX_ENTRIES 256 612 #define MT_NUM_RX_ENTRIES 128 613 #define MCU_RESP_URB_SIZE 1024 614 struct mt76_usb { 615 struct mutex usb_ctrl_mtx; 616 u8 *data; 617 u16 data_len; 618 619 struct mt76_worker status_worker; 620 struct mt76_worker rx_worker; 621 622 struct work_struct stat_work; 623 624 u8 out_ep[__MT_EP_OUT_MAX]; 625 u8 in_ep[__MT_EP_IN_MAX]; 626 bool sg_en; 627 628 struct mt76u_mcu { 629 u8 *data; 630 /* multiple reads */ 631 struct mt76_reg_pair *rp; 632 int rp_len; 633 u32 base; 634 } mcu; 635 }; 636 637 #define MT76S_XMIT_BUF_SZ 0x3fe00 638 #define MT76S_NUM_TX_ENTRIES 256 639 #define MT76S_NUM_RX_ENTRIES 512 640 struct mt76_sdio { 641 struct mt76_worker txrx_worker; 642 struct mt76_worker status_worker; 643 struct mt76_worker net_worker; 644 struct mt76_worker stat_worker; 645 646 u8 *xmit_buf; 647 u32 xmit_buf_sz; 648 649 struct sdio_func *func; 650 void *intr_data; 651 u8 hw_ver; 652 wait_queue_head_t wait; 653 654 int pse_mcu_quota_max; 655 struct { 656 int pse_data_quota; 657 int ple_data_quota; 658 int pse_mcu_quota; 659 int pse_page_size; 660 int deficit; 661 } sched; 662 663 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 664 }; 665 666 struct mt76_mmio { 667 void __iomem *regs; 668 spinlock_t irq_lock; 669 u32 irqmask; 670 671 struct mtk_wed_device wed; 672 struct mtk_wed_device wed_hif2; 673 struct completion wed_reset; 674 struct completion wed_reset_complete; 675 }; 676 677 struct mt76_rx_status { 678 union { 679 struct mt76_wcid *wcid; 680 u16 wcid_idx; 681 }; 682 683 u32 reorder_time; 684 685 u32 ampdu_ref; 686 u32 timestamp; 687 688 u8 iv[6]; 689 690 u8 phy_idx:2; 691 u8 aggr:1; 692 u8 qos_ctl; 693 u16 seqno; 694 695 u16 freq; 696 u32 flag; 697 u8 enc_flags; 698 u8 encoding:3, bw:4; 699 union { 700 struct { 701 u8 he_ru:3; 702 u8 he_gi:2; 703 u8 he_dcm:1; 704 }; 705 struct { 706 u8 ru:4; 707 u8 gi:2; 708 } eht; 709 }; 710 711 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 712 u8 rate_idx; 713 u8 nss:5, band:3; 714 s8 signal; 715 u8 chains; 716 s8 chain_signal[IEEE80211_MAX_CHAINS]; 717 }; 718 719 struct mt76_freq_range_power { 720 const struct cfg80211_sar_freq_ranges *range; 721 s8 power; 722 }; 723 724 struct mt76_testmode_ops { 725 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 726 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 727 enum mt76_testmode_state new_state); 728 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 729 }; 730 731 struct mt76_testmode_data { 732 enum mt76_testmode_state state; 733 734 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 735 struct sk_buff *tx_skb; 736 737 u32 tx_count; 738 u16 tx_mpdu_len; 739 740 u8 tx_rate_mode; 741 u8 tx_rate_idx; 742 u8 tx_rate_nss; 743 u8 tx_rate_sgi; 744 u8 tx_rate_ldpc; 745 u8 tx_rate_stbc; 746 u8 tx_ltf; 747 748 u8 tx_antenna_mask; 749 u8 tx_spe_idx; 750 751 u8 tx_duty_cycle; 752 u32 tx_time; 753 u32 tx_ipg; 754 755 u32 freq_offset; 756 757 u8 tx_power[4]; 758 u8 tx_power_control; 759 760 u8 addr[3][ETH_ALEN]; 761 762 u32 tx_pending; 763 u32 tx_queued; 764 u16 tx_queued_limit; 765 u32 tx_done; 766 struct { 767 u64 packets[__MT_RXQ_MAX]; 768 u64 fcs_error[__MT_RXQ_MAX]; 769 } rx_stats; 770 }; 771 772 struct mt76_vif_link { 773 u8 idx; 774 u8 link_idx; 775 u8 omac_idx; 776 u8 band_idx; 777 u8 wmm_idx; 778 u8 scan_seq_num; 779 u8 cipher; 780 u8 basic_rates_idx; 781 u8 mcast_rates_idx; 782 u8 beacon_rates_idx; 783 bool offchannel; 784 struct ieee80211_chanctx_conf *ctx; 785 struct mt76_wcid *wcid; 786 struct mt76_vif_data *mvif; 787 struct rcu_head rcu_head; 788 }; 789 790 struct mt76_vif_data { 791 struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 792 struct mt76_vif_link __rcu *offchannel_link; 793 794 struct mt76_phy *roc_phy; 795 u16 valid_links; 796 u8 deflink_id; 797 }; 798 799 struct mt76_phy { 800 struct ieee80211_hw *hw; 801 struct mt76_dev *dev; 802 void *priv; 803 804 unsigned long state; 805 unsigned int num_sta; 806 u8 band_idx; 807 808 spinlock_t tx_lock; 809 struct list_head tx_list; 810 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 811 812 struct cfg80211_chan_def chandef; 813 struct cfg80211_chan_def main_chandef; 814 bool offchannel; 815 bool radar_enabled; 816 817 struct delayed_work roc_work; 818 struct ieee80211_vif *roc_vif; 819 struct mt76_vif_link *roc_link; 820 821 struct mt76_chanctx *chanctx; 822 823 struct mt76_channel_state *chan_state; 824 enum mt76_dfs_state dfs_state; 825 ktime_t survey_time; 826 827 u32 aggr_stats[32]; 828 829 struct mt76_hw_cap cap; 830 struct mt76_sband sband_2g; 831 struct mt76_sband sband_5g; 832 struct mt76_sband sband_6g; 833 834 u8 macaddr[ETH_ALEN]; 835 836 int txpower_cur; 837 u8 antenna_mask; 838 u16 chainmask; 839 840 #ifdef CONFIG_NL80211_TESTMODE 841 struct mt76_testmode_data test; 842 #endif 843 844 struct delayed_work mac_work; 845 u8 mac_work_count; 846 847 struct { 848 struct sk_buff *head; 849 struct sk_buff **tail; 850 u16 seqno; 851 } rx_amsdu[__MT_RXQ_MAX]; 852 853 struct mt76_freq_range_power *frp; 854 855 struct { 856 struct led_classdev cdev; 857 char name[32]; 858 bool al; 859 u8 pin; 860 } leds; 861 }; 862 863 struct mt76_dev { 864 struct mt76_phy phy; /* must be first */ 865 struct mt76_phy *phys[__MT_MAX_BAND]; 866 struct mt76_phy *band_phys[NUM_NL80211_BANDS]; 867 868 struct ieee80211_hw *hw; 869 870 spinlock_t wed_lock; 871 spinlock_t lock; 872 spinlock_t cc_lock; 873 874 u32 cur_cc_bss_rx; 875 876 struct mt76_rx_status rx_ampdu_status; 877 u32 rx_ampdu_len; 878 u32 rx_ampdu_ref; 879 880 struct mutex mutex; 881 882 const struct mt76_bus_ops *bus; 883 const struct mt76_driver_ops *drv; 884 const struct mt76_mcu_ops *mcu_ops; 885 struct device *dev; 886 struct device *dma_dev; 887 888 struct mt76_mcu mcu; 889 890 struct net_device *napi_dev; 891 struct net_device *tx_napi_dev; 892 spinlock_t rx_lock; 893 struct napi_struct napi[__MT_RXQ_MAX]; 894 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 895 struct tasklet_struct irq_tasklet; 896 897 struct list_head txwi_cache; 898 struct list_head rxwi_cache; 899 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 900 struct mt76_queue q_rx[__MT_RXQ_MAX]; 901 const struct mt76_queue_ops *queue_ops; 902 int tx_dma_idx[4]; 903 904 struct mt76_worker tx_worker; 905 struct napi_struct tx_napi; 906 907 spinlock_t token_lock; 908 struct idr token; 909 u16 wed_token_count; 910 u16 token_count; 911 u16 token_size; 912 913 spinlock_t rx_token_lock; 914 struct idr rx_token; 915 u16 rx_token_size; 916 917 wait_queue_head_t tx_wait; 918 /* spinclock used to protect wcid pktid linked list */ 919 spinlock_t status_lock; 920 921 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 922 923 u64 vif_mask; 924 925 struct mt76_wcid global_wcid; 926 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 927 struct list_head wcid_list; 928 929 struct list_head sta_poll_list; 930 spinlock_t sta_poll_lock; 931 932 u32 rev; 933 934 struct tasklet_struct pre_tbtt_tasklet; 935 int beacon_int; 936 u8 beacon_mask; 937 938 struct debugfs_blob_wrapper eeprom; 939 struct debugfs_blob_wrapper otp; 940 941 char alpha2[3]; 942 enum nl80211_dfs_regions region; 943 944 u32 debugfs_reg; 945 946 u8 csa_complete; 947 948 u32 rxfilter; 949 950 struct delayed_work scan_work; 951 struct { 952 struct cfg80211_scan_request *req; 953 struct ieee80211_channel *chan; 954 struct ieee80211_vif *vif; 955 struct mt76_vif_link *mlink; 956 struct mt76_phy *phy; 957 int chan_idx; 958 } scan; 959 960 #ifdef CONFIG_NL80211_TESTMODE 961 const struct mt76_testmode_ops *test_ops; 962 struct { 963 const char *name; 964 u32 offset; 965 } test_mtd; 966 #endif 967 struct workqueue_struct *wq; 968 969 union { 970 struct mt76_mmio mmio; 971 struct mt76_usb usb; 972 struct mt76_sdio sdio; 973 }; 974 }; 975 976 /* per-phy stats. */ 977 struct mt76_mib_stats { 978 u32 ack_fail_cnt; 979 u32 fcs_err_cnt; 980 u32 rts_cnt; 981 u32 rts_retries_cnt; 982 u32 ba_miss_cnt; 983 u32 tx_bf_cnt; 984 u32 tx_mu_bf_cnt; 985 u32 tx_mu_mpdu_cnt; 986 u32 tx_mu_acked_mpdu_cnt; 987 u32 tx_su_acked_mpdu_cnt; 988 u32 tx_bf_ibf_ppdu_cnt; 989 u32 tx_bf_ebf_ppdu_cnt; 990 991 u32 tx_bf_rx_fb_all_cnt; 992 u32 tx_bf_rx_fb_eht_cnt; 993 u32 tx_bf_rx_fb_he_cnt; 994 u32 tx_bf_rx_fb_vht_cnt; 995 u32 tx_bf_rx_fb_ht_cnt; 996 997 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 998 u32 tx_bf_rx_fb_nc_cnt; 999 u32 tx_bf_rx_fb_nr_cnt; 1000 u32 tx_bf_fb_cpl_cnt; 1001 u32 tx_bf_fb_trig_cnt; 1002 1003 u32 tx_ampdu_cnt; 1004 u32 tx_stop_q_empty_cnt; 1005 u32 tx_mpdu_attempts_cnt; 1006 u32 tx_mpdu_success_cnt; 1007 u32 tx_pkt_ebf_cnt; 1008 u32 tx_pkt_ibf_cnt; 1009 1010 u32 tx_rwp_fail_cnt; 1011 u32 tx_rwp_need_cnt; 1012 1013 /* rx stats */ 1014 u32 rx_fifo_full_cnt; 1015 u32 channel_idle_cnt; 1016 u32 primary_cca_busy_time; 1017 u32 secondary_cca_busy_time; 1018 u32 primary_energy_detect_time; 1019 u32 cck_mdrdy_time; 1020 u32 ofdm_mdrdy_time; 1021 u32 green_mdrdy_time; 1022 u32 rx_vector_mismatch_cnt; 1023 u32 rx_delimiter_fail_cnt; 1024 u32 rx_mrdy_cnt; 1025 u32 rx_len_mismatch_cnt; 1026 u32 rx_mpdu_cnt; 1027 u32 rx_ampdu_cnt; 1028 u32 rx_ampdu_bytes_cnt; 1029 u32 rx_ampdu_valid_subframe_cnt; 1030 u32 rx_ampdu_valid_subframe_bytes_cnt; 1031 u32 rx_pfdrop_cnt; 1032 u32 rx_vec_queue_overflow_drop_cnt; 1033 u32 rx_ba_cnt; 1034 1035 u32 tx_amsdu[8]; 1036 u32 tx_amsdu_cnt; 1037 1038 /* mcu_muru_stats */ 1039 u32 dl_cck_cnt; 1040 u32 dl_ofdm_cnt; 1041 u32 dl_htmix_cnt; 1042 u32 dl_htgf_cnt; 1043 u32 dl_vht_su_cnt; 1044 u32 dl_vht_2mu_cnt; 1045 u32 dl_vht_3mu_cnt; 1046 u32 dl_vht_4mu_cnt; 1047 u32 dl_he_su_cnt; 1048 u32 dl_he_ext_su_cnt; 1049 u32 dl_he_2ru_cnt; 1050 u32 dl_he_2mu_cnt; 1051 u32 dl_he_3ru_cnt; 1052 u32 dl_he_3mu_cnt; 1053 u32 dl_he_4ru_cnt; 1054 u32 dl_he_4mu_cnt; 1055 u32 dl_he_5to8ru_cnt; 1056 u32 dl_he_9to16ru_cnt; 1057 u32 dl_he_gtr16ru_cnt; 1058 1059 u32 ul_hetrig_su_cnt; 1060 u32 ul_hetrig_2ru_cnt; 1061 u32 ul_hetrig_3ru_cnt; 1062 u32 ul_hetrig_4ru_cnt; 1063 u32 ul_hetrig_5to8ru_cnt; 1064 u32 ul_hetrig_9to16ru_cnt; 1065 u32 ul_hetrig_gtr16ru_cnt; 1066 u32 ul_hetrig_2mu_cnt; 1067 u32 ul_hetrig_3mu_cnt; 1068 u32 ul_hetrig_4mu_cnt; 1069 }; 1070 1071 struct mt76_power_limits { 1072 s8 cck[4]; 1073 s8 ofdm[8]; 1074 s8 mcs[4][10]; 1075 s8 ru[7][12]; 1076 s8 eht[16][16]; 1077 }; 1078 1079 struct mt76_ethtool_worker_info { 1080 u64 *data; 1081 int idx; 1082 int initial_stat_idx; 1083 int worker_stat_count; 1084 int sta_count; 1085 }; 1086 1087 struct mt76_chanctx { 1088 struct mt76_phy *phy; 1089 }; 1090 1091 #define CCK_RATE(_idx, _rate) { \ 1092 .bitrate = _rate, \ 1093 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 1094 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 1095 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 1096 } 1097 1098 #define OFDM_RATE(_idx, _rate) { \ 1099 .bitrate = _rate, \ 1100 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1101 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1102 } 1103 1104 extern struct ieee80211_rate mt76_rates[12]; 1105 1106 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1107 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1108 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1109 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1110 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1111 1112 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1113 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1114 1115 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1116 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1117 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1118 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1119 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1120 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1121 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1122 1123 1124 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1125 1126 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1127 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1128 1129 #define mt76_get_field(_dev, _reg, _field) \ 1130 FIELD_GET(_field, mt76_rr(dev, _reg)) 1131 1132 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1133 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1134 1135 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1136 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1137 1138 #define mt76_hw(dev) (dev)->mphy.hw 1139 1140 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1141 int timeout); 1142 1143 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1144 1145 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1146 int timeout, int kick); 1147 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1148 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1149 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1150 1151 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1152 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1153 bool mt76_pci_aspm_supported(struct pci_dev *pdev); 1154 1155 static inline u16 mt76_chip(struct mt76_dev *dev) 1156 { 1157 return dev->rev >> 16; 1158 } 1159 1160 static inline u16 mt76_rev(struct mt76_dev *dev) 1161 { 1162 return dev->rev & 0xffff; 1163 } 1164 1165 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed); 1166 void mt76_wed_offload_disable(struct mtk_wed_device *wed); 1167 void mt76_wed_reset_complete(struct mtk_wed_device *wed); 1168 void mt76_wed_dma_reset(struct mt76_dev *dev); 1169 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1170 struct net_device *netdev, enum tc_setup_type type, 1171 void *type_data); 1172 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1173 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size); 1174 int mt76_wed_offload_enable(struct mtk_wed_device *wed); 1175 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); 1176 #else 1177 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size) 1178 { 1179 return 0; 1180 } 1181 1182 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed) 1183 { 1184 return 0; 1185 } 1186 1187 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, 1188 bool reset) 1189 { 1190 return 0; 1191 } 1192 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1193 1194 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1195 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1196 1197 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1198 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1199 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1200 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__) 1201 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1202 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1203 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1204 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1205 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1206 1207 #define mt76_for_each_q_rx(dev, i) \ 1208 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1209 if ((dev)->q_rx[i].ndesc) 1210 1211 1212 #define mt76_dereference(p, dev) \ 1213 rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex)) 1214 1215 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1216 const struct ieee80211_ops *ops, 1217 const struct mt76_driver_ops *drv_ops); 1218 int mt76_register_device(struct mt76_dev *dev, bool vht, 1219 struct ieee80211_rate *rates, int n_rates); 1220 void mt76_unregister_device(struct mt76_dev *dev); 1221 void mt76_free_device(struct mt76_dev *dev); 1222 void mt76_unregister_phy(struct mt76_phy *phy); 1223 1224 struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size, 1225 u8 band_idx); 1226 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1227 const struct ieee80211_ops *ops, 1228 u8 band_idx); 1229 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1230 struct ieee80211_rate *rates, int n_rates); 1231 struct mt76_phy *mt76_vif_phy(struct ieee80211_hw *hw, 1232 struct ieee80211_vif *vif); 1233 1234 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1235 const struct file_operations *ops); 1236 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1237 { 1238 return mt76_register_debugfs_fops(&dev->phy, NULL); 1239 } 1240 1241 int mt76_queues_read(struct seq_file *s, void *data); 1242 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1243 s8 *val, int len); 1244 1245 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1246 void mt76_eeprom_override(struct mt76_phy *phy); 1247 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1248 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1249 const char *cell_name, int len); 1250 1251 struct mt76_queue * 1252 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1253 int ring_base, void *wed, u32 flags); 1254 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1255 int n_desc, int ring_base, void *wed, 1256 u32 flags) 1257 { 1258 struct mt76_queue *q; 1259 1260 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags); 1261 if (IS_ERR(q)) 1262 return PTR_ERR(q); 1263 1264 phy->q_tx[qid] = q; 1265 1266 return 0; 1267 } 1268 1269 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1270 int n_desc, int ring_base) 1271 { 1272 struct mt76_queue *q; 1273 1274 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0); 1275 if (IS_ERR(q)) 1276 return PTR_ERR(q); 1277 1278 dev->q_mcu[qid] = q; 1279 1280 return 0; 1281 } 1282 1283 static inline struct mt76_phy * 1284 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1285 { 1286 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1287 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1288 return dev->phys[phy_idx]; 1289 1290 return &dev->phy; 1291 } 1292 1293 static inline struct ieee80211_hw * 1294 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1295 { 1296 return mt76_dev_phy(dev, phy_idx)->hw; 1297 } 1298 1299 static inline u8 * 1300 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1301 { 1302 return (u8 *)t - dev->drv->txwi_size; 1303 } 1304 1305 /* increment with wrap-around */ 1306 static inline int mt76_incr(int val, int size) 1307 { 1308 return (val + 1) & (size - 1); 1309 } 1310 1311 /* decrement with wrap-around */ 1312 static inline int mt76_decr(int val, int size) 1313 { 1314 return (val - 1) & (size - 1); 1315 } 1316 1317 u8 mt76_ac_to_hwq(u8 ac); 1318 1319 static inline struct ieee80211_txq * 1320 mtxq_to_txq(struct mt76_txq *mtxq) 1321 { 1322 void *ptr = mtxq; 1323 1324 return container_of(ptr, struct ieee80211_txq, drv_priv); 1325 } 1326 1327 static inline struct ieee80211_sta * 1328 wcid_to_sta(struct mt76_wcid *wcid) 1329 { 1330 void *ptr = wcid; 1331 1332 if (!wcid || !wcid->sta) 1333 return NULL; 1334 1335 if (wcid->def_wcid) 1336 ptr = wcid->def_wcid; 1337 1338 return container_of(ptr, struct ieee80211_sta, drv_priv); 1339 } 1340 1341 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1342 { 1343 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1344 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1345 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1346 } 1347 1348 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1349 { 1350 struct mt76_rx_status mstat; 1351 u8 *data = skb->data; 1352 1353 /* Alignment concerns */ 1354 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1355 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1356 1357 mstat = *((struct mt76_rx_status *)skb->cb); 1358 1359 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1360 data += sizeof(struct ieee80211_radiotap_he); 1361 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1362 data += sizeof(struct ieee80211_radiotap_he_mu); 1363 1364 return data; 1365 } 1366 1367 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1368 { 1369 int len = ieee80211_get_hdrlen_from_skb(skb); 1370 1371 if (len % 4 == 0) 1372 return; 1373 1374 skb_push(skb, 2); 1375 memmove(skb->data, skb->data + 2, len); 1376 1377 skb->data[len] = 0; 1378 skb->data[len + 1] = 0; 1379 } 1380 1381 static inline bool mt76_is_skb_pktid(u8 pktid) 1382 { 1383 if (pktid & MT_PACKET_ID_HAS_RATE) 1384 return false; 1385 1386 return pktid >= MT_PACKET_ID_FIRST; 1387 } 1388 1389 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1390 { 1391 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1392 u8 idx = nss - 1; 1393 1394 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1395 } 1396 1397 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1398 { 1399 #ifdef CONFIG_NL80211_TESTMODE 1400 return phy->test.state != MT76_TM_STATE_OFF; 1401 #else 1402 return false; 1403 #endif 1404 } 1405 1406 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1407 struct sk_buff *skb, 1408 struct ieee80211_hw **hw) 1409 { 1410 #ifdef CONFIG_NL80211_TESTMODE 1411 int i; 1412 1413 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1414 struct mt76_phy *phy = dev->phys[i]; 1415 1416 if (phy && skb == phy->test.tx_skb) { 1417 *hw = dev->phys[i]->hw; 1418 return true; 1419 } 1420 } 1421 return false; 1422 #else 1423 return false; 1424 #endif 1425 } 1426 1427 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1428 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1429 struct mt76_wcid *wcid, struct sk_buff *skb); 1430 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1431 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1432 bool send_bar); 1433 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1434 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1435 void mt76_txq_schedule_all(struct mt76_phy *phy); 1436 void mt76_tx_worker_run(struct mt76_dev *dev); 1437 void mt76_tx_worker(struct mt76_worker *w); 1438 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1439 struct ieee80211_sta *sta, 1440 u16 tids, int nframes, 1441 enum ieee80211_frame_release_type reason, 1442 bool more_data); 1443 bool mt76_has_tx_pending(struct mt76_phy *phy); 1444 int mt76_update_channel(struct mt76_phy *phy); 1445 void mt76_update_survey(struct mt76_phy *phy); 1446 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1447 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1448 struct survey_info *survey); 1449 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1450 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1451 1452 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1453 u16 ssn, u16 size); 1454 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1455 1456 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1457 struct ieee80211_key_conf *key); 1458 1459 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1460 __acquires(&dev->status_lock); 1461 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1462 __releases(&dev->status_lock); 1463 1464 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1465 struct sk_buff *skb); 1466 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1467 struct mt76_wcid *wcid, int pktid, 1468 struct sk_buff_head *list); 1469 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1470 struct sk_buff_head *list); 1471 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1472 struct list_head *free_list); 1473 static inline void 1474 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1475 { 1476 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1477 } 1478 1479 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1480 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1481 struct ieee80211_sta *sta, 1482 enum ieee80211_sta_state old_state, 1483 enum ieee80211_sta_state new_state); 1484 void __mt76_sta_remove(struct mt76_phy *phy, struct ieee80211_vif *vif, 1485 struct ieee80211_sta *sta); 1486 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1487 struct ieee80211_sta *sta); 1488 1489 int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx); 1490 1491 s8 mt76_get_power_bound(struct mt76_phy *phy, s8 txpower); 1492 1493 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1494 unsigned int link_id, int *dbm); 1495 int mt76_init_sar_power(struct ieee80211_hw *hw, 1496 const struct cfg80211_sar_specs *sar); 1497 int mt76_get_sar_power(struct mt76_phy *phy, 1498 struct ieee80211_channel *chan, 1499 int power); 1500 1501 void mt76_csa_check(struct mt76_dev *dev); 1502 void mt76_csa_finish(struct mt76_dev *dev); 1503 1504 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1505 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1506 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1507 int mt76_get_rate(struct mt76_dev *dev, 1508 struct ieee80211_supported_band *sband, 1509 int idx, bool cck); 1510 int mt76_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1511 struct ieee80211_scan_request *hw_req); 1512 void mt76_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1513 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1514 const u8 *mac); 1515 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1516 struct ieee80211_vif *vif); 1517 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1518 int mt76_add_chanctx(struct ieee80211_hw *hw, 1519 struct ieee80211_chanctx_conf *conf); 1520 void mt76_remove_chanctx(struct ieee80211_hw *hw, 1521 struct ieee80211_chanctx_conf *conf); 1522 void mt76_change_chanctx(struct ieee80211_hw *hw, 1523 struct ieee80211_chanctx_conf *conf, 1524 u32 changed); 1525 int mt76_assign_vif_chanctx(struct ieee80211_hw *hw, 1526 struct ieee80211_vif *vif, 1527 struct ieee80211_bss_conf *link_conf, 1528 struct ieee80211_chanctx_conf *conf); 1529 void mt76_unassign_vif_chanctx(struct ieee80211_hw *hw, 1530 struct ieee80211_vif *vif, 1531 struct ieee80211_bss_conf *link_conf, 1532 struct ieee80211_chanctx_conf *conf); 1533 int mt76_switch_vif_chanctx(struct ieee80211_hw *hw, 1534 struct ieee80211_vif_chanctx_switch *vifs, 1535 int n_vifs, 1536 enum ieee80211_chanctx_switch_mode mode); 1537 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1538 struct ieee80211_channel *chan, int duration, 1539 enum ieee80211_roc_type type); 1540 int mt76_cancel_remain_on_channel(struct ieee80211_hw *hw, 1541 struct ieee80211_vif *vif); 1542 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1543 void *data, int len); 1544 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1545 struct netlink_callback *cb, void *data, int len); 1546 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1547 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1548 1549 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1550 { 1551 #ifdef CONFIG_NL80211_TESTMODE 1552 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1553 1554 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1555 state = MT76_TM_STATE_OFF; 1556 1557 mt76_testmode_set_state(phy, state); 1558 #endif 1559 } 1560 1561 1562 /* internal */ 1563 static inline struct ieee80211_hw * 1564 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1565 { 1566 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1567 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1568 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1569 1570 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1571 1572 return hw; 1573 } 1574 1575 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1576 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1577 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1578 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1579 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1580 struct napi_struct *napi); 1581 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1582 struct napi_struct *napi); 1583 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1584 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1585 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1586 struct mt76_queue_entry *e); 1587 int __mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1588 bool offchannel); 1589 int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1590 bool offchannel); 1591 void mt76_scan_work(struct work_struct *work); 1592 void mt76_abort_scan(struct mt76_dev *dev); 1593 void mt76_roc_complete_work(struct work_struct *work); 1594 void mt76_abort_roc(struct mt76_phy *phy); 1595 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy, 1596 struct ieee80211_vif *vif); 1597 void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif, 1598 struct mt76_vif_link *mlink); 1599 1600 /* usb */ 1601 static inline bool mt76u_urb_error(struct urb *urb) 1602 { 1603 return urb->status && 1604 urb->status != -ECONNRESET && 1605 urb->status != -ESHUTDOWN && 1606 urb->status != -ENOENT; 1607 } 1608 1609 static inline int 1610 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1611 int timeout, int ep) 1612 { 1613 struct usb_interface *uintf = to_usb_interface(dev->dev); 1614 struct usb_device *udev = interface_to_usbdev(uintf); 1615 struct mt76_usb *usb = &dev->usb; 1616 unsigned int pipe; 1617 1618 if (actual_len) 1619 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1620 else 1621 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1622 1623 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1624 } 1625 1626 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1627 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1628 struct mt76_sta_stats *stats, bool eht); 1629 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1630 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1631 u16 val, u16 offset, void *buf, size_t len); 1632 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1633 u8 req_type, u16 val, u16 offset, 1634 void *buf, size_t len); 1635 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1636 const u16 offset, const u32 val); 1637 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1638 void *data, int len); 1639 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1640 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1641 u32 addr, u32 val); 1642 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1643 struct mt76_bus_ops *ops); 1644 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1645 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1646 int mt76u_alloc_queues(struct mt76_dev *dev); 1647 void mt76u_stop_tx(struct mt76_dev *dev); 1648 void mt76u_stop_rx(struct mt76_dev *dev); 1649 int mt76u_resume_rx(struct mt76_dev *dev); 1650 void mt76u_queues_deinit(struct mt76_dev *dev); 1651 1652 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1653 const struct mt76_bus_ops *bus_ops); 1654 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1655 int mt76s_alloc_tx(struct mt76_dev *dev); 1656 void mt76s_deinit(struct mt76_dev *dev); 1657 void mt76s_sdio_irq(struct sdio_func *func); 1658 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1659 bool mt76s_txqs_empty(struct mt76_dev *dev); 1660 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1661 int hw_ver); 1662 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1663 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1664 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1665 u32 mt76s_read_pcr(struct mt76_dev *dev); 1666 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1667 const void *data, int len); 1668 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1669 void *data, int len); 1670 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1671 const struct mt76_reg_pair *data, 1672 int len); 1673 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1674 struct mt76_reg_pair *data, int len); 1675 1676 struct sk_buff * 1677 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1678 int len, int data_len, gfp_t gfp); 1679 static inline struct sk_buff * 1680 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1681 int data_len) 1682 { 1683 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1684 } 1685 1686 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1687 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1688 unsigned long expires); 1689 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1690 int len, bool wait_resp, struct sk_buff **ret); 1691 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1692 int cmd, bool wait_resp, struct sk_buff **ret); 1693 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1694 int len, int max_len); 1695 static inline int 1696 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1697 int len) 1698 { 1699 int max_len = 4096 - dev->mcu_ops->headroom; 1700 1701 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1702 } 1703 1704 static inline int 1705 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1706 bool wait_resp) 1707 { 1708 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1709 } 1710 1711 static inline int 1712 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1713 bool wait_resp) 1714 { 1715 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1716 } 1717 1718 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1719 1720 struct device_node * 1721 mt76_find_power_limits_node(struct mt76_dev *dev); 1722 struct device_node * 1723 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan); 1724 1725 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1726 struct ieee80211_channel *chan, 1727 struct mt76_power_limits *dest, 1728 s8 target_power); 1729 1730 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q) 1731 { 1732 int i; 1733 1734 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 1735 if (q == &dev->q_rx[i]) 1736 return true; 1737 } 1738 1739 return false; 1740 } 1741 1742 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q) 1743 { 1744 return (q->flags & MT_QFLAG_WED) && 1745 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE; 1746 } 1747 1748 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q) 1749 { 1750 return q->flags & MT_QFLAG_WED_RRO; 1751 } 1752 1753 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q) 1754 { 1755 return mt76_queue_is_wed_rro(q) && 1756 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1757 } 1758 1759 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1760 { 1761 return mt76_queue_is_wed_rro(q) && 1762 (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA || 1763 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG); 1764 } 1765 1766 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1767 { 1768 if (!(q->flags & MT_QFLAG_WED)) 1769 return false; 1770 1771 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX || 1772 mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q); 1773 1774 } 1775 1776 struct mt76_txwi_cache * 1777 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1778 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1779 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1780 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1781 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1782 struct mt76_txwi_cache *r, dma_addr_t phys); 1783 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1784 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1785 { 1786 struct page *page = virt_to_head_page(buf); 1787 1788 page_pool_put_full_page(page->pp, page, allow_direct); 1789 } 1790 1791 static inline void * 1792 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1793 { 1794 struct page *page; 1795 1796 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1797 if (!page) 1798 return NULL; 1799 1800 return page_address(page) + *offset; 1801 } 1802 1803 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1804 { 1805 spin_lock_bh(&dev->token_lock); 1806 __mt76_set_tx_blocked(dev, blocked); 1807 spin_unlock_bh(&dev->token_lock); 1808 } 1809 1810 static inline int 1811 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1812 { 1813 int token; 1814 1815 spin_lock_bh(&dev->token_lock); 1816 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1817 spin_unlock_bh(&dev->token_lock); 1818 1819 return token; 1820 } 1821 1822 static inline struct mt76_txwi_cache * 1823 mt76_token_put(struct mt76_dev *dev, int token) 1824 { 1825 struct mt76_txwi_cache *txwi; 1826 1827 spin_lock_bh(&dev->token_lock); 1828 txwi = idr_remove(&dev->token, token); 1829 spin_unlock_bh(&dev->token_lock); 1830 1831 return txwi; 1832 } 1833 1834 void mt76_wcid_init(struct mt76_wcid *wcid, u8 band_idx); 1835 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid); 1836 void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid); 1837 1838 static inline void 1839 mt76_vif_init(struct ieee80211_vif *vif, struct mt76_vif_data *mvif) 1840 { 1841 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1842 1843 mlink->mvif = mvif; 1844 rcu_assign_pointer(mvif->link[0], mlink); 1845 } 1846 1847 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif); 1848 1849 static inline struct mt76_vif_link * 1850 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id) 1851 { 1852 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1853 struct mt76_vif_data *mvif = mlink->mvif; 1854 1855 return mt76_dereference(mvif->link[link_id], dev); 1856 } 1857 1858 static inline struct mt76_vif_link * 1859 mt76_vif_conf_link(struct mt76_dev *dev, struct ieee80211_vif *vif, 1860 struct ieee80211_bss_conf *link_conf) 1861 { 1862 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1863 struct mt76_vif_data *mvif = mlink->mvif; 1864 1865 if (link_conf == &vif->bss_conf) 1866 return mlink; 1867 1868 return mt76_dereference(mvif->link[link_conf->link_id], dev); 1869 } 1870 1871 static inline struct mt76_phy * 1872 mt76_vif_link_phy(struct mt76_vif_link *mlink) 1873 { 1874 struct mt76_chanctx *ctx; 1875 1876 if (!mlink->ctx) 1877 return NULL; 1878 1879 ctx = (struct mt76_chanctx *)mlink->ctx->drv_priv; 1880 1881 return ctx->phy; 1882 } 1883 1884 #endif 1885