1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #include <linux/dma-mapping.h> 7 #include "mt76.h" 8 #include "dma.h" 9 10 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) 11 12 #define Q_READ(_q, _field) ({ \ 13 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 14 u32 _val; \ 15 if ((_q)->flags & MT_QFLAG_WED) \ 16 _val = mtk_wed_device_reg_read((_q)->wed, \ 17 ((_q)->wed_regs + \ 18 _offset)); \ 19 else \ 20 _val = readl(&(_q)->regs->_field); \ 21 _val; \ 22 }) 23 24 #define Q_WRITE(_q, _field, _val) do { \ 25 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 26 if ((_q)->flags & MT_QFLAG_WED) \ 27 mtk_wed_device_reg_write((_q)->wed, \ 28 ((_q)->wed_regs + _offset), \ 29 _val); \ 30 else \ 31 writel(_val, &(_q)->regs->_field); \ 32 } while (0) 33 34 #else 35 36 #define Q_READ(_q, _field) readl(&(_q)->regs->_field) 37 #define Q_WRITE(_q, _field, _val) writel(_val, &(_q)->regs->_field) 38 39 #endif 40 41 static struct mt76_txwi_cache * 42 mt76_alloc_txwi(struct mt76_dev *dev) 43 { 44 struct mt76_txwi_cache *t; 45 dma_addr_t addr; 46 u8 *txwi; 47 int size; 48 49 size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t)); 50 txwi = kzalloc(size, GFP_ATOMIC); 51 if (!txwi) 52 return NULL; 53 54 addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size, 55 DMA_TO_DEVICE); 56 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) { 57 kfree(txwi); 58 return NULL; 59 } 60 61 t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size); 62 t->dma_addr = addr; 63 64 return t; 65 } 66 67 static struct mt76_txwi_cache * 68 mt76_alloc_rxwi(struct mt76_dev *dev) 69 { 70 struct mt76_txwi_cache *t; 71 72 t = kzalloc(L1_CACHE_ALIGN(sizeof(*t)), GFP_ATOMIC); 73 if (!t) 74 return NULL; 75 76 t->ptr = NULL; 77 return t; 78 } 79 80 static struct mt76_txwi_cache * 81 __mt76_get_txwi(struct mt76_dev *dev) 82 { 83 struct mt76_txwi_cache *t = NULL; 84 85 spin_lock(&dev->lock); 86 if (!list_empty(&dev->txwi_cache)) { 87 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache, 88 list); 89 list_del(&t->list); 90 } 91 spin_unlock(&dev->lock); 92 93 return t; 94 } 95 96 static struct mt76_txwi_cache * 97 __mt76_get_rxwi(struct mt76_dev *dev) 98 { 99 struct mt76_txwi_cache *t = NULL; 100 101 spin_lock_bh(&dev->wed_lock); 102 if (!list_empty(&dev->rxwi_cache)) { 103 t = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache, 104 list); 105 list_del(&t->list); 106 } 107 spin_unlock_bh(&dev->wed_lock); 108 109 return t; 110 } 111 112 static struct mt76_txwi_cache * 113 mt76_get_txwi(struct mt76_dev *dev) 114 { 115 struct mt76_txwi_cache *t = __mt76_get_txwi(dev); 116 117 if (t) 118 return t; 119 120 return mt76_alloc_txwi(dev); 121 } 122 123 struct mt76_txwi_cache * 124 mt76_get_rxwi(struct mt76_dev *dev) 125 { 126 struct mt76_txwi_cache *t = __mt76_get_rxwi(dev); 127 128 if (t) 129 return t; 130 131 return mt76_alloc_rxwi(dev); 132 } 133 EXPORT_SYMBOL_GPL(mt76_get_rxwi); 134 135 void 136 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 137 { 138 if (!t) 139 return; 140 141 spin_lock(&dev->lock); 142 list_add(&t->list, &dev->txwi_cache); 143 spin_unlock(&dev->lock); 144 } 145 EXPORT_SYMBOL_GPL(mt76_put_txwi); 146 147 void 148 mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 149 { 150 if (!t) 151 return; 152 153 spin_lock_bh(&dev->wed_lock); 154 list_add(&t->list, &dev->rxwi_cache); 155 spin_unlock_bh(&dev->wed_lock); 156 } 157 EXPORT_SYMBOL_GPL(mt76_put_rxwi); 158 159 static void 160 mt76_free_pending_txwi(struct mt76_dev *dev) 161 { 162 struct mt76_txwi_cache *t; 163 164 local_bh_disable(); 165 while ((t = __mt76_get_txwi(dev)) != NULL) { 166 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 167 DMA_TO_DEVICE); 168 kfree(mt76_get_txwi_ptr(dev, t)); 169 } 170 local_bh_enable(); 171 } 172 173 void 174 mt76_free_pending_rxwi(struct mt76_dev *dev) 175 { 176 struct mt76_txwi_cache *t; 177 178 local_bh_disable(); 179 while ((t = __mt76_get_rxwi(dev)) != NULL) { 180 if (t->ptr) 181 mt76_put_page_pool_buf(t->ptr, false); 182 kfree(t); 183 } 184 local_bh_enable(); 185 } 186 EXPORT_SYMBOL_GPL(mt76_free_pending_rxwi); 187 188 static void 189 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 190 { 191 Q_WRITE(q, desc_base, q->desc_dma); 192 if (q->flags & MT_QFLAG_WED_RRO_EN) 193 Q_WRITE(q, ring_size, MT_DMA_RRO_EN | q->ndesc); 194 else 195 Q_WRITE(q, ring_size, q->ndesc); 196 q->head = Q_READ(q, dma_idx); 197 q->tail = q->head; 198 } 199 200 void __mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 201 bool reset_idx) 202 { 203 if (!q || !q->ndesc) 204 return; 205 206 if (!mt76_queue_is_wed_rro_ind(q)) { 207 int i; 208 209 /* clear descriptors */ 210 for (i = 0; i < q->ndesc; i++) 211 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 212 } 213 214 if (reset_idx) { 215 Q_WRITE(q, cpu_idx, 0); 216 Q_WRITE(q, dma_idx, 0); 217 } 218 mt76_dma_sync_idx(dev, q); 219 } 220 221 void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q) 222 { 223 __mt76_dma_queue_reset(dev, q, true); 224 } 225 226 static int 227 mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q, 228 struct mt76_queue_buf *buf, void *data) 229 { 230 struct mt76_queue_entry *entry = &q->entry[q->head]; 231 struct mt76_txwi_cache *txwi = NULL; 232 struct mt76_desc *desc; 233 int idx = q->head; 234 u32 buf1 = 0, ctrl; 235 int rx_token; 236 237 if (mt76_queue_is_wed_rro_ind(q)) { 238 struct mt76_wed_rro_desc *rro_desc; 239 240 rro_desc = (struct mt76_wed_rro_desc *)q->desc; 241 data = &rro_desc[q->head]; 242 goto done; 243 } 244 245 desc = &q->desc[q->head]; 246 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 247 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 248 buf1 = FIELD_PREP(MT_DMA_CTL_SDP0_H, buf->addr >> 32); 249 #endif 250 251 if (mt76_queue_is_wed_rx(q)) { 252 txwi = mt76_get_rxwi(dev); 253 if (!txwi) 254 return -ENOMEM; 255 256 rx_token = mt76_rx_token_consume(dev, data, txwi, buf->addr); 257 if (rx_token < 0) { 258 mt76_put_rxwi(dev, txwi); 259 return -ENOMEM; 260 } 261 262 buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token); 263 ctrl |= MT_DMA_CTL_TO_HOST; 264 } 265 266 WRITE_ONCE(desc->buf0, cpu_to_le32(buf->addr)); 267 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 268 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 269 WRITE_ONCE(desc->info, 0); 270 271 done: 272 entry->dma_addr[0] = buf->addr; 273 entry->dma_len[0] = buf->len; 274 entry->txwi = txwi; 275 entry->buf = data; 276 entry->wcid = 0xffff; 277 entry->skip_buf1 = true; 278 q->head = (q->head + 1) % q->ndesc; 279 q->queued++; 280 281 return idx; 282 } 283 284 static int 285 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, 286 struct mt76_queue_buf *buf, int nbufs, u32 info, 287 struct sk_buff *skb, void *txwi) 288 { 289 struct mt76_queue_entry *entry; 290 struct mt76_desc *desc; 291 int i, idx = -1; 292 u32 ctrl, next; 293 294 if (txwi) { 295 q->entry[q->head].txwi = DMA_DUMMY_DATA; 296 q->entry[q->head].skip_buf0 = true; 297 } 298 299 for (i = 0; i < nbufs; i += 2, buf += 2) { 300 u32 buf0 = buf[0].addr, buf1 = 0; 301 302 idx = q->head; 303 next = (q->head + 1) % q->ndesc; 304 305 desc = &q->desc[idx]; 306 entry = &q->entry[idx]; 307 308 if (buf[0].skip_unmap) 309 entry->skip_buf0 = true; 310 entry->skip_buf1 = i == nbufs - 1; 311 312 entry->dma_addr[0] = buf[0].addr; 313 entry->dma_len[0] = buf[0].len; 314 315 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 316 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 317 info |= FIELD_PREP(MT_DMA_CTL_SDP0_H, buf[0].addr >> 32); 318 #endif 319 if (i < nbufs - 1) { 320 entry->dma_addr[1] = buf[1].addr; 321 entry->dma_len[1] = buf[1].len; 322 buf1 = buf[1].addr; 323 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); 324 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 325 info |= FIELD_PREP(MT_DMA_CTL_SDP1_H, 326 buf[1].addr >> 32); 327 #endif 328 if (buf[1].skip_unmap) 329 entry->skip_buf1 = true; 330 } 331 332 if (i == nbufs - 1) 333 ctrl |= MT_DMA_CTL_LAST_SEC0; 334 else if (i == nbufs - 2) 335 ctrl |= MT_DMA_CTL_LAST_SEC1; 336 337 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); 338 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 339 WRITE_ONCE(desc->info, cpu_to_le32(info)); 340 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 341 342 q->head = next; 343 q->queued++; 344 } 345 346 q->entry[idx].txwi = txwi; 347 q->entry[idx].skb = skb; 348 q->entry[idx].wcid = 0xffff; 349 350 return idx; 351 } 352 353 static void 354 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, 355 struct mt76_queue_entry *prev_e) 356 { 357 struct mt76_queue_entry *e = &q->entry[idx]; 358 359 if (!e->skip_buf0) 360 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0], 361 DMA_TO_DEVICE); 362 363 if (!e->skip_buf1) 364 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1], 365 DMA_TO_DEVICE); 366 367 if (e->txwi == DMA_DUMMY_DATA) 368 e->txwi = NULL; 369 370 *prev_e = *e; 371 memset(e, 0, sizeof(*e)); 372 } 373 374 static void 375 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 376 { 377 wmb(); 378 Q_WRITE(q, cpu_idx, q->head); 379 } 380 381 static void 382 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush) 383 { 384 struct mt76_queue_entry entry; 385 int last; 386 387 if (!q || !q->ndesc) 388 return; 389 390 spin_lock_bh(&q->cleanup_lock); 391 if (flush) 392 last = -1; 393 else 394 last = Q_READ(q, dma_idx); 395 396 while (q->queued > 0 && q->tail != last) { 397 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); 398 mt76_queue_tx_complete(dev, q, &entry); 399 400 if (entry.txwi) { 401 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE)) 402 mt76_put_txwi(dev, entry.txwi); 403 } 404 405 if (!flush && q->tail == last) 406 last = Q_READ(q, dma_idx); 407 } 408 spin_unlock_bh(&q->cleanup_lock); 409 410 if (flush) { 411 spin_lock_bh(&q->lock); 412 mt76_dma_sync_idx(dev, q); 413 mt76_dma_kick_queue(dev, q); 414 spin_unlock_bh(&q->lock); 415 } 416 417 if (!q->queued) 418 wake_up(&dev->tx_wait); 419 } 420 421 static void * 422 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 423 int *len, u32 *info, bool *more, bool *drop) 424 { 425 struct mt76_queue_entry *e = &q->entry[idx]; 426 struct mt76_desc *desc = &q->desc[idx]; 427 u32 ctrl, desc_info, buf1; 428 void *buf = e->buf; 429 430 if (mt76_queue_is_wed_rro_ind(q)) 431 goto done; 432 433 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 434 if (len) { 435 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl); 436 *more = !(ctrl & MT_DMA_CTL_LAST_SEC0); 437 } 438 439 desc_info = le32_to_cpu(desc->info); 440 if (info) 441 *info = desc_info; 442 443 buf1 = le32_to_cpu(desc->buf1); 444 mt76_dma_should_drop_buf(drop, ctrl, buf1, desc_info); 445 446 if (mt76_queue_is_wed_rx(q)) { 447 u32 token = FIELD_GET(MT_DMA_CTL_TOKEN, buf1); 448 struct mt76_txwi_cache *t = mt76_rx_token_release(dev, token); 449 450 if (!t) 451 return NULL; 452 453 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, 454 SKB_WITH_OVERHEAD(q->buf_size), 455 page_pool_get_dma_dir(q->page_pool)); 456 457 buf = t->ptr; 458 t->dma_addr = 0; 459 t->ptr = NULL; 460 461 mt76_put_rxwi(dev, t); 462 if (drop) 463 *drop |= !!(buf1 & MT_DMA_CTL_WO_DROP); 464 } else { 465 dma_sync_single_for_cpu(dev->dma_dev, e->dma_addr[0], 466 SKB_WITH_OVERHEAD(q->buf_size), 467 page_pool_get_dma_dir(q->page_pool)); 468 } 469 470 done: 471 e->buf = NULL; 472 return buf; 473 } 474 475 static void * 476 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 477 int *len, u32 *info, bool *more, bool *drop) 478 { 479 int idx = q->tail; 480 481 *more = false; 482 if (!q->queued) 483 return NULL; 484 485 if (mt76_queue_is_wed_rro_data(q)) 486 return NULL; 487 488 if (!mt76_queue_is_wed_rro_ind(q)) { 489 if (flush) 490 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE); 491 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 492 return NULL; 493 } 494 495 q->tail = (q->tail + 1) % q->ndesc; 496 q->queued--; 497 498 return mt76_dma_get_buf(dev, q, idx, len, info, more, drop); 499 } 500 501 static int 502 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q, 503 struct sk_buff *skb, u32 tx_info) 504 { 505 struct mt76_queue_buf buf = {}; 506 dma_addr_t addr; 507 508 if (test_bit(MT76_MCU_RESET, &dev->phy.state)) 509 goto error; 510 511 if (q->queued + 1 >= q->ndesc - 1) 512 goto error; 513 514 addr = dma_map_single(dev->dma_dev, skb->data, skb->len, 515 DMA_TO_DEVICE); 516 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 517 goto error; 518 519 buf.addr = addr; 520 buf.len = skb->len; 521 522 spin_lock_bh(&q->lock); 523 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 524 mt76_dma_kick_queue(dev, q); 525 spin_unlock_bh(&q->lock); 526 527 return 0; 528 529 error: 530 dev_kfree_skb(skb); 531 return -ENOMEM; 532 } 533 534 static int 535 mt76_dma_tx_queue_skb(struct mt76_phy *phy, struct mt76_queue *q, 536 enum mt76_txq_id qid, struct sk_buff *skb, 537 struct mt76_wcid *wcid, struct ieee80211_sta *sta) 538 { 539 struct ieee80211_tx_status status = { 540 .sta = sta, 541 }; 542 struct mt76_tx_info tx_info = { 543 .skb = skb, 544 }; 545 struct mt76_dev *dev = phy->dev; 546 struct ieee80211_hw *hw; 547 int len, n = 0, ret = -ENOMEM; 548 struct mt76_txwi_cache *t; 549 struct sk_buff *iter; 550 dma_addr_t addr; 551 u8 *txwi; 552 553 if (test_bit(MT76_RESET, &phy->state)) 554 goto free_skb; 555 556 t = mt76_get_txwi(dev); 557 if (!t) 558 goto free_skb; 559 560 txwi = mt76_get_txwi_ptr(dev, t); 561 562 skb->prev = skb->next = NULL; 563 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS) 564 mt76_insert_hdr_pad(skb); 565 566 len = skb_headlen(skb); 567 addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE); 568 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 569 goto free; 570 571 tx_info.buf[n].addr = t->dma_addr; 572 tx_info.buf[n++].len = dev->drv->txwi_size; 573 tx_info.buf[n].addr = addr; 574 tx_info.buf[n++].len = len; 575 576 skb_walk_frags(skb, iter) { 577 if (n == ARRAY_SIZE(tx_info.buf)) 578 goto unmap; 579 580 addr = dma_map_single(dev->dma_dev, iter->data, iter->len, 581 DMA_TO_DEVICE); 582 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 583 goto unmap; 584 585 tx_info.buf[n].addr = addr; 586 tx_info.buf[n++].len = iter->len; 587 } 588 tx_info.nbuf = n; 589 590 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) { 591 ret = -ENOMEM; 592 goto unmap; 593 } 594 595 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 596 DMA_TO_DEVICE); 597 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info); 598 dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 599 DMA_TO_DEVICE); 600 if (ret < 0) 601 goto unmap; 602 603 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, 604 tx_info.info, tx_info.skb, t); 605 606 unmap: 607 for (n--; n > 0; n--) 608 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr, 609 tx_info.buf[n].len, DMA_TO_DEVICE); 610 611 free: 612 #ifdef CONFIG_NL80211_TESTMODE 613 /* fix tx_done accounting on queue overflow */ 614 if (mt76_is_testmode_skb(dev, skb, &hw)) { 615 struct mt76_phy *phy = hw->priv; 616 617 if (tx_info.skb == phy->test.tx_skb) 618 phy->test.tx_done--; 619 } 620 #endif 621 622 mt76_put_txwi(dev, t); 623 624 free_skb: 625 status.skb = tx_info.skb; 626 hw = mt76_tx_status_get_hw(dev, tx_info.skb); 627 spin_lock_bh(&dev->rx_lock); 628 ieee80211_tx_status_ext(hw, &status); 629 spin_unlock_bh(&dev->rx_lock); 630 631 return ret; 632 } 633 634 static int 635 mt76_dma_rx_fill_buf(struct mt76_dev *dev, struct mt76_queue *q, 636 bool allow_direct) 637 { 638 int len = SKB_WITH_OVERHEAD(q->buf_size); 639 int frames = 0; 640 641 if (!q->ndesc) 642 return 0; 643 644 while (q->queued < q->ndesc - 1) { 645 struct mt76_queue_buf qbuf = {}; 646 enum dma_data_direction dir; 647 dma_addr_t addr; 648 int offset; 649 void *buf = NULL; 650 651 if (mt76_queue_is_wed_rro_ind(q)) 652 goto done; 653 654 buf = mt76_get_page_pool_buf(q, &offset, q->buf_size); 655 if (!buf) 656 break; 657 658 addr = page_pool_get_dma_addr(virt_to_head_page(buf)) + offset; 659 dir = page_pool_get_dma_dir(q->page_pool); 660 dma_sync_single_for_device(dev->dma_dev, addr, len, dir); 661 662 qbuf.addr = addr + q->buf_offset; 663 done: 664 qbuf.len = len - q->buf_offset; 665 qbuf.skip_unmap = false; 666 if (mt76_dma_add_rx_buf(dev, q, &qbuf, buf) < 0) { 667 mt76_put_page_pool_buf(buf, allow_direct); 668 break; 669 } 670 frames++; 671 } 672 673 if (frames || mt76_queue_is_wed_rx(q)) 674 mt76_dma_kick_queue(dev, q); 675 676 return frames; 677 } 678 679 int mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q, 680 bool allow_direct) 681 { 682 int frames; 683 684 if (!q->ndesc) 685 return 0; 686 687 spin_lock_bh(&q->lock); 688 frames = mt76_dma_rx_fill_buf(dev, q, allow_direct); 689 spin_unlock_bh(&q->lock); 690 691 return frames; 692 } 693 694 static int 695 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, 696 int idx, int n_desc, int bufsize, 697 u32 ring_base) 698 { 699 int ret, size; 700 701 spin_lock_init(&q->lock); 702 spin_lock_init(&q->cleanup_lock); 703 704 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 705 q->ndesc = n_desc; 706 q->buf_size = bufsize; 707 q->hw_idx = idx; 708 709 size = mt76_queue_is_wed_rro_ind(q) ? sizeof(struct mt76_wed_rro_desc) 710 : sizeof(struct mt76_desc); 711 q->desc = dmam_alloc_coherent(dev->dma_dev, q->ndesc * size, 712 &q->desc_dma, GFP_KERNEL); 713 if (!q->desc) 714 return -ENOMEM; 715 716 if (mt76_queue_is_wed_rro_ind(q)) { 717 struct mt76_wed_rro_desc *rro_desc; 718 int i; 719 720 rro_desc = (struct mt76_wed_rro_desc *)q->desc; 721 for (i = 0; i < q->ndesc; i++) { 722 struct mt76_wed_rro_ind *cmd; 723 724 cmd = (struct mt76_wed_rro_ind *)&rro_desc[i]; 725 cmd->magic_cnt = MT_DMA_WED_IND_CMD_CNT - 1; 726 } 727 } 728 729 size = q->ndesc * sizeof(*q->entry); 730 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 731 if (!q->entry) 732 return -ENOMEM; 733 734 ret = mt76_create_page_pool(dev, q); 735 if (ret) 736 return ret; 737 738 ret = mt76_wed_dma_setup(dev, q, false); 739 if (ret) 740 return ret; 741 742 if (mtk_wed_device_active(&dev->mmio.wed)) { 743 if ((mtk_wed_get_rx_capa(&dev->mmio.wed) && mt76_queue_is_wed_rro(q)) || 744 mt76_queue_is_wed_tx_free(q)) 745 return 0; 746 } 747 748 mt76_dma_queue_reset(dev, q); 749 750 return 0; 751 } 752 753 static void 754 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) 755 { 756 void *buf; 757 bool more; 758 759 if (!q->ndesc) 760 return; 761 762 do { 763 spin_lock_bh(&q->lock); 764 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL); 765 spin_unlock_bh(&q->lock); 766 767 if (!buf) 768 break; 769 770 if (!mt76_queue_is_wed_rro(q)) 771 mt76_put_page_pool_buf(buf, false); 772 } while (1); 773 774 spin_lock_bh(&q->lock); 775 if (q->rx_head) { 776 dev_kfree_skb(q->rx_head); 777 q->rx_head = NULL; 778 } 779 780 spin_unlock_bh(&q->lock); 781 } 782 783 static void 784 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid) 785 { 786 struct mt76_queue *q = &dev->q_rx[qid]; 787 788 if (!q->ndesc) 789 return; 790 791 if (!mt76_queue_is_wed_rro_ind(q)) { 792 int i; 793 794 for (i = 0; i < q->ndesc; i++) 795 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 796 } 797 798 mt76_dma_rx_cleanup(dev, q); 799 800 /* reset WED rx queues */ 801 mt76_wed_dma_setup(dev, q, true); 802 803 if (mt76_queue_is_wed_tx_free(q)) 804 return; 805 806 if (mtk_wed_device_active(&dev->mmio.wed) && 807 mt76_queue_is_wed_rro(q)) 808 return; 809 810 mt76_dma_sync_idx(dev, q); 811 mt76_dma_rx_fill_buf(dev, q, false); 812 } 813 814 static void 815 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, 816 int len, bool more, u32 info, bool allow_direct) 817 { 818 struct sk_buff *skb = q->rx_head; 819 struct skb_shared_info *shinfo = skb_shinfo(skb); 820 int nr_frags = shinfo->nr_frags; 821 822 if (nr_frags < ARRAY_SIZE(shinfo->frags)) { 823 struct page *page = virt_to_head_page(data); 824 int offset = data - page_address(page) + q->buf_offset; 825 826 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size); 827 } else { 828 mt76_put_page_pool_buf(data, allow_direct); 829 } 830 831 if (more) 832 return; 833 834 q->rx_head = NULL; 835 if (nr_frags < ARRAY_SIZE(shinfo->frags)) 836 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 837 else 838 dev_kfree_skb(skb); 839 } 840 841 static int 842 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) 843 { 844 int len, data_len, done = 0, dma_idx; 845 struct sk_buff *skb; 846 unsigned char *data; 847 bool check_ddone = false; 848 bool allow_direct = !mt76_queue_is_wed_rx(q); 849 bool more; 850 851 if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 852 mt76_queue_is_wed_tx_free(q)) { 853 dma_idx = Q_READ(q, dma_idx); 854 check_ddone = true; 855 } 856 857 while (done < budget) { 858 bool drop = false; 859 u32 info; 860 861 if (check_ddone) { 862 if (q->tail == dma_idx) 863 dma_idx = Q_READ(q, dma_idx); 864 865 if (q->tail == dma_idx) 866 break; 867 } 868 869 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, 870 &drop); 871 if (!data) 872 break; 873 874 if (drop) 875 goto free_frag; 876 877 if (q->rx_head) 878 data_len = q->buf_size; 879 else 880 data_len = SKB_WITH_OVERHEAD(q->buf_size); 881 882 if (data_len < len + q->buf_offset) { 883 dev_kfree_skb(q->rx_head); 884 q->rx_head = NULL; 885 goto free_frag; 886 } 887 888 if (q->rx_head) { 889 mt76_add_fragment(dev, q, data, len, more, info, 890 allow_direct); 891 continue; 892 } 893 894 if (!more && dev->drv->rx_check && 895 !(dev->drv->rx_check(dev, data, len))) 896 goto free_frag; 897 898 skb = napi_build_skb(data, q->buf_size); 899 if (!skb) 900 goto free_frag; 901 902 skb_reserve(skb, q->buf_offset); 903 skb_mark_for_recycle(skb); 904 905 *(u32 *)skb->cb = info; 906 907 __skb_put(skb, len); 908 done++; 909 910 if (more) { 911 q->rx_head = skb; 912 continue; 913 } 914 915 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 916 continue; 917 918 free_frag: 919 mt76_put_page_pool_buf(data, allow_direct); 920 } 921 922 mt76_dma_rx_fill(dev, q, true); 923 return done; 924 } 925 926 int mt76_dma_rx_poll(struct napi_struct *napi, int budget) 927 { 928 struct mt76_dev *dev; 929 int qid, done = 0, cur; 930 931 dev = mt76_priv(napi->dev); 932 qid = napi - dev->napi; 933 934 rcu_read_lock(); 935 936 do { 937 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); 938 mt76_rx_poll_complete(dev, qid, napi); 939 done += cur; 940 } while (cur && done < budget); 941 942 rcu_read_unlock(); 943 944 if (done < budget && napi_complete(napi)) 945 dev->drv->rx_poll_complete(dev, qid); 946 947 return done; 948 } 949 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll); 950 951 static int 952 mt76_dma_init(struct mt76_dev *dev, 953 int (*poll)(struct napi_struct *napi, int budget)) 954 { 955 struct mt76_dev **priv; 956 int i; 957 958 dev->napi_dev = alloc_netdev_dummy(sizeof(struct mt76_dev *)); 959 if (!dev->napi_dev) 960 return -ENOMEM; 961 962 /* napi_dev private data points to mt76_dev parent, so, mt76_dev 963 * can be retrieved given napi_dev 964 */ 965 priv = netdev_priv(dev->napi_dev); 966 *priv = dev; 967 968 dev->tx_napi_dev = alloc_netdev_dummy(sizeof(struct mt76_dev *)); 969 if (!dev->tx_napi_dev) { 970 free_netdev(dev->napi_dev); 971 return -ENOMEM; 972 } 973 priv = netdev_priv(dev->tx_napi_dev); 974 *priv = dev; 975 976 snprintf(dev->napi_dev->name, sizeof(dev->napi_dev->name), "%s", 977 wiphy_name(dev->hw->wiphy)); 978 dev->napi_dev->threaded = 1; 979 init_completion(&dev->mmio.wed_reset); 980 init_completion(&dev->mmio.wed_reset_complete); 981 982 mt76_for_each_q_rx(dev, i) { 983 netif_napi_add(dev->napi_dev, &dev->napi[i], poll); 984 mt76_dma_rx_fill_buf(dev, &dev->q_rx[i], false); 985 napi_enable(&dev->napi[i]); 986 } 987 988 return 0; 989 } 990 991 static const struct mt76_queue_ops mt76_dma_ops = { 992 .init = mt76_dma_init, 993 .alloc = mt76_dma_alloc_queue, 994 .reset_q = mt76_dma_queue_reset, 995 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 996 .tx_queue_skb = mt76_dma_tx_queue_skb, 997 .tx_cleanup = mt76_dma_tx_cleanup, 998 .rx_cleanup = mt76_dma_rx_cleanup, 999 .rx_reset = mt76_dma_rx_reset, 1000 .kick = mt76_dma_kick_queue, 1001 }; 1002 1003 void mt76_dma_attach(struct mt76_dev *dev) 1004 { 1005 dev->queue_ops = &mt76_dma_ops; 1006 } 1007 EXPORT_SYMBOL_GPL(mt76_dma_attach); 1008 1009 void mt76_dma_cleanup(struct mt76_dev *dev) 1010 { 1011 int i; 1012 1013 mt76_worker_disable(&dev->tx_worker); 1014 netif_napi_del(&dev->tx_napi); 1015 1016 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1017 struct mt76_phy *phy = dev->phys[i]; 1018 int j; 1019 1020 if (!phy) 1021 continue; 1022 1023 for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++) 1024 mt76_dma_tx_cleanup(dev, phy->q_tx[j], true); 1025 } 1026 1027 for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++) 1028 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true); 1029 1030 mt76_for_each_q_rx(dev, i) { 1031 struct mt76_queue *q = &dev->q_rx[i]; 1032 1033 if (mtk_wed_device_active(&dev->mmio.wed) && 1034 mt76_queue_is_wed_rro(q)) 1035 continue; 1036 1037 netif_napi_del(&dev->napi[i]); 1038 mt76_dma_rx_cleanup(dev, q); 1039 1040 page_pool_destroy(q->page_pool); 1041 } 1042 1043 if (mtk_wed_device_active(&dev->mmio.wed)) 1044 mtk_wed_device_detach(&dev->mmio.wed); 1045 1046 if (mtk_wed_device_active(&dev->mmio.wed_hif2)) 1047 mtk_wed_device_detach(&dev->mmio.wed_hif2); 1048 1049 mt76_free_pending_txwi(dev); 1050 mt76_free_pending_rxwi(dev); 1051 free_netdev(dev->napi_dev); 1052 free_netdev(dev->tx_napi_dev); 1053 } 1054 EXPORT_SYMBOL_GPL(mt76_dma_cleanup); 1055