1 /* 2 * Marvell Wireless LAN device driver: SDIO specific definitions 3 * 4 * Copyright (C) 2011-2014, Marvell International Ltd. 5 * 6 * This software file (the "File") is distributed by Marvell International 7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991 8 * (the "License"). You may use, redistribute and/or modify this File in 9 * accordance with the terms and conditions of the License, a copy of which 10 * is available by writing to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 13 * 14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 17 * this warranty disclaimer. 18 */ 19 20 #ifndef _MWIFIEX_SDIO_H 21 #define _MWIFIEX_SDIO_H 22 23 24 #include <linux/completion.h> 25 #include <linux/mmc/sdio.h> 26 #include <linux/mmc/sdio_ids.h> 27 #include <linux/mmc/sdio_func.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 31 #include "main.h" 32 33 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin" 34 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin" 35 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin" 36 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin" 37 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin" 38 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin" 39 #define SD8977_DEFAULT_FW_NAME "mrvl/sd8977_uapsta.bin" 40 #define SD8997_DEFAULT_FW_NAME "mrvl/sd8997_uapsta.bin" 41 42 #define BLOCK_MODE 1 43 #define BYTE_MODE 0 44 45 #define REG_PORT 0 46 47 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff 48 49 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000 50 51 #define MWIFIEX_MAX_FUNC2_REG_NUM 13 52 #define MWIFIEX_SDIO_SCRATCH_SIZE 10 53 54 #define SDIO_MPA_ADDR_BASE 0x1000 55 #define CTRL_PORT 0 56 #define CTRL_PORT_MASK 0x0001 57 58 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6) 59 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7) 60 #define HOST_TERM_CMD53 (0x1U << 2) 61 #define REG_PORT 0 62 #define MEM_PORT 0x10000 63 64 #define CMD53_NEW_MODE (0x1U << 0) 65 #define CMD_PORT_RD_LEN_EN (0x1U << 2) 66 #define CMD_PORT_AUTO_EN (0x1U << 0) 67 #define CMD_PORT_SLCT 0x8000 68 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 69 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 70 71 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384) 72 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768) 73 /* we leave one block of 256 bytes for DMA alignment*/ 74 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280) 75 76 /* Misc. Config Register : Auto Re-enable interrupts */ 77 #define AUTO_RE_ENABLE_INT BIT(4) 78 79 /* Host Control Registers : Configuration */ 80 #define CONFIGURATION_REG 0x00 81 /* Host Control Registers : Host power up */ 82 #define HOST_POWER_UP (0x1U << 1) 83 84 /* Host Control Registers : Upload host interrupt mask */ 85 #define UP_LD_HOST_INT_MASK (0x1U) 86 /* Host Control Registers : Download host interrupt mask */ 87 #define DN_LD_HOST_INT_MASK (0x2U) 88 89 /* Host Control Registers : Upload host interrupt status */ 90 #define UP_LD_HOST_INT_STATUS (0x1U) 91 /* Host Control Registers : Download host interrupt status */ 92 #define DN_LD_HOST_INT_STATUS (0x2U) 93 94 /* Host Control Registers : Host interrupt status */ 95 #define CARD_INT_STATUS_REG 0x28 96 97 /* Card Control Registers : Card I/O ready */ 98 #define CARD_IO_READY (0x1U << 3) 99 /* Card Control Registers : Download card ready */ 100 #define DN_LD_CARD_RDY (0x1U << 0) 101 102 /* Max retry number of CMD53 write */ 103 #define MAX_WRITE_IOMEM_RETRY 2 104 105 /* SDIO Tx aggregation in progress ? */ 106 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0) 107 108 /* SDIO Tx aggregation buffer room for next packet ? */ 109 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \ 110 <= a->mpa_tx.buf_size) 111 112 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ 113 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \ 114 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \ 115 payload, pkt_len); \ 116 a->mpa_tx.buf_len += pkt_len; \ 117 if (!a->mpa_tx.pkt_cnt) \ 118 a->mpa_tx.start_port = port; \ 119 if (a->mpa_tx.start_port <= port) \ 120 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \ 121 else \ 122 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \ 123 (a->max_ports - \ 124 a->mp_end_port))); \ 125 a->mpa_tx.pkt_cnt++; \ 126 } while (0) 127 128 /* SDIO Tx aggregation limit ? */ 129 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \ 130 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit) 131 132 /* Reset SDIO Tx aggregation buffer parameters */ 133 #define MP_TX_AGGR_BUF_RESET(a) do { \ 134 a->mpa_tx.pkt_cnt = 0; \ 135 a->mpa_tx.buf_len = 0; \ 136 a->mpa_tx.ports = 0; \ 137 a->mpa_tx.start_port = 0; \ 138 } while (0) 139 140 /* SDIO Rx aggregation limit ? */ 141 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \ 142 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit) 143 144 /* SDIO Rx aggregation in progress ? */ 145 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0) 146 147 /* SDIO Rx aggregation buffer room for next packet ? */ 148 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ 149 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size) 150 151 /* Reset SDIO Rx aggregation buffer parameters */ 152 #define MP_RX_AGGR_BUF_RESET(a) do { \ 153 a->mpa_rx.pkt_cnt = 0; \ 154 a->mpa_rx.buf_len = 0; \ 155 a->mpa_rx.ports = 0; \ 156 a->mpa_rx.start_port = 0; \ 157 } while (0) 158 159 /* data structure for SDIO MPA TX */ 160 struct mwifiex_sdio_mpa_tx { 161 /* multiport tx aggregation buffer pointer */ 162 u8 *buf; 163 u32 buf_len; 164 u32 pkt_cnt; 165 u32 ports; 166 u16 start_port; 167 u8 enabled; 168 u32 buf_size; 169 u32 pkt_aggr_limit; 170 }; 171 172 struct mwifiex_sdio_mpa_rx { 173 u8 *buf; 174 u32 buf_len; 175 u32 pkt_cnt; 176 u32 ports; 177 u16 start_port; 178 179 struct sk_buff **skb_arr; 180 u32 *len_arr; 181 182 u8 enabled; 183 u32 buf_size; 184 u32 pkt_aggr_limit; 185 }; 186 187 int mwifiex_bus_register(void); 188 void mwifiex_bus_unregister(void); 189 190 struct mwifiex_sdio_card_reg { 191 u8 start_rd_port; 192 u8 start_wr_port; 193 u8 base_0_reg; 194 u8 base_1_reg; 195 u8 poll_reg; 196 u8 host_int_enable; 197 u8 host_int_rsr_reg; 198 u8 host_int_status_reg; 199 u8 host_int_mask_reg; 200 u8 status_reg_0; 201 u8 status_reg_1; 202 u8 sdio_int_mask; 203 u32 data_port_mask; 204 u8 io_port_0_reg; 205 u8 io_port_1_reg; 206 u8 io_port_2_reg; 207 u8 max_mp_regs; 208 u8 rd_bitmap_l; 209 u8 rd_bitmap_u; 210 u8 rd_bitmap_1l; 211 u8 rd_bitmap_1u; 212 u8 wr_bitmap_l; 213 u8 wr_bitmap_u; 214 u8 wr_bitmap_1l; 215 u8 wr_bitmap_1u; 216 u8 rd_len_p0_l; 217 u8 rd_len_p0_u; 218 u8 card_misc_cfg_reg; 219 u8 card_cfg_2_1_reg; 220 u8 cmd_rd_len_0; 221 u8 cmd_rd_len_1; 222 u8 cmd_rd_len_2; 223 u8 cmd_rd_len_3; 224 u8 cmd_cfg_0; 225 u8 cmd_cfg_1; 226 u8 cmd_cfg_2; 227 u8 cmd_cfg_3; 228 u8 fw_dump_host_ready; 229 u8 fw_dump_ctrl; 230 u8 fw_dump_start; 231 u8 fw_dump_end; 232 u8 func1_dump_reg_start; 233 u8 func1_dump_reg_end; 234 u8 func1_scratch_reg; 235 u8 func1_spec_reg_num; 236 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM]; 237 }; 238 239 struct sdio_mmc_card { 240 struct sdio_func *func; 241 struct mwifiex_adapter *adapter; 242 243 struct completion fw_done; 244 const char *firmware; 245 const struct mwifiex_sdio_card_reg *reg; 246 u8 max_ports; 247 u8 mp_agg_pkt_limit; 248 u16 tx_buf_size; 249 u32 mp_tx_agg_buf_size; 250 u32 mp_rx_agg_buf_size; 251 252 u32 mp_rd_bitmap; 253 u32 mp_wr_bitmap; 254 255 u16 mp_end_port; 256 u32 mp_data_port_mask; 257 258 u8 curr_rd_port; 259 u8 curr_wr_port; 260 261 u8 *mp_regs; 262 bool supports_sdio_new_mode; 263 bool has_control_mask; 264 bool can_dump_fw; 265 bool fw_dump_enh; 266 bool can_auto_tdls; 267 bool can_ext_scan; 268 269 struct mwifiex_sdio_mpa_tx mpa_tx; 270 struct mwifiex_sdio_mpa_rx mpa_rx; 271 272 struct work_struct work; 273 unsigned long work_flags; 274 }; 275 276 struct mwifiex_sdio_device { 277 const char *firmware; 278 const struct mwifiex_sdio_card_reg *reg; 279 u8 max_ports; 280 u8 mp_agg_pkt_limit; 281 u16 tx_buf_size; 282 u32 mp_tx_agg_buf_size; 283 u32 mp_rx_agg_buf_size; 284 bool supports_sdio_new_mode; 285 bool has_control_mask; 286 bool can_dump_fw; 287 bool fw_dump_enh; 288 bool can_auto_tdls; 289 bool can_ext_scan; 290 }; 291 292 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = { 293 .start_rd_port = 1, 294 .start_wr_port = 1, 295 .base_0_reg = 0x0040, 296 .base_1_reg = 0x0041, 297 .poll_reg = 0x30, 298 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK, 299 .host_int_rsr_reg = 0x1, 300 .host_int_mask_reg = 0x02, 301 .host_int_status_reg = 0x03, 302 .status_reg_0 = 0x60, 303 .status_reg_1 = 0x61, 304 .sdio_int_mask = 0x3f, 305 .data_port_mask = 0x0000fffe, 306 .io_port_0_reg = 0x78, 307 .io_port_1_reg = 0x79, 308 .io_port_2_reg = 0x7A, 309 .max_mp_regs = 64, 310 .rd_bitmap_l = 0x04, 311 .rd_bitmap_u = 0x05, 312 .wr_bitmap_l = 0x06, 313 .wr_bitmap_u = 0x07, 314 .rd_len_p0_l = 0x08, 315 .rd_len_p0_u = 0x09, 316 .card_misc_cfg_reg = 0x6c, 317 .func1_dump_reg_start = 0x0, 318 .func1_dump_reg_end = 0x9, 319 .func1_scratch_reg = 0x60, 320 .func1_spec_reg_num = 5, 321 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c}, 322 }; 323 324 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = { 325 .start_rd_port = 0, 326 .start_wr_port = 0, 327 .base_0_reg = 0x60, 328 .base_1_reg = 0x61, 329 .poll_reg = 0x50, 330 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 331 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 332 .host_int_rsr_reg = 0x1, 333 .host_int_status_reg = 0x03, 334 .host_int_mask_reg = 0x02, 335 .status_reg_0 = 0xc0, 336 .status_reg_1 = 0xc1, 337 .sdio_int_mask = 0xff, 338 .data_port_mask = 0xffffffff, 339 .io_port_0_reg = 0xD8, 340 .io_port_1_reg = 0xD9, 341 .io_port_2_reg = 0xDA, 342 .max_mp_regs = 184, 343 .rd_bitmap_l = 0x04, 344 .rd_bitmap_u = 0x05, 345 .rd_bitmap_1l = 0x06, 346 .rd_bitmap_1u = 0x07, 347 .wr_bitmap_l = 0x08, 348 .wr_bitmap_u = 0x09, 349 .wr_bitmap_1l = 0x0a, 350 .wr_bitmap_1u = 0x0b, 351 .rd_len_p0_l = 0x0c, 352 .rd_len_p0_u = 0x0d, 353 .card_misc_cfg_reg = 0xcc, 354 .card_cfg_2_1_reg = 0xcd, 355 .cmd_rd_len_0 = 0xb4, 356 .cmd_rd_len_1 = 0xb5, 357 .cmd_rd_len_2 = 0xb6, 358 .cmd_rd_len_3 = 0xb7, 359 .cmd_cfg_0 = 0xb8, 360 .cmd_cfg_1 = 0xb9, 361 .cmd_cfg_2 = 0xba, 362 .cmd_cfg_3 = 0xbb, 363 .fw_dump_host_ready = 0xee, 364 .fw_dump_ctrl = 0xe2, 365 .fw_dump_start = 0xe3, 366 .fw_dump_end = 0xea, 367 .func1_dump_reg_start = 0x0, 368 .func1_dump_reg_end = 0xb, 369 .func1_scratch_reg = 0xc0, 370 .func1_spec_reg_num = 8, 371 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58, 372 0x59, 0x5c, 0x5d}, 373 }; 374 375 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8977 = { 376 .start_rd_port = 0, 377 .start_wr_port = 0, 378 .base_0_reg = 0xF8, 379 .base_1_reg = 0xF9, 380 .poll_reg = 0x5C, 381 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 382 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 383 .host_int_rsr_reg = 0x4, 384 .host_int_status_reg = 0x0C, 385 .host_int_mask_reg = 0x08, 386 .status_reg_0 = 0xE8, 387 .status_reg_1 = 0xE9, 388 .sdio_int_mask = 0xff, 389 .data_port_mask = 0xffffffff, 390 .io_port_0_reg = 0xE4, 391 .io_port_1_reg = 0xE5, 392 .io_port_2_reg = 0xE6, 393 .max_mp_regs = 196, 394 .rd_bitmap_l = 0x10, 395 .rd_bitmap_u = 0x11, 396 .rd_bitmap_1l = 0x12, 397 .rd_bitmap_1u = 0x13, 398 .wr_bitmap_l = 0x14, 399 .wr_bitmap_u = 0x15, 400 .wr_bitmap_1l = 0x16, 401 .wr_bitmap_1u = 0x17, 402 .rd_len_p0_l = 0x18, 403 .rd_len_p0_u = 0x19, 404 .card_misc_cfg_reg = 0xd8, 405 .card_cfg_2_1_reg = 0xd9, 406 .cmd_rd_len_0 = 0xc0, 407 .cmd_rd_len_1 = 0xc1, 408 .cmd_rd_len_2 = 0xc2, 409 .cmd_rd_len_3 = 0xc3, 410 .cmd_cfg_0 = 0xc4, 411 .cmd_cfg_1 = 0xc5, 412 .cmd_cfg_2 = 0xc6, 413 .cmd_cfg_3 = 0xc7, 414 .fw_dump_host_ready = 0xcc, 415 .fw_dump_ctrl = 0xf0, 416 .fw_dump_start = 0xf1, 417 .fw_dump_end = 0xf8, 418 .func1_dump_reg_start = 0x10, 419 .func1_dump_reg_end = 0x17, 420 .func1_scratch_reg = 0xe8, 421 .func1_spec_reg_num = 13, 422 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 423 0x60, 0x61, 0x62, 0x64, 424 0x65, 0x66, 0x68, 0x69, 425 0x6a}, 426 }; 427 428 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8997 = { 429 .start_rd_port = 0, 430 .start_wr_port = 0, 431 .base_0_reg = 0xF8, 432 .base_1_reg = 0xF9, 433 .poll_reg = 0x5C, 434 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 435 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 436 .host_int_rsr_reg = 0x4, 437 .host_int_status_reg = 0x0C, 438 .host_int_mask_reg = 0x08, 439 .status_reg_0 = 0xE8, 440 .status_reg_1 = 0xE9, 441 .sdio_int_mask = 0xff, 442 .data_port_mask = 0xffffffff, 443 .io_port_0_reg = 0xE4, 444 .io_port_1_reg = 0xE5, 445 .io_port_2_reg = 0xE6, 446 .max_mp_regs = 196, 447 .rd_bitmap_l = 0x10, 448 .rd_bitmap_u = 0x11, 449 .rd_bitmap_1l = 0x12, 450 .rd_bitmap_1u = 0x13, 451 .wr_bitmap_l = 0x14, 452 .wr_bitmap_u = 0x15, 453 .wr_bitmap_1l = 0x16, 454 .wr_bitmap_1u = 0x17, 455 .rd_len_p0_l = 0x18, 456 .rd_len_p0_u = 0x19, 457 .card_misc_cfg_reg = 0xd8, 458 .card_cfg_2_1_reg = 0xd9, 459 .cmd_rd_len_0 = 0xc0, 460 .cmd_rd_len_1 = 0xc1, 461 .cmd_rd_len_2 = 0xc2, 462 .cmd_rd_len_3 = 0xc3, 463 .cmd_cfg_0 = 0xc4, 464 .cmd_cfg_1 = 0xc5, 465 .cmd_cfg_2 = 0xc6, 466 .cmd_cfg_3 = 0xc7, 467 .fw_dump_host_ready = 0xcc, 468 .fw_dump_ctrl = 0xf0, 469 .fw_dump_start = 0xf1, 470 .fw_dump_end = 0xf8, 471 .func1_dump_reg_start = 0x10, 472 .func1_dump_reg_end = 0x17, 473 .func1_scratch_reg = 0xe8, 474 .func1_spec_reg_num = 13, 475 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 476 0x60, 0x61, 0x62, 0x64, 477 0x65, 0x66, 0x68, 0x69, 478 0x6a}, 479 }; 480 481 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = { 482 .start_rd_port = 0, 483 .start_wr_port = 0, 484 .base_0_reg = 0x6C, 485 .base_1_reg = 0x6D, 486 .poll_reg = 0x5C, 487 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 488 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 489 .host_int_rsr_reg = 0x4, 490 .host_int_status_reg = 0x0C, 491 .host_int_mask_reg = 0x08, 492 .status_reg_0 = 0x90, 493 .status_reg_1 = 0x91, 494 .sdio_int_mask = 0xff, 495 .data_port_mask = 0xffffffff, 496 .io_port_0_reg = 0xE4, 497 .io_port_1_reg = 0xE5, 498 .io_port_2_reg = 0xE6, 499 .max_mp_regs = 196, 500 .rd_bitmap_l = 0x10, 501 .rd_bitmap_u = 0x11, 502 .rd_bitmap_1l = 0x12, 503 .rd_bitmap_1u = 0x13, 504 .wr_bitmap_l = 0x14, 505 .wr_bitmap_u = 0x15, 506 .wr_bitmap_1l = 0x16, 507 .wr_bitmap_1u = 0x17, 508 .rd_len_p0_l = 0x18, 509 .rd_len_p0_u = 0x19, 510 .card_misc_cfg_reg = 0xd8, 511 .card_cfg_2_1_reg = 0xd9, 512 .cmd_rd_len_0 = 0xc0, 513 .cmd_rd_len_1 = 0xc1, 514 .cmd_rd_len_2 = 0xc2, 515 .cmd_rd_len_3 = 0xc3, 516 .cmd_cfg_0 = 0xc4, 517 .cmd_cfg_1 = 0xc5, 518 .cmd_cfg_2 = 0xc6, 519 .cmd_cfg_3 = 0xc7, 520 .func1_dump_reg_start = 0x10, 521 .func1_dump_reg_end = 0x17, 522 .func1_scratch_reg = 0x90, 523 .func1_spec_reg_num = 13, 524 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60, 525 0x61, 0x62, 0x64, 0x65, 0x66, 526 0x68, 0x69, 0x6a}, 527 }; 528 529 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = { 530 .firmware = SD8786_DEFAULT_FW_NAME, 531 .reg = &mwifiex_reg_sd87xx, 532 .max_ports = 16, 533 .mp_agg_pkt_limit = 8, 534 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 535 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 536 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 537 .supports_sdio_new_mode = false, 538 .has_control_mask = true, 539 .can_dump_fw = false, 540 .can_auto_tdls = false, 541 .can_ext_scan = false, 542 }; 543 544 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = { 545 .firmware = SD8787_DEFAULT_FW_NAME, 546 .reg = &mwifiex_reg_sd87xx, 547 .max_ports = 16, 548 .mp_agg_pkt_limit = 8, 549 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 550 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 551 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 552 .supports_sdio_new_mode = false, 553 .has_control_mask = true, 554 .can_dump_fw = false, 555 .can_auto_tdls = false, 556 .can_ext_scan = true, 557 }; 558 559 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = { 560 .firmware = SD8797_DEFAULT_FW_NAME, 561 .reg = &mwifiex_reg_sd87xx, 562 .max_ports = 16, 563 .mp_agg_pkt_limit = 8, 564 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 565 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 566 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 567 .supports_sdio_new_mode = false, 568 .has_control_mask = true, 569 .can_dump_fw = false, 570 .can_auto_tdls = false, 571 .can_ext_scan = true, 572 }; 573 574 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = { 575 .firmware = SD8897_DEFAULT_FW_NAME, 576 .reg = &mwifiex_reg_sd8897, 577 .max_ports = 32, 578 .mp_agg_pkt_limit = 16, 579 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 580 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 581 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 582 .supports_sdio_new_mode = true, 583 .has_control_mask = false, 584 .can_dump_fw = true, 585 .can_auto_tdls = false, 586 .can_ext_scan = true, 587 }; 588 589 static const struct mwifiex_sdio_device mwifiex_sdio_sd8977 = { 590 .firmware = SD8977_DEFAULT_FW_NAME, 591 .reg = &mwifiex_reg_sd8977, 592 .max_ports = 32, 593 .mp_agg_pkt_limit = 16, 594 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 595 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 596 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 597 .supports_sdio_new_mode = true, 598 .has_control_mask = false, 599 .can_dump_fw = true, 600 .fw_dump_enh = true, 601 .can_auto_tdls = false, 602 .can_ext_scan = true, 603 }; 604 605 static const struct mwifiex_sdio_device mwifiex_sdio_sd8997 = { 606 .firmware = SD8997_DEFAULT_FW_NAME, 607 .reg = &mwifiex_reg_sd8997, 608 .max_ports = 32, 609 .mp_agg_pkt_limit = 16, 610 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 611 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 612 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 613 .supports_sdio_new_mode = true, 614 .has_control_mask = false, 615 .can_dump_fw = true, 616 .fw_dump_enh = true, 617 .can_auto_tdls = false, 618 .can_ext_scan = true, 619 }; 620 621 static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = { 622 .firmware = SD8887_DEFAULT_FW_NAME, 623 .reg = &mwifiex_reg_sd8887, 624 .max_ports = 32, 625 .mp_agg_pkt_limit = 16, 626 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 627 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 628 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 629 .supports_sdio_new_mode = true, 630 .has_control_mask = false, 631 .can_dump_fw = false, 632 .can_auto_tdls = true, 633 .can_ext_scan = true, 634 }; 635 636 static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = { 637 .firmware = SD8801_DEFAULT_FW_NAME, 638 .reg = &mwifiex_reg_sd87xx, 639 .max_ports = 16, 640 .mp_agg_pkt_limit = 8, 641 .supports_sdio_new_mode = false, 642 .has_control_mask = true, 643 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 644 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 645 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 646 .can_dump_fw = false, 647 .can_auto_tdls = false, 648 .can_ext_scan = true, 649 }; 650 651 /* 652 * .cmdrsp_complete handler 653 */ 654 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter, 655 struct sk_buff *skb) 656 { 657 dev_kfree_skb_any(skb); 658 return 0; 659 } 660 661 /* 662 * .event_complete handler 663 */ 664 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter, 665 struct sk_buff *skb) 666 { 667 dev_kfree_skb_any(skb); 668 return 0; 669 } 670 671 static inline bool 672 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card) 673 { 674 u8 tmp; 675 676 if (card->curr_rd_port < card->mpa_rx.start_port) { 677 if (card->supports_sdio_new_mode) 678 tmp = card->mp_end_port >> 1; 679 else 680 tmp = card->mp_agg_pkt_limit; 681 682 if (((card->max_ports - card->mpa_rx.start_port) + 683 card->curr_rd_port) >= tmp) 684 return true; 685 } 686 687 if (!card->supports_sdio_new_mode) 688 return false; 689 690 if ((card->curr_rd_port - card->mpa_rx.start_port) >= 691 (card->mp_end_port >> 1)) 692 return true; 693 694 return false; 695 } 696 697 static inline bool 698 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card) 699 { 700 u16 tmp; 701 702 if (card->curr_wr_port < card->mpa_tx.start_port) { 703 if (card->supports_sdio_new_mode) 704 tmp = card->mp_end_port >> 1; 705 else 706 tmp = card->mp_agg_pkt_limit; 707 708 if (((card->max_ports - card->mpa_tx.start_port) + 709 card->curr_wr_port) >= tmp) 710 return true; 711 } 712 713 if (!card->supports_sdio_new_mode) 714 return false; 715 716 if ((card->curr_wr_port - card->mpa_tx.start_port) >= 717 (card->mp_end_port >> 1)) 718 return true; 719 720 return false; 721 } 722 723 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */ 724 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card, 725 u16 rx_len, u8 port) 726 { 727 card->mpa_rx.buf_len += rx_len; 728 729 if (!card->mpa_rx.pkt_cnt) 730 card->mpa_rx.start_port = port; 731 732 if (card->supports_sdio_new_mode) { 733 card->mpa_rx.ports |= (1 << port); 734 } else { 735 if (card->mpa_rx.start_port <= port) 736 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt); 737 else 738 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1); 739 } 740 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL; 741 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len; 742 card->mpa_rx.pkt_cnt++; 743 } 744 #endif /* _MWIFIEX_SDIO_H */ 745