1 /* @file mwifiex_pcie.h 2 * 3 * @brief This file contains definitions for PCI-E interface. 4 * driver. 5 * 6 * Copyright 2011-2020 NXP 7 * 8 * This software file (the "File") is distributed by NXP 9 * under the terms of the GNU General Public License Version 2, June 1991 10 * (the "License"). You may use, redistribute and/or modify this File in 11 * accordance with the terms and conditions of the License, a copy of which 12 * is available by writing to the Free Software Foundation, Inc., 13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 15 * 16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 19 * this warranty disclaimer. 20 */ 21 22 #ifndef _MWIFIEX_PCIE_H 23 #define _MWIFIEX_PCIE_H 24 25 #include <linux/completion.h> 26 #include <linux/pci.h> 27 #include <linux/interrupt.h> 28 29 #include "decl.h" 30 #include "main.h" 31 32 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" 33 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" 34 #define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin" 35 #define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin" 36 #define PCIEUART8997_FW_NAME_V4 "mrvl/pcieuart8997_combo_v4.bin" 37 #define PCIEUSB8997_FW_NAME_V4 "mrvl/pcieusb8997_combo_v4.bin" 38 39 #define PCIE_VENDOR_ID_MARVELL (0x11ab) 40 #define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b) 41 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) 42 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) 43 #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42) 44 45 #define PCIE8897_A0 0x1100 46 #define PCIE8897_B0 0x1200 47 #define PCIE8997_A0 0x10 48 #define PCIE8997_A1 0x11 49 #define CHIP_VER_PCIEUART 0x3 50 #define CHIP_MAGIC_VALUE 0x24 51 52 /* Constants for Buffer Descriptor (BD) rings */ 53 #define MWIFIEX_MAX_TXRX_BD 0x20 54 #define MWIFIEX_TXBD_MASK 0x3F 55 #define MWIFIEX_RXBD_MASK 0x3F 56 57 #define MWIFIEX_MAX_EVT_BD 0x08 58 #define MWIFIEX_EVTBD_MASK 0x0f 59 60 /* PCIE INTERNAL REGISTERS */ 61 #define PCIE_SCRATCH_0_REG 0xC10 62 #define PCIE_SCRATCH_1_REG 0xC14 63 #define PCIE_CPU_INT_EVENT 0xC18 64 #define PCIE_CPU_INT_STATUS 0xC1C 65 #define PCIE_HOST_INT_STATUS 0xC30 66 #define PCIE_HOST_INT_MASK 0xC34 67 #define PCIE_HOST_INT_STATUS_MASK 0xC3C 68 #define PCIE_SCRATCH_2_REG 0xC40 69 #define PCIE_SCRATCH_3_REG 0xC44 70 #define PCIE_SCRATCH_4_REG 0xCD0 71 #define PCIE_SCRATCH_5_REG 0xCD4 72 #define PCIE_SCRATCH_6_REG 0xCD8 73 #define PCIE_SCRATCH_7_REG 0xCDC 74 #define PCIE_SCRATCH_8_REG 0xCE0 75 #define PCIE_SCRATCH_9_REG 0xCE4 76 #define PCIE_SCRATCH_10_REG 0xCE8 77 #define PCIE_SCRATCH_11_REG 0xCEC 78 #define PCIE_SCRATCH_12_REG 0xCF0 79 #define PCIE_SCRATCH_13_REG 0xCF4 80 #define PCIE_SCRATCH_14_REG 0xCF8 81 #define PCIE_SCRATCH_15_REG 0xCFC 82 #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C 83 #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C 84 85 #define CPU_INTR_DNLD_RDY BIT(0) 86 #define CPU_INTR_DOOR_BELL BIT(1) 87 #define CPU_INTR_SLEEP_CFM_DONE BIT(2) 88 #define CPU_INTR_RESET BIT(3) 89 #define CPU_INTR_EVENT_DONE BIT(5) 90 91 #define HOST_INTR_DNLD_DONE BIT(0) 92 #define HOST_INTR_UPLD_RDY BIT(1) 93 #define HOST_INTR_CMD_DONE BIT(2) 94 #define HOST_INTR_EVENT_RDY BIT(3) 95 #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ 96 HOST_INTR_UPLD_RDY | \ 97 HOST_INTR_CMD_DONE | \ 98 HOST_INTR_EVENT_RDY) 99 100 #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) 101 #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) 102 #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) 103 #define MWIFIEX_BD_FLAG_SOP BIT(0) 104 #define MWIFIEX_BD_FLAG_EOP BIT(1) 105 #define MWIFIEX_BD_FLAG_XS_SOP BIT(2) 106 #define MWIFIEX_BD_FLAG_XS_EOP BIT(3) 107 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) 108 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) 109 #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) 110 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) 111 112 /* Max retry number of command write */ 113 #define MAX_WRITE_IOMEM_RETRY 2 114 /* Define PCIE block size for firmware download */ 115 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 116 /* FW awake cookie after FW ready */ 117 #define FW_AWAKE_COOKIE (0xAA55AA55) 118 #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF 119 #define MWIFIEX_SLEEP_COOKIE_SIZE 4 120 #define MWIFIEX_MAX_DELAY_COUNT 100 121 122 #define MWIFIEX_PCIE_FLR_HAPPENS 0xFEDCBABA 123 124 struct mwifiex_pcie_card_reg { 125 u16 cmd_addr_lo; 126 u16 cmd_addr_hi; 127 u16 fw_status; 128 u16 cmd_size; 129 u16 cmdrsp_addr_lo; 130 u16 cmdrsp_addr_hi; 131 u16 tx_rdptr; 132 u16 tx_wrptr; 133 u16 rx_rdptr; 134 u16 rx_wrptr; 135 u16 evt_rdptr; 136 u16 evt_wrptr; 137 u16 drv_rdy; 138 u16 tx_start_ptr; 139 u32 tx_mask; 140 u32 tx_wrap_mask; 141 u32 rx_mask; 142 u32 rx_wrap_mask; 143 u32 tx_rollover_ind; 144 u32 rx_rollover_ind; 145 u32 evt_rollover_ind; 146 u8 ring_flag_sop; 147 u8 ring_flag_eop; 148 u8 ring_flag_xs_sop; 149 u8 ring_flag_xs_eop; 150 u32 ring_tx_start_ptr; 151 u8 pfu_enabled; 152 u8 sleep_cookie; 153 u16 fw_dump_ctrl; 154 u16 fw_dump_start; 155 u16 fw_dump_end; 156 u8 fw_dump_host_ready; 157 u8 fw_dump_read_done; 158 u8 msix_support; 159 }; 160 161 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { 162 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 163 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 164 .cmd_size = PCIE_SCRATCH_2_REG, 165 .fw_status = PCIE_SCRATCH_3_REG, 166 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 167 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 168 .tx_rdptr = PCIE_SCRATCH_6_REG, 169 .tx_wrptr = PCIE_SCRATCH_7_REG, 170 .rx_rdptr = PCIE_SCRATCH_8_REG, 171 .rx_wrptr = PCIE_SCRATCH_9_REG, 172 .evt_rdptr = PCIE_SCRATCH_10_REG, 173 .evt_wrptr = PCIE_SCRATCH_11_REG, 174 .drv_rdy = PCIE_SCRATCH_12_REG, 175 .tx_start_ptr = 0, 176 .tx_mask = MWIFIEX_TXBD_MASK, 177 .tx_wrap_mask = 0, 178 .rx_mask = MWIFIEX_RXBD_MASK, 179 .rx_wrap_mask = 0, 180 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 181 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 182 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 183 .ring_flag_sop = 0, 184 .ring_flag_eop = 0, 185 .ring_flag_xs_sop = 0, 186 .ring_flag_xs_eop = 0, 187 .ring_tx_start_ptr = 0, 188 .pfu_enabled = 0, 189 .sleep_cookie = 1, 190 .msix_support = 0, 191 }; 192 193 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { 194 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 195 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 196 .cmd_size = PCIE_SCRATCH_2_REG, 197 .fw_status = PCIE_SCRATCH_3_REG, 198 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 199 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 200 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, 201 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, 202 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, 203 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, 204 .evt_rdptr = PCIE_SCRATCH_10_REG, 205 .evt_wrptr = PCIE_SCRATCH_11_REG, 206 .drv_rdy = PCIE_SCRATCH_12_REG, 207 .tx_start_ptr = 16, 208 .tx_mask = 0x03FF0000, 209 .tx_wrap_mask = 0x07FF0000, 210 .rx_mask = 0x000003FF, 211 .rx_wrap_mask = 0x000007FF, 212 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, 213 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, 214 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 215 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 216 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 217 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 218 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 219 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 220 .pfu_enabled = 1, 221 .sleep_cookie = 0, 222 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 223 .fw_dump_start = PCIE_SCRATCH_14_REG, 224 .fw_dump_end = 0xcff, 225 .fw_dump_host_ready = 0xee, 226 .fw_dump_read_done = 0xfe, 227 .msix_support = 0, 228 }; 229 230 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { 231 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 232 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 233 .cmd_size = PCIE_SCRATCH_2_REG, 234 .fw_status = PCIE_SCRATCH_3_REG, 235 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 236 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 237 .tx_rdptr = 0xC1A4, 238 .tx_wrptr = 0xC174, 239 .rx_rdptr = 0xC174, 240 .rx_wrptr = 0xC1A4, 241 .evt_rdptr = PCIE_SCRATCH_10_REG, 242 .evt_wrptr = PCIE_SCRATCH_11_REG, 243 .drv_rdy = PCIE_SCRATCH_12_REG, 244 .tx_start_ptr = 16, 245 .tx_mask = 0x0FFF0000, 246 .tx_wrap_mask = 0x1FFF0000, 247 .rx_mask = 0x00000FFF, 248 .rx_wrap_mask = 0x00001FFF, 249 .tx_rollover_ind = BIT(28), 250 .rx_rollover_ind = BIT(12), 251 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 252 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 253 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 254 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 255 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 256 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 257 .pfu_enabled = 1, 258 .sleep_cookie = 0, 259 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 260 .fw_dump_start = PCIE_SCRATCH_14_REG, 261 .fw_dump_end = 0xcff, 262 .fw_dump_host_ready = 0xcc, 263 .fw_dump_read_done = 0xdd, 264 .msix_support = 0, 265 }; 266 267 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { 268 {"ITCM", NULL, 0, 0xF0}, 269 {"DTCM", NULL, 0, 0xF1}, 270 {"SQRAM", NULL, 0, 0xF2}, 271 {"IRAM", NULL, 0, 0xF3}, 272 {"APU", NULL, 0, 0xF4}, 273 {"CIU", NULL, 0, 0xF5}, 274 {"ICU", NULL, 0, 0xF6}, 275 {"MAC", NULL, 0, 0xF7}, 276 }; 277 278 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = { 279 {"DUMP", NULL, 0, 0xDD}, 280 }; 281 282 struct mwifiex_pcie_device { 283 const struct mwifiex_pcie_card_reg *reg; 284 u16 blksz_fw_dl; 285 u16 tx_buf_size; 286 bool can_dump_fw; 287 struct memory_type_mapping *mem_type_mapping_tbl; 288 u8 num_mem_types; 289 bool can_ext_scan; 290 }; 291 292 static const struct mwifiex_pcie_device mwifiex_pcie8766 = { 293 .reg = &mwifiex_reg_8766, 294 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 295 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 296 .can_dump_fw = false, 297 .can_ext_scan = true, 298 }; 299 300 static const struct mwifiex_pcie_device mwifiex_pcie8897 = { 301 .reg = &mwifiex_reg_8897, 302 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 303 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 304 .can_dump_fw = true, 305 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, 306 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), 307 .can_ext_scan = true, 308 }; 309 310 static const struct mwifiex_pcie_device mwifiex_pcie8997 = { 311 .reg = &mwifiex_reg_8997, 312 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 313 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 314 .can_dump_fw = true, 315 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997, 316 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997), 317 .can_ext_scan = true, 318 }; 319 320 struct mwifiex_evt_buf_desc { 321 u64 paddr; 322 u16 len; 323 u16 flags; 324 } __packed; 325 326 struct mwifiex_pcie_buf_desc { 327 u64 paddr; 328 u16 len; 329 u16 flags; 330 } __packed; 331 332 struct mwifiex_pfu_buf_desc { 333 u16 flags; 334 u16 offset; 335 u16 frag_len; 336 u16 len; 337 u64 paddr; 338 u32 reserved; 339 } __packed; 340 341 #define MWIFIEX_NUM_MSIX_VECTORS 4 342 343 struct mwifiex_msix_context { 344 struct pci_dev *dev; 345 u16 msg_id; 346 }; 347 348 struct pcie_service_card { 349 struct pci_dev *dev; 350 struct mwifiex_adapter *adapter; 351 struct mwifiex_pcie_device pcie; 352 struct completion fw_done; 353 354 u8 txbd_flush; 355 u32 txbd_wrptr; 356 u32 txbd_rdptr; 357 u32 txbd_ring_size; 358 u8 *txbd_ring_vbase; 359 dma_addr_t txbd_ring_pbase; 360 void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; 361 struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; 362 363 u32 rxbd_wrptr; 364 u32 rxbd_rdptr; 365 u32 rxbd_ring_size; 366 u8 *rxbd_ring_vbase; 367 dma_addr_t rxbd_ring_pbase; 368 void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; 369 struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; 370 371 u32 evtbd_wrptr; 372 u32 evtbd_rdptr; 373 u32 evtbd_ring_size; 374 u8 *evtbd_ring_vbase; 375 dma_addr_t evtbd_ring_pbase; 376 void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; 377 struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; 378 379 struct sk_buff *cmd_buf; 380 struct sk_buff *cmdrsp_buf; 381 u8 *sleep_cookie_vbase; 382 dma_addr_t sleep_cookie_pbase; 383 void __iomem *pci_mmap; 384 void __iomem *pci_mmap1; 385 int msi_enable; 386 int msix_enable; 387 #ifdef CONFIG_PCI 388 struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS]; 389 #endif 390 struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS]; 391 struct mwifiex_msix_context share_irq_ctx; 392 struct work_struct work; 393 unsigned long work_flags; 394 }; 395 396 static inline int 397 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) 398 { 399 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 400 401 switch (card->dev->device) { 402 case PCIE_DEVICE_ID_MARVELL_88W8766P: 403 if (((card->txbd_wrptr & reg->tx_mask) == 404 (rdptr & reg->tx_mask)) && 405 ((card->txbd_wrptr & reg->tx_rollover_ind) != 406 (rdptr & reg->tx_rollover_ind))) 407 return 1; 408 break; 409 case PCIE_DEVICE_ID_MARVELL_88W8897: 410 case PCIE_DEVICE_ID_MARVELL_88W8997: 411 if (((card->txbd_wrptr & reg->tx_mask) == 412 (rdptr & reg->tx_mask)) && 413 ((card->txbd_wrptr & reg->tx_rollover_ind) == 414 (rdptr & reg->tx_rollover_ind))) 415 return 1; 416 break; 417 } 418 419 return 0; 420 } 421 422 static inline int 423 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) 424 { 425 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 426 427 switch (card->dev->device) { 428 case PCIE_DEVICE_ID_MARVELL_88W8766P: 429 if (((card->txbd_wrptr & reg->tx_mask) != 430 (card->txbd_rdptr & reg->tx_mask)) || 431 ((card->txbd_wrptr & reg->tx_rollover_ind) != 432 (card->txbd_rdptr & reg->tx_rollover_ind))) 433 return 1; 434 break; 435 case PCIE_DEVICE_ID_MARVELL_88W8897: 436 case PCIE_DEVICE_ID_MARVELL_88W8997: 437 if (((card->txbd_wrptr & reg->tx_mask) != 438 (card->txbd_rdptr & reg->tx_mask)) || 439 ((card->txbd_wrptr & reg->tx_rollover_ind) == 440 (card->txbd_rdptr & reg->tx_rollover_ind))) 441 return 1; 442 break; 443 } 444 445 return 0; 446 } 447 448 #endif /* _MWIFIEX_PCIE_H */ 449