1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * NXP Wireless LAN device driver: generic data structures and APIs 4 * 5 * Copyright 2011-2020 NXP 6 */ 7 8 #ifndef _MWIFIEX_DECL_H_ 9 #define _MWIFIEX_DECL_H_ 10 11 #undef pr_fmt 12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14 #include <linux/wait.h> 15 #include <linux/timer.h> 16 #include <linux/ieee80211.h> 17 #include <uapi/linux/if_arp.h> 18 #include <net/cfg80211.h> 19 20 #define MWIFIEX_BSS_COEX_COUNT 2 21 #define MWIFIEX_MAX_BSS_NUM (3) 22 23 #define MWIFIEX_DMA_ALIGN_SZ 64 24 #define MWIFIEX_RX_HEADROOM 64 25 #define MAX_TXPD_SZ 32 26 #define INTF_HDR_ALIGN 4 27 28 #define MWIFIEX_MIN_DATA_HEADER_LEN (MWIFIEX_DMA_ALIGN_SZ + INTF_HDR_ALIGN + \ 29 MAX_TXPD_SZ) 30 #define MWIFIEX_MGMT_FRAME_HEADER_SIZE 8 /* sizeof(pkt_type) 31 * + sizeof(tx_control) 32 */ 33 34 #define FRMCTL_LEN 2 35 #define DURATION_LEN 2 36 #define SEQCTL_LEN 2 37 /* special FW 4 address management header */ 38 #define MWIFIEX_MGMT_HEADER_LEN (FRMCTL_LEN + DURATION_LEN + ETH_ALEN + \ 39 ETH_ALEN + ETH_ALEN + SEQCTL_LEN + ETH_ALEN) 40 41 #define AUTH_ALG_LEN 2 42 #define AUTH_TRANSACTION_LEN 2 43 #define AUTH_STATUS_LEN 2 44 #define MWIFIEX_AUTH_BODY_LEN (AUTH_ALG_LEN + AUTH_TRANSACTION_LEN + \ 45 AUTH_STATUS_LEN) 46 47 #define HOST_MLME_AUTH_PENDING BIT(0) 48 #define HOST_MLME_AUTH_DONE BIT(1) 49 50 #define HOST_MLME_MGMT_MASK (BIT(IEEE80211_STYPE_AUTH >> 4) | \ 51 BIT(IEEE80211_STYPE_DEAUTH >> 4) | \ 52 BIT(IEEE80211_STYPE_DISASSOC >> 4)) 53 #define AUTH_TX_DEFAULT_WAIT_TIME 2400 54 55 #define WLAN_AUTH_NONE 0xFFFF 56 57 #define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED 2 58 #define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED 16 59 #define MWIFIEX_MAX_TDLS_PEER_SUPPORTED 8 60 61 #define MWIFIEX_STA_AMPDU_DEF_TXWINSIZE 64 62 #define MWIFIEX_STA_AMPDU_DEF_RXWINSIZE 64 63 #define MWIFIEX_STA_COEX_AMPDU_DEF_RXWINSIZE 16 64 65 #define MWIFIEX_UAP_AMPDU_DEF_TXWINSIZE 32 66 67 #define MWIFIEX_UAP_COEX_AMPDU_DEF_RXWINSIZE 16 68 69 #define MWIFIEX_UAP_AMPDU_DEF_RXWINSIZE 16 70 #define MWIFIEX_11AC_STA_AMPDU_DEF_TXWINSIZE 64 71 #define MWIFIEX_11AC_STA_AMPDU_DEF_RXWINSIZE 64 72 #define MWIFIEX_11AC_UAP_AMPDU_DEF_TXWINSIZE 64 73 #define MWIFIEX_11AC_UAP_AMPDU_DEF_RXWINSIZE 64 74 75 #define MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT 0xffff 76 77 #define MWIFIEX_RATE_BITMAP_MCS0 32 78 79 #define MWIFIEX_RX_DATA_BUF_SIZE (4 * 1024) 80 #define MWIFIEX_RX_CMD_BUF_SIZE (2 * 1024) 81 82 #define MAX_BEACON_PERIOD (4000) 83 #define MIN_BEACON_PERIOD (50) 84 #define MAX_DTIM_PERIOD (100) 85 #define MIN_DTIM_PERIOD (1) 86 87 #define MWIFIEX_RTS_MIN_VALUE (0) 88 #define MWIFIEX_RTS_MAX_VALUE (2347) 89 #define MWIFIEX_FRAG_MIN_VALUE (256) 90 #define MWIFIEX_FRAG_MAX_VALUE (2346) 91 #define MWIFIEX_WMM_VERSION 0x01 92 #define MWIFIEX_WMM_SUBTYPE 0x01 93 94 #define MWIFIEX_RETRY_LIMIT 14 95 #define MWIFIEX_SDIO_BLOCK_SIZE 256 96 97 #define MWIFIEX_BUF_FLAG_REQUEUED_PKT BIT(0) 98 #define MWIFIEX_BUF_FLAG_BRIDGED_PKT BIT(1) 99 #define MWIFIEX_BUF_FLAG_TDLS_PKT BIT(2) 100 #define MWIFIEX_BUF_FLAG_EAPOL_TX_STATUS BIT(3) 101 #define MWIFIEX_BUF_FLAG_ACTION_TX_STATUS BIT(4) 102 #define MWIFIEX_BUF_FLAG_AGGR_PKT BIT(5) 103 104 #define MWIFIEX_BRIDGED_PKTS_THR_HIGH 1024 105 #define MWIFIEX_BRIDGED_PKTS_THR_LOW 128 106 107 #define MWIFIEX_TDLS_DISABLE_LINK 0x00 108 #define MWIFIEX_TDLS_ENABLE_LINK 0x01 109 #define MWIFIEX_TDLS_CREATE_LINK 0x02 110 #define MWIFIEX_TDLS_CONFIG_LINK 0x03 111 112 #define MWIFIEX_TDLS_RSSI_HIGH 50 113 #define MWIFIEX_TDLS_RSSI_LOW 55 114 #define MWIFIEX_TDLS_MAX_FAIL_COUNT 4 115 #define MWIFIEX_AUTO_TDLS_IDLE_TIME 10 116 117 /* 54M rates, index from 0 to 11 */ 118 #define MWIFIEX_RATE_INDEX_MCS0 12 119 /* 12-27=MCS0-15(BW20) */ 120 #define MWIFIEX_BW20_MCS_NUM 15 121 122 /* Rate index for OFDM 0 */ 123 #define MWIFIEX_RATE_INDEX_OFDM0 4 124 125 #define MWIFIEX_MAX_STA_NUM 3 126 #define MWIFIEX_MAX_UAP_NUM 3 127 #define MWIFIEX_MAX_P2P_NUM 3 128 129 #define MWIFIEX_A_BAND_START_FREQ 5000 130 131 /* SDIO Aggr data packet special info */ 132 #define SDIO_MAX_AGGR_BUF_SIZE (256 * 255) 133 #define BLOCK_NUMBER_OFFSET 15 134 #define SDIO_HEADER_OFFSET 28 135 136 #define MWIFIEX_SIZE_4K 0x4000 137 138 enum mwifiex_bss_type { 139 MWIFIEX_BSS_TYPE_STA = 0, 140 MWIFIEX_BSS_TYPE_UAP = 1, 141 MWIFIEX_BSS_TYPE_P2P = 2, 142 MWIFIEX_BSS_TYPE_ANY = 0xff, 143 }; 144 145 enum mwifiex_bss_role { 146 MWIFIEX_BSS_ROLE_STA = 0, 147 MWIFIEX_BSS_ROLE_UAP = 1, 148 MWIFIEX_BSS_ROLE_ANY = 0xff, 149 }; 150 151 enum mwifiex_tdls_status { 152 TDLS_NOT_SETUP = 0, 153 TDLS_SETUP_INPROGRESS, 154 TDLS_SETUP_COMPLETE, 155 TDLS_SETUP_FAILURE, 156 TDLS_LINK_TEARDOWN, 157 TDLS_CHAN_SWITCHING, 158 TDLS_IN_BASE_CHAN, 159 TDLS_IN_OFF_CHAN, 160 }; 161 162 enum mwifiex_tdls_error_code { 163 TDLS_ERR_NO_ERROR = 0, 164 TDLS_ERR_INTERNAL_ERROR, 165 TDLS_ERR_MAX_LINKS_EST, 166 TDLS_ERR_LINK_EXISTS, 167 TDLS_ERR_LINK_NONEXISTENT, 168 TDLS_ERR_PEER_STA_UNREACHABLE = 25, 169 }; 170 171 #define BSS_ROLE_BIT_MASK BIT(0) 172 173 #define GET_BSS_ROLE(priv) ((priv)->bss_role & BSS_ROLE_BIT_MASK) 174 175 enum mwifiex_data_frame_type { 176 MWIFIEX_DATA_FRAME_TYPE_ETH_II = 0, 177 MWIFIEX_DATA_FRAME_TYPE_802_11, 178 }; 179 180 struct mwifiex_fw_image { 181 u8 *helper_buf; 182 u32 helper_len; 183 u8 *fw_buf; 184 u32 fw_len; 185 }; 186 187 struct mwifiex_802_11_ssid { 188 u32 ssid_len; 189 u8 ssid[IEEE80211_MAX_SSID_LEN]; 190 }; 191 192 struct mwifiex_wait_queue { 193 wait_queue_head_t wait; 194 int status; 195 }; 196 197 struct mwifiex_rxinfo { 198 struct sk_buff *parent; 199 u8 bss_num; 200 u8 bss_type; 201 u8 use_count; 202 u8 buf_type; 203 }; 204 205 struct mwifiex_txinfo { 206 u8 flags; 207 u8 bss_num; 208 u8 bss_type; 209 u8 aggr_num; 210 u32 pkt_len; 211 u8 ack_frame_id; 212 u64 cookie; 213 }; 214 215 enum mwifiex_wmm_ac_e { 216 WMM_AC_BK, 217 WMM_AC_BE, 218 WMM_AC_VI, 219 WMM_AC_VO 220 } __packed; 221 222 struct ieee_types_wmm_ac_parameters { 223 u8 aci_aifsn_bitmap; 224 u8 ecw_bitmap; 225 __le16 tx_op_limit; 226 } __packed; 227 228 struct mwifiex_types_wmm_info { 229 u8 oui[4]; 230 u8 subtype; 231 u8 version; 232 u8 qos_info; 233 u8 reserved; 234 struct ieee_types_wmm_ac_parameters ac_params[IEEE80211_NUM_ACS]; 235 } __packed; 236 237 struct mwifiex_arp_eth_header { 238 struct arphdr hdr; 239 u8 ar_sha[ETH_ALEN]; 240 u8 ar_sip[4]; 241 u8 ar_tha[ETH_ALEN]; 242 u8 ar_tip[4]; 243 } __packed; 244 245 struct mwifiex_chan_stats { 246 u8 chan_num; 247 u8 bandcfg; 248 u8 flags; 249 s8 noise; 250 u16 total_bss; 251 u16 cca_scan_dur; 252 u16 cca_busy_dur; 253 } __packed; 254 255 #define MWIFIEX_HIST_MAX_SAMPLES 1048576 256 #define MWIFIEX_MAX_RX_RATES 44 257 #define MWIFIEX_MAX_AC_RX_RATES 74 258 #define MWIFIEX_MAX_SNR 256 259 #define MWIFIEX_MAX_NOISE_FLR 256 260 #define MWIFIEX_MAX_SIG_STRENGTH 256 261 262 struct mwifiex_histogram_data { 263 atomic_t rx_rate[MWIFIEX_MAX_AC_RX_RATES]; 264 atomic_t snr[MWIFIEX_MAX_SNR]; 265 atomic_t noise_flr[MWIFIEX_MAX_NOISE_FLR]; 266 atomic_t sig_str[MWIFIEX_MAX_SIG_STRENGTH]; 267 atomic_t num_samples; 268 }; 269 270 struct mwifiex_iface_comb { 271 u8 sta_intf; 272 u8 uap_intf; 273 u8 p2p_intf; 274 }; 275 276 struct mwifiex_radar_params { 277 struct cfg80211_chan_def *chandef; 278 u32 cac_time_ms; 279 } __packed; 280 281 struct mwifiex_11h_intf_state { 282 bool is_11h_enabled; 283 bool is_11h_active; 284 } __packed; 285 286 #define MWIFIEX_FW_DUMP_IDX 0xff 287 #define MWIFIEX_FW_DUMP_MAX_MEMSIZE 0x160000 288 #define MWIFIEX_DRV_INFO_IDX 20 289 #define FW_DUMP_MAX_NAME_LEN 8 290 #define FW_DUMP_HOST_READY 0xEE 291 #define FW_DUMP_DONE 0xFF 292 #define FW_DUMP_READ_DONE 0xFE 293 294 struct memory_type_mapping { 295 u8 mem_name[FW_DUMP_MAX_NAME_LEN]; 296 u8 *mem_ptr; 297 u32 mem_size; 298 u8 done_flag; 299 }; 300 301 enum rdwr_status { 302 RDWR_STATUS_SUCCESS = 0, 303 RDWR_STATUS_FAILURE = 1, 304 RDWR_STATUS_DONE = 2 305 }; 306 307 enum mwifiex_chan_width { 308 CHAN_BW_20MHZ = 0, 309 CHAN_BW_10MHZ, 310 CHAN_BW_40MHZ, 311 CHAN_BW_80MHZ, 312 CHAN_BW_8080MHZ, 313 CHAN_BW_160MHZ, 314 CHAN_BW_5MHZ, 315 }; 316 317 enum mwifiex_chan_offset { 318 SEC_CHAN_NONE = 0, 319 SEC_CHAN_ABOVE = 1, 320 SEC_CHAN_5MHZ = 2, 321 SEC_CHAN_BELOW = 3 322 }; 323 324 #endif /* !_MWIFIEX_DECL_H_ */ 325