1*828c91f7SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2277b024eSKalle Valo /*
3932183aaSGanapathi Bhat * NXP Wireless LAN device driver: 802.11n RX Re-ordering
4277b024eSKalle Valo *
5932183aaSGanapathi Bhat * Copyright 2011-2020 NXP
6277b024eSKalle Valo */
7277b024eSKalle Valo
8277b024eSKalle Valo #ifndef _MWIFIEX_11N_RXREORDER_H_
9277b024eSKalle Valo #define _MWIFIEX_11N_RXREORDER_H_
10277b024eSKalle Valo
11277b024eSKalle Valo #define MIN_FLUSH_TIMER_MS 50
12277b024eSKalle Valo #define MIN_FLUSH_TIMER_15_MS 15
13277b024eSKalle Valo #define MWIFIEX_BA_WIN_SIZE_32 32
14277b024eSKalle Valo
15277b024eSKalle Valo #define PKT_TYPE_BAR 0xE7
16277b024eSKalle Valo #define MAX_TID_VALUE (2 << 11)
17277b024eSKalle Valo #define TWOPOW11 (2 << 10)
18277b024eSKalle Valo
19277b024eSKalle Valo #define BLOCKACKPARAM_TID_POS 2
20277b024eSKalle Valo #define BLOCKACKPARAM_AMSDU_SUPP_MASK 0x1
21277b024eSKalle Valo #define BLOCKACKPARAM_WINSIZE_POS 6
22277b024eSKalle Valo #define DELBA_TID_POS 12
23277b024eSKalle Valo #define DELBA_INITIATOR_POS 11
24277b024eSKalle Valo #define TYPE_DELBA_SENT 1
25277b024eSKalle Valo #define TYPE_DELBA_RECEIVE 2
26277b024eSKalle Valo #define IMMEDIATE_BLOCK_ACK 0x2
27277b024eSKalle Valo
28277b024eSKalle Valo #define ADDBA_RSP_STATUS_ACCEPT 0
29277b024eSKalle Valo
30277b024eSKalle Valo #define MWIFIEX_DEF_11N_RX_SEQ_NUM 0xffff
31277b024eSKalle Valo #define BA_SETUP_MAX_PACKET_THRESHOLD 16
32277b024eSKalle Valo #define BA_SETUP_PACKET_OFFSET 16
33277b024eSKalle Valo
34277b024eSKalle Valo enum mwifiex_rxreor_flags {
35277b024eSKalle Valo RXREOR_FORCE_NO_DROP = 1<<0,
36277b024eSKalle Valo RXREOR_INIT_WINDOW_SHIFT = 1<<1,
37277b024eSKalle Valo };
38277b024eSKalle Valo
mwifiex_reset_11n_rx_seq_num(struct mwifiex_private * priv)39277b024eSKalle Valo static inline void mwifiex_reset_11n_rx_seq_num(struct mwifiex_private *priv)
40277b024eSKalle Valo {
41277b024eSKalle Valo memset(priv->rx_seq, 0xff, sizeof(priv->rx_seq));
42277b024eSKalle Valo }
43277b024eSKalle Valo
44277b024eSKalle Valo int mwifiex_11n_rx_reorder_pkt(struct mwifiex_private *,
45277b024eSKalle Valo u16 seqNum,
46277b024eSKalle Valo u16 tid, u8 *ta,
47277b024eSKalle Valo u8 pkttype, void *payload);
48277b024eSKalle Valo void mwifiex_del_ba_tbl(struct mwifiex_private *priv, int Tid,
49277b024eSKalle Valo u8 *PeerMACAddr, u8 type, int initiator);
50277b024eSKalle Valo void mwifiex_11n_ba_stream_timeout(struct mwifiex_private *priv,
51277b024eSKalle Valo struct host_cmd_ds_11n_batimeout *event);
52277b024eSKalle Valo int mwifiex_ret_11n_addba_resp(struct mwifiex_private *priv,
53277b024eSKalle Valo struct host_cmd_ds_command
54277b024eSKalle Valo *resp);
55277b024eSKalle Valo int mwifiex_cmd_11n_delba(struct host_cmd_ds_command *cmd,
56277b024eSKalle Valo void *data_buf);
57277b024eSKalle Valo int mwifiex_cmd_11n_addba_rsp_gen(struct mwifiex_private *priv,
58277b024eSKalle Valo struct host_cmd_ds_command *cmd,
59277b024eSKalle Valo struct host_cmd_ds_11n_addba_req
60277b024eSKalle Valo *cmd_addba_req);
61277b024eSKalle Valo int mwifiex_cmd_11n_addba_req(struct host_cmd_ds_command *cmd,
62277b024eSKalle Valo void *data_buf);
63277b024eSKalle Valo void mwifiex_11n_cleanup_reorder_tbl(struct mwifiex_private *priv);
64277b024eSKalle Valo struct mwifiex_rx_reorder_tbl *mwifiex_11n_get_rxreorder_tbl(struct
65277b024eSKalle Valo mwifiex_private
66277b024eSKalle Valo *priv, int tid,
67277b024eSKalle Valo u8 *ta);
68277b024eSKalle Valo struct mwifiex_rx_reorder_tbl *
69277b024eSKalle Valo mwifiex_11n_get_rx_reorder_tbl(struct mwifiex_private *priv, int tid, u8 *ta);
70277b024eSKalle Valo void mwifiex_11n_del_rx_reorder_tbl_by_ta(struct mwifiex_private *priv, u8 *ta);
71277b024eSKalle Valo void mwifiex_update_rxreor_flags(struct mwifiex_adapter *adapter, u8 flags);
7299ffe72cSXinming Hu void mwifiex_11n_rxba_sync_event(struct mwifiex_private *priv,
7399ffe72cSXinming Hu u8 *event_buf, u16 len);
74277b024eSKalle Valo #endif /* _MWIFIEX_11N_RXREORDER_H_ */
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