1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * linux/drivers/net/wireless/libertas/if_spi.c 4 * 5 * Driver for Marvell SPI WLAN cards. 6 * 7 * Copyright 2008 Analog Devices Inc. 8 * 9 * Authors: 10 * Andrey Yurovsky <andrey@cozybit.com> 11 * Colin McCabe <colin@cozybit.com> 12 */ 13 14 #ifndef _LBS_IF_SPI_H_ 15 #define _LBS_IF_SPI_H_ 16 17 #define IPFIELD_ALIGN_OFFSET 2 18 #define IF_SPI_CMD_BUF_SIZE 2400 19 20 /***************** Firmware *****************/ 21 22 #define IF_SPI_FW_NAME_MAX 30 23 24 #define MAX_MAIN_FW_LOAD_CRC_ERR 10 25 26 /* Chunk size when loading the helper firmware */ 27 #define HELPER_FW_LOAD_CHUNK_SZ 64 28 29 /* Value to write to indicate end of helper firmware dnld */ 30 #define FIRMWARE_DNLD_OK 0x0000 31 32 /* Value to check once the main firmware is downloaded */ 33 #define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888 34 35 /***************** SPI Interface Unit *****************/ 36 /* Masks used in SPI register read/write operations */ 37 #define IF_SPI_READ_OPERATION_MASK 0x0 38 #define IF_SPI_WRITE_OPERATION_MASK 0x8000 39 40 /* SPI register offsets. 4-byte aligned. */ 41 #define IF_SPI_DEVICEID_CTRL_REG 0x00 /* DeviceID controller reg */ 42 #define IF_SPI_IO_READBASE_REG 0x04 /* Read I/O base reg */ 43 #define IF_SPI_IO_WRITEBASE_REG 0x08 /* Write I/O base reg */ 44 #define IF_SPI_IO_RDWRPORT_REG 0x0C /* Read/Write I/O port reg */ 45 46 #define IF_SPI_CMD_READBASE_REG 0x10 /* Read command base reg */ 47 #define IF_SPI_CMD_WRITEBASE_REG 0x14 /* Write command base reg */ 48 #define IF_SPI_CMD_RDWRPORT_REG 0x18 /* Read/Write command port reg */ 49 50 #define IF_SPI_DATA_READBASE_REG 0x1C /* Read data base reg */ 51 #define IF_SPI_DATA_WRITEBASE_REG 0x20 /* Write data base reg */ 52 #define IF_SPI_DATA_RDWRPORT_REG 0x24 /* Read/Write data port reg */ 53 54 #define IF_SPI_SCRATCH_1_REG 0x28 /* Scratch reg 1 */ 55 #define IF_SPI_SCRATCH_2_REG 0x2C /* Scratch reg 2 */ 56 #define IF_SPI_SCRATCH_3_REG 0x30 /* Scratch reg 3 */ 57 #define IF_SPI_SCRATCH_4_REG 0x34 /* Scratch reg 4 */ 58 59 #define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38 /* Tx frame sequence number reg */ 60 #define IF_SPI_TX_FRAME_STATUS_REG 0x3C /* Tx frame status reg */ 61 62 #define IF_SPI_HOST_INT_CTRL_REG 0x40 /* Host interrupt controller reg */ 63 64 #define IF_SPI_CARD_INT_CAUSE_REG 0x44 /* Card interrupt cause reg */ 65 #define IF_SPI_CARD_INT_STATUS_REG 0x48 /* Card interrupt status reg */ 66 #define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C /* Card interrupt event mask */ 67 #define IF_SPI_CARD_INT_STATUS_MASK_REG 0x50 /* Card interrupt status mask */ 68 69 #define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54 /* Card interrupt reset select */ 70 71 #define IF_SPI_HOST_INT_CAUSE_REG 0x58 /* Host interrupt cause reg */ 72 #define IF_SPI_HOST_INT_STATUS_REG 0x5C /* Host interrupt status reg */ 73 #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */ 74 #define IF_SPI_HOST_INT_STATUS_MASK_REG 0x64 /* Host interrupt status mask */ 75 #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */ 76 77 #define IF_SPI_DELAY_READ_REG 0x6C /* Delay read reg */ 78 #define IF_SPI_SPU_BUS_MODE_REG 0x70 /* SPU BUS mode reg */ 79 80 /***************** IF_SPI_DEVICEID_CTRL_REG *****************/ 81 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16) 82 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff) 83 84 /***************** IF_SPI_HOST_INT_CTRL_REG *****************/ 85 /* Host Interrupt Control bit : Wake up */ 86 #define IF_SPI_HICT_WAKE_UP (1<<0) 87 /* Host Interrupt Control bit : WLAN ready */ 88 #define IF_SPI_HICT_WLAN_READY (1<<1) 89 /*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY (1<<2) */ 90 /*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY (1<<3) */ 91 /*#define IF_SPI_HICT_IRQSRC_WLAN (1<<4) */ 92 /* Host Interrupt Control bit : Tx auto download */ 93 #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO (1<<5) 94 /* Host Interrupt Control bit : Rx auto upload */ 95 #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO (1<<6) 96 /* Host Interrupt Control bit : Command auto download */ 97 #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO (1<<7) 98 /* Host Interrupt Control bit : Command auto upload */ 99 #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO (1<<8) 100 101 /***************** IF_SPI_CARD_INT_CAUSE_REG *****************/ 102 /* Card Interrupt Case bit : Tx download over */ 103 #define IF_SPI_CIC_TX_DOWNLOAD_OVER (1<<0) 104 /* Card Interrupt Case bit : Rx upload over */ 105 #define IF_SPI_CIC_RX_UPLOAD_OVER (1<<1) 106 /* Card Interrupt Case bit : Command download over */ 107 #define IF_SPI_CIC_CMD_DOWNLOAD_OVER (1<<2) 108 /* Card Interrupt Case bit : Host event */ 109 #define IF_SPI_CIC_HOST_EVENT (1<<3) 110 /* Card Interrupt Case bit : Command upload over */ 111 #define IF_SPI_CIC_CMD_UPLOAD_OVER (1<<4) 112 /* Card Interrupt Case bit : Power down */ 113 #define IF_SPI_CIC_POWER_DOWN (1<<5) 114 115 /***************** IF_SPI_CARD_INT_STATUS_REG *****************/ 116 #define IF_SPI_CIS_TX_DOWNLOAD_OVER (1<<0) 117 #define IF_SPI_CIS_RX_UPLOAD_OVER (1<<1) 118 #define IF_SPI_CIS_CMD_DOWNLOAD_OVER (1<<2) 119 #define IF_SPI_CIS_HOST_EVENT (1<<3) 120 #define IF_SPI_CIS_CMD_UPLOAD_OVER (1<<4) 121 #define IF_SPI_CIS_POWER_DOWN (1<<5) 122 123 /***************** IF_SPI_HOST_INT_CAUSE_REG *****************/ 124 #define IF_SPI_HICU_TX_DOWNLOAD_RDY (1<<0) 125 #define IF_SPI_HICU_RX_UPLOAD_RDY (1<<1) 126 #define IF_SPI_HICU_CMD_DOWNLOAD_RDY (1<<2) 127 #define IF_SPI_HICU_CARD_EVENT (1<<3) 128 #define IF_SPI_HICU_CMD_UPLOAD_RDY (1<<4) 129 #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW (1<<5) 130 #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW (1<<6) 131 #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW (1<<7) 132 #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW (1<<8) 133 #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW (1<<9) 134 #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW (1<<10) 135 136 /***************** IF_SPI_HOST_INT_STATUS_REG *****************/ 137 /* Host Interrupt Status bit : Tx download ready */ 138 #define IF_SPI_HIST_TX_DOWNLOAD_RDY (1<<0) 139 /* Host Interrupt Status bit : Rx upload ready */ 140 #define IF_SPI_HIST_RX_UPLOAD_RDY (1<<1) 141 /* Host Interrupt Status bit : Command download ready */ 142 #define IF_SPI_HIST_CMD_DOWNLOAD_RDY (1<<2) 143 /* Host Interrupt Status bit : Card event */ 144 #define IF_SPI_HIST_CARD_EVENT (1<<3) 145 /* Host Interrupt Status bit : Command upload ready */ 146 #define IF_SPI_HIST_CMD_UPLOAD_RDY (1<<4) 147 /* Host Interrupt Status bit : I/O write FIFO overflow */ 148 #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW (1<<5) 149 /* Host Interrupt Status bit : I/O read FIFO underflow */ 150 #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW (1<<6) 151 /* Host Interrupt Status bit : Data write FIFO overflow */ 152 #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW (1<<7) 153 /* Host Interrupt Status bit : Data read FIFO underflow */ 154 #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW (1<<8) 155 /* Host Interrupt Status bit : Command write FIFO overflow */ 156 #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW (1<<9) 157 /* Host Interrupt Status bit : Command read FIFO underflow */ 158 #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW (1<<10) 159 160 /***************** IF_SPI_HOST_INT_STATUS_MASK_REG *****************/ 161 /* Host Interrupt Status Mask bit : Tx download ready */ 162 #define IF_SPI_HISM_TX_DOWNLOAD_RDY (1<<0) 163 /* Host Interrupt Status Mask bit : Rx upload ready */ 164 #define IF_SPI_HISM_RX_UPLOAD_RDY (1<<1) 165 /* Host Interrupt Status Mask bit : Command download ready */ 166 #define IF_SPI_HISM_CMD_DOWNLOAD_RDY (1<<2) 167 /* Host Interrupt Status Mask bit : Card event */ 168 #define IF_SPI_HISM_CARDEVENT (1<<3) 169 /* Host Interrupt Status Mask bit : Command upload ready */ 170 #define IF_SPI_HISM_CMD_UPLOAD_RDY (1<<4) 171 /* Host Interrupt Status Mask bit : I/O write FIFO overflow */ 172 #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW (1<<5) 173 /* Host Interrupt Status Mask bit : I/O read FIFO underflow */ 174 #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW (1<<6) 175 /* Host Interrupt Status Mask bit : Data write FIFO overflow */ 176 #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW (1<<7) 177 /* Host Interrupt Status Mask bit : Data write FIFO underflow */ 178 #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW (1<<8) 179 /* Host Interrupt Status Mask bit : Command write FIFO overflow */ 180 #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW (1<<9) 181 /* Host Interrupt Status Mask bit : Command write FIFO underflow */ 182 #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW (1<<10) 183 184 /***************** IF_SPI_SPU_BUS_MODE_REG *****************/ 185 /* SCK edge on which the WLAN module outputs data on MISO */ 186 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8 187 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0 188 189 /* In a SPU read operation, there is a delay between writing the SPU 190 * register name and getting back data from the WLAN module. 191 * This can be specified in terms of nanoseconds or in terms of dummy 192 * clock cycles which the master must output before receiving a response. */ 193 #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4 194 #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0 195 196 /* Some different modes of SPI operation */ 197 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00 198 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01 199 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02 200 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03 201 202 #endif 203