1*d3466830SKalle Valo /* 2*d3466830SKalle Valo * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de> 3*d3466830SKalle Valo * Copyright 2008 Johannes Berg <johannes@sipsolutions.net> 4*d3466830SKalle Valo * 5*d3466830SKalle Valo * This driver is a port from stlc45xx: 6*d3466830SKalle Valo * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies). 7*d3466830SKalle Valo * 8*d3466830SKalle Valo * This program is free software; you can redistribute it and/or 9*d3466830SKalle Valo * modify it under the terms of the GNU General Public License 10*d3466830SKalle Valo * version 2 as published by the Free Software Foundation. 11*d3466830SKalle Valo * 12*d3466830SKalle Valo * This program is distributed in the hope that it will be useful, but 13*d3466830SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 14*d3466830SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15*d3466830SKalle Valo * General Public License for more details. 16*d3466830SKalle Valo * 17*d3466830SKalle Valo * You should have received a copy of the GNU General Public License 18*d3466830SKalle Valo * along with this program; if not, write to the Free Software 19*d3466830SKalle Valo * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20*d3466830SKalle Valo * 02110-1301 USA 21*d3466830SKalle Valo */ 22*d3466830SKalle Valo 23*d3466830SKalle Valo #include <linux/module.h> 24*d3466830SKalle Valo #include <linux/platform_device.h> 25*d3466830SKalle Valo #include <linux/interrupt.h> 26*d3466830SKalle Valo #include <linux/firmware.h> 27*d3466830SKalle Valo #include <linux/delay.h> 28*d3466830SKalle Valo #include <linux/irq.h> 29*d3466830SKalle Valo #include <linux/spi/spi.h> 30*d3466830SKalle Valo #include <linux/etherdevice.h> 31*d3466830SKalle Valo #include <linux/gpio.h> 32*d3466830SKalle Valo #include <linux/slab.h> 33*d3466830SKalle Valo 34*d3466830SKalle Valo #include "p54spi.h" 35*d3466830SKalle Valo #include "p54.h" 36*d3466830SKalle Valo 37*d3466830SKalle Valo #include "lmac.h" 38*d3466830SKalle Valo 39*d3466830SKalle Valo #ifdef CONFIG_P54_SPI_DEFAULT_EEPROM 40*d3466830SKalle Valo #include "p54spi_eeprom.h" 41*d3466830SKalle Valo #endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */ 42*d3466830SKalle Valo 43*d3466830SKalle Valo MODULE_FIRMWARE("3826.arm"); 44*d3466830SKalle Valo 45*d3466830SKalle Valo /* gpios should be handled in board files and provided via platform data, 46*d3466830SKalle Valo * but because it's currently impossible for p54spi to have a header file 47*d3466830SKalle Valo * in include/linux, let's use module paramaters for now 48*d3466830SKalle Valo */ 49*d3466830SKalle Valo 50*d3466830SKalle Valo static int p54spi_gpio_power = 97; 51*d3466830SKalle Valo module_param(p54spi_gpio_power, int, 0444); 52*d3466830SKalle Valo MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line"); 53*d3466830SKalle Valo 54*d3466830SKalle Valo static int p54spi_gpio_irq = 87; 55*d3466830SKalle Valo module_param(p54spi_gpio_irq, int, 0444); 56*d3466830SKalle Valo MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line"); 57*d3466830SKalle Valo 58*d3466830SKalle Valo static void p54spi_spi_read(struct p54s_priv *priv, u8 address, 59*d3466830SKalle Valo void *buf, size_t len) 60*d3466830SKalle Valo { 61*d3466830SKalle Valo struct spi_transfer t[2]; 62*d3466830SKalle Valo struct spi_message m; 63*d3466830SKalle Valo __le16 addr; 64*d3466830SKalle Valo 65*d3466830SKalle Valo /* We first push the address */ 66*d3466830SKalle Valo addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15); 67*d3466830SKalle Valo 68*d3466830SKalle Valo spi_message_init(&m); 69*d3466830SKalle Valo memset(t, 0, sizeof(t)); 70*d3466830SKalle Valo 71*d3466830SKalle Valo t[0].tx_buf = &addr; 72*d3466830SKalle Valo t[0].len = sizeof(addr); 73*d3466830SKalle Valo spi_message_add_tail(&t[0], &m); 74*d3466830SKalle Valo 75*d3466830SKalle Valo t[1].rx_buf = buf; 76*d3466830SKalle Valo t[1].len = len; 77*d3466830SKalle Valo spi_message_add_tail(&t[1], &m); 78*d3466830SKalle Valo 79*d3466830SKalle Valo spi_sync(priv->spi, &m); 80*d3466830SKalle Valo } 81*d3466830SKalle Valo 82*d3466830SKalle Valo 83*d3466830SKalle Valo static void p54spi_spi_write(struct p54s_priv *priv, u8 address, 84*d3466830SKalle Valo const void *buf, size_t len) 85*d3466830SKalle Valo { 86*d3466830SKalle Valo struct spi_transfer t[3]; 87*d3466830SKalle Valo struct spi_message m; 88*d3466830SKalle Valo __le16 addr; 89*d3466830SKalle Valo 90*d3466830SKalle Valo /* We first push the address */ 91*d3466830SKalle Valo addr = cpu_to_le16(address << 8); 92*d3466830SKalle Valo 93*d3466830SKalle Valo spi_message_init(&m); 94*d3466830SKalle Valo memset(t, 0, sizeof(t)); 95*d3466830SKalle Valo 96*d3466830SKalle Valo t[0].tx_buf = &addr; 97*d3466830SKalle Valo t[0].len = sizeof(addr); 98*d3466830SKalle Valo spi_message_add_tail(&t[0], &m); 99*d3466830SKalle Valo 100*d3466830SKalle Valo t[1].tx_buf = buf; 101*d3466830SKalle Valo t[1].len = len & ~1; 102*d3466830SKalle Valo spi_message_add_tail(&t[1], &m); 103*d3466830SKalle Valo 104*d3466830SKalle Valo if (len % 2) { 105*d3466830SKalle Valo __le16 last_word; 106*d3466830SKalle Valo last_word = cpu_to_le16(((u8 *)buf)[len - 1]); 107*d3466830SKalle Valo 108*d3466830SKalle Valo t[2].tx_buf = &last_word; 109*d3466830SKalle Valo t[2].len = sizeof(last_word); 110*d3466830SKalle Valo spi_message_add_tail(&t[2], &m); 111*d3466830SKalle Valo } 112*d3466830SKalle Valo 113*d3466830SKalle Valo spi_sync(priv->spi, &m); 114*d3466830SKalle Valo } 115*d3466830SKalle Valo 116*d3466830SKalle Valo static u32 p54spi_read32(struct p54s_priv *priv, u8 addr) 117*d3466830SKalle Valo { 118*d3466830SKalle Valo __le32 val; 119*d3466830SKalle Valo 120*d3466830SKalle Valo p54spi_spi_read(priv, addr, &val, sizeof(val)); 121*d3466830SKalle Valo 122*d3466830SKalle Valo return le32_to_cpu(val); 123*d3466830SKalle Valo } 124*d3466830SKalle Valo 125*d3466830SKalle Valo static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val) 126*d3466830SKalle Valo { 127*d3466830SKalle Valo p54spi_spi_write(priv, addr, &val, sizeof(val)); 128*d3466830SKalle Valo } 129*d3466830SKalle Valo 130*d3466830SKalle Valo static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val) 131*d3466830SKalle Valo { 132*d3466830SKalle Valo p54spi_spi_write(priv, addr, &val, sizeof(val)); 133*d3466830SKalle Valo } 134*d3466830SKalle Valo 135*d3466830SKalle Valo static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits) 136*d3466830SKalle Valo { 137*d3466830SKalle Valo int i; 138*d3466830SKalle Valo 139*d3466830SKalle Valo for (i = 0; i < 2000; i++) { 140*d3466830SKalle Valo u32 buffer = p54spi_read32(priv, reg); 141*d3466830SKalle Valo if ((buffer & bits) == bits) 142*d3466830SKalle Valo return 1; 143*d3466830SKalle Valo } 144*d3466830SKalle Valo return 0; 145*d3466830SKalle Valo } 146*d3466830SKalle Valo 147*d3466830SKalle Valo static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base, 148*d3466830SKalle Valo const void *buf, size_t len) 149*d3466830SKalle Valo { 150*d3466830SKalle Valo if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) { 151*d3466830SKalle Valo dev_err(&priv->spi->dev, "spi_write_dma not allowed " 152*d3466830SKalle Valo "to DMA write.\n"); 153*d3466830SKalle Valo return -EAGAIN; 154*d3466830SKalle Valo } 155*d3466830SKalle Valo 156*d3466830SKalle Valo p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL, 157*d3466830SKalle Valo cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE)); 158*d3466830SKalle Valo 159*d3466830SKalle Valo p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len)); 160*d3466830SKalle Valo p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base); 161*d3466830SKalle Valo p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len); 162*d3466830SKalle Valo return 0; 163*d3466830SKalle Valo } 164*d3466830SKalle Valo 165*d3466830SKalle Valo static int p54spi_request_firmware(struct ieee80211_hw *dev) 166*d3466830SKalle Valo { 167*d3466830SKalle Valo struct p54s_priv *priv = dev->priv; 168*d3466830SKalle Valo int ret; 169*d3466830SKalle Valo 170*d3466830SKalle Valo /* FIXME: should driver use it's own struct device? */ 171*d3466830SKalle Valo ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev); 172*d3466830SKalle Valo 173*d3466830SKalle Valo if (ret < 0) { 174*d3466830SKalle Valo dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret); 175*d3466830SKalle Valo return ret; 176*d3466830SKalle Valo } 177*d3466830SKalle Valo 178*d3466830SKalle Valo ret = p54_parse_firmware(dev, priv->firmware); 179*d3466830SKalle Valo if (ret) { 180*d3466830SKalle Valo release_firmware(priv->firmware); 181*d3466830SKalle Valo return ret; 182*d3466830SKalle Valo } 183*d3466830SKalle Valo 184*d3466830SKalle Valo return 0; 185*d3466830SKalle Valo } 186*d3466830SKalle Valo 187*d3466830SKalle Valo static int p54spi_request_eeprom(struct ieee80211_hw *dev) 188*d3466830SKalle Valo { 189*d3466830SKalle Valo struct p54s_priv *priv = dev->priv; 190*d3466830SKalle Valo const struct firmware *eeprom; 191*d3466830SKalle Valo int ret; 192*d3466830SKalle Valo 193*d3466830SKalle Valo /* allow users to customize their eeprom. 194*d3466830SKalle Valo */ 195*d3466830SKalle Valo 196*d3466830SKalle Valo ret = request_firmware_direct(&eeprom, "3826.eeprom", &priv->spi->dev); 197*d3466830SKalle Valo if (ret < 0) { 198*d3466830SKalle Valo #ifdef CONFIG_P54_SPI_DEFAULT_EEPROM 199*d3466830SKalle Valo dev_info(&priv->spi->dev, "loading default eeprom...\n"); 200*d3466830SKalle Valo ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom, 201*d3466830SKalle Valo sizeof(p54spi_eeprom)); 202*d3466830SKalle Valo #else 203*d3466830SKalle Valo dev_err(&priv->spi->dev, "Failed to request user eeprom\n"); 204*d3466830SKalle Valo #endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */ 205*d3466830SKalle Valo } else { 206*d3466830SKalle Valo dev_info(&priv->spi->dev, "loading user eeprom...\n"); 207*d3466830SKalle Valo ret = p54_parse_eeprom(dev, (void *) eeprom->data, 208*d3466830SKalle Valo (int)eeprom->size); 209*d3466830SKalle Valo release_firmware(eeprom); 210*d3466830SKalle Valo } 211*d3466830SKalle Valo return ret; 212*d3466830SKalle Valo } 213*d3466830SKalle Valo 214*d3466830SKalle Valo static int p54spi_upload_firmware(struct ieee80211_hw *dev) 215*d3466830SKalle Valo { 216*d3466830SKalle Valo struct p54s_priv *priv = dev->priv; 217*d3466830SKalle Valo unsigned long fw_len, _fw_len; 218*d3466830SKalle Valo unsigned int offset = 0; 219*d3466830SKalle Valo int err = 0; 220*d3466830SKalle Valo u8 *fw; 221*d3466830SKalle Valo 222*d3466830SKalle Valo fw_len = priv->firmware->size; 223*d3466830SKalle Valo fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL); 224*d3466830SKalle Valo if (!fw) 225*d3466830SKalle Valo return -ENOMEM; 226*d3466830SKalle Valo 227*d3466830SKalle Valo /* stop the device */ 228*d3466830SKalle Valo p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 229*d3466830SKalle Valo SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET | 230*d3466830SKalle Valo SPI_CTRL_STAT_START_HALTED)); 231*d3466830SKalle Valo 232*d3466830SKalle Valo msleep(TARGET_BOOT_SLEEP); 233*d3466830SKalle Valo 234*d3466830SKalle Valo p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 235*d3466830SKalle Valo SPI_CTRL_STAT_HOST_OVERRIDE | 236*d3466830SKalle Valo SPI_CTRL_STAT_START_HALTED)); 237*d3466830SKalle Valo 238*d3466830SKalle Valo msleep(TARGET_BOOT_SLEEP); 239*d3466830SKalle Valo 240*d3466830SKalle Valo while (fw_len > 0) { 241*d3466830SKalle Valo _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE); 242*d3466830SKalle Valo 243*d3466830SKalle Valo err = p54spi_spi_write_dma(priv, cpu_to_le32( 244*d3466830SKalle Valo ISL38XX_DEV_FIRMWARE_ADDR + offset), 245*d3466830SKalle Valo (fw + offset), _fw_len); 246*d3466830SKalle Valo if (err < 0) 247*d3466830SKalle Valo goto out; 248*d3466830SKalle Valo 249*d3466830SKalle Valo fw_len -= _fw_len; 250*d3466830SKalle Valo offset += _fw_len; 251*d3466830SKalle Valo } 252*d3466830SKalle Valo 253*d3466830SKalle Valo BUG_ON(fw_len != 0); 254*d3466830SKalle Valo 255*d3466830SKalle Valo /* enable host interrupts */ 256*d3466830SKalle Valo p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, 257*d3466830SKalle Valo cpu_to_le32(SPI_HOST_INTS_DEFAULT)); 258*d3466830SKalle Valo 259*d3466830SKalle Valo /* boot the device */ 260*d3466830SKalle Valo p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 261*d3466830SKalle Valo SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET | 262*d3466830SKalle Valo SPI_CTRL_STAT_RAM_BOOT)); 263*d3466830SKalle Valo 264*d3466830SKalle Valo msleep(TARGET_BOOT_SLEEP); 265*d3466830SKalle Valo 266*d3466830SKalle Valo p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 267*d3466830SKalle Valo SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT)); 268*d3466830SKalle Valo msleep(TARGET_BOOT_SLEEP); 269*d3466830SKalle Valo 270*d3466830SKalle Valo out: 271*d3466830SKalle Valo kfree(fw); 272*d3466830SKalle Valo return err; 273*d3466830SKalle Valo } 274*d3466830SKalle Valo 275*d3466830SKalle Valo static void p54spi_power_off(struct p54s_priv *priv) 276*d3466830SKalle Valo { 277*d3466830SKalle Valo disable_irq(gpio_to_irq(p54spi_gpio_irq)); 278*d3466830SKalle Valo gpio_set_value(p54spi_gpio_power, 0); 279*d3466830SKalle Valo } 280*d3466830SKalle Valo 281*d3466830SKalle Valo static void p54spi_power_on(struct p54s_priv *priv) 282*d3466830SKalle Valo { 283*d3466830SKalle Valo gpio_set_value(p54spi_gpio_power, 1); 284*d3466830SKalle Valo enable_irq(gpio_to_irq(p54spi_gpio_irq)); 285*d3466830SKalle Valo 286*d3466830SKalle Valo /* need to wait a while before device can be accessed, the length 287*d3466830SKalle Valo * is just a guess 288*d3466830SKalle Valo */ 289*d3466830SKalle Valo msleep(10); 290*d3466830SKalle Valo } 291*d3466830SKalle Valo 292*d3466830SKalle Valo static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val) 293*d3466830SKalle Valo { 294*d3466830SKalle Valo p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val)); 295*d3466830SKalle Valo } 296*d3466830SKalle Valo 297*d3466830SKalle Valo static int p54spi_wakeup(struct p54s_priv *priv) 298*d3466830SKalle Valo { 299*d3466830SKalle Valo /* wake the chip */ 300*d3466830SKalle Valo p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS, 301*d3466830SKalle Valo cpu_to_le32(SPI_TARGET_INT_WAKEUP)); 302*d3466830SKalle Valo 303*d3466830SKalle Valo /* And wait for the READY interrupt */ 304*d3466830SKalle Valo if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS, 305*d3466830SKalle Valo SPI_HOST_INT_READY)) { 306*d3466830SKalle Valo dev_err(&priv->spi->dev, "INT_READY timeout\n"); 307*d3466830SKalle Valo return -EBUSY; 308*d3466830SKalle Valo } 309*d3466830SKalle Valo 310*d3466830SKalle Valo p54spi_int_ack(priv, SPI_HOST_INT_READY); 311*d3466830SKalle Valo return 0; 312*d3466830SKalle Valo } 313*d3466830SKalle Valo 314*d3466830SKalle Valo static inline void p54spi_sleep(struct p54s_priv *priv) 315*d3466830SKalle Valo { 316*d3466830SKalle Valo p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS, 317*d3466830SKalle Valo cpu_to_le32(SPI_TARGET_INT_SLEEP)); 318*d3466830SKalle Valo } 319*d3466830SKalle Valo 320*d3466830SKalle Valo static void p54spi_int_ready(struct p54s_priv *priv) 321*d3466830SKalle Valo { 322*d3466830SKalle Valo p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32( 323*d3466830SKalle Valo SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)); 324*d3466830SKalle Valo 325*d3466830SKalle Valo switch (priv->fw_state) { 326*d3466830SKalle Valo case FW_STATE_BOOTING: 327*d3466830SKalle Valo priv->fw_state = FW_STATE_READY; 328*d3466830SKalle Valo complete(&priv->fw_comp); 329*d3466830SKalle Valo break; 330*d3466830SKalle Valo case FW_STATE_RESETTING: 331*d3466830SKalle Valo priv->fw_state = FW_STATE_READY; 332*d3466830SKalle Valo /* TODO: reinitialize state */ 333*d3466830SKalle Valo break; 334*d3466830SKalle Valo default: 335*d3466830SKalle Valo break; 336*d3466830SKalle Valo } 337*d3466830SKalle Valo } 338*d3466830SKalle Valo 339*d3466830SKalle Valo static int p54spi_rx(struct p54s_priv *priv) 340*d3466830SKalle Valo { 341*d3466830SKalle Valo struct sk_buff *skb; 342*d3466830SKalle Valo u16 len; 343*d3466830SKalle Valo u16 rx_head[2]; 344*d3466830SKalle Valo #define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16)) 345*d3466830SKalle Valo 346*d3466830SKalle Valo if (p54spi_wakeup(priv) < 0) 347*d3466830SKalle Valo return -EBUSY; 348*d3466830SKalle Valo 349*d3466830SKalle Valo /* Read data size and first data word in one SPI transaction 350*d3466830SKalle Valo * This is workaround for firmware/DMA bug, 351*d3466830SKalle Valo * when first data word gets lost under high load. 352*d3466830SKalle Valo */ 353*d3466830SKalle Valo p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head)); 354*d3466830SKalle Valo len = rx_head[0]; 355*d3466830SKalle Valo 356*d3466830SKalle Valo if (len == 0) { 357*d3466830SKalle Valo p54spi_sleep(priv); 358*d3466830SKalle Valo dev_err(&priv->spi->dev, "rx request of zero bytes\n"); 359*d3466830SKalle Valo return 0; 360*d3466830SKalle Valo } 361*d3466830SKalle Valo 362*d3466830SKalle Valo /* Firmware may insert up to 4 padding bytes after the lmac header, 363*d3466830SKalle Valo * but it does not amend the size of SPI data transfer. 364*d3466830SKalle Valo * Such packets has correct data size in header, thus referencing 365*d3466830SKalle Valo * past the end of allocated skb. Reserve extra 4 bytes for this case 366*d3466830SKalle Valo */ 367*d3466830SKalle Valo skb = dev_alloc_skb(len + 4); 368*d3466830SKalle Valo if (!skb) { 369*d3466830SKalle Valo p54spi_sleep(priv); 370*d3466830SKalle Valo dev_err(&priv->spi->dev, "could not alloc skb"); 371*d3466830SKalle Valo return -ENOMEM; 372*d3466830SKalle Valo } 373*d3466830SKalle Valo 374*d3466830SKalle Valo if (len <= READAHEAD_SZ) { 375*d3466830SKalle Valo memcpy(skb_put(skb, len), rx_head + 1, len); 376*d3466830SKalle Valo } else { 377*d3466830SKalle Valo memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ); 378*d3466830SKalle Valo p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, 379*d3466830SKalle Valo skb_put(skb, len - READAHEAD_SZ), 380*d3466830SKalle Valo len - READAHEAD_SZ); 381*d3466830SKalle Valo } 382*d3466830SKalle Valo p54spi_sleep(priv); 383*d3466830SKalle Valo /* Put additional bytes to compensate for the possible 384*d3466830SKalle Valo * alignment-caused truncation 385*d3466830SKalle Valo */ 386*d3466830SKalle Valo skb_put(skb, 4); 387*d3466830SKalle Valo 388*d3466830SKalle Valo if (p54_rx(priv->hw, skb) == 0) 389*d3466830SKalle Valo dev_kfree_skb(skb); 390*d3466830SKalle Valo 391*d3466830SKalle Valo return 0; 392*d3466830SKalle Valo } 393*d3466830SKalle Valo 394*d3466830SKalle Valo 395*d3466830SKalle Valo static irqreturn_t p54spi_interrupt(int irq, void *config) 396*d3466830SKalle Valo { 397*d3466830SKalle Valo struct spi_device *spi = config; 398*d3466830SKalle Valo struct p54s_priv *priv = spi_get_drvdata(spi); 399*d3466830SKalle Valo 400*d3466830SKalle Valo ieee80211_queue_work(priv->hw, &priv->work); 401*d3466830SKalle Valo 402*d3466830SKalle Valo return IRQ_HANDLED; 403*d3466830SKalle Valo } 404*d3466830SKalle Valo 405*d3466830SKalle Valo static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb) 406*d3466830SKalle Valo { 407*d3466830SKalle Valo struct p54_hdr *hdr = (struct p54_hdr *) skb->data; 408*d3466830SKalle Valo int ret = 0; 409*d3466830SKalle Valo 410*d3466830SKalle Valo if (p54spi_wakeup(priv) < 0) 411*d3466830SKalle Valo return -EBUSY; 412*d3466830SKalle Valo 413*d3466830SKalle Valo ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len); 414*d3466830SKalle Valo if (ret < 0) 415*d3466830SKalle Valo goto out; 416*d3466830SKalle Valo 417*d3466830SKalle Valo if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS, 418*d3466830SKalle Valo SPI_HOST_INT_WR_READY)) { 419*d3466830SKalle Valo dev_err(&priv->spi->dev, "WR_READY timeout\n"); 420*d3466830SKalle Valo ret = -EAGAIN; 421*d3466830SKalle Valo goto out; 422*d3466830SKalle Valo } 423*d3466830SKalle Valo 424*d3466830SKalle Valo p54spi_int_ack(priv, SPI_HOST_INT_WR_READY); 425*d3466830SKalle Valo 426*d3466830SKalle Valo if (FREE_AFTER_TX(skb)) 427*d3466830SKalle Valo p54_free_skb(priv->hw, skb); 428*d3466830SKalle Valo out: 429*d3466830SKalle Valo p54spi_sleep(priv); 430*d3466830SKalle Valo return ret; 431*d3466830SKalle Valo } 432*d3466830SKalle Valo 433*d3466830SKalle Valo static int p54spi_wq_tx(struct p54s_priv *priv) 434*d3466830SKalle Valo { 435*d3466830SKalle Valo struct p54s_tx_info *entry; 436*d3466830SKalle Valo struct sk_buff *skb; 437*d3466830SKalle Valo struct ieee80211_tx_info *info; 438*d3466830SKalle Valo struct p54_tx_info *minfo; 439*d3466830SKalle Valo struct p54s_tx_info *dinfo; 440*d3466830SKalle Valo unsigned long flags; 441*d3466830SKalle Valo int ret = 0; 442*d3466830SKalle Valo 443*d3466830SKalle Valo spin_lock_irqsave(&priv->tx_lock, flags); 444*d3466830SKalle Valo 445*d3466830SKalle Valo while (!list_empty(&priv->tx_pending)) { 446*d3466830SKalle Valo entry = list_entry(priv->tx_pending.next, 447*d3466830SKalle Valo struct p54s_tx_info, tx_list); 448*d3466830SKalle Valo 449*d3466830SKalle Valo list_del_init(&entry->tx_list); 450*d3466830SKalle Valo 451*d3466830SKalle Valo spin_unlock_irqrestore(&priv->tx_lock, flags); 452*d3466830SKalle Valo 453*d3466830SKalle Valo dinfo = container_of((void *) entry, struct p54s_tx_info, 454*d3466830SKalle Valo tx_list); 455*d3466830SKalle Valo minfo = container_of((void *) dinfo, struct p54_tx_info, 456*d3466830SKalle Valo data); 457*d3466830SKalle Valo info = container_of((void *) minfo, struct ieee80211_tx_info, 458*d3466830SKalle Valo rate_driver_data); 459*d3466830SKalle Valo skb = container_of((void *) info, struct sk_buff, cb); 460*d3466830SKalle Valo 461*d3466830SKalle Valo ret = p54spi_tx_frame(priv, skb); 462*d3466830SKalle Valo 463*d3466830SKalle Valo if (ret < 0) { 464*d3466830SKalle Valo p54_free_skb(priv->hw, skb); 465*d3466830SKalle Valo return ret; 466*d3466830SKalle Valo } 467*d3466830SKalle Valo 468*d3466830SKalle Valo spin_lock_irqsave(&priv->tx_lock, flags); 469*d3466830SKalle Valo } 470*d3466830SKalle Valo spin_unlock_irqrestore(&priv->tx_lock, flags); 471*d3466830SKalle Valo return ret; 472*d3466830SKalle Valo } 473*d3466830SKalle Valo 474*d3466830SKalle Valo static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb) 475*d3466830SKalle Valo { 476*d3466830SKalle Valo struct p54s_priv *priv = dev->priv; 477*d3466830SKalle Valo struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 478*d3466830SKalle Valo struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data; 479*d3466830SKalle Valo struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data; 480*d3466830SKalle Valo unsigned long flags; 481*d3466830SKalle Valo 482*d3466830SKalle Valo BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data))); 483*d3466830SKalle Valo 484*d3466830SKalle Valo spin_lock_irqsave(&priv->tx_lock, flags); 485*d3466830SKalle Valo list_add_tail(&di->tx_list, &priv->tx_pending); 486*d3466830SKalle Valo spin_unlock_irqrestore(&priv->tx_lock, flags); 487*d3466830SKalle Valo 488*d3466830SKalle Valo ieee80211_queue_work(priv->hw, &priv->work); 489*d3466830SKalle Valo } 490*d3466830SKalle Valo 491*d3466830SKalle Valo static void p54spi_work(struct work_struct *work) 492*d3466830SKalle Valo { 493*d3466830SKalle Valo struct p54s_priv *priv = container_of(work, struct p54s_priv, work); 494*d3466830SKalle Valo u32 ints; 495*d3466830SKalle Valo int ret; 496*d3466830SKalle Valo 497*d3466830SKalle Valo mutex_lock(&priv->mutex); 498*d3466830SKalle Valo 499*d3466830SKalle Valo if (priv->fw_state == FW_STATE_OFF) 500*d3466830SKalle Valo goto out; 501*d3466830SKalle Valo 502*d3466830SKalle Valo ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); 503*d3466830SKalle Valo 504*d3466830SKalle Valo if (ints & SPI_HOST_INT_READY) { 505*d3466830SKalle Valo p54spi_int_ready(priv); 506*d3466830SKalle Valo p54spi_int_ack(priv, SPI_HOST_INT_READY); 507*d3466830SKalle Valo } 508*d3466830SKalle Valo 509*d3466830SKalle Valo if (priv->fw_state != FW_STATE_READY) 510*d3466830SKalle Valo goto out; 511*d3466830SKalle Valo 512*d3466830SKalle Valo if (ints & SPI_HOST_INT_UPDATE) { 513*d3466830SKalle Valo p54spi_int_ack(priv, SPI_HOST_INT_UPDATE); 514*d3466830SKalle Valo ret = p54spi_rx(priv); 515*d3466830SKalle Valo if (ret < 0) 516*d3466830SKalle Valo goto out; 517*d3466830SKalle Valo } 518*d3466830SKalle Valo if (ints & SPI_HOST_INT_SW_UPDATE) { 519*d3466830SKalle Valo p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE); 520*d3466830SKalle Valo ret = p54spi_rx(priv); 521*d3466830SKalle Valo if (ret < 0) 522*d3466830SKalle Valo goto out; 523*d3466830SKalle Valo } 524*d3466830SKalle Valo 525*d3466830SKalle Valo ret = p54spi_wq_tx(priv); 526*d3466830SKalle Valo out: 527*d3466830SKalle Valo mutex_unlock(&priv->mutex); 528*d3466830SKalle Valo } 529*d3466830SKalle Valo 530*d3466830SKalle Valo static int p54spi_op_start(struct ieee80211_hw *dev) 531*d3466830SKalle Valo { 532*d3466830SKalle Valo struct p54s_priv *priv = dev->priv; 533*d3466830SKalle Valo unsigned long timeout; 534*d3466830SKalle Valo int ret = 0; 535*d3466830SKalle Valo 536*d3466830SKalle Valo if (mutex_lock_interruptible(&priv->mutex)) { 537*d3466830SKalle Valo ret = -EINTR; 538*d3466830SKalle Valo goto out; 539*d3466830SKalle Valo } 540*d3466830SKalle Valo 541*d3466830SKalle Valo priv->fw_state = FW_STATE_BOOTING; 542*d3466830SKalle Valo 543*d3466830SKalle Valo p54spi_power_on(priv); 544*d3466830SKalle Valo 545*d3466830SKalle Valo ret = p54spi_upload_firmware(dev); 546*d3466830SKalle Valo if (ret < 0) { 547*d3466830SKalle Valo p54spi_power_off(priv); 548*d3466830SKalle Valo goto out_unlock; 549*d3466830SKalle Valo } 550*d3466830SKalle Valo 551*d3466830SKalle Valo mutex_unlock(&priv->mutex); 552*d3466830SKalle Valo 553*d3466830SKalle Valo timeout = msecs_to_jiffies(2000); 554*d3466830SKalle Valo timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp, 555*d3466830SKalle Valo timeout); 556*d3466830SKalle Valo if (!timeout) { 557*d3466830SKalle Valo dev_err(&priv->spi->dev, "firmware boot failed"); 558*d3466830SKalle Valo p54spi_power_off(priv); 559*d3466830SKalle Valo ret = -1; 560*d3466830SKalle Valo goto out; 561*d3466830SKalle Valo } 562*d3466830SKalle Valo 563*d3466830SKalle Valo if (mutex_lock_interruptible(&priv->mutex)) { 564*d3466830SKalle Valo ret = -EINTR; 565*d3466830SKalle Valo p54spi_power_off(priv); 566*d3466830SKalle Valo goto out; 567*d3466830SKalle Valo } 568*d3466830SKalle Valo 569*d3466830SKalle Valo WARN_ON(priv->fw_state != FW_STATE_READY); 570*d3466830SKalle Valo 571*d3466830SKalle Valo out_unlock: 572*d3466830SKalle Valo mutex_unlock(&priv->mutex); 573*d3466830SKalle Valo 574*d3466830SKalle Valo out: 575*d3466830SKalle Valo return ret; 576*d3466830SKalle Valo } 577*d3466830SKalle Valo 578*d3466830SKalle Valo static void p54spi_op_stop(struct ieee80211_hw *dev) 579*d3466830SKalle Valo { 580*d3466830SKalle Valo struct p54s_priv *priv = dev->priv; 581*d3466830SKalle Valo unsigned long flags; 582*d3466830SKalle Valo 583*d3466830SKalle Valo mutex_lock(&priv->mutex); 584*d3466830SKalle Valo WARN_ON(priv->fw_state != FW_STATE_READY); 585*d3466830SKalle Valo 586*d3466830SKalle Valo p54spi_power_off(priv); 587*d3466830SKalle Valo spin_lock_irqsave(&priv->tx_lock, flags); 588*d3466830SKalle Valo INIT_LIST_HEAD(&priv->tx_pending); 589*d3466830SKalle Valo spin_unlock_irqrestore(&priv->tx_lock, flags); 590*d3466830SKalle Valo 591*d3466830SKalle Valo priv->fw_state = FW_STATE_OFF; 592*d3466830SKalle Valo mutex_unlock(&priv->mutex); 593*d3466830SKalle Valo 594*d3466830SKalle Valo cancel_work_sync(&priv->work); 595*d3466830SKalle Valo } 596*d3466830SKalle Valo 597*d3466830SKalle Valo static int p54spi_probe(struct spi_device *spi) 598*d3466830SKalle Valo { 599*d3466830SKalle Valo struct p54s_priv *priv = NULL; 600*d3466830SKalle Valo struct ieee80211_hw *hw; 601*d3466830SKalle Valo int ret = -EINVAL; 602*d3466830SKalle Valo 603*d3466830SKalle Valo hw = p54_init_common(sizeof(*priv)); 604*d3466830SKalle Valo if (!hw) { 605*d3466830SKalle Valo dev_err(&spi->dev, "could not alloc ieee80211_hw"); 606*d3466830SKalle Valo return -ENOMEM; 607*d3466830SKalle Valo } 608*d3466830SKalle Valo 609*d3466830SKalle Valo priv = hw->priv; 610*d3466830SKalle Valo priv->hw = hw; 611*d3466830SKalle Valo spi_set_drvdata(spi, priv); 612*d3466830SKalle Valo priv->spi = spi; 613*d3466830SKalle Valo 614*d3466830SKalle Valo spi->bits_per_word = 16; 615*d3466830SKalle Valo spi->max_speed_hz = 24000000; 616*d3466830SKalle Valo 617*d3466830SKalle Valo ret = spi_setup(spi); 618*d3466830SKalle Valo if (ret < 0) { 619*d3466830SKalle Valo dev_err(&priv->spi->dev, "spi_setup failed"); 620*d3466830SKalle Valo goto err_free; 621*d3466830SKalle Valo } 622*d3466830SKalle Valo 623*d3466830SKalle Valo ret = gpio_request(p54spi_gpio_power, "p54spi power"); 624*d3466830SKalle Valo if (ret < 0) { 625*d3466830SKalle Valo dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret); 626*d3466830SKalle Valo goto err_free; 627*d3466830SKalle Valo } 628*d3466830SKalle Valo 629*d3466830SKalle Valo ret = gpio_request(p54spi_gpio_irq, "p54spi irq"); 630*d3466830SKalle Valo if (ret < 0) { 631*d3466830SKalle Valo dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret); 632*d3466830SKalle Valo goto err_free_gpio_power; 633*d3466830SKalle Valo } 634*d3466830SKalle Valo 635*d3466830SKalle Valo gpio_direction_output(p54spi_gpio_power, 0); 636*d3466830SKalle Valo gpio_direction_input(p54spi_gpio_irq); 637*d3466830SKalle Valo 638*d3466830SKalle Valo ret = request_irq(gpio_to_irq(p54spi_gpio_irq), 639*d3466830SKalle Valo p54spi_interrupt, 0, "p54spi", 640*d3466830SKalle Valo priv->spi); 641*d3466830SKalle Valo if (ret < 0) { 642*d3466830SKalle Valo dev_err(&priv->spi->dev, "request_irq() failed"); 643*d3466830SKalle Valo goto err_free_gpio_irq; 644*d3466830SKalle Valo } 645*d3466830SKalle Valo 646*d3466830SKalle Valo irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING); 647*d3466830SKalle Valo 648*d3466830SKalle Valo disable_irq(gpio_to_irq(p54spi_gpio_irq)); 649*d3466830SKalle Valo 650*d3466830SKalle Valo INIT_WORK(&priv->work, p54spi_work); 651*d3466830SKalle Valo init_completion(&priv->fw_comp); 652*d3466830SKalle Valo INIT_LIST_HEAD(&priv->tx_pending); 653*d3466830SKalle Valo mutex_init(&priv->mutex); 654*d3466830SKalle Valo spin_lock_init(&priv->tx_lock); 655*d3466830SKalle Valo SET_IEEE80211_DEV(hw, &spi->dev); 656*d3466830SKalle Valo priv->common.open = p54spi_op_start; 657*d3466830SKalle Valo priv->common.stop = p54spi_op_stop; 658*d3466830SKalle Valo priv->common.tx = p54spi_op_tx; 659*d3466830SKalle Valo 660*d3466830SKalle Valo ret = p54spi_request_firmware(hw); 661*d3466830SKalle Valo if (ret < 0) 662*d3466830SKalle Valo goto err_free_common; 663*d3466830SKalle Valo 664*d3466830SKalle Valo ret = p54spi_request_eeprom(hw); 665*d3466830SKalle Valo if (ret) 666*d3466830SKalle Valo goto err_free_common; 667*d3466830SKalle Valo 668*d3466830SKalle Valo ret = p54_register_common(hw, &priv->spi->dev); 669*d3466830SKalle Valo if (ret) 670*d3466830SKalle Valo goto err_free_common; 671*d3466830SKalle Valo 672*d3466830SKalle Valo return 0; 673*d3466830SKalle Valo 674*d3466830SKalle Valo err_free_common: 675*d3466830SKalle Valo free_irq(gpio_to_irq(p54spi_gpio_irq), spi); 676*d3466830SKalle Valo err_free_gpio_irq: 677*d3466830SKalle Valo gpio_free(p54spi_gpio_irq); 678*d3466830SKalle Valo err_free_gpio_power: 679*d3466830SKalle Valo gpio_free(p54spi_gpio_power); 680*d3466830SKalle Valo err_free: 681*d3466830SKalle Valo p54_free_common(priv->hw); 682*d3466830SKalle Valo return ret; 683*d3466830SKalle Valo } 684*d3466830SKalle Valo 685*d3466830SKalle Valo static int p54spi_remove(struct spi_device *spi) 686*d3466830SKalle Valo { 687*d3466830SKalle Valo struct p54s_priv *priv = spi_get_drvdata(spi); 688*d3466830SKalle Valo 689*d3466830SKalle Valo p54_unregister_common(priv->hw); 690*d3466830SKalle Valo 691*d3466830SKalle Valo free_irq(gpio_to_irq(p54spi_gpio_irq), spi); 692*d3466830SKalle Valo 693*d3466830SKalle Valo gpio_free(p54spi_gpio_power); 694*d3466830SKalle Valo gpio_free(p54spi_gpio_irq); 695*d3466830SKalle Valo release_firmware(priv->firmware); 696*d3466830SKalle Valo 697*d3466830SKalle Valo mutex_destroy(&priv->mutex); 698*d3466830SKalle Valo 699*d3466830SKalle Valo p54_free_common(priv->hw); 700*d3466830SKalle Valo 701*d3466830SKalle Valo return 0; 702*d3466830SKalle Valo } 703*d3466830SKalle Valo 704*d3466830SKalle Valo 705*d3466830SKalle Valo static struct spi_driver p54spi_driver = { 706*d3466830SKalle Valo .driver = { 707*d3466830SKalle Valo .name = "p54spi", 708*d3466830SKalle Valo }, 709*d3466830SKalle Valo 710*d3466830SKalle Valo .probe = p54spi_probe, 711*d3466830SKalle Valo .remove = p54spi_remove, 712*d3466830SKalle Valo }; 713*d3466830SKalle Valo 714*d3466830SKalle Valo module_spi_driver(p54spi_driver); 715*d3466830SKalle Valo 716*d3466830SKalle Valo MODULE_LICENSE("GPL"); 717*d3466830SKalle Valo MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>"); 718*d3466830SKalle Valo MODULE_ALIAS("spi:cx3110x"); 719*d3466830SKalle Valo MODULE_ALIAS("spi:p54spi"); 720*d3466830SKalle Valo MODULE_ALIAS("spi:stlc45xx"); 721