1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/pci.h> 65 #include <linux/interrupt.h> 66 #include <linux/debugfs.h> 67 #include <linux/sched.h> 68 #include <linux/bitops.h> 69 #include <linux/gfp.h> 70 #include <linux/vmalloc.h> 71 #include <linux/module.h> 72 #include <linux/wait.h> 73 #include <linux/seq_file.h> 74 75 #include "iwl-drv.h" 76 #include "iwl-trans.h" 77 #include "iwl-csr.h" 78 #include "iwl-prph.h" 79 #include "iwl-scd.h" 80 #include "iwl-agn-hw.h" 81 #include "fw/error-dump.h" 82 #include "fw/dbg.h" 83 #include "fw/api/tx.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92 { 93 #define PCI_DUMP_SIZE 352 94 #define PCI_MEM_DUMP_SIZE 64 95 #define PCI_PARENT_DUMP_SIZE 524 96 #define PREFIX_LEN 32 97 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 98 struct pci_dev *pdev = trans_pcie->pci_dev; 99 u32 i, pos, alloc_size, *ptr, *buf; 100 char *prefix; 101 102 if (trans_pcie->pcie_dbg_dumped_once) 103 return; 104 105 /* Should be a multiple of 4 */ 106 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 107 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 108 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 109 110 /* Alloc a max size buffer */ 111 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 112 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 113 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 114 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 115 116 buf = kmalloc(alloc_size, GFP_ATOMIC); 117 if (!buf) 118 return; 119 prefix = (char *)buf + alloc_size - PREFIX_LEN; 120 121 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 122 123 /* Print wifi device registers */ 124 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 125 IWL_ERR(trans, "iwlwifi device config registers:\n"); 126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127 if (pci_read_config_dword(pdev, i, ptr)) 128 goto err_read; 129 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 130 131 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 132 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 133 *ptr = iwl_read32(trans, i); 134 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 135 136 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 137 if (pos) { 138 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 139 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 140 if (pci_read_config_dword(pdev, pos + i, ptr)) 141 goto err_read; 142 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 143 32, 4, buf, i, 0); 144 } 145 146 /* Print parent device registers next */ 147 if (!pdev->bus->self) 148 goto out; 149 150 pdev = pdev->bus->self; 151 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 152 153 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 154 pci_name(pdev)); 155 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 156 if (pci_read_config_dword(pdev, i, ptr)) 157 goto err_read; 158 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 159 160 /* Print root port AER registers */ 161 pos = 0; 162 pdev = pcie_find_root_port(pdev); 163 if (pdev) 164 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 165 if (pos) { 166 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 167 pci_name(pdev)); 168 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 169 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 170 if (pci_read_config_dword(pdev, pos + i, ptr)) 171 goto err_read; 172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 173 4, buf, i, 0); 174 } 175 goto out; 176 177 err_read: 178 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 179 IWL_ERR(trans, "Read failed at 0x%X\n", i); 180 out: 181 trans_pcie->pcie_dbg_dumped_once = 1; 182 kfree(buf); 183 } 184 185 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 186 { 187 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 188 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 189 usleep_range(5000, 6000); 190 } 191 192 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 193 { 194 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 195 196 if (!fw_mon->size) 197 return; 198 199 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 200 fw_mon->physical); 201 202 fw_mon->block = NULL; 203 fw_mon->physical = 0; 204 fw_mon->size = 0; 205 } 206 207 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 208 u8 max_power, u8 min_power) 209 { 210 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 211 void *block = NULL; 212 dma_addr_t physical = 0; 213 u32 size = 0; 214 u8 power; 215 216 if (fw_mon->size) 217 return; 218 219 for (power = max_power; power >= min_power; power--) { 220 size = BIT(power); 221 block = dma_alloc_coherent(trans->dev, size, &physical, 222 GFP_KERNEL | __GFP_NOWARN); 223 if (!block) 224 continue; 225 226 IWL_INFO(trans, 227 "Allocated 0x%08x bytes for firmware monitor.\n", 228 size); 229 break; 230 } 231 232 if (WARN_ON_ONCE(!block)) 233 return; 234 235 if (power != max_power) 236 IWL_ERR(trans, 237 "Sorry - debug buffer is only %luK while you requested %luK\n", 238 (unsigned long)BIT(power - 10), 239 (unsigned long)BIT(max_power - 10)); 240 241 fw_mon->block = block; 242 fw_mon->physical = physical; 243 fw_mon->size = size; 244 } 245 246 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 247 { 248 if (!max_power) { 249 /* default max_power is maximum */ 250 max_power = 26; 251 } else { 252 max_power += 11; 253 } 254 255 if (WARN(max_power > 26, 256 "External buffer size for monitor is too big %d, check the FW TLV\n", 257 max_power)) 258 return; 259 260 if (trans->dbg.fw_mon.size) 261 return; 262 263 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 264 } 265 266 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 267 { 268 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 269 ((reg & 0x0000ffff) | (2 << 28))); 270 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 271 } 272 273 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 274 { 275 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 276 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 277 ((reg & 0x0000ffff) | (3 << 28))); 278 } 279 280 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 281 { 282 if (trans->cfg->apmg_not_supported) 283 return; 284 285 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 286 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 287 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 288 ~APMG_PS_CTRL_MSK_PWR_SRC); 289 else 290 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 291 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 292 ~APMG_PS_CTRL_MSK_PWR_SRC); 293 } 294 295 /* PCI registers */ 296 #define PCI_CFG_RETRY_TIMEOUT 0x041 297 298 void iwl_pcie_apm_config(struct iwl_trans *trans) 299 { 300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 301 u16 lctl; 302 u16 cap; 303 304 /* 305 * L0S states have been found to be unstable with our devices 306 * and in newer hardware they are not officially supported at 307 * all, so we must always set the L0S_DISABLED bit. 308 */ 309 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 310 311 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 312 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 313 314 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 315 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 316 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 317 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 318 trans->ltr_enabled ? "En" : "Dis"); 319 } 320 321 /* 322 * Start up NIC's basic functionality after it has been reset 323 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 324 * NOTE: This does not load uCode nor start the embedded processor 325 */ 326 static int iwl_pcie_apm_init(struct iwl_trans *trans) 327 { 328 int ret; 329 330 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 331 332 /* 333 * Use "set_bit" below rather than "write", to preserve any hardware 334 * bits already set by default after reset. 335 */ 336 337 /* Disable L0S exit timer (platform NMI Work/Around) */ 338 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 339 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 340 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 341 342 /* 343 * Disable L0s without affecting L1; 344 * don't wait for ICH L0s (ICH bug W/A) 345 */ 346 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 347 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 348 349 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 350 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 351 352 /* 353 * Enable HAP INTA (interrupt from management bus) to 354 * wake device's PCI Express link L1a -> L0s 355 */ 356 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 357 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 358 359 iwl_pcie_apm_config(trans); 360 361 /* Configure analog phase-lock-loop before activating to D0A */ 362 if (trans->trans_cfg->base_params->pll_cfg) 363 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 364 365 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 366 if (ret) 367 return ret; 368 369 if (trans->cfg->host_interrupt_operation_mode) { 370 /* 371 * This is a bit of an abuse - This is needed for 7260 / 3160 372 * only check host_interrupt_operation_mode even if this is 373 * not related to host_interrupt_operation_mode. 374 * 375 * Enable the oscillator to count wake up time for L1 exit. This 376 * consumes slightly more power (100uA) - but allows to be sure 377 * that we wake up from L1 on time. 378 * 379 * This looks weird: read twice the same register, discard the 380 * value, set a bit, and yet again, read that same register 381 * just to discard the value. But that's the way the hardware 382 * seems to like it. 383 */ 384 iwl_read_prph(trans, OSC_CLK); 385 iwl_read_prph(trans, OSC_CLK); 386 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 387 iwl_read_prph(trans, OSC_CLK); 388 iwl_read_prph(trans, OSC_CLK); 389 } 390 391 /* 392 * Enable DMA clock and wait for it to stabilize. 393 * 394 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 395 * bits do not disable clocks. This preserves any hardware 396 * bits already set by default in "CLK_CTRL_REG" after reset. 397 */ 398 if (!trans->cfg->apmg_not_supported) { 399 iwl_write_prph(trans, APMG_CLK_EN_REG, 400 APMG_CLK_VAL_DMA_CLK_RQT); 401 udelay(20); 402 403 /* Disable L1-Active */ 404 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 405 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 406 407 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 408 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 409 APMG_RTC_INT_STT_RFKILL); 410 } 411 412 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 413 414 return 0; 415 } 416 417 /* 418 * Enable LP XTAL to avoid HW bug where device may consume much power if 419 * FW is not loaded after device reset. LP XTAL is disabled by default 420 * after device HW reset. Do it only if XTAL is fed by internal source. 421 * Configure device's "persistence" mode to avoid resetting XTAL again when 422 * SHRD_HW_RST occurs in S3. 423 */ 424 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 425 { 426 int ret; 427 u32 apmg_gp1_reg; 428 u32 apmg_xtal_cfg_reg; 429 u32 dl_cfg_reg; 430 431 /* Force XTAL ON */ 432 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 433 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 434 435 iwl_trans_pcie_sw_reset(trans); 436 437 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 438 if (WARN_ON(ret)) { 439 /* Release XTAL ON request */ 440 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 441 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 442 return; 443 } 444 445 /* 446 * Clear "disable persistence" to avoid LP XTAL resetting when 447 * SHRD_HW_RST is applied in S3. 448 */ 449 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 450 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 451 452 /* 453 * Force APMG XTAL to be active to prevent its disabling by HW 454 * caused by APMG idle state. 455 */ 456 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 457 SHR_APMG_XTAL_CFG_REG); 458 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 459 apmg_xtal_cfg_reg | 460 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 461 462 iwl_trans_pcie_sw_reset(trans); 463 464 /* Enable LP XTAL by indirect access through CSR */ 465 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 466 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 467 SHR_APMG_GP1_WF_XTAL_LP_EN | 468 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 469 470 /* Clear delay line clock power up */ 471 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 472 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 473 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 474 475 /* 476 * Enable persistence mode to avoid LP XTAL resetting when 477 * SHRD_HW_RST is applied in S3. 478 */ 479 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 480 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 481 482 /* 483 * Clear "initialization complete" bit to move adapter from 484 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 485 */ 486 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 487 488 /* Activates XTAL resources monitor */ 489 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 490 CSR_MONITOR_XTAL_RESOURCES); 491 492 /* Release XTAL ON request */ 493 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 494 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 495 udelay(10); 496 497 /* Release APMG XTAL */ 498 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 499 apmg_xtal_cfg_reg & 500 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 501 } 502 503 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 504 { 505 int ret; 506 507 /* stop device's busmaster DMA activity */ 508 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 509 510 ret = iwl_poll_bit(trans, CSR_RESET, 511 CSR_RESET_REG_FLAG_MASTER_DISABLED, 512 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 513 if (ret < 0) 514 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 515 516 IWL_DEBUG_INFO(trans, "stop master\n"); 517 } 518 519 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 520 { 521 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 522 523 if (op_mode_leave) { 524 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 525 iwl_pcie_apm_init(trans); 526 527 /* inform ME that we are leaving */ 528 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 529 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 530 APMG_PCIDEV_STT_VAL_WAKE_ME); 531 else if (trans->trans_cfg->device_family >= 532 IWL_DEVICE_FAMILY_8000) { 533 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 534 CSR_RESET_LINK_PWR_MGMT_DISABLED); 535 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 536 CSR_HW_IF_CONFIG_REG_PREPARE | 537 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 538 mdelay(1); 539 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 540 CSR_RESET_LINK_PWR_MGMT_DISABLED); 541 } 542 mdelay(5); 543 } 544 545 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 546 547 /* Stop device's DMA activity */ 548 iwl_pcie_apm_stop_master(trans); 549 550 if (trans->cfg->lp_xtal_workaround) { 551 iwl_pcie_apm_lp_xtal_enable(trans); 552 return; 553 } 554 555 iwl_trans_pcie_sw_reset(trans); 556 557 /* 558 * Clear "initialization complete" bit to move adapter from 559 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 560 */ 561 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 562 } 563 564 static int iwl_pcie_nic_init(struct iwl_trans *trans) 565 { 566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 567 int ret; 568 569 /* nic_init */ 570 spin_lock(&trans_pcie->irq_lock); 571 ret = iwl_pcie_apm_init(trans); 572 spin_unlock(&trans_pcie->irq_lock); 573 574 if (ret) 575 return ret; 576 577 iwl_pcie_set_pwr(trans, false); 578 579 iwl_op_mode_nic_config(trans->op_mode); 580 581 /* Allocate the RX queue, or reset if it is already allocated */ 582 iwl_pcie_rx_init(trans); 583 584 /* Allocate or reset and init all Tx and Command queues */ 585 if (iwl_pcie_tx_init(trans)) 586 return -ENOMEM; 587 588 if (trans->trans_cfg->base_params->shadow_reg_enable) { 589 /* enable shadow regs in HW */ 590 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 591 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 592 } 593 594 return 0; 595 } 596 597 #define HW_READY_TIMEOUT (50) 598 599 /* Note: returns poll_bit return value, which is >= 0 if success */ 600 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 601 { 602 int ret; 603 604 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 605 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 606 607 /* See if we got it */ 608 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 609 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 610 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 611 HW_READY_TIMEOUT); 612 613 if (ret >= 0) 614 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 615 616 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 617 return ret; 618 } 619 620 /* Note: returns standard 0/-ERROR code */ 621 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 622 { 623 int ret; 624 int t = 0; 625 int iter; 626 627 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 628 629 ret = iwl_pcie_set_hw_ready(trans); 630 /* If the card is ready, exit 0 */ 631 if (ret >= 0) 632 return 0; 633 634 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 635 CSR_RESET_LINK_PWR_MGMT_DISABLED); 636 usleep_range(1000, 2000); 637 638 for (iter = 0; iter < 10; iter++) { 639 /* If HW is not ready, prepare the conditions to check again */ 640 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 641 CSR_HW_IF_CONFIG_REG_PREPARE); 642 643 do { 644 ret = iwl_pcie_set_hw_ready(trans); 645 if (ret >= 0) 646 return 0; 647 648 usleep_range(200, 1000); 649 t += 200; 650 } while (t < 150000); 651 msleep(25); 652 } 653 654 IWL_ERR(trans, "Couldn't prepare the card\n"); 655 656 return ret; 657 } 658 659 /* 660 * ucode 661 */ 662 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 663 u32 dst_addr, dma_addr_t phy_addr, 664 u32 byte_cnt) 665 { 666 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 667 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 668 669 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 670 dst_addr); 671 672 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 673 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 674 675 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 676 (iwl_get_dma_hi_addr(phy_addr) 677 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 678 679 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 680 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 681 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 682 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 683 684 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 685 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 686 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 687 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 688 } 689 690 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 691 u32 dst_addr, dma_addr_t phy_addr, 692 u32 byte_cnt) 693 { 694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 695 unsigned long flags; 696 int ret; 697 698 trans_pcie->ucode_write_complete = false; 699 700 if (!iwl_trans_grab_nic_access(trans, &flags)) 701 return -EIO; 702 703 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 704 byte_cnt); 705 iwl_trans_release_nic_access(trans, &flags); 706 707 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 708 trans_pcie->ucode_write_complete, 5 * HZ); 709 if (!ret) { 710 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 711 iwl_trans_pcie_dump_regs(trans); 712 return -ETIMEDOUT; 713 } 714 715 return 0; 716 } 717 718 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 719 const struct fw_desc *section) 720 { 721 u8 *v_addr; 722 dma_addr_t p_addr; 723 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 724 int ret = 0; 725 726 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 727 section_num); 728 729 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 730 GFP_KERNEL | __GFP_NOWARN); 731 if (!v_addr) { 732 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 733 chunk_sz = PAGE_SIZE; 734 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 735 &p_addr, GFP_KERNEL); 736 if (!v_addr) 737 return -ENOMEM; 738 } 739 740 for (offset = 0; offset < section->len; offset += chunk_sz) { 741 u32 copy_size, dst_addr; 742 bool extended_addr = false; 743 744 copy_size = min_t(u32, chunk_sz, section->len - offset); 745 dst_addr = section->offset + offset; 746 747 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 748 dst_addr <= IWL_FW_MEM_EXTENDED_END) 749 extended_addr = true; 750 751 if (extended_addr) 752 iwl_set_bits_prph(trans, LMPM_CHICK, 753 LMPM_CHICK_EXTENDED_ADDR_SPACE); 754 755 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 756 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 757 copy_size); 758 759 if (extended_addr) 760 iwl_clear_bits_prph(trans, LMPM_CHICK, 761 LMPM_CHICK_EXTENDED_ADDR_SPACE); 762 763 if (ret) { 764 IWL_ERR(trans, 765 "Could not load the [%d] uCode section\n", 766 section_num); 767 break; 768 } 769 } 770 771 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 772 return ret; 773 } 774 775 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 776 const struct fw_img *image, 777 int cpu, 778 int *first_ucode_section) 779 { 780 int shift_param; 781 int i, ret = 0, sec_num = 0x1; 782 u32 val, last_read_idx = 0; 783 784 if (cpu == 1) { 785 shift_param = 0; 786 *first_ucode_section = 0; 787 } else { 788 shift_param = 16; 789 (*first_ucode_section)++; 790 } 791 792 for (i = *first_ucode_section; i < image->num_sec; i++) { 793 last_read_idx = i; 794 795 /* 796 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 797 * CPU1 to CPU2. 798 * PAGING_SEPARATOR_SECTION delimiter - separate between 799 * CPU2 non paged to CPU2 paging sec. 800 */ 801 if (!image->sec[i].data || 802 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 803 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 804 IWL_DEBUG_FW(trans, 805 "Break since Data not valid or Empty section, sec = %d\n", 806 i); 807 break; 808 } 809 810 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 811 if (ret) 812 return ret; 813 814 /* Notify ucode of loaded section number and status */ 815 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 816 val = val | (sec_num << shift_param); 817 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 818 819 sec_num = (sec_num << 1) | 0x1; 820 } 821 822 *first_ucode_section = last_read_idx; 823 824 iwl_enable_interrupts(trans); 825 826 if (trans->trans_cfg->use_tfh) { 827 if (cpu == 1) 828 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 829 0xFFFF); 830 else 831 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 832 0xFFFFFFFF); 833 } else { 834 if (cpu == 1) 835 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 836 0xFFFF); 837 else 838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 839 0xFFFFFFFF); 840 } 841 842 return 0; 843 } 844 845 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 846 const struct fw_img *image, 847 int cpu, 848 int *first_ucode_section) 849 { 850 int i, ret = 0; 851 u32 last_read_idx = 0; 852 853 if (cpu == 1) 854 *first_ucode_section = 0; 855 else 856 (*first_ucode_section)++; 857 858 for (i = *first_ucode_section; i < image->num_sec; i++) { 859 last_read_idx = i; 860 861 /* 862 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 863 * CPU1 to CPU2. 864 * PAGING_SEPARATOR_SECTION delimiter - separate between 865 * CPU2 non paged to CPU2 paging sec. 866 */ 867 if (!image->sec[i].data || 868 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 869 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 870 IWL_DEBUG_FW(trans, 871 "Break since Data not valid or Empty section, sec = %d\n", 872 i); 873 break; 874 } 875 876 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 877 if (ret) 878 return ret; 879 } 880 881 *first_ucode_section = last_read_idx; 882 883 return 0; 884 } 885 886 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 887 { 888 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 889 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 890 &trans->dbg.fw_mon_cfg[alloc_id]; 891 struct iwl_dram_data *frag; 892 893 if (!iwl_trans_dbg_ini_valid(trans)) 894 return; 895 896 if (le32_to_cpu(fw_mon_cfg->buf_location) == 897 IWL_FW_INI_LOCATION_SRAM_PATH) { 898 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 899 /* set sram monitor by enabling bit 7 */ 900 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 901 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 902 903 return; 904 } 905 906 if (le32_to_cpu(fw_mon_cfg->buf_location) != 907 IWL_FW_INI_LOCATION_DRAM_PATH || 908 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 909 return; 910 911 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 912 913 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 914 alloc_id); 915 916 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 917 frag->physical >> MON_BUFF_SHIFT_VER2); 918 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 919 (frag->physical + frag->size - 256) >> 920 MON_BUFF_SHIFT_VER2); 921 } 922 923 void iwl_pcie_apply_destination(struct iwl_trans *trans) 924 { 925 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 926 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 927 int i; 928 929 if (iwl_trans_dbg_ini_valid(trans)) { 930 iwl_pcie_apply_destination_ini(trans); 931 return; 932 } 933 934 IWL_INFO(trans, "Applying debug destination %s\n", 935 get_fw_dbg_mode_string(dest->monitor_mode)); 936 937 if (dest->monitor_mode == EXTERNAL_MODE) 938 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 939 else 940 IWL_WARN(trans, "PCI should have external buffer debug\n"); 941 942 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 943 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 944 u32 val = le32_to_cpu(dest->reg_ops[i].val); 945 946 switch (dest->reg_ops[i].op) { 947 case CSR_ASSIGN: 948 iwl_write32(trans, addr, val); 949 break; 950 case CSR_SETBIT: 951 iwl_set_bit(trans, addr, BIT(val)); 952 break; 953 case CSR_CLEARBIT: 954 iwl_clear_bit(trans, addr, BIT(val)); 955 break; 956 case PRPH_ASSIGN: 957 iwl_write_prph(trans, addr, val); 958 break; 959 case PRPH_SETBIT: 960 iwl_set_bits_prph(trans, addr, BIT(val)); 961 break; 962 case PRPH_CLEARBIT: 963 iwl_clear_bits_prph(trans, addr, BIT(val)); 964 break; 965 case PRPH_BLOCKBIT: 966 if (iwl_read_prph(trans, addr) & BIT(val)) { 967 IWL_ERR(trans, 968 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 969 val, addr); 970 goto monitor; 971 } 972 break; 973 default: 974 IWL_ERR(trans, "FW debug - unknown OP %d\n", 975 dest->reg_ops[i].op); 976 break; 977 } 978 } 979 980 monitor: 981 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 982 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 983 fw_mon->physical >> dest->base_shift); 984 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 986 (fw_mon->physical + fw_mon->size - 987 256) >> dest->end_shift); 988 else 989 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 990 (fw_mon->physical + fw_mon->size) >> 991 dest->end_shift); 992 } 993 } 994 995 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 996 const struct fw_img *image) 997 { 998 int ret = 0; 999 int first_ucode_section; 1000 1001 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1002 image->is_dual_cpus ? "Dual" : "Single"); 1003 1004 /* load to FW the binary non secured sections of CPU1 */ 1005 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1006 if (ret) 1007 return ret; 1008 1009 if (image->is_dual_cpus) { 1010 /* set CPU2 header address */ 1011 iwl_write_prph(trans, 1012 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1013 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1014 1015 /* load to FW the binary sections of CPU2 */ 1016 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1017 &first_ucode_section); 1018 if (ret) 1019 return ret; 1020 } 1021 1022 if (iwl_pcie_dbg_on(trans)) 1023 iwl_pcie_apply_destination(trans); 1024 1025 iwl_enable_interrupts(trans); 1026 1027 /* release CPU reset */ 1028 iwl_write32(trans, CSR_RESET, 0); 1029 1030 return 0; 1031 } 1032 1033 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1034 const struct fw_img *image) 1035 { 1036 int ret = 0; 1037 int first_ucode_section; 1038 1039 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1040 image->is_dual_cpus ? "Dual" : "Single"); 1041 1042 if (iwl_pcie_dbg_on(trans)) 1043 iwl_pcie_apply_destination(trans); 1044 1045 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1046 iwl_read_prph(trans, WFPM_GP2)); 1047 1048 /* 1049 * Set default value. On resume reading the values that were 1050 * zeored can provide debug data on the resume flow. 1051 * This is for debugging only and has no functional impact. 1052 */ 1053 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1054 1055 /* configure the ucode to be ready to get the secured image */ 1056 /* release CPU reset */ 1057 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1058 1059 /* load to FW the binary Secured sections of CPU1 */ 1060 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1061 &first_ucode_section); 1062 if (ret) 1063 return ret; 1064 1065 /* load to FW the binary sections of CPU2 */ 1066 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1067 &first_ucode_section); 1068 } 1069 1070 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1071 { 1072 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1073 bool hw_rfkill = iwl_is_rfkill_set(trans); 1074 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1075 bool report; 1076 1077 if (hw_rfkill) { 1078 set_bit(STATUS_RFKILL_HW, &trans->status); 1079 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1080 } else { 1081 clear_bit(STATUS_RFKILL_HW, &trans->status); 1082 if (trans_pcie->opmode_down) 1083 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1084 } 1085 1086 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1087 1088 if (prev != report) 1089 iwl_trans_pcie_rf_kill(trans, report); 1090 1091 return hw_rfkill; 1092 } 1093 1094 struct iwl_causes_list { 1095 u32 cause_num; 1096 u32 mask_reg; 1097 u8 addr; 1098 }; 1099 1100 static struct iwl_causes_list causes_list[] = { 1101 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1102 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1103 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1104 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1105 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1106 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1107 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 1108 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1109 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1110 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1111 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1112 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1113 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1114 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1115 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1116 }; 1117 1118 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1119 { 1120 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1121 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1122 int i, arr_size = ARRAY_SIZE(causes_list); 1123 struct iwl_causes_list *causes = causes_list; 1124 1125 /* 1126 * Access all non RX causes and map them to the default irq. 1127 * In case we are missing at least one interrupt vector, 1128 * the first interrupt vector will serve non-RX and FBQ causes. 1129 */ 1130 for (i = 0; i < arr_size; i++) { 1131 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1132 iwl_clear_bit(trans, causes[i].mask_reg, 1133 causes[i].cause_num); 1134 } 1135 } 1136 1137 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1138 { 1139 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1140 u32 offset = 1141 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1142 u32 val, idx; 1143 1144 /* 1145 * The first RX queue - fallback queue, which is designated for 1146 * management frame, command responses etc, is always mapped to the 1147 * first interrupt vector. The other RX queues are mapped to 1148 * the other (N - 2) interrupt vectors. 1149 */ 1150 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1151 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1152 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1153 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1154 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1155 } 1156 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1157 1158 val = MSIX_FH_INT_CAUSES_Q(0); 1159 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1160 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1161 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1162 1163 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1164 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1165 } 1166 1167 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1168 { 1169 struct iwl_trans *trans = trans_pcie->trans; 1170 1171 if (!trans_pcie->msix_enabled) { 1172 if (trans->trans_cfg->mq_rx_supported && 1173 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1174 iwl_write_umac_prph(trans, UREG_CHICK, 1175 UREG_CHICK_MSI_ENABLE); 1176 return; 1177 } 1178 /* 1179 * The IVAR table needs to be configured again after reset, 1180 * but if the device is disabled, we can't write to 1181 * prph. 1182 */ 1183 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1184 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1185 1186 /* 1187 * Each cause from the causes list above and the RX causes is 1188 * represented as a byte in the IVAR table. The first nibble 1189 * represents the bound interrupt vector of the cause, the second 1190 * represents no auto clear for this cause. This will be set if its 1191 * interrupt vector is bound to serve other causes. 1192 */ 1193 iwl_pcie_map_rx_causes(trans); 1194 1195 iwl_pcie_map_non_rx_causes(trans); 1196 } 1197 1198 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1199 { 1200 struct iwl_trans *trans = trans_pcie->trans; 1201 1202 iwl_pcie_conf_msix_hw(trans_pcie); 1203 1204 if (!trans_pcie->msix_enabled) 1205 return; 1206 1207 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1208 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1209 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1210 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1211 } 1212 1213 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1214 { 1215 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1216 1217 lockdep_assert_held(&trans_pcie->mutex); 1218 1219 if (trans_pcie->is_down) 1220 return; 1221 1222 trans_pcie->is_down = true; 1223 1224 /* tell the device to stop sending interrupts */ 1225 iwl_disable_interrupts(trans); 1226 1227 /* device going down, Stop using ICT table */ 1228 iwl_pcie_disable_ict(trans); 1229 1230 /* 1231 * If a HW restart happens during firmware loading, 1232 * then the firmware loading might call this function 1233 * and later it might be called again due to the 1234 * restart. So don't process again if the device is 1235 * already dead. 1236 */ 1237 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1238 IWL_DEBUG_INFO(trans, 1239 "DEVICE_ENABLED bit was set and is now cleared\n"); 1240 iwl_pcie_tx_stop(trans); 1241 iwl_pcie_rx_stop(trans); 1242 1243 /* Power-down device's busmaster DMA clocks */ 1244 if (!trans->cfg->apmg_not_supported) { 1245 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1246 APMG_CLK_VAL_DMA_CLK_RQT); 1247 udelay(5); 1248 } 1249 } 1250 1251 /* Make sure (redundant) we've released our request to stay awake */ 1252 iwl_clear_bit(trans, CSR_GP_CNTRL, 1253 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1254 1255 /* Stop the device, and put it in low power state */ 1256 iwl_pcie_apm_stop(trans, false); 1257 1258 iwl_trans_pcie_sw_reset(trans); 1259 1260 /* 1261 * Upon stop, the IVAR table gets erased, so msi-x won't 1262 * work. This causes a bug in RF-KILL flows, since the interrupt 1263 * that enables radio won't fire on the correct irq, and the 1264 * driver won't be able to handle the interrupt. 1265 * Configure the IVAR table again after reset. 1266 */ 1267 iwl_pcie_conf_msix_hw(trans_pcie); 1268 1269 /* 1270 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1271 * This is a bug in certain verions of the hardware. 1272 * Certain devices also keep sending HW RF kill interrupt all 1273 * the time, unless the interrupt is ACKed even if the interrupt 1274 * should be masked. Re-ACK all the interrupts here. 1275 */ 1276 iwl_disable_interrupts(trans); 1277 1278 /* clear all status bits */ 1279 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1280 clear_bit(STATUS_INT_ENABLED, &trans->status); 1281 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1282 1283 /* 1284 * Even if we stop the HW, we still want the RF kill 1285 * interrupt 1286 */ 1287 iwl_enable_rfkill_int(trans); 1288 1289 /* re-take ownership to prevent other users from stealing the device */ 1290 iwl_pcie_prepare_card_hw(trans); 1291 } 1292 1293 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1294 { 1295 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1296 1297 if (trans_pcie->msix_enabled) { 1298 int i; 1299 1300 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1301 synchronize_irq(trans_pcie->msix_entries[i].vector); 1302 } else { 1303 synchronize_irq(trans_pcie->pci_dev->irq); 1304 } 1305 } 1306 1307 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1308 const struct fw_img *fw, bool run_in_rfkill) 1309 { 1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1311 bool hw_rfkill; 1312 int ret; 1313 1314 /* This may fail if AMT took ownership of the device */ 1315 if (iwl_pcie_prepare_card_hw(trans)) { 1316 IWL_WARN(trans, "Exit HW not ready\n"); 1317 ret = -EIO; 1318 goto out; 1319 } 1320 1321 iwl_enable_rfkill_int(trans); 1322 1323 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1324 1325 /* 1326 * We enabled the RF-Kill interrupt and the handler may very 1327 * well be running. Disable the interrupts to make sure no other 1328 * interrupt can be fired. 1329 */ 1330 iwl_disable_interrupts(trans); 1331 1332 /* Make sure it finished running */ 1333 iwl_pcie_synchronize_irqs(trans); 1334 1335 mutex_lock(&trans_pcie->mutex); 1336 1337 /* If platform's RF_KILL switch is NOT set to KILL */ 1338 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1339 if (hw_rfkill && !run_in_rfkill) { 1340 ret = -ERFKILL; 1341 goto out; 1342 } 1343 1344 /* Someone called stop_device, don't try to start_fw */ 1345 if (trans_pcie->is_down) { 1346 IWL_WARN(trans, 1347 "Can't start_fw since the HW hasn't been started\n"); 1348 ret = -EIO; 1349 goto out; 1350 } 1351 1352 /* make sure rfkill handshake bits are cleared */ 1353 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1354 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1355 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1356 1357 /* clear (again), then enable host interrupts */ 1358 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1359 1360 ret = iwl_pcie_nic_init(trans); 1361 if (ret) { 1362 IWL_ERR(trans, "Unable to init nic\n"); 1363 goto out; 1364 } 1365 1366 /* 1367 * Now, we load the firmware and don't want to be interrupted, even 1368 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1369 * FH_TX interrupt which is needed to load the firmware). If the 1370 * RF-Kill switch is toggled, we will find out after having loaded 1371 * the firmware and return the proper value to the caller. 1372 */ 1373 iwl_enable_fw_load_int(trans); 1374 1375 /* really make sure rfkill handshake bits are cleared */ 1376 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1377 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1378 1379 /* Load the given image to the HW */ 1380 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1381 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1382 else 1383 ret = iwl_pcie_load_given_ucode(trans, fw); 1384 1385 /* re-check RF-Kill state since we may have missed the interrupt */ 1386 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1387 if (hw_rfkill && !run_in_rfkill) 1388 ret = -ERFKILL; 1389 1390 out: 1391 mutex_unlock(&trans_pcie->mutex); 1392 return ret; 1393 } 1394 1395 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1396 { 1397 iwl_pcie_reset_ict(trans); 1398 iwl_pcie_tx_start(trans, scd_addr); 1399 } 1400 1401 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1402 bool was_in_rfkill) 1403 { 1404 bool hw_rfkill; 1405 1406 /* 1407 * Check again since the RF kill state may have changed while 1408 * all the interrupts were disabled, in this case we couldn't 1409 * receive the RF kill interrupt and update the state in the 1410 * op_mode. 1411 * Don't call the op_mode if the rkfill state hasn't changed. 1412 * This allows the op_mode to call stop_device from the rfkill 1413 * notification without endless recursion. Under very rare 1414 * circumstances, we might have a small recursion if the rfkill 1415 * state changed exactly now while we were called from stop_device. 1416 * This is very unlikely but can happen and is supported. 1417 */ 1418 hw_rfkill = iwl_is_rfkill_set(trans); 1419 if (hw_rfkill) { 1420 set_bit(STATUS_RFKILL_HW, &trans->status); 1421 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1422 } else { 1423 clear_bit(STATUS_RFKILL_HW, &trans->status); 1424 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1425 } 1426 if (hw_rfkill != was_in_rfkill) 1427 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1428 } 1429 1430 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1431 { 1432 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1433 bool was_in_rfkill; 1434 1435 mutex_lock(&trans_pcie->mutex); 1436 trans_pcie->opmode_down = true; 1437 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1438 _iwl_trans_pcie_stop_device(trans); 1439 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1440 mutex_unlock(&trans_pcie->mutex); 1441 } 1442 1443 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1444 { 1445 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1446 IWL_TRANS_GET_PCIE_TRANS(trans); 1447 1448 lockdep_assert_held(&trans_pcie->mutex); 1449 1450 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1451 state ? "disabled" : "enabled"); 1452 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1453 if (trans->trans_cfg->gen2) 1454 _iwl_trans_pcie_gen2_stop_device(trans); 1455 else 1456 _iwl_trans_pcie_stop_device(trans); 1457 } 1458 } 1459 1460 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1461 bool test, bool reset) 1462 { 1463 iwl_disable_interrupts(trans); 1464 1465 /* 1466 * in testing mode, the host stays awake and the 1467 * hardware won't be reset (not even partially) 1468 */ 1469 if (test) 1470 return; 1471 1472 iwl_pcie_disable_ict(trans); 1473 1474 iwl_pcie_synchronize_irqs(trans); 1475 1476 iwl_clear_bit(trans, CSR_GP_CNTRL, 1477 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1478 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1479 1480 if (reset) { 1481 /* 1482 * reset TX queues -- some of their registers reset during S3 1483 * so if we don't reset everything here the D3 image would try 1484 * to execute some invalid memory upon resume 1485 */ 1486 iwl_trans_pcie_tx_reset(trans); 1487 } 1488 1489 iwl_pcie_set_pwr(trans, true); 1490 } 1491 1492 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1493 bool reset) 1494 { 1495 int ret; 1496 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1497 1498 /* 1499 * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW. 1500 */ 1501 if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 1502 /* Enable persistence mode to avoid reset */ 1503 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1504 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1505 } 1506 1507 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1508 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1509 UREG_DOORBELL_TO_ISR6_SUSPEND); 1510 1511 ret = wait_event_timeout(trans_pcie->sx_waitq, 1512 trans_pcie->sx_complete, 2 * HZ); 1513 /* 1514 * Invalidate it toward resume. 1515 */ 1516 trans_pcie->sx_complete = false; 1517 1518 if (!ret) { 1519 IWL_ERR(trans, "Timeout entering D3\n"); 1520 return -ETIMEDOUT; 1521 } 1522 } 1523 iwl_pcie_d3_complete_suspend(trans, test, reset); 1524 1525 return 0; 1526 } 1527 1528 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1529 enum iwl_d3_status *status, 1530 bool test, bool reset) 1531 { 1532 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1533 u32 val; 1534 int ret; 1535 1536 if (test) { 1537 iwl_enable_interrupts(trans); 1538 *status = IWL_D3_STATUS_ALIVE; 1539 goto out; 1540 } 1541 1542 iwl_set_bit(trans, CSR_GP_CNTRL, 1543 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1544 1545 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 1546 if (ret) 1547 return ret; 1548 1549 /* 1550 * Reconfigure IVAR table in case of MSIX or reset ict table in 1551 * MSI mode since HW reset erased it. 1552 * Also enables interrupts - none will happen as 1553 * the device doesn't know we're waking it up, only when 1554 * the opmode actually tells it after this call. 1555 */ 1556 iwl_pcie_conf_msix_hw(trans_pcie); 1557 if (!trans_pcie->msix_enabled) 1558 iwl_pcie_reset_ict(trans); 1559 iwl_enable_interrupts(trans); 1560 1561 iwl_pcie_set_pwr(trans, false); 1562 1563 if (!reset) { 1564 iwl_clear_bit(trans, CSR_GP_CNTRL, 1565 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1566 } else { 1567 iwl_trans_pcie_tx_reset(trans); 1568 1569 ret = iwl_pcie_rx_init(trans); 1570 if (ret) { 1571 IWL_ERR(trans, 1572 "Failed to resume the device (RX reset)\n"); 1573 return ret; 1574 } 1575 } 1576 1577 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1578 iwl_read_umac_prph(trans, WFPM_GP2)); 1579 1580 val = iwl_read32(trans, CSR_RESET); 1581 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1582 *status = IWL_D3_STATUS_RESET; 1583 else 1584 *status = IWL_D3_STATUS_ALIVE; 1585 1586 out: 1587 if (*status == IWL_D3_STATUS_ALIVE && 1588 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1589 trans_pcie->sx_complete = false; 1590 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1591 UREG_DOORBELL_TO_ISR6_RESUME); 1592 1593 ret = wait_event_timeout(trans_pcie->sx_waitq, 1594 trans_pcie->sx_complete, 2 * HZ); 1595 /* 1596 * Invalidate it toward next suspend. 1597 */ 1598 trans_pcie->sx_complete = false; 1599 1600 if (!ret) { 1601 IWL_ERR(trans, "Timeout exiting D3\n"); 1602 return -ETIMEDOUT; 1603 } 1604 } 1605 return 0; 1606 } 1607 1608 static void 1609 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1610 struct iwl_trans *trans, 1611 const struct iwl_cfg_trans_params *cfg_trans) 1612 { 1613 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1614 int max_irqs, num_irqs, i, ret; 1615 u16 pci_cmd; 1616 1617 if (!cfg_trans->mq_rx_supported) 1618 goto enable_msi; 1619 1620 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 1621 for (i = 0; i < max_irqs; i++) 1622 trans_pcie->msix_entries[i].entry = i; 1623 1624 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1625 MSIX_MIN_INTERRUPT_VECTORS, 1626 max_irqs); 1627 if (num_irqs < 0) { 1628 IWL_DEBUG_INFO(trans, 1629 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1630 num_irqs); 1631 goto enable_msi; 1632 } 1633 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1634 1635 IWL_DEBUG_INFO(trans, 1636 "MSI-X enabled. %d interrupt vectors were allocated\n", 1637 num_irqs); 1638 1639 /* 1640 * In case the OS provides fewer interrupts than requested, different 1641 * causes will share the same interrupt vector as follows: 1642 * One interrupt less: non rx causes shared with FBQ. 1643 * Two interrupts less: non rx causes shared with FBQ and RSS. 1644 * More than two interrupts: we will use fewer RSS queues. 1645 */ 1646 if (num_irqs <= max_irqs - 2) { 1647 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1648 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1649 IWL_SHARED_IRQ_FIRST_RSS; 1650 } else if (num_irqs == max_irqs - 1) { 1651 trans_pcie->trans->num_rx_queues = num_irqs; 1652 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1653 } else { 1654 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1655 } 1656 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1657 1658 trans_pcie->alloc_vecs = num_irqs; 1659 trans_pcie->msix_enabled = true; 1660 return; 1661 1662 enable_msi: 1663 ret = pci_enable_msi(pdev); 1664 if (ret) { 1665 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1666 /* enable rfkill interrupt: hw bug w/a */ 1667 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1668 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1669 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1670 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1671 } 1672 } 1673 } 1674 1675 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1676 { 1677 int iter_rx_q, i, ret, cpu, offset; 1678 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1679 1680 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1681 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1682 offset = 1 + i; 1683 for (; i < iter_rx_q ; i++) { 1684 /* 1685 * Get the cpu prior to the place to search 1686 * (i.e. return will be > i - 1). 1687 */ 1688 cpu = cpumask_next(i - offset, cpu_online_mask); 1689 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1690 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1691 &trans_pcie->affinity_mask[i]); 1692 if (ret) 1693 IWL_ERR(trans_pcie->trans, 1694 "Failed to set affinity mask for IRQ %d\n", 1695 i); 1696 } 1697 } 1698 1699 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1700 struct iwl_trans_pcie *trans_pcie) 1701 { 1702 int i; 1703 1704 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1705 int ret; 1706 struct msix_entry *msix_entry; 1707 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1708 1709 if (!qname) 1710 return -ENOMEM; 1711 1712 msix_entry = &trans_pcie->msix_entries[i]; 1713 ret = devm_request_threaded_irq(&pdev->dev, 1714 msix_entry->vector, 1715 iwl_pcie_msix_isr, 1716 (i == trans_pcie->def_irq) ? 1717 iwl_pcie_irq_msix_handler : 1718 iwl_pcie_irq_rx_msix_handler, 1719 IRQF_SHARED, 1720 qname, 1721 msix_entry); 1722 if (ret) { 1723 IWL_ERR(trans_pcie->trans, 1724 "Error allocating IRQ %d\n", i); 1725 1726 return ret; 1727 } 1728 } 1729 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1730 1731 return 0; 1732 } 1733 1734 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1735 { 1736 u32 hpm, wprot; 1737 1738 switch (trans->trans_cfg->device_family) { 1739 case IWL_DEVICE_FAMILY_9000: 1740 wprot = PREG_PRPH_WPROT_9000; 1741 break; 1742 case IWL_DEVICE_FAMILY_22000: 1743 wprot = PREG_PRPH_WPROT_22000; 1744 break; 1745 default: 1746 return 0; 1747 } 1748 1749 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1750 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1751 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1752 1753 if (wprot_val & PREG_WFPM_ACCESS) { 1754 IWL_ERR(trans, 1755 "Error, can not clear persistence bit\n"); 1756 return -EPERM; 1757 } 1758 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1759 hpm & ~PERSISTENCE_BIT); 1760 } 1761 1762 return 0; 1763 } 1764 1765 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1766 { 1767 int ret; 1768 1769 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 1770 if (ret < 0) 1771 return ret; 1772 1773 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1774 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1775 udelay(20); 1776 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1777 HPM_HIPM_GEN_CFG_CR_PG_EN | 1778 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1779 udelay(20); 1780 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1781 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1782 1783 iwl_trans_pcie_sw_reset(trans); 1784 1785 return 0; 1786 } 1787 1788 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1789 { 1790 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1791 int err; 1792 1793 lockdep_assert_held(&trans_pcie->mutex); 1794 1795 err = iwl_pcie_prepare_card_hw(trans); 1796 if (err) { 1797 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1798 return err; 1799 } 1800 1801 err = iwl_trans_pcie_clear_persistence_bit(trans); 1802 if (err) 1803 return err; 1804 1805 iwl_trans_pcie_sw_reset(trans); 1806 1807 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1808 trans->trans_cfg->integrated) { 1809 err = iwl_pcie_gen2_force_power_gating(trans); 1810 if (err) 1811 return err; 1812 } 1813 1814 err = iwl_pcie_apm_init(trans); 1815 if (err) 1816 return err; 1817 1818 iwl_pcie_init_msix(trans_pcie); 1819 1820 /* From now on, the op_mode will be kept updated about RF kill state */ 1821 iwl_enable_rfkill_int(trans); 1822 1823 trans_pcie->opmode_down = false; 1824 1825 /* Set is_down to false here so that...*/ 1826 trans_pcie->is_down = false; 1827 1828 /* ...rfkill can call stop_device and set it false if needed */ 1829 iwl_pcie_check_hw_rf_kill(trans); 1830 1831 return 0; 1832 } 1833 1834 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1835 { 1836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1837 int ret; 1838 1839 mutex_lock(&trans_pcie->mutex); 1840 ret = _iwl_trans_pcie_start_hw(trans); 1841 mutex_unlock(&trans_pcie->mutex); 1842 1843 return ret; 1844 } 1845 1846 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1847 { 1848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1849 1850 mutex_lock(&trans_pcie->mutex); 1851 1852 /* disable interrupts - don't enable HW RF kill interrupt */ 1853 iwl_disable_interrupts(trans); 1854 1855 iwl_pcie_apm_stop(trans, true); 1856 1857 iwl_disable_interrupts(trans); 1858 1859 iwl_pcie_disable_ict(trans); 1860 1861 mutex_unlock(&trans_pcie->mutex); 1862 1863 iwl_pcie_synchronize_irqs(trans); 1864 } 1865 1866 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1867 { 1868 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1869 } 1870 1871 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1872 { 1873 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1874 } 1875 1876 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1877 { 1878 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1879 } 1880 1881 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1882 { 1883 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1884 return 0x00FFFFFF; 1885 else 1886 return 0x000FFFFF; 1887 } 1888 1889 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1890 { 1891 u32 mask = iwl_trans_pcie_prph_msk(trans); 1892 1893 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1894 ((reg & mask) | (3 << 24))); 1895 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1896 } 1897 1898 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1899 u32 val) 1900 { 1901 u32 mask = iwl_trans_pcie_prph_msk(trans); 1902 1903 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1904 ((addr & mask) | (3 << 24))); 1905 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1906 } 1907 1908 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1909 const struct iwl_trans_config *trans_cfg) 1910 { 1911 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1912 1913 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1914 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1915 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1916 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1917 trans_pcie->n_no_reclaim_cmds = 0; 1918 else 1919 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1920 if (trans_pcie->n_no_reclaim_cmds) 1921 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1922 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1923 1924 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1925 trans_pcie->rx_page_order = 1926 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1927 trans_pcie->rx_buf_bytes = 1928 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1929 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1930 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1931 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1932 1933 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1934 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1935 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1936 1937 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1938 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1939 1940 trans->command_groups = trans_cfg->command_groups; 1941 trans->command_groups_size = trans_cfg->command_groups_size; 1942 1943 /* Initialize NAPI here - it should be before registering to mac80211 1944 * in the opmode but after the HW struct is allocated. 1945 * As this function may be called again in some corner cases don't 1946 * do anything if NAPI was already initialized. 1947 */ 1948 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1949 init_dummy_netdev(&trans_pcie->napi_dev); 1950 } 1951 1952 void iwl_trans_pcie_free(struct iwl_trans *trans) 1953 { 1954 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1955 int i; 1956 1957 iwl_pcie_synchronize_irqs(trans); 1958 1959 if (trans->trans_cfg->gen2) 1960 iwl_pcie_gen2_tx_free(trans); 1961 else 1962 iwl_pcie_tx_free(trans); 1963 iwl_pcie_rx_free(trans); 1964 1965 if (trans_pcie->rba.alloc_wq) { 1966 destroy_workqueue(trans_pcie->rba.alloc_wq); 1967 trans_pcie->rba.alloc_wq = NULL; 1968 } 1969 1970 if (trans_pcie->msix_enabled) { 1971 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1972 irq_set_affinity_hint( 1973 trans_pcie->msix_entries[i].vector, 1974 NULL); 1975 } 1976 1977 trans_pcie->msix_enabled = false; 1978 } else { 1979 iwl_pcie_free_ict(trans); 1980 } 1981 1982 iwl_pcie_free_fw_monitor(trans); 1983 1984 for_each_possible_cpu(i) { 1985 struct iwl_tso_hdr_page *p = 1986 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1987 1988 if (p->page) 1989 __free_page(p->page); 1990 } 1991 1992 free_percpu(trans_pcie->tso_hdr_page); 1993 mutex_destroy(&trans_pcie->mutex); 1994 iwl_trans_free(trans); 1995 } 1996 1997 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1998 { 1999 if (state) 2000 set_bit(STATUS_TPOWER_PMI, &trans->status); 2001 else 2002 clear_bit(STATUS_TPOWER_PMI, &trans->status); 2003 } 2004 2005 struct iwl_trans_pcie_removal { 2006 struct pci_dev *pdev; 2007 struct work_struct work; 2008 }; 2009 2010 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2011 { 2012 struct iwl_trans_pcie_removal *removal = 2013 container_of(wk, struct iwl_trans_pcie_removal, work); 2014 struct pci_dev *pdev = removal->pdev; 2015 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2016 2017 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2018 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2019 pci_lock_rescan_remove(); 2020 pci_dev_put(pdev); 2021 pci_stop_and_remove_bus_device(pdev); 2022 pci_unlock_rescan_remove(); 2023 2024 kfree(removal); 2025 module_put(THIS_MODULE); 2026 } 2027 2028 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 2029 unsigned long *flags) 2030 { 2031 int ret; 2032 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2033 2034 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 2035 2036 if (trans_pcie->cmd_hold_nic_awake) 2037 goto out; 2038 2039 /* this bit wakes up the NIC */ 2040 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 2041 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2042 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2043 udelay(2); 2044 2045 /* 2046 * These bits say the device is running, and should keep running for 2047 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2048 * but they do not indicate that embedded SRAM is restored yet; 2049 * HW with volatile SRAM must save/restore contents to/from 2050 * host DRAM when sleeping/waking for power-saving. 2051 * Each direction takes approximately 1/4 millisecond; with this 2052 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2053 * series of register accesses are expected (e.g. reading Event Log), 2054 * to keep device from sleeping. 2055 * 2056 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2057 * SRAM is okay/restored. We don't check that here because this call 2058 * is just for hardware register access; but GP1 MAC_SLEEP 2059 * check is a good idea before accessing the SRAM of HW with 2060 * volatile SRAM (e.g. reading Event Log). 2061 * 2062 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2063 * and do not save/restore SRAM when power cycling. 2064 */ 2065 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2066 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 2067 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2068 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2069 if (unlikely(ret < 0)) { 2070 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2071 2072 WARN_ONCE(1, 2073 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2074 cntrl); 2075 2076 iwl_trans_pcie_dump_regs(trans); 2077 2078 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 2079 struct iwl_trans_pcie_removal *removal; 2080 2081 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2082 goto err; 2083 2084 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2085 2086 /* 2087 * get a module reference to avoid doing this 2088 * while unloading anyway and to avoid 2089 * scheduling a work with code that's being 2090 * removed. 2091 */ 2092 if (!try_module_get(THIS_MODULE)) { 2093 IWL_ERR(trans, 2094 "Module is being unloaded - abort\n"); 2095 goto err; 2096 } 2097 2098 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2099 if (!removal) { 2100 module_put(THIS_MODULE); 2101 goto err; 2102 } 2103 /* 2104 * we don't need to clear this flag, because 2105 * the trans will be freed and reallocated. 2106 */ 2107 set_bit(STATUS_TRANS_DEAD, &trans->status); 2108 2109 removal->pdev = to_pci_dev(trans->dev); 2110 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2111 pci_dev_get(removal->pdev); 2112 schedule_work(&removal->work); 2113 } else { 2114 iwl_write32(trans, CSR_RESET, 2115 CSR_RESET_REG_FLAG_FORCE_NMI); 2116 } 2117 2118 err: 2119 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2120 return false; 2121 } 2122 2123 out: 2124 /* 2125 * Fool sparse by faking we release the lock - sparse will 2126 * track nic_access anyway. 2127 */ 2128 __release(&trans_pcie->reg_lock); 2129 return true; 2130 } 2131 2132 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2133 unsigned long *flags) 2134 { 2135 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2136 2137 lockdep_assert_held(&trans_pcie->reg_lock); 2138 2139 /* 2140 * Fool sparse by faking we acquiring the lock - sparse will 2141 * track nic_access anyway. 2142 */ 2143 __acquire(&trans_pcie->reg_lock); 2144 2145 if (trans_pcie->cmd_hold_nic_awake) 2146 goto out; 2147 2148 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2149 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2150 /* 2151 * Above we read the CSR_GP_CNTRL register, which will flush 2152 * any previous writes, but we need the write that clears the 2153 * MAC_ACCESS_REQ bit to be performed before any other writes 2154 * scheduled on different CPUs (after we drop reg_lock). 2155 */ 2156 out: 2157 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2158 } 2159 2160 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2161 void *buf, int dwords) 2162 { 2163 unsigned long flags; 2164 int offs, ret = 0; 2165 u32 *vals = buf; 2166 2167 if (iwl_trans_grab_nic_access(trans, &flags)) { 2168 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2169 for (offs = 0; offs < dwords; offs++) 2170 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2171 iwl_trans_release_nic_access(trans, &flags); 2172 } else { 2173 ret = -EBUSY; 2174 } 2175 return ret; 2176 } 2177 2178 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2179 const void *buf, int dwords) 2180 { 2181 unsigned long flags; 2182 int offs, ret = 0; 2183 const u32 *vals = buf; 2184 2185 if (iwl_trans_grab_nic_access(trans, &flags)) { 2186 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2187 for (offs = 0; offs < dwords; offs++) 2188 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2189 vals ? vals[offs] : 0); 2190 iwl_trans_release_nic_access(trans, &flags); 2191 } else { 2192 ret = -EBUSY; 2193 } 2194 return ret; 2195 } 2196 2197 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2198 u32 *val) 2199 { 2200 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2201 ofs, val); 2202 } 2203 2204 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2205 unsigned long txqs, 2206 bool freeze) 2207 { 2208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2209 int queue; 2210 2211 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2212 struct iwl_txq *txq = trans_pcie->txq[queue]; 2213 unsigned long now; 2214 2215 spin_lock_bh(&txq->lock); 2216 2217 now = jiffies; 2218 2219 if (txq->frozen == freeze) 2220 goto next_queue; 2221 2222 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2223 freeze ? "Freezing" : "Waking", queue); 2224 2225 txq->frozen = freeze; 2226 2227 if (txq->read_ptr == txq->write_ptr) 2228 goto next_queue; 2229 2230 if (freeze) { 2231 if (unlikely(time_after(now, 2232 txq->stuck_timer.expires))) { 2233 /* 2234 * The timer should have fired, maybe it is 2235 * spinning right now on the lock. 2236 */ 2237 goto next_queue; 2238 } 2239 /* remember how long until the timer fires */ 2240 txq->frozen_expiry_remainder = 2241 txq->stuck_timer.expires - now; 2242 del_timer(&txq->stuck_timer); 2243 goto next_queue; 2244 } 2245 2246 /* 2247 * Wake a non-empty queue -> arm timer with the 2248 * remainder before it froze 2249 */ 2250 mod_timer(&txq->stuck_timer, 2251 now + txq->frozen_expiry_remainder); 2252 2253 next_queue: 2254 spin_unlock_bh(&txq->lock); 2255 } 2256 } 2257 2258 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2259 { 2260 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2261 int i; 2262 2263 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2264 struct iwl_txq *txq = trans_pcie->txq[i]; 2265 2266 if (i == trans_pcie->cmd_queue) 2267 continue; 2268 2269 spin_lock_bh(&txq->lock); 2270 2271 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2272 txq->block--; 2273 if (!txq->block) { 2274 iwl_write32(trans, HBUS_TARG_WRPTR, 2275 txq->write_ptr | (i << 8)); 2276 } 2277 } else if (block) { 2278 txq->block++; 2279 } 2280 2281 spin_unlock_bh(&txq->lock); 2282 } 2283 } 2284 2285 #define IWL_FLUSH_WAIT_MS 2000 2286 2287 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2288 { 2289 u32 txq_id = txq->id; 2290 u32 status; 2291 bool active; 2292 u8 fifo; 2293 2294 if (trans->trans_cfg->use_tfh) { 2295 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2296 txq->read_ptr, txq->write_ptr); 2297 /* TODO: access new SCD registers and dump them */ 2298 return; 2299 } 2300 2301 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2302 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2303 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2304 2305 IWL_ERR(trans, 2306 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2307 txq_id, active ? "" : "in", fifo, 2308 jiffies_to_msecs(txq->wd_timeout), 2309 txq->read_ptr, txq->write_ptr, 2310 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2311 (trans->trans_cfg->base_params->max_tfd_queue_size - 1), 2312 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2313 (trans->trans_cfg->base_params->max_tfd_queue_size - 1), 2314 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2315 } 2316 2317 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2318 struct iwl_trans_rxq_dma_data *data) 2319 { 2320 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2321 2322 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2323 return -EINVAL; 2324 2325 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2326 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2327 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2328 data->fr_bd_wid = 0; 2329 2330 return 0; 2331 } 2332 2333 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2334 { 2335 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2336 struct iwl_txq *txq; 2337 unsigned long now = jiffies; 2338 bool overflow_tx; 2339 u8 wr_ptr; 2340 2341 /* Make sure the NIC is still alive in the bus */ 2342 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2343 return -ENODEV; 2344 2345 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2346 return -EINVAL; 2347 2348 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2349 txq = trans_pcie->txq[txq_idx]; 2350 2351 spin_lock_bh(&txq->lock); 2352 overflow_tx = txq->overflow_tx || 2353 !skb_queue_empty(&txq->overflow_q); 2354 spin_unlock_bh(&txq->lock); 2355 2356 wr_ptr = READ_ONCE(txq->write_ptr); 2357 2358 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2359 overflow_tx) && 2360 !time_after(jiffies, 2361 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2362 u8 write_ptr = READ_ONCE(txq->write_ptr); 2363 2364 /* 2365 * If write pointer moved during the wait, warn only 2366 * if the TX came from op mode. In case TX came from 2367 * trans layer (overflow TX) don't warn. 2368 */ 2369 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2370 "WR pointer moved while flushing %d -> %d\n", 2371 wr_ptr, write_ptr)) 2372 return -ETIMEDOUT; 2373 wr_ptr = write_ptr; 2374 2375 usleep_range(1000, 2000); 2376 2377 spin_lock_bh(&txq->lock); 2378 overflow_tx = txq->overflow_tx || 2379 !skb_queue_empty(&txq->overflow_q); 2380 spin_unlock_bh(&txq->lock); 2381 } 2382 2383 if (txq->read_ptr != txq->write_ptr) { 2384 IWL_ERR(trans, 2385 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2386 iwl_trans_pcie_log_scd_error(trans, txq); 2387 return -ETIMEDOUT; 2388 } 2389 2390 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2391 2392 return 0; 2393 } 2394 2395 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2396 { 2397 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2398 int cnt; 2399 int ret = 0; 2400 2401 /* waiting for all the tx frames complete might take a while */ 2402 for (cnt = 0; 2403 cnt < trans->trans_cfg->base_params->num_of_queues; 2404 cnt++) { 2405 2406 if (cnt == trans_pcie->cmd_queue) 2407 continue; 2408 if (!test_bit(cnt, trans_pcie->queue_used)) 2409 continue; 2410 if (!(BIT(cnt) & txq_bm)) 2411 continue; 2412 2413 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2414 if (ret) 2415 break; 2416 } 2417 2418 return ret; 2419 } 2420 2421 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2422 u32 mask, u32 value) 2423 { 2424 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2425 unsigned long flags; 2426 2427 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2428 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2429 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2430 } 2431 2432 static const char *get_csr_string(int cmd) 2433 { 2434 #define IWL_CMD(x) case x: return #x 2435 switch (cmd) { 2436 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2437 IWL_CMD(CSR_INT_COALESCING); 2438 IWL_CMD(CSR_INT); 2439 IWL_CMD(CSR_INT_MASK); 2440 IWL_CMD(CSR_FH_INT_STATUS); 2441 IWL_CMD(CSR_GPIO_IN); 2442 IWL_CMD(CSR_RESET); 2443 IWL_CMD(CSR_GP_CNTRL); 2444 IWL_CMD(CSR_HW_REV); 2445 IWL_CMD(CSR_EEPROM_REG); 2446 IWL_CMD(CSR_EEPROM_GP); 2447 IWL_CMD(CSR_OTP_GP_REG); 2448 IWL_CMD(CSR_GIO_REG); 2449 IWL_CMD(CSR_GP_UCODE_REG); 2450 IWL_CMD(CSR_GP_DRIVER_REG); 2451 IWL_CMD(CSR_UCODE_DRV_GP1); 2452 IWL_CMD(CSR_UCODE_DRV_GP2); 2453 IWL_CMD(CSR_LED_REG); 2454 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2455 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2456 IWL_CMD(CSR_ANA_PLL_CFG); 2457 IWL_CMD(CSR_HW_REV_WA_REG); 2458 IWL_CMD(CSR_MONITOR_STATUS_REG); 2459 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2460 default: 2461 return "UNKNOWN"; 2462 } 2463 #undef IWL_CMD 2464 } 2465 2466 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2467 { 2468 int i; 2469 static const u32 csr_tbl[] = { 2470 CSR_HW_IF_CONFIG_REG, 2471 CSR_INT_COALESCING, 2472 CSR_INT, 2473 CSR_INT_MASK, 2474 CSR_FH_INT_STATUS, 2475 CSR_GPIO_IN, 2476 CSR_RESET, 2477 CSR_GP_CNTRL, 2478 CSR_HW_REV, 2479 CSR_EEPROM_REG, 2480 CSR_EEPROM_GP, 2481 CSR_OTP_GP_REG, 2482 CSR_GIO_REG, 2483 CSR_GP_UCODE_REG, 2484 CSR_GP_DRIVER_REG, 2485 CSR_UCODE_DRV_GP1, 2486 CSR_UCODE_DRV_GP2, 2487 CSR_LED_REG, 2488 CSR_DRAM_INT_TBL_REG, 2489 CSR_GIO_CHICKEN_BITS, 2490 CSR_ANA_PLL_CFG, 2491 CSR_MONITOR_STATUS_REG, 2492 CSR_HW_REV_WA_REG, 2493 CSR_DBG_HPET_MEM_REG 2494 }; 2495 IWL_ERR(trans, "CSR values:\n"); 2496 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2497 "CSR_INT_PERIODIC_REG)\n"); 2498 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2499 IWL_ERR(trans, " %25s: 0X%08x\n", 2500 get_csr_string(csr_tbl[i]), 2501 iwl_read32(trans, csr_tbl[i])); 2502 } 2503 } 2504 2505 #ifdef CONFIG_IWLWIFI_DEBUGFS 2506 /* create and remove of files */ 2507 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2508 debugfs_create_file(#name, mode, parent, trans, \ 2509 &iwl_dbgfs_##name##_ops); \ 2510 } while (0) 2511 2512 /* file operation */ 2513 #define DEBUGFS_READ_FILE_OPS(name) \ 2514 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2515 .read = iwl_dbgfs_##name##_read, \ 2516 .open = simple_open, \ 2517 .llseek = generic_file_llseek, \ 2518 }; 2519 2520 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2521 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2522 .write = iwl_dbgfs_##name##_write, \ 2523 .open = simple_open, \ 2524 .llseek = generic_file_llseek, \ 2525 }; 2526 2527 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2528 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2529 .write = iwl_dbgfs_##name##_write, \ 2530 .read = iwl_dbgfs_##name##_read, \ 2531 .open = simple_open, \ 2532 .llseek = generic_file_llseek, \ 2533 }; 2534 2535 struct iwl_dbgfs_tx_queue_priv { 2536 struct iwl_trans *trans; 2537 }; 2538 2539 struct iwl_dbgfs_tx_queue_state { 2540 loff_t pos; 2541 }; 2542 2543 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2544 { 2545 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2546 struct iwl_dbgfs_tx_queue_state *state; 2547 2548 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2549 return NULL; 2550 2551 state = kmalloc(sizeof(*state), GFP_KERNEL); 2552 if (!state) 2553 return NULL; 2554 state->pos = *pos; 2555 return state; 2556 } 2557 2558 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2559 void *v, loff_t *pos) 2560 { 2561 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2562 struct iwl_dbgfs_tx_queue_state *state = v; 2563 2564 *pos = ++state->pos; 2565 2566 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2567 return NULL; 2568 2569 return state; 2570 } 2571 2572 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2573 { 2574 kfree(v); 2575 } 2576 2577 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2578 { 2579 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2580 struct iwl_dbgfs_tx_queue_state *state = v; 2581 struct iwl_trans *trans = priv->trans; 2582 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2583 struct iwl_txq *txq = trans_pcie->txq[state->pos]; 2584 2585 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2586 (unsigned int)state->pos, 2587 !!test_bit(state->pos, trans_pcie->queue_used), 2588 !!test_bit(state->pos, trans_pcie->queue_stopped)); 2589 if (txq) 2590 seq_printf(seq, 2591 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2592 txq->read_ptr, txq->write_ptr, 2593 txq->need_update, txq->frozen, 2594 txq->n_window, txq->ampdu); 2595 else 2596 seq_puts(seq, "(unallocated)"); 2597 2598 if (state->pos == trans_pcie->cmd_queue) 2599 seq_puts(seq, " (HCMD)"); 2600 seq_puts(seq, "\n"); 2601 2602 return 0; 2603 } 2604 2605 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2606 .start = iwl_dbgfs_tx_queue_seq_start, 2607 .next = iwl_dbgfs_tx_queue_seq_next, 2608 .stop = iwl_dbgfs_tx_queue_seq_stop, 2609 .show = iwl_dbgfs_tx_queue_seq_show, 2610 }; 2611 2612 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2613 { 2614 struct iwl_dbgfs_tx_queue_priv *priv; 2615 2616 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2617 sizeof(*priv)); 2618 2619 if (!priv) 2620 return -ENOMEM; 2621 2622 priv->trans = inode->i_private; 2623 return 0; 2624 } 2625 2626 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2627 char __user *user_buf, 2628 size_t count, loff_t *ppos) 2629 { 2630 struct iwl_trans *trans = file->private_data; 2631 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2632 char *buf; 2633 int pos = 0, i, ret; 2634 size_t bufsz; 2635 2636 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2637 2638 if (!trans_pcie->rxq) 2639 return -EAGAIN; 2640 2641 buf = kzalloc(bufsz, GFP_KERNEL); 2642 if (!buf) 2643 return -ENOMEM; 2644 2645 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2646 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2647 2648 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2649 i); 2650 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2651 rxq->read); 2652 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2653 rxq->write); 2654 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2655 rxq->write_actual); 2656 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2657 rxq->need_update); 2658 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2659 rxq->free_count); 2660 if (rxq->rb_stts) { 2661 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2662 rxq)); 2663 pos += scnprintf(buf + pos, bufsz - pos, 2664 "\tclosed_rb_num: %u\n", 2665 r & 0x0FFF); 2666 } else { 2667 pos += scnprintf(buf + pos, bufsz - pos, 2668 "\tclosed_rb_num: Not Allocated\n"); 2669 } 2670 } 2671 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2672 kfree(buf); 2673 2674 return ret; 2675 } 2676 2677 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2678 char __user *user_buf, 2679 size_t count, loff_t *ppos) 2680 { 2681 struct iwl_trans *trans = file->private_data; 2682 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2683 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2684 2685 int pos = 0; 2686 char *buf; 2687 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2688 ssize_t ret; 2689 2690 buf = kzalloc(bufsz, GFP_KERNEL); 2691 if (!buf) 2692 return -ENOMEM; 2693 2694 pos += scnprintf(buf + pos, bufsz - pos, 2695 "Interrupt Statistics Report:\n"); 2696 2697 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2698 isr_stats->hw); 2699 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2700 isr_stats->sw); 2701 if (isr_stats->sw || isr_stats->hw) { 2702 pos += scnprintf(buf + pos, bufsz - pos, 2703 "\tLast Restarting Code: 0x%X\n", 2704 isr_stats->err_code); 2705 } 2706 #ifdef CONFIG_IWLWIFI_DEBUG 2707 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2708 isr_stats->sch); 2709 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2710 isr_stats->alive); 2711 #endif 2712 pos += scnprintf(buf + pos, bufsz - pos, 2713 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2714 2715 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2716 isr_stats->ctkill); 2717 2718 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2719 isr_stats->wakeup); 2720 2721 pos += scnprintf(buf + pos, bufsz - pos, 2722 "Rx command responses:\t\t %u\n", isr_stats->rx); 2723 2724 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2725 isr_stats->tx); 2726 2727 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2728 isr_stats->unhandled); 2729 2730 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2731 kfree(buf); 2732 return ret; 2733 } 2734 2735 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2736 const char __user *user_buf, 2737 size_t count, loff_t *ppos) 2738 { 2739 struct iwl_trans *trans = file->private_data; 2740 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2741 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2742 u32 reset_flag; 2743 int ret; 2744 2745 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2746 if (ret) 2747 return ret; 2748 if (reset_flag == 0) 2749 memset(isr_stats, 0, sizeof(*isr_stats)); 2750 2751 return count; 2752 } 2753 2754 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2755 const char __user *user_buf, 2756 size_t count, loff_t *ppos) 2757 { 2758 struct iwl_trans *trans = file->private_data; 2759 2760 iwl_pcie_dump_csr(trans); 2761 2762 return count; 2763 } 2764 2765 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2766 char __user *user_buf, 2767 size_t count, loff_t *ppos) 2768 { 2769 struct iwl_trans *trans = file->private_data; 2770 char *buf = NULL; 2771 ssize_t ret; 2772 2773 ret = iwl_dump_fh(trans, &buf); 2774 if (ret < 0) 2775 return ret; 2776 if (!buf) 2777 return -EINVAL; 2778 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2779 kfree(buf); 2780 return ret; 2781 } 2782 2783 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2784 char __user *user_buf, 2785 size_t count, loff_t *ppos) 2786 { 2787 struct iwl_trans *trans = file->private_data; 2788 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2789 char buf[100]; 2790 int pos; 2791 2792 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2793 trans_pcie->debug_rfkill, 2794 !(iwl_read32(trans, CSR_GP_CNTRL) & 2795 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2796 2797 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2798 } 2799 2800 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2801 const char __user *user_buf, 2802 size_t count, loff_t *ppos) 2803 { 2804 struct iwl_trans *trans = file->private_data; 2805 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2806 bool new_value; 2807 int ret; 2808 2809 ret = kstrtobool_from_user(user_buf, count, &new_value); 2810 if (ret) 2811 return ret; 2812 if (new_value == trans_pcie->debug_rfkill) 2813 return count; 2814 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2815 trans_pcie->debug_rfkill, new_value); 2816 trans_pcie->debug_rfkill = new_value; 2817 iwl_pcie_handle_rfkill_irq(trans); 2818 2819 return count; 2820 } 2821 2822 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2823 struct file *file) 2824 { 2825 struct iwl_trans *trans = inode->i_private; 2826 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2827 2828 if (!trans->dbg.dest_tlv || 2829 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2830 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2831 return -ENOENT; 2832 } 2833 2834 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2835 return -EBUSY; 2836 2837 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2838 return simple_open(inode, file); 2839 } 2840 2841 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2842 struct file *file) 2843 { 2844 struct iwl_trans_pcie *trans_pcie = 2845 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2846 2847 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2848 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2849 return 0; 2850 } 2851 2852 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2853 void *buf, ssize_t *size, 2854 ssize_t *bytes_copied) 2855 { 2856 int buf_size_left = count - *bytes_copied; 2857 2858 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2859 if (*size > buf_size_left) 2860 *size = buf_size_left; 2861 2862 *size -= copy_to_user(user_buf, buf, *size); 2863 *bytes_copied += *size; 2864 2865 if (buf_size_left == *size) 2866 return true; 2867 return false; 2868 } 2869 2870 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2871 char __user *user_buf, 2872 size_t count, loff_t *ppos) 2873 { 2874 struct iwl_trans *trans = file->private_data; 2875 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2876 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2877 struct cont_rec *data = &trans_pcie->fw_mon_data; 2878 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2879 ssize_t size, bytes_copied = 0; 2880 bool b_full; 2881 2882 if (trans->dbg.dest_tlv) { 2883 write_ptr_addr = 2884 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2885 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2886 } else { 2887 write_ptr_addr = MON_BUFF_WRPTR; 2888 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2889 } 2890 2891 if (unlikely(!trans->dbg.rec_on)) 2892 return 0; 2893 2894 mutex_lock(&data->mutex); 2895 if (data->state == 2896 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2897 mutex_unlock(&data->mutex); 2898 return 0; 2899 } 2900 2901 /* write_ptr position in bytes rather then DW */ 2902 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2903 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2904 2905 if (data->prev_wrap_cnt == wrap_cnt) { 2906 size = write_ptr - data->prev_wr_ptr; 2907 curr_buf = cpu_addr + data->prev_wr_ptr; 2908 b_full = iwl_write_to_user_buf(user_buf, count, 2909 curr_buf, &size, 2910 &bytes_copied); 2911 data->prev_wr_ptr += size; 2912 2913 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2914 write_ptr < data->prev_wr_ptr) { 2915 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2916 curr_buf = cpu_addr + data->prev_wr_ptr; 2917 b_full = iwl_write_to_user_buf(user_buf, count, 2918 curr_buf, &size, 2919 &bytes_copied); 2920 data->prev_wr_ptr += size; 2921 2922 if (!b_full) { 2923 size = write_ptr; 2924 b_full = iwl_write_to_user_buf(user_buf, count, 2925 cpu_addr, &size, 2926 &bytes_copied); 2927 data->prev_wr_ptr = size; 2928 data->prev_wrap_cnt++; 2929 } 2930 } else { 2931 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2932 write_ptr > data->prev_wr_ptr) 2933 IWL_WARN(trans, 2934 "write pointer passed previous write pointer, start copying from the beginning\n"); 2935 else if (!unlikely(data->prev_wrap_cnt == 0 && 2936 data->prev_wr_ptr == 0)) 2937 IWL_WARN(trans, 2938 "monitor data is out of sync, start copying from the beginning\n"); 2939 2940 size = write_ptr; 2941 b_full = iwl_write_to_user_buf(user_buf, count, 2942 cpu_addr, &size, 2943 &bytes_copied); 2944 data->prev_wr_ptr = size; 2945 data->prev_wrap_cnt = wrap_cnt; 2946 } 2947 2948 mutex_unlock(&data->mutex); 2949 2950 return bytes_copied; 2951 } 2952 2953 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2954 DEBUGFS_READ_FILE_OPS(fh_reg); 2955 DEBUGFS_READ_FILE_OPS(rx_queue); 2956 DEBUGFS_WRITE_FILE_OPS(csr); 2957 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2958 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2959 .owner = THIS_MODULE, 2960 .open = iwl_dbgfs_tx_queue_open, 2961 .read = seq_read, 2962 .llseek = seq_lseek, 2963 .release = seq_release_private, 2964 }; 2965 2966 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2967 .read = iwl_dbgfs_monitor_data_read, 2968 .open = iwl_dbgfs_monitor_data_open, 2969 .release = iwl_dbgfs_monitor_data_release, 2970 }; 2971 2972 /* Create the debugfs files and directories */ 2973 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2974 { 2975 struct dentry *dir = trans->dbgfs_dir; 2976 2977 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 2978 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 2979 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 2980 DEBUGFS_ADD_FILE(csr, dir, 0200); 2981 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 2982 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2983 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2984 } 2985 2986 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2987 { 2988 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2989 struct cont_rec *data = &trans_pcie->fw_mon_data; 2990 2991 mutex_lock(&data->mutex); 2992 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2993 mutex_unlock(&data->mutex); 2994 } 2995 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2996 2997 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2998 { 2999 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3000 u32 cmdlen = 0; 3001 int i; 3002 3003 for (i = 0; i < trans_pcie->max_tbs; i++) 3004 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 3005 3006 return cmdlen; 3007 } 3008 3009 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3010 struct iwl_fw_error_dump_data **data, 3011 int allocated_rb_nums) 3012 { 3013 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3014 int max_len = trans_pcie->rx_buf_bytes; 3015 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3016 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3017 u32 i, r, j, rb_len = 0; 3018 3019 spin_lock(&rxq->lock); 3020 3021 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3022 3023 for (i = rxq->read, j = 0; 3024 i != r && j < allocated_rb_nums; 3025 i = (i + 1) & RX_QUEUE_MASK, j++) { 3026 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3027 struct iwl_fw_error_dump_rb *rb; 3028 3029 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 3030 DMA_FROM_DEVICE); 3031 3032 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3033 3034 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3035 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3036 rb = (void *)(*data)->data; 3037 rb->index = cpu_to_le32(i); 3038 memcpy(rb->data, page_address(rxb->page), max_len); 3039 /* remap the page for the free benefit */ 3040 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 3041 rxb->offset, max_len, 3042 DMA_FROM_DEVICE); 3043 3044 *data = iwl_fw_error_next_data(*data); 3045 } 3046 3047 spin_unlock(&rxq->lock); 3048 3049 return rb_len; 3050 } 3051 #define IWL_CSR_TO_DUMP (0x250) 3052 3053 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3054 struct iwl_fw_error_dump_data **data) 3055 { 3056 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3057 __le32 *val; 3058 int i; 3059 3060 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3061 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3062 val = (void *)(*data)->data; 3063 3064 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3065 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3066 3067 *data = iwl_fw_error_next_data(*data); 3068 3069 return csr_len; 3070 } 3071 3072 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3073 struct iwl_fw_error_dump_data **data) 3074 { 3075 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3076 unsigned long flags; 3077 __le32 *val; 3078 int i; 3079 3080 if (!iwl_trans_grab_nic_access(trans, &flags)) 3081 return 0; 3082 3083 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3084 (*data)->len = cpu_to_le32(fh_regs_len); 3085 val = (void *)(*data)->data; 3086 3087 if (!trans->trans_cfg->gen2) 3088 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3089 i += sizeof(u32)) 3090 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3091 else 3092 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3093 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3094 i += sizeof(u32)) 3095 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3096 i)); 3097 3098 iwl_trans_release_nic_access(trans, &flags); 3099 3100 *data = iwl_fw_error_next_data(*data); 3101 3102 return sizeof(**data) + fh_regs_len; 3103 } 3104 3105 static u32 3106 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3107 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3108 u32 monitor_len) 3109 { 3110 u32 buf_size_in_dwords = (monitor_len >> 2); 3111 u32 *buffer = (u32 *)fw_mon_data->data; 3112 unsigned long flags; 3113 u32 i; 3114 3115 if (!iwl_trans_grab_nic_access(trans, &flags)) 3116 return 0; 3117 3118 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3119 for (i = 0; i < buf_size_in_dwords; i++) 3120 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3121 MON_DMARB_RD_DATA_ADDR); 3122 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3123 3124 iwl_trans_release_nic_access(trans, &flags); 3125 3126 return monitor_len; 3127 } 3128 3129 static void 3130 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3131 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3132 { 3133 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3134 3135 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3136 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3137 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3138 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3139 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3140 } else if (trans->dbg.dest_tlv) { 3141 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3142 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3143 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3144 } else { 3145 base = MON_BUFF_BASE_ADDR; 3146 write_ptr = MON_BUFF_WRPTR; 3147 wrap_cnt = MON_BUFF_CYCLE_CNT; 3148 } 3149 3150 write_ptr_val = iwl_read_prph(trans, write_ptr); 3151 fw_mon_data->fw_mon_cycle_cnt = 3152 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3153 fw_mon_data->fw_mon_base_ptr = 3154 cpu_to_le32(iwl_read_prph(trans, base)); 3155 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3156 fw_mon_data->fw_mon_base_high_ptr = 3157 cpu_to_le32(iwl_read_prph(trans, base_high)); 3158 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3159 } 3160 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3161 } 3162 3163 static u32 3164 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3165 struct iwl_fw_error_dump_data **data, 3166 u32 monitor_len) 3167 { 3168 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3169 u32 len = 0; 3170 3171 if (trans->dbg.dest_tlv || 3172 (fw_mon->size && 3173 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3174 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3175 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3176 3177 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3178 fw_mon_data = (void *)(*data)->data; 3179 3180 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3181 3182 len += sizeof(**data) + sizeof(*fw_mon_data); 3183 if (fw_mon->size) { 3184 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3185 monitor_len = fw_mon->size; 3186 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3187 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3188 /* 3189 * Update pointers to reflect actual values after 3190 * shifting 3191 */ 3192 if (trans->dbg.dest_tlv->version) { 3193 base = (iwl_read_prph(trans, base) & 3194 IWL_LDBG_M2S_BUF_BA_MSK) << 3195 trans->dbg.dest_tlv->base_shift; 3196 base *= IWL_M2S_UNIT_SIZE; 3197 base += trans->cfg->smem_offset; 3198 } else { 3199 base = iwl_read_prph(trans, base) << 3200 trans->dbg.dest_tlv->base_shift; 3201 } 3202 3203 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3204 monitor_len / sizeof(u32)); 3205 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3206 monitor_len = 3207 iwl_trans_pci_dump_marbh_monitor(trans, 3208 fw_mon_data, 3209 monitor_len); 3210 } else { 3211 /* Didn't match anything - output no monitor data */ 3212 monitor_len = 0; 3213 } 3214 3215 len += monitor_len; 3216 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3217 } 3218 3219 return len; 3220 } 3221 3222 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3223 { 3224 if (trans->dbg.fw_mon.size) { 3225 *len += sizeof(struct iwl_fw_error_dump_data) + 3226 sizeof(struct iwl_fw_error_dump_fw_mon) + 3227 trans->dbg.fw_mon.size; 3228 return trans->dbg.fw_mon.size; 3229 } else if (trans->dbg.dest_tlv) { 3230 u32 base, end, cfg_reg, monitor_len; 3231 3232 if (trans->dbg.dest_tlv->version == 1) { 3233 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3234 cfg_reg = iwl_read_prph(trans, cfg_reg); 3235 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3236 trans->dbg.dest_tlv->base_shift; 3237 base *= IWL_M2S_UNIT_SIZE; 3238 base += trans->cfg->smem_offset; 3239 3240 monitor_len = 3241 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3242 trans->dbg.dest_tlv->end_shift; 3243 monitor_len *= IWL_M2S_UNIT_SIZE; 3244 } else { 3245 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3246 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3247 3248 base = iwl_read_prph(trans, base) << 3249 trans->dbg.dest_tlv->base_shift; 3250 end = iwl_read_prph(trans, end) << 3251 trans->dbg.dest_tlv->end_shift; 3252 3253 /* Make "end" point to the actual end */ 3254 if (trans->trans_cfg->device_family >= 3255 IWL_DEVICE_FAMILY_8000 || 3256 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3257 end += (1 << trans->dbg.dest_tlv->end_shift); 3258 monitor_len = end - base; 3259 } 3260 *len += sizeof(struct iwl_fw_error_dump_data) + 3261 sizeof(struct iwl_fw_error_dump_fw_mon) + 3262 monitor_len; 3263 return monitor_len; 3264 } 3265 return 0; 3266 } 3267 3268 static struct iwl_trans_dump_data 3269 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3270 u32 dump_mask) 3271 { 3272 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3273 struct iwl_fw_error_dump_data *data; 3274 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3275 struct iwl_fw_error_dump_txcmd *txcmd; 3276 struct iwl_trans_dump_data *dump_data; 3277 u32 len, num_rbs = 0, monitor_len = 0; 3278 int i, ptr; 3279 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3280 !trans->trans_cfg->mq_rx_supported && 3281 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3282 3283 if (!dump_mask) 3284 return NULL; 3285 3286 /* transport dump header */ 3287 len = sizeof(*dump_data); 3288 3289 /* host commands */ 3290 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3291 len += sizeof(*data) + 3292 cmdq->n_window * (sizeof(*txcmd) + 3293 TFD_MAX_PAYLOAD_SIZE); 3294 3295 /* FW monitor */ 3296 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3297 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3298 3299 /* CSR registers */ 3300 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3301 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3302 3303 /* FH registers */ 3304 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3305 if (trans->trans_cfg->gen2) 3306 len += sizeof(*data) + 3307 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3308 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3309 else 3310 len += sizeof(*data) + 3311 (FH_MEM_UPPER_BOUND - 3312 FH_MEM_LOWER_BOUND); 3313 } 3314 3315 if (dump_rbs) { 3316 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3317 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3318 /* RBs */ 3319 num_rbs = 3320 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3321 & 0x0FFF; 3322 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3323 len += num_rbs * (sizeof(*data) + 3324 sizeof(struct iwl_fw_error_dump_rb) + 3325 (PAGE_SIZE << trans_pcie->rx_page_order)); 3326 } 3327 3328 /* Paged memory for gen2 HW */ 3329 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3330 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3331 len += sizeof(*data) + 3332 sizeof(struct iwl_fw_error_dump_paging) + 3333 trans->init_dram.paging[i].size; 3334 3335 dump_data = vzalloc(len); 3336 if (!dump_data) 3337 return NULL; 3338 3339 len = 0; 3340 data = (void *)dump_data->data; 3341 3342 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3343 u16 tfd_size = trans_pcie->tfd_size; 3344 3345 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3346 txcmd = (void *)data->data; 3347 spin_lock_bh(&cmdq->lock); 3348 ptr = cmdq->write_ptr; 3349 for (i = 0; i < cmdq->n_window; i++) { 3350 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3351 u8 tfdidx; 3352 u32 caplen, cmdlen; 3353 3354 if (trans->trans_cfg->use_tfh) 3355 tfdidx = idx; 3356 else 3357 tfdidx = ptr; 3358 3359 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3360 (u8 *)cmdq->tfds + 3361 tfd_size * tfdidx); 3362 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3363 3364 if (cmdlen) { 3365 len += sizeof(*txcmd) + caplen; 3366 txcmd->cmdlen = cpu_to_le32(cmdlen); 3367 txcmd->caplen = cpu_to_le32(caplen); 3368 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3369 caplen); 3370 txcmd = (void *)((u8 *)txcmd->data + caplen); 3371 } 3372 3373 ptr = iwl_queue_dec_wrap(trans, ptr); 3374 } 3375 spin_unlock_bh(&cmdq->lock); 3376 3377 data->len = cpu_to_le32(len); 3378 len += sizeof(*data); 3379 data = iwl_fw_error_next_data(data); 3380 } 3381 3382 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3383 len += iwl_trans_pcie_dump_csr(trans, &data); 3384 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3385 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3386 if (dump_rbs) 3387 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3388 3389 /* Paged memory for gen2 HW */ 3390 if (trans->trans_cfg->gen2 && 3391 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3392 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3393 struct iwl_fw_error_dump_paging *paging; 3394 u32 page_len = trans->init_dram.paging[i].size; 3395 3396 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3397 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3398 paging = (void *)data->data; 3399 paging->index = cpu_to_le32(i); 3400 memcpy(paging->data, 3401 trans->init_dram.paging[i].block, page_len); 3402 data = iwl_fw_error_next_data(data); 3403 3404 len += sizeof(*data) + sizeof(*paging) + page_len; 3405 } 3406 } 3407 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3408 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3409 3410 dump_data->len = len; 3411 3412 return dump_data; 3413 } 3414 3415 #ifdef CONFIG_PM_SLEEP 3416 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 3417 { 3418 return 0; 3419 } 3420 3421 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 3422 { 3423 } 3424 #endif /* CONFIG_PM_SLEEP */ 3425 3426 #define IWL_TRANS_COMMON_OPS \ 3427 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3428 .write8 = iwl_trans_pcie_write8, \ 3429 .write32 = iwl_trans_pcie_write32, \ 3430 .read32 = iwl_trans_pcie_read32, \ 3431 .read_prph = iwl_trans_pcie_read_prph, \ 3432 .write_prph = iwl_trans_pcie_write_prph, \ 3433 .read_mem = iwl_trans_pcie_read_mem, \ 3434 .write_mem = iwl_trans_pcie_write_mem, \ 3435 .read_config32 = iwl_trans_pcie_read_config32, \ 3436 .configure = iwl_trans_pcie_configure, \ 3437 .set_pmi = iwl_trans_pcie_set_pmi, \ 3438 .sw_reset = iwl_trans_pcie_sw_reset, \ 3439 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3440 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3441 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3442 .dump_data = iwl_trans_pcie_dump_data, \ 3443 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3444 .d3_resume = iwl_trans_pcie_d3_resume, \ 3445 .sync_nmi = iwl_trans_pcie_sync_nmi 3446 3447 #ifdef CONFIG_PM_SLEEP 3448 #define IWL_TRANS_PM_OPS \ 3449 .suspend = iwl_trans_pcie_suspend, \ 3450 .resume = iwl_trans_pcie_resume, 3451 #else 3452 #define IWL_TRANS_PM_OPS 3453 #endif /* CONFIG_PM_SLEEP */ 3454 3455 static const struct iwl_trans_ops trans_ops_pcie = { 3456 IWL_TRANS_COMMON_OPS, 3457 IWL_TRANS_PM_OPS 3458 .start_hw = iwl_trans_pcie_start_hw, 3459 .fw_alive = iwl_trans_pcie_fw_alive, 3460 .start_fw = iwl_trans_pcie_start_fw, 3461 .stop_device = iwl_trans_pcie_stop_device, 3462 3463 .send_cmd = iwl_trans_pcie_send_hcmd, 3464 3465 .tx = iwl_trans_pcie_tx, 3466 .reclaim = iwl_trans_pcie_reclaim, 3467 3468 .txq_disable = iwl_trans_pcie_txq_disable, 3469 .txq_enable = iwl_trans_pcie_txq_enable, 3470 3471 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3472 3473 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3474 3475 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 3476 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3477 #ifdef CONFIG_IWLWIFI_DEBUGFS 3478 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3479 #endif 3480 }; 3481 3482 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3483 IWL_TRANS_COMMON_OPS, 3484 IWL_TRANS_PM_OPS 3485 .start_hw = iwl_trans_pcie_start_hw, 3486 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3487 .start_fw = iwl_trans_pcie_gen2_start_fw, 3488 .stop_device = iwl_trans_pcie_gen2_stop_device, 3489 3490 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3491 3492 .tx = iwl_trans_pcie_gen2_tx, 3493 .reclaim = iwl_trans_pcie_reclaim, 3494 3495 .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, 3496 3497 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 3498 .txq_free = iwl_trans_pcie_dyn_txq_free, 3499 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3500 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3501 #ifdef CONFIG_IWLWIFI_DEBUGFS 3502 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3503 #endif 3504 }; 3505 3506 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3507 const struct pci_device_id *ent, 3508 const struct iwl_cfg_trans_params *cfg_trans) 3509 { 3510 struct iwl_trans_pcie *trans_pcie; 3511 struct iwl_trans *trans; 3512 int ret, addr_size, txcmd_size, txcmd_align; 3513 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3514 3515 if (!cfg_trans->gen2) { 3516 ops = &trans_ops_pcie; 3517 txcmd_size = sizeof(struct iwl_tx_cmd); 3518 txcmd_align = sizeof(void *); 3519 } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) { 3520 txcmd_size = sizeof(struct iwl_tx_cmd_gen2); 3521 txcmd_align = 64; 3522 } else { 3523 txcmd_size = sizeof(struct iwl_tx_cmd_gen3); 3524 txcmd_align = 128; 3525 } 3526 3527 txcmd_size += sizeof(struct iwl_cmd_header); 3528 txcmd_size += 36; /* biggest possible 802.11 header */ 3529 3530 /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */ 3531 if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align)) 3532 return ERR_PTR(-EINVAL); 3533 3534 ret = pcim_enable_device(pdev); 3535 if (ret) 3536 return ERR_PTR(ret); 3537 3538 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3539 txcmd_size, txcmd_align); 3540 if (!trans) 3541 return ERR_PTR(-ENOMEM); 3542 3543 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3544 3545 trans_pcie->trans = trans; 3546 trans_pcie->opmode_down = true; 3547 spin_lock_init(&trans_pcie->irq_lock); 3548 spin_lock_init(&trans_pcie->reg_lock); 3549 spin_lock_init(&trans_pcie->alloc_page_lock); 3550 mutex_init(&trans_pcie->mutex); 3551 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3552 3553 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3554 WQ_HIGHPRI | WQ_UNBOUND, 1); 3555 if (!trans_pcie->rba.alloc_wq) { 3556 ret = -ENOMEM; 3557 goto out_free_trans; 3558 } 3559 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3560 3561 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3562 if (!trans_pcie->tso_hdr_page) { 3563 ret = -ENOMEM; 3564 goto out_no_pci; 3565 } 3566 trans_pcie->debug_rfkill = -1; 3567 3568 if (!cfg_trans->base_params->pcie_l1_allowed) { 3569 /* 3570 * W/A - seems to solve weird behavior. We need to remove this 3571 * if we don't want to stay in L1 all the time. This wastes a 3572 * lot of power. 3573 */ 3574 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3575 PCIE_LINK_STATE_L1 | 3576 PCIE_LINK_STATE_CLKPM); 3577 } 3578 3579 trans_pcie->def_rx_queue = 0; 3580 3581 if (cfg_trans->use_tfh) { 3582 addr_size = 64; 3583 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 3584 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 3585 } else { 3586 addr_size = 36; 3587 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 3588 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 3589 } 3590 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 3591 3592 pci_set_master(pdev); 3593 3594 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3595 if (!ret) 3596 ret = pci_set_consistent_dma_mask(pdev, 3597 DMA_BIT_MASK(addr_size)); 3598 if (ret) { 3599 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3600 if (!ret) 3601 ret = pci_set_consistent_dma_mask(pdev, 3602 DMA_BIT_MASK(32)); 3603 /* both attempts failed: */ 3604 if (ret) { 3605 dev_err(&pdev->dev, "No suitable DMA available\n"); 3606 goto out_no_pci; 3607 } 3608 } 3609 3610 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3611 if (ret) { 3612 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3613 goto out_no_pci; 3614 } 3615 3616 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3617 if (!trans_pcie->hw_base) { 3618 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3619 ret = -ENODEV; 3620 goto out_no_pci; 3621 } 3622 3623 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3624 * PCI Tx retries from interfering with C3 CPU state */ 3625 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3626 3627 trans_pcie->pci_dev = pdev; 3628 iwl_disable_interrupts(trans); 3629 3630 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3631 if (trans->hw_rev == 0xffffffff) { 3632 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3633 ret = -EIO; 3634 goto out_no_pci; 3635 } 3636 3637 /* 3638 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3639 * changed, and now the revision step also includes bit 0-1 (no more 3640 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3641 * in the old format. 3642 */ 3643 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) { 3644 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3645 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3646 3647 ret = iwl_pcie_prepare_card_hw(trans); 3648 if (ret) { 3649 IWL_WARN(trans, "Exit HW not ready\n"); 3650 goto out_no_pci; 3651 } 3652 3653 /* 3654 * in-order to recognize C step driver should read chip version 3655 * id located at the AUX bus MISC address space. 3656 */ 3657 ret = iwl_finish_nic_init(trans, cfg_trans); 3658 if (ret) 3659 goto out_no_pci; 3660 3661 } 3662 3663 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3664 3665 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3666 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3667 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3668 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3669 3670 /* Initialize the wait queue for commands */ 3671 init_waitqueue_head(&trans_pcie->wait_command_queue); 3672 3673 init_waitqueue_head(&trans_pcie->sx_waitq); 3674 3675 if (trans_pcie->msix_enabled) { 3676 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3677 if (ret) 3678 goto out_no_pci; 3679 } else { 3680 ret = iwl_pcie_alloc_ict(trans); 3681 if (ret) 3682 goto out_no_pci; 3683 3684 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3685 iwl_pcie_isr, 3686 iwl_pcie_irq_handler, 3687 IRQF_SHARED, DRV_NAME, trans); 3688 if (ret) { 3689 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3690 goto out_free_ict; 3691 } 3692 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3693 } 3694 3695 #ifdef CONFIG_IWLWIFI_DEBUGFS 3696 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3697 mutex_init(&trans_pcie->fw_mon_data.mutex); 3698 #endif 3699 3700 iwl_dbg_tlv_init(trans); 3701 3702 return trans; 3703 3704 out_free_ict: 3705 iwl_pcie_free_ict(trans); 3706 out_no_pci: 3707 free_percpu(trans_pcie->tso_hdr_page); 3708 destroy_workqueue(trans_pcie->rba.alloc_wq); 3709 out_free_trans: 3710 iwl_trans_free(trans); 3711 return ERR_PTR(ret); 3712 } 3713 3714 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3715 { 3716 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3717 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3718 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 3719 u32 inta_addr, sw_err_bit; 3720 3721 if (trans_pcie->msix_enabled) { 3722 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3723 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3724 } else { 3725 inta_addr = CSR_INT; 3726 sw_err_bit = CSR_INT_BIT_SW_ERR; 3727 } 3728 3729 /* if the interrupts were already disabled, there is no point in 3730 * calling iwl_disable_interrupts 3731 */ 3732 if (interrupts_enabled) 3733 iwl_disable_interrupts(trans); 3734 3735 iwl_force_nmi(trans); 3736 while (time_after(timeout, jiffies)) { 3737 u32 inta_hw = iwl_read32(trans, inta_addr); 3738 3739 /* Error detected by uCode */ 3740 if (inta_hw & sw_err_bit) { 3741 /* Clear causes register */ 3742 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 3743 break; 3744 } 3745 3746 mdelay(1); 3747 } 3748 3749 /* enable interrupts only if there were already enabled before this 3750 * function to avoid a case were the driver enable interrupts before 3751 * proper configurations were made 3752 */ 3753 if (interrupts_enabled) 3754 iwl_enable_interrupts(trans); 3755 3756 iwl_trans_fw_error(trans); 3757 } 3758