1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2020 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 18 #include "iwl-drv.h" 19 #include "iwl-trans.h" 20 #include "iwl-csr.h" 21 #include "iwl-prph.h" 22 #include "iwl-scd.h" 23 #include "iwl-agn-hw.h" 24 #include "fw/error-dump.h" 25 #include "fw/dbg.h" 26 #include "fw/api/tx.h" 27 #include "mei/iwl-mei.h" 28 #include "internal.h" 29 #include "iwl-fh.h" 30 #include "iwl-context-info-gen3.h" 31 32 /* extended range in FW SRAM */ 33 #define IWL_FW_MEM_EXTENDED_START 0x40000 34 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35 36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37 { 38 #define PCI_DUMP_SIZE 352 39 #define PCI_MEM_DUMP_SIZE 64 40 #define PCI_PARENT_DUMP_SIZE 524 41 #define PREFIX_LEN 32 42 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43 struct pci_dev *pdev = trans_pcie->pci_dev; 44 u32 i, pos, alloc_size, *ptr, *buf; 45 char *prefix; 46 47 if (trans_pcie->pcie_dbg_dumped_once) 48 return; 49 50 /* Should be a multiple of 4 */ 51 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54 55 /* Alloc a max size buffer */ 56 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60 61 buf = kmalloc(alloc_size, GFP_ATOMIC); 62 if (!buf) 63 return; 64 prefix = (char *)buf + alloc_size - PREFIX_LEN; 65 66 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67 68 /* Print wifi device registers */ 69 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70 IWL_ERR(trans, "iwlwifi device config registers:\n"); 71 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72 if (pci_read_config_dword(pdev, i, ptr)) 73 goto err_read; 74 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75 76 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78 *ptr = iwl_read32(trans, i); 79 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80 81 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82 if (pos) { 83 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85 if (pci_read_config_dword(pdev, pos + i, ptr)) 86 goto err_read; 87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88 32, 4, buf, i, 0); 89 } 90 91 /* Print parent device registers next */ 92 if (!pdev->bus->self) 93 goto out; 94 95 pdev = pdev->bus->self; 96 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97 98 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99 pci_name(pdev)); 100 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101 if (pci_read_config_dword(pdev, i, ptr)) 102 goto err_read; 103 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104 105 /* Print root port AER registers */ 106 pos = 0; 107 pdev = pcie_find_root_port(pdev); 108 if (pdev) 109 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110 if (pos) { 111 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112 pci_name(pdev)); 113 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115 if (pci_read_config_dword(pdev, pos + i, ptr)) 116 goto err_read; 117 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118 4, buf, i, 0); 119 } 120 goto out; 121 122 err_read: 123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124 IWL_ERR(trans, "Read failed at 0x%X\n", i); 125 out: 126 trans_pcie->pcie_dbg_dumped_once = 1; 127 kfree(buf); 128 } 129 130 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 131 { 132 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 133 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 134 iwl_set_bit(trans, CSR_GP_CNTRL, 135 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 136 else 137 iwl_set_bit(trans, CSR_RESET, 138 CSR_RESET_REG_FLAG_SW_RESET); 139 usleep_range(5000, 6000); 140 } 141 142 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 143 { 144 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 145 146 if (!fw_mon->size) 147 return; 148 149 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 150 fw_mon->physical); 151 152 fw_mon->block = NULL; 153 fw_mon->physical = 0; 154 fw_mon->size = 0; 155 } 156 157 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 158 u8 max_power, u8 min_power) 159 { 160 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 161 void *block = NULL; 162 dma_addr_t physical = 0; 163 u32 size = 0; 164 u8 power; 165 166 if (fw_mon->size) 167 return; 168 169 for (power = max_power; power >= min_power; power--) { 170 size = BIT(power); 171 block = dma_alloc_coherent(trans->dev, size, &physical, 172 GFP_KERNEL | __GFP_NOWARN); 173 if (!block) 174 continue; 175 176 IWL_INFO(trans, 177 "Allocated 0x%08x bytes for firmware monitor.\n", 178 size); 179 break; 180 } 181 182 if (WARN_ON_ONCE(!block)) 183 return; 184 185 if (power != max_power) 186 IWL_ERR(trans, 187 "Sorry - debug buffer is only %luK while you requested %luK\n", 188 (unsigned long)BIT(power - 10), 189 (unsigned long)BIT(max_power - 10)); 190 191 fw_mon->block = block; 192 fw_mon->physical = physical; 193 fw_mon->size = size; 194 } 195 196 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 197 { 198 if (!max_power) { 199 /* default max_power is maximum */ 200 max_power = 26; 201 } else { 202 max_power += 11; 203 } 204 205 if (WARN(max_power > 26, 206 "External buffer size for monitor is too big %d, check the FW TLV\n", 207 max_power)) 208 return; 209 210 if (trans->dbg.fw_mon.size) 211 return; 212 213 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 214 } 215 216 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 217 { 218 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 219 ((reg & 0x0000ffff) | (2 << 28))); 220 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 221 } 222 223 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 224 { 225 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 226 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 227 ((reg & 0x0000ffff) | (3 << 28))); 228 } 229 230 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 231 { 232 if (trans->cfg->apmg_not_supported) 233 return; 234 235 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 236 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 237 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 238 ~APMG_PS_CTRL_MSK_PWR_SRC); 239 else 240 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 241 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 242 ~APMG_PS_CTRL_MSK_PWR_SRC); 243 } 244 245 /* PCI registers */ 246 #define PCI_CFG_RETRY_TIMEOUT 0x041 247 248 void iwl_pcie_apm_config(struct iwl_trans *trans) 249 { 250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251 u16 lctl; 252 u16 cap; 253 254 /* 255 * L0S states have been found to be unstable with our devices 256 * and in newer hardware they are not officially supported at 257 * all, so we must always set the L0S_DISABLED bit. 258 */ 259 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 260 261 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 262 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 263 264 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 265 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 266 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 267 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 268 trans->ltr_enabled ? "En" : "Dis"); 269 } 270 271 /* 272 * Start up NIC's basic functionality after it has been reset 273 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 274 * NOTE: This does not load uCode nor start the embedded processor 275 */ 276 static int iwl_pcie_apm_init(struct iwl_trans *trans) 277 { 278 int ret; 279 280 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 281 282 /* 283 * Use "set_bit" below rather than "write", to preserve any hardware 284 * bits already set by default after reset. 285 */ 286 287 /* Disable L0S exit timer (platform NMI Work/Around) */ 288 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 289 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 290 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 291 292 /* 293 * Disable L0s without affecting L1; 294 * don't wait for ICH L0s (ICH bug W/A) 295 */ 296 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 297 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 298 299 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 300 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 301 302 /* 303 * Enable HAP INTA (interrupt from management bus) to 304 * wake device's PCI Express link L1a -> L0s 305 */ 306 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 307 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 308 309 iwl_pcie_apm_config(trans); 310 311 /* Configure analog phase-lock-loop before activating to D0A */ 312 if (trans->trans_cfg->base_params->pll_cfg) 313 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 314 315 ret = iwl_finish_nic_init(trans); 316 if (ret) 317 return ret; 318 319 if (trans->cfg->host_interrupt_operation_mode) { 320 /* 321 * This is a bit of an abuse - This is needed for 7260 / 3160 322 * only check host_interrupt_operation_mode even if this is 323 * not related to host_interrupt_operation_mode. 324 * 325 * Enable the oscillator to count wake up time for L1 exit. This 326 * consumes slightly more power (100uA) - but allows to be sure 327 * that we wake up from L1 on time. 328 * 329 * This looks weird: read twice the same register, discard the 330 * value, set a bit, and yet again, read that same register 331 * just to discard the value. But that's the way the hardware 332 * seems to like it. 333 */ 334 iwl_read_prph(trans, OSC_CLK); 335 iwl_read_prph(trans, OSC_CLK); 336 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 337 iwl_read_prph(trans, OSC_CLK); 338 iwl_read_prph(trans, OSC_CLK); 339 } 340 341 /* 342 * Enable DMA clock and wait for it to stabilize. 343 * 344 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 345 * bits do not disable clocks. This preserves any hardware 346 * bits already set by default in "CLK_CTRL_REG" after reset. 347 */ 348 if (!trans->cfg->apmg_not_supported) { 349 iwl_write_prph(trans, APMG_CLK_EN_REG, 350 APMG_CLK_VAL_DMA_CLK_RQT); 351 udelay(20); 352 353 /* Disable L1-Active */ 354 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 355 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 356 357 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 358 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 359 APMG_RTC_INT_STT_RFKILL); 360 } 361 362 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 363 364 return 0; 365 } 366 367 /* 368 * Enable LP XTAL to avoid HW bug where device may consume much power if 369 * FW is not loaded after device reset. LP XTAL is disabled by default 370 * after device HW reset. Do it only if XTAL is fed by internal source. 371 * Configure device's "persistence" mode to avoid resetting XTAL again when 372 * SHRD_HW_RST occurs in S3. 373 */ 374 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 375 { 376 int ret; 377 u32 apmg_gp1_reg; 378 u32 apmg_xtal_cfg_reg; 379 u32 dl_cfg_reg; 380 381 /* Force XTAL ON */ 382 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 384 385 iwl_trans_pcie_sw_reset(trans); 386 387 ret = iwl_finish_nic_init(trans); 388 if (WARN_ON(ret)) { 389 /* Release XTAL ON request */ 390 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 391 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 392 return; 393 } 394 395 /* 396 * Clear "disable persistence" to avoid LP XTAL resetting when 397 * SHRD_HW_RST is applied in S3. 398 */ 399 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 400 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 401 402 /* 403 * Force APMG XTAL to be active to prevent its disabling by HW 404 * caused by APMG idle state. 405 */ 406 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 407 SHR_APMG_XTAL_CFG_REG); 408 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 409 apmg_xtal_cfg_reg | 410 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 411 412 iwl_trans_pcie_sw_reset(trans); 413 414 /* Enable LP XTAL by indirect access through CSR */ 415 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 416 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 417 SHR_APMG_GP1_WF_XTAL_LP_EN | 418 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 419 420 /* Clear delay line clock power up */ 421 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 422 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 423 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 424 425 /* 426 * Enable persistence mode to avoid LP XTAL resetting when 427 * SHRD_HW_RST is applied in S3. 428 */ 429 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 430 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 431 432 /* 433 * Clear "initialization complete" bit to move adapter from 434 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 435 */ 436 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 437 438 /* Activates XTAL resources monitor */ 439 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 440 CSR_MONITOR_XTAL_RESOURCES); 441 442 /* Release XTAL ON request */ 443 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 444 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 445 udelay(10); 446 447 /* Release APMG XTAL */ 448 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 449 apmg_xtal_cfg_reg & 450 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 451 } 452 453 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 454 { 455 int ret; 456 457 /* stop device's busmaster DMA activity */ 458 459 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 460 iwl_set_bit(trans, CSR_GP_CNTRL, 461 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 462 463 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 464 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 465 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 466 100); 467 msleep(100); 468 } else { 469 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 470 471 ret = iwl_poll_bit(trans, CSR_RESET, 472 CSR_RESET_REG_FLAG_MASTER_DISABLED, 473 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 474 } 475 476 if (ret < 0) 477 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 478 479 IWL_DEBUG_INFO(trans, "stop master\n"); 480 } 481 482 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 483 { 484 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 485 486 if (op_mode_leave) { 487 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 488 iwl_pcie_apm_init(trans); 489 490 /* inform ME that we are leaving */ 491 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 492 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 493 APMG_PCIDEV_STT_VAL_WAKE_ME); 494 else if (trans->trans_cfg->device_family >= 495 IWL_DEVICE_FAMILY_8000) { 496 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 497 CSR_RESET_LINK_PWR_MGMT_DISABLED); 498 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 499 CSR_HW_IF_CONFIG_REG_PREPARE | 500 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 501 mdelay(1); 502 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 503 CSR_RESET_LINK_PWR_MGMT_DISABLED); 504 } 505 mdelay(5); 506 } 507 508 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 509 510 /* Stop device's DMA activity */ 511 iwl_pcie_apm_stop_master(trans); 512 513 if (trans->cfg->lp_xtal_workaround) { 514 iwl_pcie_apm_lp_xtal_enable(trans); 515 return; 516 } 517 518 iwl_trans_pcie_sw_reset(trans); 519 520 /* 521 * Clear "initialization complete" bit to move adapter from 522 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 523 */ 524 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 525 } 526 527 static int iwl_pcie_nic_init(struct iwl_trans *trans) 528 { 529 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 530 int ret; 531 532 /* nic_init */ 533 spin_lock_bh(&trans_pcie->irq_lock); 534 ret = iwl_pcie_apm_init(trans); 535 spin_unlock_bh(&trans_pcie->irq_lock); 536 537 if (ret) 538 return ret; 539 540 iwl_pcie_set_pwr(trans, false); 541 542 iwl_op_mode_nic_config(trans->op_mode); 543 544 /* Allocate the RX queue, or reset if it is already allocated */ 545 ret = iwl_pcie_rx_init(trans); 546 if (ret) 547 return ret; 548 549 /* Allocate or reset and init all Tx and Command queues */ 550 if (iwl_pcie_tx_init(trans)) { 551 iwl_pcie_rx_free(trans); 552 return -ENOMEM; 553 } 554 555 if (trans->trans_cfg->base_params->shadow_reg_enable) { 556 /* enable shadow regs in HW */ 557 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 558 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 559 } 560 561 return 0; 562 } 563 564 #define HW_READY_TIMEOUT (50) 565 566 /* Note: returns poll_bit return value, which is >= 0 if success */ 567 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 568 { 569 int ret; 570 571 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 572 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 573 574 /* See if we got it */ 575 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 576 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 577 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 578 HW_READY_TIMEOUT); 579 580 if (ret >= 0) 581 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 582 583 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 584 return ret; 585 } 586 587 /* Note: returns standard 0/-ERROR code */ 588 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 589 { 590 int ret; 591 int t = 0; 592 int iter; 593 594 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 595 596 ret = iwl_pcie_set_hw_ready(trans); 597 /* If the card is ready, exit 0 */ 598 if (ret >= 0) { 599 trans->csme_own = false; 600 return 0; 601 } 602 603 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 604 CSR_RESET_LINK_PWR_MGMT_DISABLED); 605 usleep_range(1000, 2000); 606 607 for (iter = 0; iter < 10; iter++) { 608 /* If HW is not ready, prepare the conditions to check again */ 609 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 610 CSR_HW_IF_CONFIG_REG_PREPARE); 611 612 do { 613 ret = iwl_pcie_set_hw_ready(trans); 614 if (ret >= 0) { 615 trans->csme_own = false; 616 return 0; 617 } 618 619 if (iwl_mei_is_connected()) { 620 IWL_DEBUG_INFO(trans, 621 "Couldn't prepare the card but SAP is connected\n"); 622 trans->csme_own = true; 623 if (trans->trans_cfg->device_family != 624 IWL_DEVICE_FAMILY_9000) 625 IWL_ERR(trans, 626 "SAP not supported for this NIC family\n"); 627 628 return -EBUSY; 629 } 630 631 usleep_range(200, 1000); 632 t += 200; 633 } while (t < 150000); 634 msleep(25); 635 } 636 637 IWL_ERR(trans, "Couldn't prepare the card\n"); 638 639 return ret; 640 } 641 642 /* 643 * ucode 644 */ 645 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 646 u32 dst_addr, dma_addr_t phy_addr, 647 u32 byte_cnt) 648 { 649 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 650 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 651 652 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 653 dst_addr); 654 655 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 656 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 657 658 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 659 (iwl_get_dma_hi_addr(phy_addr) 660 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 661 662 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 663 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 664 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 665 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 666 667 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 668 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 669 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 670 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 671 } 672 673 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 674 u32 dst_addr, dma_addr_t phy_addr, 675 u32 byte_cnt) 676 { 677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 678 int ret; 679 680 trans_pcie->ucode_write_complete = false; 681 682 if (!iwl_trans_grab_nic_access(trans)) 683 return -EIO; 684 685 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 686 byte_cnt); 687 iwl_trans_release_nic_access(trans); 688 689 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 690 trans_pcie->ucode_write_complete, 5 * HZ); 691 if (!ret) { 692 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 693 iwl_trans_pcie_dump_regs(trans); 694 return -ETIMEDOUT; 695 } 696 697 return 0; 698 } 699 700 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 701 const struct fw_desc *section) 702 { 703 u8 *v_addr; 704 dma_addr_t p_addr; 705 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 706 int ret = 0; 707 708 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 709 section_num); 710 711 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 712 GFP_KERNEL | __GFP_NOWARN); 713 if (!v_addr) { 714 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 715 chunk_sz = PAGE_SIZE; 716 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 717 &p_addr, GFP_KERNEL); 718 if (!v_addr) 719 return -ENOMEM; 720 } 721 722 for (offset = 0; offset < section->len; offset += chunk_sz) { 723 u32 copy_size, dst_addr; 724 bool extended_addr = false; 725 726 copy_size = min_t(u32, chunk_sz, section->len - offset); 727 dst_addr = section->offset + offset; 728 729 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 730 dst_addr <= IWL_FW_MEM_EXTENDED_END) 731 extended_addr = true; 732 733 if (extended_addr) 734 iwl_set_bits_prph(trans, LMPM_CHICK, 735 LMPM_CHICK_EXTENDED_ADDR_SPACE); 736 737 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 738 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 739 copy_size); 740 741 if (extended_addr) 742 iwl_clear_bits_prph(trans, LMPM_CHICK, 743 LMPM_CHICK_EXTENDED_ADDR_SPACE); 744 745 if (ret) { 746 IWL_ERR(trans, 747 "Could not load the [%d] uCode section\n", 748 section_num); 749 break; 750 } 751 } 752 753 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 754 return ret; 755 } 756 757 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 758 const struct fw_img *image, 759 int cpu, 760 int *first_ucode_section) 761 { 762 int shift_param; 763 int i, ret = 0, sec_num = 0x1; 764 u32 val, last_read_idx = 0; 765 766 if (cpu == 1) { 767 shift_param = 0; 768 *first_ucode_section = 0; 769 } else { 770 shift_param = 16; 771 (*first_ucode_section)++; 772 } 773 774 for (i = *first_ucode_section; i < image->num_sec; i++) { 775 last_read_idx = i; 776 777 /* 778 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 779 * CPU1 to CPU2. 780 * PAGING_SEPARATOR_SECTION delimiter - separate between 781 * CPU2 non paged to CPU2 paging sec. 782 */ 783 if (!image->sec[i].data || 784 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 785 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 786 IWL_DEBUG_FW(trans, 787 "Break since Data not valid or Empty section, sec = %d\n", 788 i); 789 break; 790 } 791 792 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 793 if (ret) 794 return ret; 795 796 /* Notify ucode of loaded section number and status */ 797 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 798 val = val | (sec_num << shift_param); 799 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 800 801 sec_num = (sec_num << 1) | 0x1; 802 } 803 804 *first_ucode_section = last_read_idx; 805 806 iwl_enable_interrupts(trans); 807 808 if (trans->trans_cfg->use_tfh) { 809 if (cpu == 1) 810 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 811 0xFFFF); 812 else 813 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 814 0xFFFFFFFF); 815 } else { 816 if (cpu == 1) 817 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 818 0xFFFF); 819 else 820 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 821 0xFFFFFFFF); 822 } 823 824 return 0; 825 } 826 827 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 828 const struct fw_img *image, 829 int cpu, 830 int *first_ucode_section) 831 { 832 int i, ret = 0; 833 u32 last_read_idx = 0; 834 835 if (cpu == 1) 836 *first_ucode_section = 0; 837 else 838 (*first_ucode_section)++; 839 840 for (i = *first_ucode_section; i < image->num_sec; i++) { 841 last_read_idx = i; 842 843 /* 844 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 845 * CPU1 to CPU2. 846 * PAGING_SEPARATOR_SECTION delimiter - separate between 847 * CPU2 non paged to CPU2 paging sec. 848 */ 849 if (!image->sec[i].data || 850 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 851 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 852 IWL_DEBUG_FW(trans, 853 "Break since Data not valid or Empty section, sec = %d\n", 854 i); 855 break; 856 } 857 858 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 859 if (ret) 860 return ret; 861 } 862 863 *first_ucode_section = last_read_idx; 864 865 return 0; 866 } 867 868 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 869 { 870 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 871 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 872 &trans->dbg.fw_mon_cfg[alloc_id]; 873 struct iwl_dram_data *frag; 874 875 if (!iwl_trans_dbg_ini_valid(trans)) 876 return; 877 878 if (le32_to_cpu(fw_mon_cfg->buf_location) == 879 IWL_FW_INI_LOCATION_SRAM_PATH) { 880 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 881 /* set sram monitor by enabling bit 7 */ 882 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 883 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 884 885 return; 886 } 887 888 if (le32_to_cpu(fw_mon_cfg->buf_location) != 889 IWL_FW_INI_LOCATION_DRAM_PATH || 890 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 891 return; 892 893 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 894 895 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 896 alloc_id); 897 898 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 899 frag->physical >> MON_BUFF_SHIFT_VER2); 900 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 901 (frag->physical + frag->size - 256) >> 902 MON_BUFF_SHIFT_VER2); 903 } 904 905 void iwl_pcie_apply_destination(struct iwl_trans *trans) 906 { 907 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 908 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 909 int i; 910 911 if (iwl_trans_dbg_ini_valid(trans)) { 912 iwl_pcie_apply_destination_ini(trans); 913 return; 914 } 915 916 IWL_INFO(trans, "Applying debug destination %s\n", 917 get_fw_dbg_mode_string(dest->monitor_mode)); 918 919 if (dest->monitor_mode == EXTERNAL_MODE) 920 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 921 else 922 IWL_WARN(trans, "PCI should have external buffer debug\n"); 923 924 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 925 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 926 u32 val = le32_to_cpu(dest->reg_ops[i].val); 927 928 switch (dest->reg_ops[i].op) { 929 case CSR_ASSIGN: 930 iwl_write32(trans, addr, val); 931 break; 932 case CSR_SETBIT: 933 iwl_set_bit(trans, addr, BIT(val)); 934 break; 935 case CSR_CLEARBIT: 936 iwl_clear_bit(trans, addr, BIT(val)); 937 break; 938 case PRPH_ASSIGN: 939 iwl_write_prph(trans, addr, val); 940 break; 941 case PRPH_SETBIT: 942 iwl_set_bits_prph(trans, addr, BIT(val)); 943 break; 944 case PRPH_CLEARBIT: 945 iwl_clear_bits_prph(trans, addr, BIT(val)); 946 break; 947 case PRPH_BLOCKBIT: 948 if (iwl_read_prph(trans, addr) & BIT(val)) { 949 IWL_ERR(trans, 950 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 951 val, addr); 952 goto monitor; 953 } 954 break; 955 default: 956 IWL_ERR(trans, "FW debug - unknown OP %d\n", 957 dest->reg_ops[i].op); 958 break; 959 } 960 } 961 962 monitor: 963 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 964 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 965 fw_mon->physical >> dest->base_shift); 966 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 967 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 968 (fw_mon->physical + fw_mon->size - 969 256) >> dest->end_shift); 970 else 971 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 972 (fw_mon->physical + fw_mon->size) >> 973 dest->end_shift); 974 } 975 } 976 977 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 978 const struct fw_img *image) 979 { 980 int ret = 0; 981 int first_ucode_section; 982 983 IWL_DEBUG_FW(trans, "working with %s CPU\n", 984 image->is_dual_cpus ? "Dual" : "Single"); 985 986 /* load to FW the binary non secured sections of CPU1 */ 987 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 988 if (ret) 989 return ret; 990 991 if (image->is_dual_cpus) { 992 /* set CPU2 header address */ 993 iwl_write_prph(trans, 994 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 995 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 996 997 /* load to FW the binary sections of CPU2 */ 998 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 999 &first_ucode_section); 1000 if (ret) 1001 return ret; 1002 } 1003 1004 if (iwl_pcie_dbg_on(trans)) 1005 iwl_pcie_apply_destination(trans); 1006 1007 iwl_enable_interrupts(trans); 1008 1009 /* release CPU reset */ 1010 iwl_write32(trans, CSR_RESET, 0); 1011 1012 return 0; 1013 } 1014 1015 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1016 const struct fw_img *image) 1017 { 1018 int ret = 0; 1019 int first_ucode_section; 1020 1021 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1022 image->is_dual_cpus ? "Dual" : "Single"); 1023 1024 if (iwl_pcie_dbg_on(trans)) 1025 iwl_pcie_apply_destination(trans); 1026 1027 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1028 iwl_read_prph(trans, WFPM_GP2)); 1029 1030 /* 1031 * Set default value. On resume reading the values that were 1032 * zeored can provide debug data on the resume flow. 1033 * This is for debugging only and has no functional impact. 1034 */ 1035 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1036 1037 /* configure the ucode to be ready to get the secured image */ 1038 /* release CPU reset */ 1039 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1040 1041 /* load to FW the binary Secured sections of CPU1 */ 1042 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1043 &first_ucode_section); 1044 if (ret) 1045 return ret; 1046 1047 /* load to FW the binary sections of CPU2 */ 1048 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1049 &first_ucode_section); 1050 } 1051 1052 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1053 { 1054 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1055 bool hw_rfkill = iwl_is_rfkill_set(trans); 1056 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1057 bool report; 1058 1059 if (hw_rfkill) { 1060 set_bit(STATUS_RFKILL_HW, &trans->status); 1061 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1062 } else { 1063 clear_bit(STATUS_RFKILL_HW, &trans->status); 1064 if (trans_pcie->opmode_down) 1065 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1066 } 1067 1068 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1069 1070 if (prev != report) 1071 iwl_trans_pcie_rf_kill(trans, report); 1072 1073 return hw_rfkill; 1074 } 1075 1076 struct iwl_causes_list { 1077 u32 cause_num; 1078 u32 mask_reg; 1079 u8 addr; 1080 }; 1081 1082 static const struct iwl_causes_list causes_list_common[] = { 1083 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1084 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1085 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1086 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1087 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1088 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1089 {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 1090 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1091 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1092 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1093 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1094 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1095 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1096 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1097 }; 1098 1099 static const struct iwl_causes_list causes_list_pre_bz[] = { 1100 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1101 }; 1102 1103 static const struct iwl_causes_list causes_list_bz[] = { 1104 {MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1105 }; 1106 1107 static void iwl_pcie_map_list(struct iwl_trans *trans, 1108 const struct iwl_causes_list *causes, 1109 int arr_size, int val) 1110 { 1111 int i; 1112 1113 for (i = 0; i < arr_size; i++) { 1114 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1115 iwl_clear_bit(trans, causes[i].mask_reg, 1116 causes[i].cause_num); 1117 } 1118 } 1119 1120 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1121 { 1122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1123 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1124 /* 1125 * Access all non RX causes and map them to the default irq. 1126 * In case we are missing at least one interrupt vector, 1127 * the first interrupt vector will serve non-RX and FBQ causes. 1128 */ 1129 iwl_pcie_map_list(trans, causes_list_common, 1130 ARRAY_SIZE(causes_list_common), val); 1131 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1132 iwl_pcie_map_list(trans, causes_list_bz, 1133 ARRAY_SIZE(causes_list_bz), val); 1134 else 1135 iwl_pcie_map_list(trans, causes_list_pre_bz, 1136 ARRAY_SIZE(causes_list_pre_bz), val); 1137 } 1138 1139 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1140 { 1141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1142 u32 offset = 1143 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1144 u32 val, idx; 1145 1146 /* 1147 * The first RX queue - fallback queue, which is designated for 1148 * management frame, command responses etc, is always mapped to the 1149 * first interrupt vector. The other RX queues are mapped to 1150 * the other (N - 2) interrupt vectors. 1151 */ 1152 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1153 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1154 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1155 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1156 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1157 } 1158 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1159 1160 val = MSIX_FH_INT_CAUSES_Q(0); 1161 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1162 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1163 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1164 1165 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1166 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1167 } 1168 1169 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1170 { 1171 struct iwl_trans *trans = trans_pcie->trans; 1172 1173 if (!trans_pcie->msix_enabled) { 1174 if (trans->trans_cfg->mq_rx_supported && 1175 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1176 iwl_write_umac_prph(trans, UREG_CHICK, 1177 UREG_CHICK_MSI_ENABLE); 1178 return; 1179 } 1180 /* 1181 * The IVAR table needs to be configured again after reset, 1182 * but if the device is disabled, we can't write to 1183 * prph. 1184 */ 1185 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1186 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1187 1188 /* 1189 * Each cause from the causes list above and the RX causes is 1190 * represented as a byte in the IVAR table. The first nibble 1191 * represents the bound interrupt vector of the cause, the second 1192 * represents no auto clear for this cause. This will be set if its 1193 * interrupt vector is bound to serve other causes. 1194 */ 1195 iwl_pcie_map_rx_causes(trans); 1196 1197 iwl_pcie_map_non_rx_causes(trans); 1198 } 1199 1200 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1201 { 1202 struct iwl_trans *trans = trans_pcie->trans; 1203 1204 iwl_pcie_conf_msix_hw(trans_pcie); 1205 1206 if (!trans_pcie->msix_enabled) 1207 return; 1208 1209 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1210 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1211 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1212 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1213 } 1214 1215 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1216 { 1217 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1218 1219 lockdep_assert_held(&trans_pcie->mutex); 1220 1221 if (trans_pcie->is_down) 1222 return; 1223 1224 trans_pcie->is_down = true; 1225 1226 /* tell the device to stop sending interrupts */ 1227 iwl_disable_interrupts(trans); 1228 1229 /* device going down, Stop using ICT table */ 1230 iwl_pcie_disable_ict(trans); 1231 1232 /* 1233 * If a HW restart happens during firmware loading, 1234 * then the firmware loading might call this function 1235 * and later it might be called again due to the 1236 * restart. So don't process again if the device is 1237 * already dead. 1238 */ 1239 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1240 IWL_DEBUG_INFO(trans, 1241 "DEVICE_ENABLED bit was set and is now cleared\n"); 1242 iwl_pcie_tx_stop(trans); 1243 iwl_pcie_rx_stop(trans); 1244 1245 /* Power-down device's busmaster DMA clocks */ 1246 if (!trans->cfg->apmg_not_supported) { 1247 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1248 APMG_CLK_VAL_DMA_CLK_RQT); 1249 udelay(5); 1250 } 1251 } 1252 1253 /* Make sure (redundant) we've released our request to stay awake */ 1254 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1255 iwl_clear_bit(trans, CSR_GP_CNTRL, 1256 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1257 else 1258 iwl_clear_bit(trans, CSR_GP_CNTRL, 1259 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1260 1261 /* Stop the device, and put it in low power state */ 1262 iwl_pcie_apm_stop(trans, false); 1263 1264 iwl_trans_pcie_sw_reset(trans); 1265 1266 /* 1267 * Upon stop, the IVAR table gets erased, so msi-x won't 1268 * work. This causes a bug in RF-KILL flows, since the interrupt 1269 * that enables radio won't fire on the correct irq, and the 1270 * driver won't be able to handle the interrupt. 1271 * Configure the IVAR table again after reset. 1272 */ 1273 iwl_pcie_conf_msix_hw(trans_pcie); 1274 1275 /* 1276 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1277 * This is a bug in certain verions of the hardware. 1278 * Certain devices also keep sending HW RF kill interrupt all 1279 * the time, unless the interrupt is ACKed even if the interrupt 1280 * should be masked. Re-ACK all the interrupts here. 1281 */ 1282 iwl_disable_interrupts(trans); 1283 1284 /* clear all status bits */ 1285 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1286 clear_bit(STATUS_INT_ENABLED, &trans->status); 1287 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1288 1289 /* 1290 * Even if we stop the HW, we still want the RF kill 1291 * interrupt 1292 */ 1293 iwl_enable_rfkill_int(trans); 1294 1295 /* re-take ownership to prevent other users from stealing the device */ 1296 iwl_pcie_prepare_card_hw(trans); 1297 } 1298 1299 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1300 { 1301 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1302 1303 if (trans_pcie->msix_enabled) { 1304 int i; 1305 1306 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1307 synchronize_irq(trans_pcie->msix_entries[i].vector); 1308 } else { 1309 synchronize_irq(trans_pcie->pci_dev->irq); 1310 } 1311 } 1312 1313 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1314 const struct fw_img *fw, bool run_in_rfkill) 1315 { 1316 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1317 bool hw_rfkill; 1318 int ret; 1319 1320 /* This may fail if AMT took ownership of the device */ 1321 if (iwl_pcie_prepare_card_hw(trans)) { 1322 IWL_WARN(trans, "Exit HW not ready\n"); 1323 ret = -EIO; 1324 goto out; 1325 } 1326 1327 iwl_enable_rfkill_int(trans); 1328 1329 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1330 1331 /* 1332 * We enabled the RF-Kill interrupt and the handler may very 1333 * well be running. Disable the interrupts to make sure no other 1334 * interrupt can be fired. 1335 */ 1336 iwl_disable_interrupts(trans); 1337 1338 /* Make sure it finished running */ 1339 iwl_pcie_synchronize_irqs(trans); 1340 1341 mutex_lock(&trans_pcie->mutex); 1342 1343 /* If platform's RF_KILL switch is NOT set to KILL */ 1344 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1345 if (hw_rfkill && !run_in_rfkill) { 1346 ret = -ERFKILL; 1347 goto out; 1348 } 1349 1350 /* Someone called stop_device, don't try to start_fw */ 1351 if (trans_pcie->is_down) { 1352 IWL_WARN(trans, 1353 "Can't start_fw since the HW hasn't been started\n"); 1354 ret = -EIO; 1355 goto out; 1356 } 1357 1358 /* make sure rfkill handshake bits are cleared */ 1359 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1360 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1361 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1362 1363 /* clear (again), then enable host interrupts */ 1364 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1365 1366 ret = iwl_pcie_nic_init(trans); 1367 if (ret) { 1368 IWL_ERR(trans, "Unable to init nic\n"); 1369 goto out; 1370 } 1371 1372 /* 1373 * Now, we load the firmware and don't want to be interrupted, even 1374 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1375 * FH_TX interrupt which is needed to load the firmware). If the 1376 * RF-Kill switch is toggled, we will find out after having loaded 1377 * the firmware and return the proper value to the caller. 1378 */ 1379 iwl_enable_fw_load_int(trans); 1380 1381 /* really make sure rfkill handshake bits are cleared */ 1382 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1383 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1384 1385 /* Load the given image to the HW */ 1386 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1387 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1388 else 1389 ret = iwl_pcie_load_given_ucode(trans, fw); 1390 1391 /* re-check RF-Kill state since we may have missed the interrupt */ 1392 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1393 if (hw_rfkill && !run_in_rfkill) 1394 ret = -ERFKILL; 1395 1396 out: 1397 mutex_unlock(&trans_pcie->mutex); 1398 return ret; 1399 } 1400 1401 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1402 { 1403 iwl_pcie_reset_ict(trans); 1404 iwl_pcie_tx_start(trans, scd_addr); 1405 } 1406 1407 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1408 bool was_in_rfkill) 1409 { 1410 bool hw_rfkill; 1411 1412 /* 1413 * Check again since the RF kill state may have changed while 1414 * all the interrupts were disabled, in this case we couldn't 1415 * receive the RF kill interrupt and update the state in the 1416 * op_mode. 1417 * Don't call the op_mode if the rkfill state hasn't changed. 1418 * This allows the op_mode to call stop_device from the rfkill 1419 * notification without endless recursion. Under very rare 1420 * circumstances, we might have a small recursion if the rfkill 1421 * state changed exactly now while we were called from stop_device. 1422 * This is very unlikely but can happen and is supported. 1423 */ 1424 hw_rfkill = iwl_is_rfkill_set(trans); 1425 if (hw_rfkill) { 1426 set_bit(STATUS_RFKILL_HW, &trans->status); 1427 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1428 } else { 1429 clear_bit(STATUS_RFKILL_HW, &trans->status); 1430 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1431 } 1432 if (hw_rfkill != was_in_rfkill) 1433 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1434 } 1435 1436 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1437 { 1438 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1439 bool was_in_rfkill; 1440 1441 iwl_op_mode_time_point(trans->op_mode, 1442 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1443 NULL); 1444 1445 mutex_lock(&trans_pcie->mutex); 1446 trans_pcie->opmode_down = true; 1447 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1448 _iwl_trans_pcie_stop_device(trans); 1449 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1450 mutex_unlock(&trans_pcie->mutex); 1451 } 1452 1453 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1454 { 1455 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1456 IWL_TRANS_GET_PCIE_TRANS(trans); 1457 1458 lockdep_assert_held(&trans_pcie->mutex); 1459 1460 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1461 state ? "disabled" : "enabled"); 1462 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1463 if (trans->trans_cfg->gen2) 1464 _iwl_trans_pcie_gen2_stop_device(trans); 1465 else 1466 _iwl_trans_pcie_stop_device(trans); 1467 } 1468 } 1469 1470 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1471 bool test, bool reset) 1472 { 1473 iwl_disable_interrupts(trans); 1474 1475 /* 1476 * in testing mode, the host stays awake and the 1477 * hardware won't be reset (not even partially) 1478 */ 1479 if (test) 1480 return; 1481 1482 iwl_pcie_disable_ict(trans); 1483 1484 iwl_pcie_synchronize_irqs(trans); 1485 1486 iwl_clear_bit(trans, CSR_GP_CNTRL, 1487 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1488 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1489 1490 if (reset) { 1491 /* 1492 * reset TX queues -- some of their registers reset during S3 1493 * so if we don't reset everything here the D3 image would try 1494 * to execute some invalid memory upon resume 1495 */ 1496 iwl_trans_pcie_tx_reset(trans); 1497 } 1498 1499 iwl_pcie_set_pwr(trans, true); 1500 } 1501 1502 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1503 bool reset) 1504 { 1505 int ret; 1506 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1507 1508 if (!reset) 1509 /* Enable persistence mode to avoid reset */ 1510 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1511 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1512 1513 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1514 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1515 UREG_DOORBELL_TO_ISR6_SUSPEND); 1516 1517 ret = wait_event_timeout(trans_pcie->sx_waitq, 1518 trans_pcie->sx_complete, 2 * HZ); 1519 /* 1520 * Invalidate it toward resume. 1521 */ 1522 trans_pcie->sx_complete = false; 1523 1524 if (!ret) { 1525 IWL_ERR(trans, "Timeout entering D3\n"); 1526 return -ETIMEDOUT; 1527 } 1528 } 1529 iwl_pcie_d3_complete_suspend(trans, test, reset); 1530 1531 return 0; 1532 } 1533 1534 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1535 enum iwl_d3_status *status, 1536 bool test, bool reset) 1537 { 1538 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1539 u32 val; 1540 int ret; 1541 1542 if (test) { 1543 iwl_enable_interrupts(trans); 1544 *status = IWL_D3_STATUS_ALIVE; 1545 goto out; 1546 } 1547 1548 iwl_set_bit(trans, CSR_GP_CNTRL, 1549 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1550 1551 ret = iwl_finish_nic_init(trans); 1552 if (ret) 1553 return ret; 1554 1555 /* 1556 * Reconfigure IVAR table in case of MSIX or reset ict table in 1557 * MSI mode since HW reset erased it. 1558 * Also enables interrupts - none will happen as 1559 * the device doesn't know we're waking it up, only when 1560 * the opmode actually tells it after this call. 1561 */ 1562 iwl_pcie_conf_msix_hw(trans_pcie); 1563 if (!trans_pcie->msix_enabled) 1564 iwl_pcie_reset_ict(trans); 1565 iwl_enable_interrupts(trans); 1566 1567 iwl_pcie_set_pwr(trans, false); 1568 1569 if (!reset) { 1570 iwl_clear_bit(trans, CSR_GP_CNTRL, 1571 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1572 } else { 1573 iwl_trans_pcie_tx_reset(trans); 1574 1575 ret = iwl_pcie_rx_init(trans); 1576 if (ret) { 1577 IWL_ERR(trans, 1578 "Failed to resume the device (RX reset)\n"); 1579 return ret; 1580 } 1581 } 1582 1583 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1584 iwl_read_umac_prph(trans, WFPM_GP2)); 1585 1586 val = iwl_read32(trans, CSR_RESET); 1587 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1588 *status = IWL_D3_STATUS_RESET; 1589 else 1590 *status = IWL_D3_STATUS_ALIVE; 1591 1592 out: 1593 if (*status == IWL_D3_STATUS_ALIVE && 1594 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1595 trans_pcie->sx_complete = false; 1596 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1597 UREG_DOORBELL_TO_ISR6_RESUME); 1598 1599 ret = wait_event_timeout(trans_pcie->sx_waitq, 1600 trans_pcie->sx_complete, 2 * HZ); 1601 /* 1602 * Invalidate it toward next suspend. 1603 */ 1604 trans_pcie->sx_complete = false; 1605 1606 if (!ret) { 1607 IWL_ERR(trans, "Timeout exiting D3\n"); 1608 return -ETIMEDOUT; 1609 } 1610 } 1611 return 0; 1612 } 1613 1614 static void 1615 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1616 struct iwl_trans *trans, 1617 const struct iwl_cfg_trans_params *cfg_trans) 1618 { 1619 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1620 int max_irqs, num_irqs, i, ret; 1621 u16 pci_cmd; 1622 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1623 1624 if (!cfg_trans->mq_rx_supported) 1625 goto enable_msi; 1626 1627 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1628 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1629 1630 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1631 for (i = 0; i < max_irqs; i++) 1632 trans_pcie->msix_entries[i].entry = i; 1633 1634 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1635 MSIX_MIN_INTERRUPT_VECTORS, 1636 max_irqs); 1637 if (num_irqs < 0) { 1638 IWL_DEBUG_INFO(trans, 1639 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1640 num_irqs); 1641 goto enable_msi; 1642 } 1643 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1644 1645 IWL_DEBUG_INFO(trans, 1646 "MSI-X enabled. %d interrupt vectors were allocated\n", 1647 num_irqs); 1648 1649 /* 1650 * In case the OS provides fewer interrupts than requested, different 1651 * causes will share the same interrupt vector as follows: 1652 * One interrupt less: non rx causes shared with FBQ. 1653 * Two interrupts less: non rx causes shared with FBQ and RSS. 1654 * More than two interrupts: we will use fewer RSS queues. 1655 */ 1656 if (num_irqs <= max_irqs - 2) { 1657 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1658 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1659 IWL_SHARED_IRQ_FIRST_RSS; 1660 } else if (num_irqs == max_irqs - 1) { 1661 trans_pcie->trans->num_rx_queues = num_irqs; 1662 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1663 } else { 1664 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1665 } 1666 1667 IWL_DEBUG_INFO(trans, 1668 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1669 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1670 1671 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1672 1673 trans_pcie->alloc_vecs = num_irqs; 1674 trans_pcie->msix_enabled = true; 1675 return; 1676 1677 enable_msi: 1678 ret = pci_enable_msi(pdev); 1679 if (ret) { 1680 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1681 /* enable rfkill interrupt: hw bug w/a */ 1682 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1683 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1684 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1685 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1686 } 1687 } 1688 } 1689 1690 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1691 { 1692 int iter_rx_q, i, ret, cpu, offset; 1693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1694 1695 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1696 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1697 offset = 1 + i; 1698 for (; i < iter_rx_q ; i++) { 1699 /* 1700 * Get the cpu prior to the place to search 1701 * (i.e. return will be > i - 1). 1702 */ 1703 cpu = cpumask_next(i - offset, cpu_online_mask); 1704 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1705 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1706 &trans_pcie->affinity_mask[i]); 1707 if (ret) 1708 IWL_ERR(trans_pcie->trans, 1709 "Failed to set affinity mask for IRQ %d\n", 1710 trans_pcie->msix_entries[i].vector); 1711 } 1712 } 1713 1714 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1715 struct iwl_trans_pcie *trans_pcie) 1716 { 1717 int i; 1718 1719 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1720 int ret; 1721 struct msix_entry *msix_entry; 1722 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1723 1724 if (!qname) 1725 return -ENOMEM; 1726 1727 msix_entry = &trans_pcie->msix_entries[i]; 1728 ret = devm_request_threaded_irq(&pdev->dev, 1729 msix_entry->vector, 1730 iwl_pcie_msix_isr, 1731 (i == trans_pcie->def_irq) ? 1732 iwl_pcie_irq_msix_handler : 1733 iwl_pcie_irq_rx_msix_handler, 1734 IRQF_SHARED, 1735 qname, 1736 msix_entry); 1737 if (ret) { 1738 IWL_ERR(trans_pcie->trans, 1739 "Error allocating IRQ %d\n", i); 1740 1741 return ret; 1742 } 1743 } 1744 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1745 1746 return 0; 1747 } 1748 1749 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1750 { 1751 u32 hpm, wprot; 1752 1753 switch (trans->trans_cfg->device_family) { 1754 case IWL_DEVICE_FAMILY_9000: 1755 wprot = PREG_PRPH_WPROT_9000; 1756 break; 1757 case IWL_DEVICE_FAMILY_22000: 1758 wprot = PREG_PRPH_WPROT_22000; 1759 break; 1760 default: 1761 return 0; 1762 } 1763 1764 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1765 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1766 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1767 1768 if (wprot_val & PREG_WFPM_ACCESS) { 1769 IWL_ERR(trans, 1770 "Error, can not clear persistence bit\n"); 1771 return -EPERM; 1772 } 1773 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1774 hpm & ~PERSISTENCE_BIT); 1775 } 1776 1777 return 0; 1778 } 1779 1780 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1781 { 1782 int ret; 1783 1784 ret = iwl_finish_nic_init(trans); 1785 if (ret < 0) 1786 return ret; 1787 1788 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1789 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1790 udelay(20); 1791 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1792 HPM_HIPM_GEN_CFG_CR_PG_EN | 1793 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1794 udelay(20); 1795 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1796 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1797 1798 iwl_trans_pcie_sw_reset(trans); 1799 1800 return 0; 1801 } 1802 1803 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1804 { 1805 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1806 int err; 1807 1808 lockdep_assert_held(&trans_pcie->mutex); 1809 1810 err = iwl_pcie_prepare_card_hw(trans); 1811 if (err) { 1812 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1813 return err; 1814 } 1815 1816 err = iwl_trans_pcie_clear_persistence_bit(trans); 1817 if (err) 1818 return err; 1819 1820 iwl_trans_pcie_sw_reset(trans); 1821 1822 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1823 trans->trans_cfg->integrated) { 1824 err = iwl_pcie_gen2_force_power_gating(trans); 1825 if (err) 1826 return err; 1827 } 1828 1829 err = iwl_pcie_apm_init(trans); 1830 if (err) 1831 return err; 1832 1833 iwl_pcie_init_msix(trans_pcie); 1834 1835 /* From now on, the op_mode will be kept updated about RF kill state */ 1836 iwl_enable_rfkill_int(trans); 1837 1838 trans_pcie->opmode_down = false; 1839 1840 /* Set is_down to false here so that...*/ 1841 trans_pcie->is_down = false; 1842 1843 /* ...rfkill can call stop_device and set it false if needed */ 1844 iwl_pcie_check_hw_rf_kill(trans); 1845 1846 return 0; 1847 } 1848 1849 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1850 { 1851 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1852 int ret; 1853 1854 mutex_lock(&trans_pcie->mutex); 1855 ret = _iwl_trans_pcie_start_hw(trans); 1856 mutex_unlock(&trans_pcie->mutex); 1857 1858 return ret; 1859 } 1860 1861 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1862 { 1863 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1864 1865 mutex_lock(&trans_pcie->mutex); 1866 1867 /* disable interrupts - don't enable HW RF kill interrupt */ 1868 iwl_disable_interrupts(trans); 1869 1870 iwl_pcie_apm_stop(trans, true); 1871 1872 iwl_disable_interrupts(trans); 1873 1874 iwl_pcie_disable_ict(trans); 1875 1876 mutex_unlock(&trans_pcie->mutex); 1877 1878 iwl_pcie_synchronize_irqs(trans); 1879 } 1880 1881 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1882 { 1883 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1884 } 1885 1886 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1887 { 1888 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1889 } 1890 1891 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1892 { 1893 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1894 } 1895 1896 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1897 { 1898 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1899 return 0x00FFFFFF; 1900 else 1901 return 0x000FFFFF; 1902 } 1903 1904 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1905 { 1906 u32 mask = iwl_trans_pcie_prph_msk(trans); 1907 1908 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1909 ((reg & mask) | (3 << 24))); 1910 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1911 } 1912 1913 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1914 u32 val) 1915 { 1916 u32 mask = iwl_trans_pcie_prph_msk(trans); 1917 1918 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1919 ((addr & mask) | (3 << 24))); 1920 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1921 } 1922 1923 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1924 const struct iwl_trans_config *trans_cfg) 1925 { 1926 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1927 1928 /* free all first - we might be reconfigured for a different size */ 1929 iwl_pcie_free_rbs_pool(trans); 1930 1931 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 1932 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 1933 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1934 trans->txqs.page_offs = trans_cfg->cb_data_offs; 1935 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1936 1937 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1938 trans_pcie->n_no_reclaim_cmds = 0; 1939 else 1940 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1941 if (trans_pcie->n_no_reclaim_cmds) 1942 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1943 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1944 1945 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1946 trans_pcie->rx_page_order = 1947 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1948 trans_pcie->rx_buf_bytes = 1949 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1950 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1951 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1952 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1953 1954 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1955 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1956 1957 trans->command_groups = trans_cfg->command_groups; 1958 trans->command_groups_size = trans_cfg->command_groups_size; 1959 1960 /* Initialize NAPI here - it should be before registering to mac80211 1961 * in the opmode but after the HW struct is allocated. 1962 * As this function may be called again in some corner cases don't 1963 * do anything if NAPI was already initialized. 1964 */ 1965 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1966 init_dummy_netdev(&trans_pcie->napi_dev); 1967 1968 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1969 } 1970 1971 void iwl_trans_pcie_free(struct iwl_trans *trans) 1972 { 1973 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1974 int i; 1975 1976 iwl_pcie_synchronize_irqs(trans); 1977 1978 if (trans->trans_cfg->gen2) 1979 iwl_txq_gen2_tx_free(trans); 1980 else 1981 iwl_pcie_tx_free(trans); 1982 iwl_pcie_rx_free(trans); 1983 1984 if (trans_pcie->rba.alloc_wq) { 1985 destroy_workqueue(trans_pcie->rba.alloc_wq); 1986 trans_pcie->rba.alloc_wq = NULL; 1987 } 1988 1989 if (trans_pcie->msix_enabled) { 1990 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1991 irq_set_affinity_hint( 1992 trans_pcie->msix_entries[i].vector, 1993 NULL); 1994 } 1995 1996 trans_pcie->msix_enabled = false; 1997 } else { 1998 iwl_pcie_free_ict(trans); 1999 } 2000 2001 iwl_pcie_free_fw_monitor(trans); 2002 2003 if (trans_pcie->pnvm_dram.size) 2004 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 2005 trans_pcie->pnvm_dram.block, 2006 trans_pcie->pnvm_dram.physical); 2007 2008 if (trans_pcie->reduce_power_dram.size) 2009 dma_free_coherent(trans->dev, 2010 trans_pcie->reduce_power_dram.size, 2011 trans_pcie->reduce_power_dram.block, 2012 trans_pcie->reduce_power_dram.physical); 2013 2014 mutex_destroy(&trans_pcie->mutex); 2015 iwl_trans_free(trans); 2016 } 2017 2018 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2019 { 2020 if (state) 2021 set_bit(STATUS_TPOWER_PMI, &trans->status); 2022 else 2023 clear_bit(STATUS_TPOWER_PMI, &trans->status); 2024 } 2025 2026 struct iwl_trans_pcie_removal { 2027 struct pci_dev *pdev; 2028 struct work_struct work; 2029 }; 2030 2031 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2032 { 2033 struct iwl_trans_pcie_removal *removal = 2034 container_of(wk, struct iwl_trans_pcie_removal, work); 2035 struct pci_dev *pdev = removal->pdev; 2036 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2037 2038 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2039 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2040 pci_lock_rescan_remove(); 2041 pci_dev_put(pdev); 2042 pci_stop_and_remove_bus_device(pdev); 2043 pci_unlock_rescan_remove(); 2044 2045 kfree(removal); 2046 module_put(THIS_MODULE); 2047 } 2048 2049 /* 2050 * This version doesn't disable BHs but rather assumes they're 2051 * already disabled. 2052 */ 2053 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2054 { 2055 int ret; 2056 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2057 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2058 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2059 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2060 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2061 2062 spin_lock(&trans_pcie->reg_lock); 2063 2064 if (trans_pcie->cmd_hold_nic_awake) 2065 goto out; 2066 2067 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2068 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2069 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2070 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2071 } 2072 2073 /* this bit wakes up the NIC */ 2074 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2075 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2076 udelay(2); 2077 2078 /* 2079 * These bits say the device is running, and should keep running for 2080 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2081 * but they do not indicate that embedded SRAM is restored yet; 2082 * HW with volatile SRAM must save/restore contents to/from 2083 * host DRAM when sleeping/waking for power-saving. 2084 * Each direction takes approximately 1/4 millisecond; with this 2085 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2086 * series of register accesses are expected (e.g. reading Event Log), 2087 * to keep device from sleeping. 2088 * 2089 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2090 * SRAM is okay/restored. We don't check that here because this call 2091 * is just for hardware register access; but GP1 MAC_SLEEP 2092 * check is a good idea before accessing the SRAM of HW with 2093 * volatile SRAM (e.g. reading Event Log). 2094 * 2095 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2096 * and do not save/restore SRAM when power cycling. 2097 */ 2098 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2099 if (unlikely(ret < 0)) { 2100 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2101 2102 WARN_ONCE(1, 2103 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2104 cntrl); 2105 2106 iwl_trans_pcie_dump_regs(trans); 2107 2108 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 2109 struct iwl_trans_pcie_removal *removal; 2110 2111 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2112 goto err; 2113 2114 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2115 2116 /* 2117 * get a module reference to avoid doing this 2118 * while unloading anyway and to avoid 2119 * scheduling a work with code that's being 2120 * removed. 2121 */ 2122 if (!try_module_get(THIS_MODULE)) { 2123 IWL_ERR(trans, 2124 "Module is being unloaded - abort\n"); 2125 goto err; 2126 } 2127 2128 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2129 if (!removal) { 2130 module_put(THIS_MODULE); 2131 goto err; 2132 } 2133 /* 2134 * we don't need to clear this flag, because 2135 * the trans will be freed and reallocated. 2136 */ 2137 set_bit(STATUS_TRANS_DEAD, &trans->status); 2138 2139 removal->pdev = to_pci_dev(trans->dev); 2140 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2141 pci_dev_get(removal->pdev); 2142 schedule_work(&removal->work); 2143 } else { 2144 iwl_write32(trans, CSR_RESET, 2145 CSR_RESET_REG_FLAG_FORCE_NMI); 2146 } 2147 2148 err: 2149 spin_unlock(&trans_pcie->reg_lock); 2150 return false; 2151 } 2152 2153 out: 2154 /* 2155 * Fool sparse by faking we release the lock - sparse will 2156 * track nic_access anyway. 2157 */ 2158 __release(&trans_pcie->reg_lock); 2159 return true; 2160 } 2161 2162 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2163 { 2164 bool ret; 2165 2166 local_bh_disable(); 2167 ret = __iwl_trans_pcie_grab_nic_access(trans); 2168 if (ret) { 2169 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2170 return ret; 2171 } 2172 local_bh_enable(); 2173 return false; 2174 } 2175 2176 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2177 { 2178 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2179 2180 lockdep_assert_held(&trans_pcie->reg_lock); 2181 2182 /* 2183 * Fool sparse by faking we acquiring the lock - sparse will 2184 * track nic_access anyway. 2185 */ 2186 __acquire(&trans_pcie->reg_lock); 2187 2188 if (trans_pcie->cmd_hold_nic_awake) 2189 goto out; 2190 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2191 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2192 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2193 else 2194 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2195 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2196 /* 2197 * Above we read the CSR_GP_CNTRL register, which will flush 2198 * any previous writes, but we need the write that clears the 2199 * MAC_ACCESS_REQ bit to be performed before any other writes 2200 * scheduled on different CPUs (after we drop reg_lock). 2201 */ 2202 out: 2203 spin_unlock_bh(&trans_pcie->reg_lock); 2204 } 2205 2206 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2207 void *buf, int dwords) 2208 { 2209 int offs = 0; 2210 u32 *vals = buf; 2211 2212 while (offs < dwords) { 2213 /* limit the time we spin here under lock to 1/2s */ 2214 unsigned long end = jiffies + HZ / 2; 2215 bool resched = false; 2216 2217 if (iwl_trans_grab_nic_access(trans)) { 2218 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2219 addr + 4 * offs); 2220 2221 while (offs < dwords) { 2222 vals[offs] = iwl_read32(trans, 2223 HBUS_TARG_MEM_RDAT); 2224 offs++; 2225 2226 if (time_after(jiffies, end)) { 2227 resched = true; 2228 break; 2229 } 2230 } 2231 iwl_trans_release_nic_access(trans); 2232 2233 if (resched) 2234 cond_resched(); 2235 } else { 2236 return -EBUSY; 2237 } 2238 } 2239 2240 return 0; 2241 } 2242 2243 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2244 const void *buf, int dwords) 2245 { 2246 int offs, ret = 0; 2247 const u32 *vals = buf; 2248 2249 if (iwl_trans_grab_nic_access(trans)) { 2250 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2251 for (offs = 0; offs < dwords; offs++) 2252 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2253 vals ? vals[offs] : 0); 2254 iwl_trans_release_nic_access(trans); 2255 } else { 2256 ret = -EBUSY; 2257 } 2258 return ret; 2259 } 2260 2261 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2262 u32 *val) 2263 { 2264 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2265 ofs, val); 2266 } 2267 2268 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2269 { 2270 int i; 2271 2272 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2273 struct iwl_txq *txq = trans->txqs.txq[i]; 2274 2275 if (i == trans->txqs.cmd.q_id) 2276 continue; 2277 2278 spin_lock_bh(&txq->lock); 2279 2280 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2281 txq->block--; 2282 if (!txq->block) { 2283 iwl_write32(trans, HBUS_TARG_WRPTR, 2284 txq->write_ptr | (i << 8)); 2285 } 2286 } else if (block) { 2287 txq->block++; 2288 } 2289 2290 spin_unlock_bh(&txq->lock); 2291 } 2292 } 2293 2294 #define IWL_FLUSH_WAIT_MS 2000 2295 2296 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2297 struct iwl_trans_rxq_dma_data *data) 2298 { 2299 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2300 2301 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2302 return -EINVAL; 2303 2304 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2305 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2306 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2307 data->fr_bd_wid = 0; 2308 2309 return 0; 2310 } 2311 2312 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2313 { 2314 struct iwl_txq *txq; 2315 unsigned long now = jiffies; 2316 bool overflow_tx; 2317 u8 wr_ptr; 2318 2319 /* Make sure the NIC is still alive in the bus */ 2320 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2321 return -ENODEV; 2322 2323 if (!test_bit(txq_idx, trans->txqs.queue_used)) 2324 return -EINVAL; 2325 2326 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2327 txq = trans->txqs.txq[txq_idx]; 2328 2329 spin_lock_bh(&txq->lock); 2330 overflow_tx = txq->overflow_tx || 2331 !skb_queue_empty(&txq->overflow_q); 2332 spin_unlock_bh(&txq->lock); 2333 2334 wr_ptr = READ_ONCE(txq->write_ptr); 2335 2336 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2337 overflow_tx) && 2338 !time_after(jiffies, 2339 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2340 u8 write_ptr = READ_ONCE(txq->write_ptr); 2341 2342 /* 2343 * If write pointer moved during the wait, warn only 2344 * if the TX came from op mode. In case TX came from 2345 * trans layer (overflow TX) don't warn. 2346 */ 2347 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2348 "WR pointer moved while flushing %d -> %d\n", 2349 wr_ptr, write_ptr)) 2350 return -ETIMEDOUT; 2351 wr_ptr = write_ptr; 2352 2353 usleep_range(1000, 2000); 2354 2355 spin_lock_bh(&txq->lock); 2356 overflow_tx = txq->overflow_tx || 2357 !skb_queue_empty(&txq->overflow_q); 2358 spin_unlock_bh(&txq->lock); 2359 } 2360 2361 if (txq->read_ptr != txq->write_ptr) { 2362 IWL_ERR(trans, 2363 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2364 iwl_txq_log_scd_error(trans, txq); 2365 return -ETIMEDOUT; 2366 } 2367 2368 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2369 2370 return 0; 2371 } 2372 2373 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2374 { 2375 int cnt; 2376 int ret = 0; 2377 2378 /* waiting for all the tx frames complete might take a while */ 2379 for (cnt = 0; 2380 cnt < trans->trans_cfg->base_params->num_of_queues; 2381 cnt++) { 2382 2383 if (cnt == trans->txqs.cmd.q_id) 2384 continue; 2385 if (!test_bit(cnt, trans->txqs.queue_used)) 2386 continue; 2387 if (!(BIT(cnt) & txq_bm)) 2388 continue; 2389 2390 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2391 if (ret) 2392 break; 2393 } 2394 2395 return ret; 2396 } 2397 2398 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2399 u32 mask, u32 value) 2400 { 2401 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2402 2403 spin_lock_bh(&trans_pcie->reg_lock); 2404 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2405 spin_unlock_bh(&trans_pcie->reg_lock); 2406 } 2407 2408 static const char *get_csr_string(int cmd) 2409 { 2410 #define IWL_CMD(x) case x: return #x 2411 switch (cmd) { 2412 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2413 IWL_CMD(CSR_INT_COALESCING); 2414 IWL_CMD(CSR_INT); 2415 IWL_CMD(CSR_INT_MASK); 2416 IWL_CMD(CSR_FH_INT_STATUS); 2417 IWL_CMD(CSR_GPIO_IN); 2418 IWL_CMD(CSR_RESET); 2419 IWL_CMD(CSR_GP_CNTRL); 2420 IWL_CMD(CSR_HW_REV); 2421 IWL_CMD(CSR_EEPROM_REG); 2422 IWL_CMD(CSR_EEPROM_GP); 2423 IWL_CMD(CSR_OTP_GP_REG); 2424 IWL_CMD(CSR_GIO_REG); 2425 IWL_CMD(CSR_GP_UCODE_REG); 2426 IWL_CMD(CSR_GP_DRIVER_REG); 2427 IWL_CMD(CSR_UCODE_DRV_GP1); 2428 IWL_CMD(CSR_UCODE_DRV_GP2); 2429 IWL_CMD(CSR_LED_REG); 2430 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2431 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2432 IWL_CMD(CSR_ANA_PLL_CFG); 2433 IWL_CMD(CSR_HW_REV_WA_REG); 2434 IWL_CMD(CSR_MONITOR_STATUS_REG); 2435 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2436 default: 2437 return "UNKNOWN"; 2438 } 2439 #undef IWL_CMD 2440 } 2441 2442 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2443 { 2444 int i; 2445 static const u32 csr_tbl[] = { 2446 CSR_HW_IF_CONFIG_REG, 2447 CSR_INT_COALESCING, 2448 CSR_INT, 2449 CSR_INT_MASK, 2450 CSR_FH_INT_STATUS, 2451 CSR_GPIO_IN, 2452 CSR_RESET, 2453 CSR_GP_CNTRL, 2454 CSR_HW_REV, 2455 CSR_EEPROM_REG, 2456 CSR_EEPROM_GP, 2457 CSR_OTP_GP_REG, 2458 CSR_GIO_REG, 2459 CSR_GP_UCODE_REG, 2460 CSR_GP_DRIVER_REG, 2461 CSR_UCODE_DRV_GP1, 2462 CSR_UCODE_DRV_GP2, 2463 CSR_LED_REG, 2464 CSR_DRAM_INT_TBL_REG, 2465 CSR_GIO_CHICKEN_BITS, 2466 CSR_ANA_PLL_CFG, 2467 CSR_MONITOR_STATUS_REG, 2468 CSR_HW_REV_WA_REG, 2469 CSR_DBG_HPET_MEM_REG 2470 }; 2471 IWL_ERR(trans, "CSR values:\n"); 2472 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2473 "CSR_INT_PERIODIC_REG)\n"); 2474 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2475 IWL_ERR(trans, " %25s: 0X%08x\n", 2476 get_csr_string(csr_tbl[i]), 2477 iwl_read32(trans, csr_tbl[i])); 2478 } 2479 } 2480 2481 #ifdef CONFIG_IWLWIFI_DEBUGFS 2482 /* create and remove of files */ 2483 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2484 debugfs_create_file(#name, mode, parent, trans, \ 2485 &iwl_dbgfs_##name##_ops); \ 2486 } while (0) 2487 2488 /* file operation */ 2489 #define DEBUGFS_READ_FILE_OPS(name) \ 2490 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2491 .read = iwl_dbgfs_##name##_read, \ 2492 .open = simple_open, \ 2493 .llseek = generic_file_llseek, \ 2494 }; 2495 2496 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2497 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2498 .write = iwl_dbgfs_##name##_write, \ 2499 .open = simple_open, \ 2500 .llseek = generic_file_llseek, \ 2501 }; 2502 2503 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2504 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2505 .write = iwl_dbgfs_##name##_write, \ 2506 .read = iwl_dbgfs_##name##_read, \ 2507 .open = simple_open, \ 2508 .llseek = generic_file_llseek, \ 2509 }; 2510 2511 struct iwl_dbgfs_tx_queue_priv { 2512 struct iwl_trans *trans; 2513 }; 2514 2515 struct iwl_dbgfs_tx_queue_state { 2516 loff_t pos; 2517 }; 2518 2519 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2520 { 2521 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2522 struct iwl_dbgfs_tx_queue_state *state; 2523 2524 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2525 return NULL; 2526 2527 state = kmalloc(sizeof(*state), GFP_KERNEL); 2528 if (!state) 2529 return NULL; 2530 state->pos = *pos; 2531 return state; 2532 } 2533 2534 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2535 void *v, loff_t *pos) 2536 { 2537 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2538 struct iwl_dbgfs_tx_queue_state *state = v; 2539 2540 *pos = ++state->pos; 2541 2542 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2543 return NULL; 2544 2545 return state; 2546 } 2547 2548 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2549 { 2550 kfree(v); 2551 } 2552 2553 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2554 { 2555 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2556 struct iwl_dbgfs_tx_queue_state *state = v; 2557 struct iwl_trans *trans = priv->trans; 2558 struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2559 2560 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2561 (unsigned int)state->pos, 2562 !!test_bit(state->pos, trans->txqs.queue_used), 2563 !!test_bit(state->pos, trans->txqs.queue_stopped)); 2564 if (txq) 2565 seq_printf(seq, 2566 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2567 txq->read_ptr, txq->write_ptr, 2568 txq->need_update, txq->frozen, 2569 txq->n_window, txq->ampdu); 2570 else 2571 seq_puts(seq, "(unallocated)"); 2572 2573 if (state->pos == trans->txqs.cmd.q_id) 2574 seq_puts(seq, " (HCMD)"); 2575 seq_puts(seq, "\n"); 2576 2577 return 0; 2578 } 2579 2580 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2581 .start = iwl_dbgfs_tx_queue_seq_start, 2582 .next = iwl_dbgfs_tx_queue_seq_next, 2583 .stop = iwl_dbgfs_tx_queue_seq_stop, 2584 .show = iwl_dbgfs_tx_queue_seq_show, 2585 }; 2586 2587 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2588 { 2589 struct iwl_dbgfs_tx_queue_priv *priv; 2590 2591 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2592 sizeof(*priv)); 2593 2594 if (!priv) 2595 return -ENOMEM; 2596 2597 priv->trans = inode->i_private; 2598 return 0; 2599 } 2600 2601 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2602 char __user *user_buf, 2603 size_t count, loff_t *ppos) 2604 { 2605 struct iwl_trans *trans = file->private_data; 2606 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2607 char *buf; 2608 int pos = 0, i, ret; 2609 size_t bufsz; 2610 2611 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2612 2613 if (!trans_pcie->rxq) 2614 return -EAGAIN; 2615 2616 buf = kzalloc(bufsz, GFP_KERNEL); 2617 if (!buf) 2618 return -ENOMEM; 2619 2620 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2621 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2622 2623 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2624 i); 2625 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2626 rxq->read); 2627 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2628 rxq->write); 2629 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2630 rxq->write_actual); 2631 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2632 rxq->need_update); 2633 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2634 rxq->free_count); 2635 if (rxq->rb_stts) { 2636 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2637 rxq)); 2638 pos += scnprintf(buf + pos, bufsz - pos, 2639 "\tclosed_rb_num: %u\n", 2640 r & 0x0FFF); 2641 } else { 2642 pos += scnprintf(buf + pos, bufsz - pos, 2643 "\tclosed_rb_num: Not Allocated\n"); 2644 } 2645 } 2646 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2647 kfree(buf); 2648 2649 return ret; 2650 } 2651 2652 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2653 char __user *user_buf, 2654 size_t count, loff_t *ppos) 2655 { 2656 struct iwl_trans *trans = file->private_data; 2657 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2658 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2659 2660 int pos = 0; 2661 char *buf; 2662 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2663 ssize_t ret; 2664 2665 buf = kzalloc(bufsz, GFP_KERNEL); 2666 if (!buf) 2667 return -ENOMEM; 2668 2669 pos += scnprintf(buf + pos, bufsz - pos, 2670 "Interrupt Statistics Report:\n"); 2671 2672 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2673 isr_stats->hw); 2674 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2675 isr_stats->sw); 2676 if (isr_stats->sw || isr_stats->hw) { 2677 pos += scnprintf(buf + pos, bufsz - pos, 2678 "\tLast Restarting Code: 0x%X\n", 2679 isr_stats->err_code); 2680 } 2681 #ifdef CONFIG_IWLWIFI_DEBUG 2682 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2683 isr_stats->sch); 2684 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2685 isr_stats->alive); 2686 #endif 2687 pos += scnprintf(buf + pos, bufsz - pos, 2688 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2689 2690 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2691 isr_stats->ctkill); 2692 2693 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2694 isr_stats->wakeup); 2695 2696 pos += scnprintf(buf + pos, bufsz - pos, 2697 "Rx command responses:\t\t %u\n", isr_stats->rx); 2698 2699 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2700 isr_stats->tx); 2701 2702 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2703 isr_stats->unhandled); 2704 2705 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2706 kfree(buf); 2707 return ret; 2708 } 2709 2710 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2711 const char __user *user_buf, 2712 size_t count, loff_t *ppos) 2713 { 2714 struct iwl_trans *trans = file->private_data; 2715 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2716 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2717 u32 reset_flag; 2718 int ret; 2719 2720 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2721 if (ret) 2722 return ret; 2723 if (reset_flag == 0) 2724 memset(isr_stats, 0, sizeof(*isr_stats)); 2725 2726 return count; 2727 } 2728 2729 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2730 const char __user *user_buf, 2731 size_t count, loff_t *ppos) 2732 { 2733 struct iwl_trans *trans = file->private_data; 2734 2735 iwl_pcie_dump_csr(trans); 2736 2737 return count; 2738 } 2739 2740 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2741 char __user *user_buf, 2742 size_t count, loff_t *ppos) 2743 { 2744 struct iwl_trans *trans = file->private_data; 2745 char *buf = NULL; 2746 ssize_t ret; 2747 2748 ret = iwl_dump_fh(trans, &buf); 2749 if (ret < 0) 2750 return ret; 2751 if (!buf) 2752 return -EINVAL; 2753 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2754 kfree(buf); 2755 return ret; 2756 } 2757 2758 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2759 char __user *user_buf, 2760 size_t count, loff_t *ppos) 2761 { 2762 struct iwl_trans *trans = file->private_data; 2763 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2764 char buf[100]; 2765 int pos; 2766 2767 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2768 trans_pcie->debug_rfkill, 2769 !(iwl_read32(trans, CSR_GP_CNTRL) & 2770 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2771 2772 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2773 } 2774 2775 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2776 const char __user *user_buf, 2777 size_t count, loff_t *ppos) 2778 { 2779 struct iwl_trans *trans = file->private_data; 2780 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2781 bool new_value; 2782 int ret; 2783 2784 ret = kstrtobool_from_user(user_buf, count, &new_value); 2785 if (ret) 2786 return ret; 2787 if (new_value == trans_pcie->debug_rfkill) 2788 return count; 2789 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2790 trans_pcie->debug_rfkill, new_value); 2791 trans_pcie->debug_rfkill = new_value; 2792 iwl_pcie_handle_rfkill_irq(trans); 2793 2794 return count; 2795 } 2796 2797 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2798 struct file *file) 2799 { 2800 struct iwl_trans *trans = inode->i_private; 2801 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2802 2803 if (!trans->dbg.dest_tlv || 2804 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2805 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2806 return -ENOENT; 2807 } 2808 2809 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2810 return -EBUSY; 2811 2812 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2813 return simple_open(inode, file); 2814 } 2815 2816 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2817 struct file *file) 2818 { 2819 struct iwl_trans_pcie *trans_pcie = 2820 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2821 2822 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2823 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2824 return 0; 2825 } 2826 2827 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2828 void *buf, ssize_t *size, 2829 ssize_t *bytes_copied) 2830 { 2831 int buf_size_left = count - *bytes_copied; 2832 2833 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2834 if (*size > buf_size_left) 2835 *size = buf_size_left; 2836 2837 *size -= copy_to_user(user_buf, buf, *size); 2838 *bytes_copied += *size; 2839 2840 if (buf_size_left == *size) 2841 return true; 2842 return false; 2843 } 2844 2845 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2846 char __user *user_buf, 2847 size_t count, loff_t *ppos) 2848 { 2849 struct iwl_trans *trans = file->private_data; 2850 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2851 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2852 struct cont_rec *data = &trans_pcie->fw_mon_data; 2853 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2854 ssize_t size, bytes_copied = 0; 2855 bool b_full; 2856 2857 if (trans->dbg.dest_tlv) { 2858 write_ptr_addr = 2859 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2860 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2861 } else { 2862 write_ptr_addr = MON_BUFF_WRPTR; 2863 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2864 } 2865 2866 if (unlikely(!trans->dbg.rec_on)) 2867 return 0; 2868 2869 mutex_lock(&data->mutex); 2870 if (data->state == 2871 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2872 mutex_unlock(&data->mutex); 2873 return 0; 2874 } 2875 2876 /* write_ptr position in bytes rather then DW */ 2877 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2878 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2879 2880 if (data->prev_wrap_cnt == wrap_cnt) { 2881 size = write_ptr - data->prev_wr_ptr; 2882 curr_buf = cpu_addr + data->prev_wr_ptr; 2883 b_full = iwl_write_to_user_buf(user_buf, count, 2884 curr_buf, &size, 2885 &bytes_copied); 2886 data->prev_wr_ptr += size; 2887 2888 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2889 write_ptr < data->prev_wr_ptr) { 2890 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2891 curr_buf = cpu_addr + data->prev_wr_ptr; 2892 b_full = iwl_write_to_user_buf(user_buf, count, 2893 curr_buf, &size, 2894 &bytes_copied); 2895 data->prev_wr_ptr += size; 2896 2897 if (!b_full) { 2898 size = write_ptr; 2899 b_full = iwl_write_to_user_buf(user_buf, count, 2900 cpu_addr, &size, 2901 &bytes_copied); 2902 data->prev_wr_ptr = size; 2903 data->prev_wrap_cnt++; 2904 } 2905 } else { 2906 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2907 write_ptr > data->prev_wr_ptr) 2908 IWL_WARN(trans, 2909 "write pointer passed previous write pointer, start copying from the beginning\n"); 2910 else if (!unlikely(data->prev_wrap_cnt == 0 && 2911 data->prev_wr_ptr == 0)) 2912 IWL_WARN(trans, 2913 "monitor data is out of sync, start copying from the beginning\n"); 2914 2915 size = write_ptr; 2916 b_full = iwl_write_to_user_buf(user_buf, count, 2917 cpu_addr, &size, 2918 &bytes_copied); 2919 data->prev_wr_ptr = size; 2920 data->prev_wrap_cnt = wrap_cnt; 2921 } 2922 2923 mutex_unlock(&data->mutex); 2924 2925 return bytes_copied; 2926 } 2927 2928 static ssize_t iwl_dbgfs_rf_read(struct file *file, 2929 char __user *user_buf, 2930 size_t count, loff_t *ppos) 2931 { 2932 struct iwl_trans *trans = file->private_data; 2933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2934 2935 if (!trans_pcie->rf_name[0]) 2936 return -ENODEV; 2937 2938 return simple_read_from_buffer(user_buf, count, ppos, 2939 trans_pcie->rf_name, 2940 strlen(trans_pcie->rf_name)); 2941 } 2942 2943 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2944 DEBUGFS_READ_FILE_OPS(fh_reg); 2945 DEBUGFS_READ_FILE_OPS(rx_queue); 2946 DEBUGFS_WRITE_FILE_OPS(csr); 2947 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2948 DEBUGFS_READ_FILE_OPS(rf); 2949 2950 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2951 .owner = THIS_MODULE, 2952 .open = iwl_dbgfs_tx_queue_open, 2953 .read = seq_read, 2954 .llseek = seq_lseek, 2955 .release = seq_release_private, 2956 }; 2957 2958 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2959 .read = iwl_dbgfs_monitor_data_read, 2960 .open = iwl_dbgfs_monitor_data_open, 2961 .release = iwl_dbgfs_monitor_data_release, 2962 }; 2963 2964 /* Create the debugfs files and directories */ 2965 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2966 { 2967 struct dentry *dir = trans->dbgfs_dir; 2968 2969 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 2970 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 2971 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 2972 DEBUGFS_ADD_FILE(csr, dir, 0200); 2973 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 2974 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2975 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2976 DEBUGFS_ADD_FILE(rf, dir, 0400); 2977 } 2978 2979 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2980 { 2981 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2982 struct cont_rec *data = &trans_pcie->fw_mon_data; 2983 2984 mutex_lock(&data->mutex); 2985 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2986 mutex_unlock(&data->mutex); 2987 } 2988 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2989 2990 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2991 { 2992 u32 cmdlen = 0; 2993 int i; 2994 2995 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 2996 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 2997 2998 return cmdlen; 2999 } 3000 3001 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3002 struct iwl_fw_error_dump_data **data, 3003 int allocated_rb_nums) 3004 { 3005 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3006 int max_len = trans_pcie->rx_buf_bytes; 3007 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3008 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3009 u32 i, r, j, rb_len = 0; 3010 3011 spin_lock(&rxq->lock); 3012 3013 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3014 3015 for (i = rxq->read, j = 0; 3016 i != r && j < allocated_rb_nums; 3017 i = (i + 1) & RX_QUEUE_MASK, j++) { 3018 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3019 struct iwl_fw_error_dump_rb *rb; 3020 3021 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3022 max_len, DMA_FROM_DEVICE); 3023 3024 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3025 3026 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3027 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3028 rb = (void *)(*data)->data; 3029 rb->index = cpu_to_le32(i); 3030 memcpy(rb->data, page_address(rxb->page), max_len); 3031 3032 *data = iwl_fw_error_next_data(*data); 3033 } 3034 3035 spin_unlock(&rxq->lock); 3036 3037 return rb_len; 3038 } 3039 #define IWL_CSR_TO_DUMP (0x250) 3040 3041 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3042 struct iwl_fw_error_dump_data **data) 3043 { 3044 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3045 __le32 *val; 3046 int i; 3047 3048 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3049 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3050 val = (void *)(*data)->data; 3051 3052 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3053 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3054 3055 *data = iwl_fw_error_next_data(*data); 3056 3057 return csr_len; 3058 } 3059 3060 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3061 struct iwl_fw_error_dump_data **data) 3062 { 3063 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3064 __le32 *val; 3065 int i; 3066 3067 if (!iwl_trans_grab_nic_access(trans)) 3068 return 0; 3069 3070 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3071 (*data)->len = cpu_to_le32(fh_regs_len); 3072 val = (void *)(*data)->data; 3073 3074 if (!trans->trans_cfg->gen2) 3075 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3076 i += sizeof(u32)) 3077 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3078 else 3079 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3080 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3081 i += sizeof(u32)) 3082 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3083 i)); 3084 3085 iwl_trans_release_nic_access(trans); 3086 3087 *data = iwl_fw_error_next_data(*data); 3088 3089 return sizeof(**data) + fh_regs_len; 3090 } 3091 3092 static u32 3093 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3094 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3095 u32 monitor_len) 3096 { 3097 u32 buf_size_in_dwords = (monitor_len >> 2); 3098 u32 *buffer = (u32 *)fw_mon_data->data; 3099 u32 i; 3100 3101 if (!iwl_trans_grab_nic_access(trans)) 3102 return 0; 3103 3104 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3105 for (i = 0; i < buf_size_in_dwords; i++) 3106 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3107 MON_DMARB_RD_DATA_ADDR); 3108 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3109 3110 iwl_trans_release_nic_access(trans); 3111 3112 return monitor_len; 3113 } 3114 3115 static void 3116 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3117 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3118 { 3119 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3120 3121 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3122 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3123 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3124 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3125 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3126 } else if (trans->dbg.dest_tlv) { 3127 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3128 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3129 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3130 } else { 3131 base = MON_BUFF_BASE_ADDR; 3132 write_ptr = MON_BUFF_WRPTR; 3133 wrap_cnt = MON_BUFF_CYCLE_CNT; 3134 } 3135 3136 write_ptr_val = iwl_read_prph(trans, write_ptr); 3137 fw_mon_data->fw_mon_cycle_cnt = 3138 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3139 fw_mon_data->fw_mon_base_ptr = 3140 cpu_to_le32(iwl_read_prph(trans, base)); 3141 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3142 fw_mon_data->fw_mon_base_high_ptr = 3143 cpu_to_le32(iwl_read_prph(trans, base_high)); 3144 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3145 /* convert wrtPtr to DWs, to align with all HWs */ 3146 write_ptr_val >>= 2; 3147 } 3148 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3149 } 3150 3151 static u32 3152 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3153 struct iwl_fw_error_dump_data **data, 3154 u32 monitor_len) 3155 { 3156 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3157 u32 len = 0; 3158 3159 if (trans->dbg.dest_tlv || 3160 (fw_mon->size && 3161 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3162 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3163 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3164 3165 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3166 fw_mon_data = (void *)(*data)->data; 3167 3168 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3169 3170 len += sizeof(**data) + sizeof(*fw_mon_data); 3171 if (fw_mon->size) { 3172 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3173 monitor_len = fw_mon->size; 3174 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3175 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3176 /* 3177 * Update pointers to reflect actual values after 3178 * shifting 3179 */ 3180 if (trans->dbg.dest_tlv->version) { 3181 base = (iwl_read_prph(trans, base) & 3182 IWL_LDBG_M2S_BUF_BA_MSK) << 3183 trans->dbg.dest_tlv->base_shift; 3184 base *= IWL_M2S_UNIT_SIZE; 3185 base += trans->cfg->smem_offset; 3186 } else { 3187 base = iwl_read_prph(trans, base) << 3188 trans->dbg.dest_tlv->base_shift; 3189 } 3190 3191 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3192 monitor_len / sizeof(u32)); 3193 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3194 monitor_len = 3195 iwl_trans_pci_dump_marbh_monitor(trans, 3196 fw_mon_data, 3197 monitor_len); 3198 } else { 3199 /* Didn't match anything - output no monitor data */ 3200 monitor_len = 0; 3201 } 3202 3203 len += monitor_len; 3204 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3205 } 3206 3207 return len; 3208 } 3209 3210 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3211 { 3212 if (trans->dbg.fw_mon.size) { 3213 *len += sizeof(struct iwl_fw_error_dump_data) + 3214 sizeof(struct iwl_fw_error_dump_fw_mon) + 3215 trans->dbg.fw_mon.size; 3216 return trans->dbg.fw_mon.size; 3217 } else if (trans->dbg.dest_tlv) { 3218 u32 base, end, cfg_reg, monitor_len; 3219 3220 if (trans->dbg.dest_tlv->version == 1) { 3221 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3222 cfg_reg = iwl_read_prph(trans, cfg_reg); 3223 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3224 trans->dbg.dest_tlv->base_shift; 3225 base *= IWL_M2S_UNIT_SIZE; 3226 base += trans->cfg->smem_offset; 3227 3228 monitor_len = 3229 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3230 trans->dbg.dest_tlv->end_shift; 3231 monitor_len *= IWL_M2S_UNIT_SIZE; 3232 } else { 3233 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3234 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3235 3236 base = iwl_read_prph(trans, base) << 3237 trans->dbg.dest_tlv->base_shift; 3238 end = iwl_read_prph(trans, end) << 3239 trans->dbg.dest_tlv->end_shift; 3240 3241 /* Make "end" point to the actual end */ 3242 if (trans->trans_cfg->device_family >= 3243 IWL_DEVICE_FAMILY_8000 || 3244 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3245 end += (1 << trans->dbg.dest_tlv->end_shift); 3246 monitor_len = end - base; 3247 } 3248 *len += sizeof(struct iwl_fw_error_dump_data) + 3249 sizeof(struct iwl_fw_error_dump_fw_mon) + 3250 monitor_len; 3251 return monitor_len; 3252 } 3253 return 0; 3254 } 3255 3256 static struct iwl_trans_dump_data * 3257 iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3258 u32 dump_mask, 3259 const struct iwl_dump_sanitize_ops *sanitize_ops, 3260 void *sanitize_ctx) 3261 { 3262 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3263 struct iwl_fw_error_dump_data *data; 3264 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3265 struct iwl_fw_error_dump_txcmd *txcmd; 3266 struct iwl_trans_dump_data *dump_data; 3267 u32 len, num_rbs = 0, monitor_len = 0; 3268 int i, ptr; 3269 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3270 !trans->trans_cfg->mq_rx_supported && 3271 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3272 3273 if (!dump_mask) 3274 return NULL; 3275 3276 /* transport dump header */ 3277 len = sizeof(*dump_data); 3278 3279 /* host commands */ 3280 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3281 len += sizeof(*data) + 3282 cmdq->n_window * (sizeof(*txcmd) + 3283 TFD_MAX_PAYLOAD_SIZE); 3284 3285 /* FW monitor */ 3286 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3287 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3288 3289 /* CSR registers */ 3290 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3291 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3292 3293 /* FH registers */ 3294 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3295 if (trans->trans_cfg->gen2) 3296 len += sizeof(*data) + 3297 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3298 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3299 else 3300 len += sizeof(*data) + 3301 (FH_MEM_UPPER_BOUND - 3302 FH_MEM_LOWER_BOUND); 3303 } 3304 3305 if (dump_rbs) { 3306 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3307 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3308 /* RBs */ 3309 num_rbs = 3310 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3311 & 0x0FFF; 3312 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3313 len += num_rbs * (sizeof(*data) + 3314 sizeof(struct iwl_fw_error_dump_rb) + 3315 (PAGE_SIZE << trans_pcie->rx_page_order)); 3316 } 3317 3318 /* Paged memory for gen2 HW */ 3319 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3320 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3321 len += sizeof(*data) + 3322 sizeof(struct iwl_fw_error_dump_paging) + 3323 trans->init_dram.paging[i].size; 3324 3325 dump_data = vzalloc(len); 3326 if (!dump_data) 3327 return NULL; 3328 3329 len = 0; 3330 data = (void *)dump_data->data; 3331 3332 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3333 u16 tfd_size = trans->txqs.tfd.size; 3334 3335 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3336 txcmd = (void *)data->data; 3337 spin_lock_bh(&cmdq->lock); 3338 ptr = cmdq->write_ptr; 3339 for (i = 0; i < cmdq->n_window; i++) { 3340 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3341 u8 tfdidx; 3342 u32 caplen, cmdlen; 3343 3344 if (trans->trans_cfg->use_tfh) 3345 tfdidx = idx; 3346 else 3347 tfdidx = ptr; 3348 3349 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3350 (u8 *)cmdq->tfds + 3351 tfd_size * tfdidx); 3352 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3353 3354 if (cmdlen) { 3355 len += sizeof(*txcmd) + caplen; 3356 txcmd->cmdlen = cpu_to_le32(cmdlen); 3357 txcmd->caplen = cpu_to_le32(caplen); 3358 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3359 caplen); 3360 if (sanitize_ops && sanitize_ops->frob_hcmd) 3361 sanitize_ops->frob_hcmd(sanitize_ctx, 3362 txcmd->data, 3363 caplen); 3364 txcmd = (void *)((u8 *)txcmd->data + caplen); 3365 } 3366 3367 ptr = iwl_txq_dec_wrap(trans, ptr); 3368 } 3369 spin_unlock_bh(&cmdq->lock); 3370 3371 data->len = cpu_to_le32(len); 3372 len += sizeof(*data); 3373 data = iwl_fw_error_next_data(data); 3374 } 3375 3376 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3377 len += iwl_trans_pcie_dump_csr(trans, &data); 3378 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3379 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3380 if (dump_rbs) 3381 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3382 3383 /* Paged memory for gen2 HW */ 3384 if (trans->trans_cfg->gen2 && 3385 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3386 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3387 struct iwl_fw_error_dump_paging *paging; 3388 u32 page_len = trans->init_dram.paging[i].size; 3389 3390 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3391 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3392 paging = (void *)data->data; 3393 paging->index = cpu_to_le32(i); 3394 memcpy(paging->data, 3395 trans->init_dram.paging[i].block, page_len); 3396 data = iwl_fw_error_next_data(data); 3397 3398 len += sizeof(*data) + sizeof(*paging) + page_len; 3399 } 3400 } 3401 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3402 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3403 3404 dump_data->len = len; 3405 3406 return dump_data; 3407 } 3408 3409 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3410 { 3411 if (enable) 3412 iwl_enable_interrupts(trans); 3413 else 3414 iwl_disable_interrupts(trans); 3415 } 3416 3417 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3418 { 3419 u32 inta_addr, sw_err_bit; 3420 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3421 3422 if (trans_pcie->msix_enabled) { 3423 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3424 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3425 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3426 else 3427 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3428 } else { 3429 inta_addr = CSR_INT; 3430 sw_err_bit = CSR_INT_BIT_SW_ERR; 3431 } 3432 3433 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3434 } 3435 3436 #define IWL_TRANS_COMMON_OPS \ 3437 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3438 .write8 = iwl_trans_pcie_write8, \ 3439 .write32 = iwl_trans_pcie_write32, \ 3440 .read32 = iwl_trans_pcie_read32, \ 3441 .read_prph = iwl_trans_pcie_read_prph, \ 3442 .write_prph = iwl_trans_pcie_write_prph, \ 3443 .read_mem = iwl_trans_pcie_read_mem, \ 3444 .write_mem = iwl_trans_pcie_write_mem, \ 3445 .read_config32 = iwl_trans_pcie_read_config32, \ 3446 .configure = iwl_trans_pcie_configure, \ 3447 .set_pmi = iwl_trans_pcie_set_pmi, \ 3448 .sw_reset = iwl_trans_pcie_sw_reset, \ 3449 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3450 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3451 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3452 .dump_data = iwl_trans_pcie_dump_data, \ 3453 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3454 .d3_resume = iwl_trans_pcie_d3_resume, \ 3455 .interrupts = iwl_trans_pci_interrupts, \ 3456 .sync_nmi = iwl_trans_pcie_sync_nmi \ 3457 3458 static const struct iwl_trans_ops trans_ops_pcie = { 3459 IWL_TRANS_COMMON_OPS, 3460 .start_hw = iwl_trans_pcie_start_hw, 3461 .fw_alive = iwl_trans_pcie_fw_alive, 3462 .start_fw = iwl_trans_pcie_start_fw, 3463 .stop_device = iwl_trans_pcie_stop_device, 3464 3465 .send_cmd = iwl_pcie_enqueue_hcmd, 3466 3467 .tx = iwl_trans_pcie_tx, 3468 .reclaim = iwl_txq_reclaim, 3469 3470 .txq_disable = iwl_trans_pcie_txq_disable, 3471 .txq_enable = iwl_trans_pcie_txq_enable, 3472 3473 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3474 3475 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3476 3477 .freeze_txq_timer = iwl_trans_txq_freeze_timer, 3478 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3479 #ifdef CONFIG_IWLWIFI_DEBUGFS 3480 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3481 #endif 3482 }; 3483 3484 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3485 IWL_TRANS_COMMON_OPS, 3486 .start_hw = iwl_trans_pcie_start_hw, 3487 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3488 .start_fw = iwl_trans_pcie_gen2_start_fw, 3489 .stop_device = iwl_trans_pcie_gen2_stop_device, 3490 3491 .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3492 3493 .tx = iwl_txq_gen2_tx, 3494 .reclaim = iwl_txq_reclaim, 3495 3496 .set_q_ptrs = iwl_txq_set_q_ptrs, 3497 3498 .txq_alloc = iwl_txq_dyn_alloc, 3499 .txq_free = iwl_txq_dyn_free, 3500 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3501 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3502 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3503 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3504 #ifdef CONFIG_IWLWIFI_DEBUGFS 3505 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3506 #endif 3507 }; 3508 3509 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3510 const struct pci_device_id *ent, 3511 const struct iwl_cfg_trans_params *cfg_trans) 3512 { 3513 struct iwl_trans_pcie *trans_pcie; 3514 struct iwl_trans *trans; 3515 int ret, addr_size; 3516 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3517 void __iomem * const *table; 3518 3519 if (!cfg_trans->gen2) 3520 ops = &trans_ops_pcie; 3521 3522 ret = pcim_enable_device(pdev); 3523 if (ret) 3524 return ERR_PTR(ret); 3525 3526 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3527 cfg_trans); 3528 if (!trans) 3529 return ERR_PTR(-ENOMEM); 3530 3531 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3532 3533 trans_pcie->trans = trans; 3534 trans_pcie->opmode_down = true; 3535 spin_lock_init(&trans_pcie->irq_lock); 3536 spin_lock_init(&trans_pcie->reg_lock); 3537 spin_lock_init(&trans_pcie->alloc_page_lock); 3538 mutex_init(&trans_pcie->mutex); 3539 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3540 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3541 3542 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3543 WQ_HIGHPRI | WQ_UNBOUND, 1); 3544 if (!trans_pcie->rba.alloc_wq) { 3545 ret = -ENOMEM; 3546 goto out_free_trans; 3547 } 3548 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3549 3550 trans_pcie->debug_rfkill = -1; 3551 3552 if (!cfg_trans->base_params->pcie_l1_allowed) { 3553 /* 3554 * W/A - seems to solve weird behavior. We need to remove this 3555 * if we don't want to stay in L1 all the time. This wastes a 3556 * lot of power. 3557 */ 3558 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3559 PCIE_LINK_STATE_L1 | 3560 PCIE_LINK_STATE_CLKPM); 3561 } 3562 3563 trans_pcie->def_rx_queue = 0; 3564 3565 pci_set_master(pdev); 3566 3567 addr_size = trans->txqs.tfd.addr_size; 3568 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3569 if (ret) { 3570 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3571 /* both attempts failed: */ 3572 if (ret) { 3573 dev_err(&pdev->dev, "No suitable DMA available\n"); 3574 goto out_no_pci; 3575 } 3576 } 3577 3578 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3579 if (ret) { 3580 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3581 goto out_no_pci; 3582 } 3583 3584 table = pcim_iomap_table(pdev); 3585 if (!table) { 3586 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3587 ret = -ENOMEM; 3588 goto out_no_pci; 3589 } 3590 3591 trans_pcie->hw_base = table[0]; 3592 if (!trans_pcie->hw_base) { 3593 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3594 ret = -ENODEV; 3595 goto out_no_pci; 3596 } 3597 3598 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3599 * PCI Tx retries from interfering with C3 CPU state */ 3600 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3601 3602 trans_pcie->pci_dev = pdev; 3603 iwl_disable_interrupts(trans); 3604 3605 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3606 if (trans->hw_rev == 0xffffffff) { 3607 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3608 ret = -EIO; 3609 goto out_no_pci; 3610 } 3611 3612 /* 3613 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3614 * changed, and now the revision step also includes bit 0-1 (no more 3615 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3616 * in the old format. 3617 */ 3618 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3619 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3620 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3621 3622 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3623 3624 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3625 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3626 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3627 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3628 3629 init_waitqueue_head(&trans_pcie->sx_waitq); 3630 3631 3632 if (trans_pcie->msix_enabled) { 3633 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3634 if (ret) 3635 goto out_no_pci; 3636 } else { 3637 ret = iwl_pcie_alloc_ict(trans); 3638 if (ret) 3639 goto out_no_pci; 3640 3641 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3642 iwl_pcie_isr, 3643 iwl_pcie_irq_handler, 3644 IRQF_SHARED, DRV_NAME, trans); 3645 if (ret) { 3646 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3647 goto out_free_ict; 3648 } 3649 } 3650 3651 #ifdef CONFIG_IWLWIFI_DEBUGFS 3652 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3653 mutex_init(&trans_pcie->fw_mon_data.mutex); 3654 #endif 3655 3656 iwl_dbg_tlv_init(trans); 3657 3658 return trans; 3659 3660 out_free_ict: 3661 iwl_pcie_free_ict(trans); 3662 out_no_pci: 3663 destroy_workqueue(trans_pcie->rba.alloc_wq); 3664 out_free_trans: 3665 iwl_trans_free(trans); 3666 return ERR_PTR(ret); 3667 } 3668