1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 18 #include "iwl-drv.h" 19 #include "iwl-trans.h" 20 #include "iwl-csr.h" 21 #include "iwl-prph.h" 22 #include "iwl-scd.h" 23 #include "iwl-agn-hw.h" 24 #include "fw/error-dump.h" 25 #include "fw/dbg.h" 26 #include "fw/api/tx.h" 27 #include "fw/acpi.h" 28 #include "mei/iwl-mei.h" 29 #include "internal.h" 30 #include "iwl-fh.h" 31 #include "iwl-context-info-gen3.h" 32 33 /* extended range in FW SRAM */ 34 #define IWL_FW_MEM_EXTENDED_START 0x40000 35 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 36 37 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 38 { 39 #define PCI_DUMP_SIZE 352 40 #define PCI_MEM_DUMP_SIZE 64 41 #define PCI_PARENT_DUMP_SIZE 524 42 #define PREFIX_LEN 32 43 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 44 struct pci_dev *pdev = trans_pcie->pci_dev; 45 u32 i, pos, alloc_size, *ptr, *buf; 46 char *prefix; 47 48 if (trans_pcie->pcie_dbg_dumped_once) 49 return; 50 51 /* Should be a multiple of 4 */ 52 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 53 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 54 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 55 56 /* Alloc a max size buffer */ 57 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 58 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 59 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 60 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 61 62 buf = kmalloc(alloc_size, GFP_ATOMIC); 63 if (!buf) 64 return; 65 prefix = (char *)buf + alloc_size - PREFIX_LEN; 66 67 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 68 69 /* Print wifi device registers */ 70 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 71 IWL_ERR(trans, "iwlwifi device config registers:\n"); 72 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 73 if (pci_read_config_dword(pdev, i, ptr)) 74 goto err_read; 75 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 76 77 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 78 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 79 *ptr = iwl_read32(trans, i); 80 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 81 82 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 83 if (pos) { 84 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 85 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 86 if (pci_read_config_dword(pdev, pos + i, ptr)) 87 goto err_read; 88 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 89 32, 4, buf, i, 0); 90 } 91 92 /* Print parent device registers next */ 93 if (!pdev->bus->self) 94 goto out; 95 96 pdev = pdev->bus->self; 97 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 98 99 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 100 pci_name(pdev)); 101 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 102 if (pci_read_config_dword(pdev, i, ptr)) 103 goto err_read; 104 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 105 106 /* Print root port AER registers */ 107 pos = 0; 108 pdev = pcie_find_root_port(pdev); 109 if (pdev) 110 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 111 if (pos) { 112 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 113 pci_name(pdev)); 114 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 115 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 116 if (pci_read_config_dword(pdev, pos + i, ptr)) 117 goto err_read; 118 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 119 4, buf, i, 0); 120 } 121 goto out; 122 123 err_read: 124 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 125 IWL_ERR(trans, "Read failed at 0x%X\n", i); 126 out: 127 trans_pcie->pcie_dbg_dumped_once = 1; 128 kfree(buf); 129 } 130 131 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership) 132 { 133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 135 iwl_set_bit(trans, CSR_GP_CNTRL, 136 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 137 usleep_range(10000, 20000); 138 } else { 139 iwl_set_bit(trans, CSR_RESET, 140 CSR_RESET_REG_FLAG_SW_RESET); 141 usleep_range(5000, 6000); 142 } 143 144 if (retake_ownership) 145 return iwl_pcie_prepare_card_hw(trans); 146 147 return 0; 148 } 149 150 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 151 { 152 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 153 154 if (!fw_mon->size) 155 return; 156 157 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 158 fw_mon->physical); 159 160 fw_mon->block = NULL; 161 fw_mon->physical = 0; 162 fw_mon->size = 0; 163 } 164 165 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 166 u8 max_power) 167 { 168 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 169 void *block = NULL; 170 dma_addr_t physical = 0; 171 u32 size = 0; 172 u8 power; 173 174 if (fw_mon->size) { 175 memset(fw_mon->block, 0, fw_mon->size); 176 return; 177 } 178 179 /* need at least 2 KiB, so stop at 11 */ 180 for (power = max_power; power >= 11; power--) { 181 size = BIT(power); 182 block = dma_alloc_coherent(trans->dev, size, &physical, 183 GFP_KERNEL | __GFP_NOWARN); 184 if (!block) 185 continue; 186 187 IWL_INFO(trans, 188 "Allocated 0x%08x bytes for firmware monitor.\n", 189 size); 190 break; 191 } 192 193 if (WARN_ON_ONCE(!block)) 194 return; 195 196 if (power != max_power) 197 IWL_ERR(trans, 198 "Sorry - debug buffer is only %luK while you requested %luK\n", 199 (unsigned long)BIT(power - 10), 200 (unsigned long)BIT(max_power - 10)); 201 202 fw_mon->block = block; 203 fw_mon->physical = physical; 204 fw_mon->size = size; 205 } 206 207 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 208 { 209 if (!max_power) { 210 /* default max_power is maximum */ 211 max_power = 26; 212 } else { 213 max_power += 11; 214 } 215 216 if (WARN(max_power > 26, 217 "External buffer size for monitor is too big %d, check the FW TLV\n", 218 max_power)) 219 return; 220 221 iwl_pcie_alloc_fw_monitor_block(trans, max_power); 222 } 223 224 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 225 { 226 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 227 ((reg & 0x0000ffff) | (2 << 28))); 228 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 229 } 230 231 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 232 { 233 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 234 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 235 ((reg & 0x0000ffff) | (3 << 28))); 236 } 237 238 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 239 { 240 if (trans->cfg->apmg_not_supported) 241 return; 242 243 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 244 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 245 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 246 ~APMG_PS_CTRL_MSK_PWR_SRC); 247 else 248 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 249 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 250 ~APMG_PS_CTRL_MSK_PWR_SRC); 251 } 252 253 /* PCI registers */ 254 #define PCI_CFG_RETRY_TIMEOUT 0x041 255 256 void iwl_pcie_apm_config(struct iwl_trans *trans) 257 { 258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 259 u16 lctl; 260 u16 cap; 261 262 /* 263 * L0S states have been found to be unstable with our devices 264 * and in newer hardware they are not officially supported at 265 * all, so we must always set the L0S_DISABLED bit. 266 */ 267 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 268 269 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 270 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 271 272 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 273 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 274 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 275 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 276 trans->ltr_enabled ? "En" : "Dis"); 277 } 278 279 /* 280 * Start up NIC's basic functionality after it has been reset 281 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 282 * NOTE: This does not load uCode nor start the embedded processor 283 */ 284 static int iwl_pcie_apm_init(struct iwl_trans *trans) 285 { 286 int ret; 287 288 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 289 290 /* 291 * Use "set_bit" below rather than "write", to preserve any hardware 292 * bits already set by default after reset. 293 */ 294 295 /* Disable L0S exit timer (platform NMI Work/Around) */ 296 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 297 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 298 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 299 300 /* 301 * Disable L0s without affecting L1; 302 * don't wait for ICH L0s (ICH bug W/A) 303 */ 304 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 305 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 306 307 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 308 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 309 310 /* 311 * Enable HAP INTA (interrupt from management bus) to 312 * wake device's PCI Express link L1a -> L0s 313 */ 314 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 315 CSR_HW_IF_CONFIG_REG_HAP_WAKE); 316 317 iwl_pcie_apm_config(trans); 318 319 /* Configure analog phase-lock-loop before activating to D0A */ 320 if (trans->trans_cfg->base_params->pll_cfg) 321 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 322 323 ret = iwl_finish_nic_init(trans); 324 if (ret) 325 return ret; 326 327 if (trans->cfg->host_interrupt_operation_mode) { 328 /* 329 * This is a bit of an abuse - This is needed for 7260 / 3160 330 * only check host_interrupt_operation_mode even if this is 331 * not related to host_interrupt_operation_mode. 332 * 333 * Enable the oscillator to count wake up time for L1 exit. This 334 * consumes slightly more power (100uA) - but allows to be sure 335 * that we wake up from L1 on time. 336 * 337 * This looks weird: read twice the same register, discard the 338 * value, set a bit, and yet again, read that same register 339 * just to discard the value. But that's the way the hardware 340 * seems to like it. 341 */ 342 iwl_read_prph(trans, OSC_CLK); 343 iwl_read_prph(trans, OSC_CLK); 344 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 345 iwl_read_prph(trans, OSC_CLK); 346 iwl_read_prph(trans, OSC_CLK); 347 } 348 349 /* 350 * Enable DMA clock and wait for it to stabilize. 351 * 352 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 353 * bits do not disable clocks. This preserves any hardware 354 * bits already set by default in "CLK_CTRL_REG" after reset. 355 */ 356 if (!trans->cfg->apmg_not_supported) { 357 iwl_write_prph(trans, APMG_CLK_EN_REG, 358 APMG_CLK_VAL_DMA_CLK_RQT); 359 udelay(20); 360 361 /* Disable L1-Active */ 362 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 363 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 364 365 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 366 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 367 APMG_RTC_INT_STT_RFKILL); 368 } 369 370 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 371 372 return 0; 373 } 374 375 /* 376 * Enable LP XTAL to avoid HW bug where device may consume much power if 377 * FW is not loaded after device reset. LP XTAL is disabled by default 378 * after device HW reset. Do it only if XTAL is fed by internal source. 379 * Configure device's "persistence" mode to avoid resetting XTAL again when 380 * SHRD_HW_RST occurs in S3. 381 */ 382 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 383 { 384 int ret; 385 u32 apmg_gp1_reg; 386 u32 apmg_xtal_cfg_reg; 387 u32 dl_cfg_reg; 388 389 /* Force XTAL ON */ 390 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 391 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 392 393 ret = iwl_trans_pcie_sw_reset(trans, true); 394 395 if (!ret) 396 ret = iwl_finish_nic_init(trans); 397 398 if (WARN_ON(ret)) { 399 /* Release XTAL ON request */ 400 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 401 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 402 return; 403 } 404 405 /* 406 * Clear "disable persistence" to avoid LP XTAL resetting when 407 * SHRD_HW_RST is applied in S3. 408 */ 409 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 410 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 411 412 /* 413 * Force APMG XTAL to be active to prevent its disabling by HW 414 * caused by APMG idle state. 415 */ 416 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 417 SHR_APMG_XTAL_CFG_REG); 418 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 419 apmg_xtal_cfg_reg | 420 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 421 422 ret = iwl_trans_pcie_sw_reset(trans, true); 423 if (ret) 424 IWL_ERR(trans, 425 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 426 427 /* Enable LP XTAL by indirect access through CSR */ 428 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 429 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 430 SHR_APMG_GP1_WF_XTAL_LP_EN | 431 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 432 433 /* Clear delay line clock power up */ 434 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 435 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 436 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 437 438 /* 439 * Enable persistence mode to avoid LP XTAL resetting when 440 * SHRD_HW_RST is applied in S3. 441 */ 442 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 443 CSR_HW_IF_CONFIG_REG_PERSISTENCE); 444 445 /* 446 * Clear "initialization complete" bit to move adapter from 447 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 448 */ 449 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 450 451 /* Activates XTAL resources monitor */ 452 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 453 CSR_MONITOR_XTAL_RESOURCES); 454 455 /* Release XTAL ON request */ 456 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 457 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 458 udelay(10); 459 460 /* Release APMG XTAL */ 461 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 462 apmg_xtal_cfg_reg & 463 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 464 } 465 466 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 467 { 468 int ret; 469 470 /* stop device's busmaster DMA activity */ 471 472 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 473 iwl_set_bit(trans, CSR_GP_CNTRL, 474 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 475 476 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 477 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 478 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 479 100); 480 usleep_range(10000, 20000); 481 } else { 482 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 483 484 ret = iwl_poll_bit(trans, CSR_RESET, 485 CSR_RESET_REG_FLAG_MASTER_DISABLED, 486 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 487 } 488 489 if (ret < 0) 490 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 491 492 IWL_DEBUG_INFO(trans, "stop master\n"); 493 } 494 495 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 496 { 497 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 498 499 if (op_mode_leave) { 500 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 501 iwl_pcie_apm_init(trans); 502 503 /* inform ME that we are leaving */ 504 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 505 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 506 APMG_PCIDEV_STT_VAL_WAKE_ME); 507 else if (trans->trans_cfg->device_family >= 508 IWL_DEVICE_FAMILY_8000) { 509 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 510 CSR_RESET_LINK_PWR_MGMT_DISABLED); 511 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 512 CSR_HW_IF_CONFIG_REG_WAKE_ME | 513 CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN); 514 mdelay(1); 515 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 516 CSR_RESET_LINK_PWR_MGMT_DISABLED); 517 } 518 mdelay(5); 519 } 520 521 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 522 523 /* Stop device's DMA activity */ 524 iwl_pcie_apm_stop_master(trans); 525 526 if (trans->cfg->lp_xtal_workaround) { 527 iwl_pcie_apm_lp_xtal_enable(trans); 528 return; 529 } 530 531 iwl_trans_pcie_sw_reset(trans, false); 532 533 /* 534 * Clear "initialization complete" bit to move adapter from 535 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 536 */ 537 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 538 } 539 540 static int iwl_pcie_nic_init(struct iwl_trans *trans) 541 { 542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 543 int ret; 544 545 /* nic_init */ 546 spin_lock_bh(&trans_pcie->irq_lock); 547 ret = iwl_pcie_apm_init(trans); 548 spin_unlock_bh(&trans_pcie->irq_lock); 549 550 if (ret) 551 return ret; 552 553 iwl_pcie_set_pwr(trans, false); 554 555 iwl_op_mode_nic_config(trans->op_mode); 556 557 /* Allocate the RX queue, or reset if it is already allocated */ 558 ret = iwl_pcie_rx_init(trans); 559 if (ret) 560 return ret; 561 562 /* Allocate or reset and init all Tx and Command queues */ 563 if (iwl_pcie_tx_init(trans)) { 564 iwl_pcie_rx_free(trans); 565 return -ENOMEM; 566 } 567 568 if (trans->trans_cfg->base_params->shadow_reg_enable) { 569 /* enable shadow regs in HW */ 570 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 571 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 572 } 573 574 return 0; 575 } 576 577 #define HW_READY_TIMEOUT (50) 578 579 /* Note: returns poll_bit return value, which is >= 0 if success */ 580 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 581 { 582 int ret; 583 584 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 585 CSR_HW_IF_CONFIG_REG_PCI_OWN_SET); 586 587 /* See if we got it */ 588 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 589 CSR_HW_IF_CONFIG_REG_PCI_OWN_SET, 590 CSR_HW_IF_CONFIG_REG_PCI_OWN_SET, 591 HW_READY_TIMEOUT); 592 593 if (ret >= 0) 594 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 595 596 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 597 return ret; 598 } 599 600 /* Note: returns standard 0/-ERROR code */ 601 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 602 { 603 int ret; 604 int iter; 605 606 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 607 608 ret = iwl_pcie_set_hw_ready(trans); 609 /* If the card is ready, exit 0 */ 610 if (ret >= 0) { 611 trans->csme_own = false; 612 return 0; 613 } 614 615 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 616 CSR_RESET_LINK_PWR_MGMT_DISABLED); 617 usleep_range(1000, 2000); 618 619 for (iter = 0; iter < 10; iter++) { 620 int t = 0; 621 622 /* If HW is not ready, prepare the conditions to check again */ 623 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 624 CSR_HW_IF_CONFIG_REG_WAKE_ME); 625 626 do { 627 ret = iwl_pcie_set_hw_ready(trans); 628 if (ret >= 0) { 629 trans->csme_own = false; 630 return 0; 631 } 632 633 if (iwl_mei_is_connected()) { 634 IWL_DEBUG_INFO(trans, 635 "Couldn't prepare the card but SAP is connected\n"); 636 trans->csme_own = true; 637 if (trans->trans_cfg->device_family != 638 IWL_DEVICE_FAMILY_9000) 639 IWL_ERR(trans, 640 "SAP not supported for this NIC family\n"); 641 642 return -EBUSY; 643 } 644 645 usleep_range(200, 1000); 646 t += 200; 647 } while (t < 150000); 648 msleep(25); 649 } 650 651 IWL_ERR(trans, "Couldn't prepare the card\n"); 652 653 return ret; 654 } 655 656 /* 657 * ucode 658 */ 659 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 660 u32 dst_addr, dma_addr_t phy_addr, 661 u32 byte_cnt) 662 { 663 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 664 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 665 666 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 667 dst_addr); 668 669 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 670 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 671 672 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 673 (iwl_get_dma_hi_addr(phy_addr) 674 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 675 676 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 677 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 678 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 679 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 680 681 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 682 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 683 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 684 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 685 } 686 687 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 688 u32 dst_addr, dma_addr_t phy_addr, 689 u32 byte_cnt) 690 { 691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 692 int ret; 693 694 trans_pcie->ucode_write_complete = false; 695 696 if (!iwl_trans_grab_nic_access(trans)) 697 return -EIO; 698 699 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 700 byte_cnt); 701 iwl_trans_release_nic_access(trans); 702 703 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 704 trans_pcie->ucode_write_complete, 5 * HZ); 705 if (!ret) { 706 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 707 iwl_trans_pcie_dump_regs(trans); 708 return -ETIMEDOUT; 709 } 710 711 return 0; 712 } 713 714 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 715 const struct fw_desc *section) 716 { 717 u8 *v_addr; 718 dma_addr_t p_addr; 719 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 720 int ret = 0; 721 722 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 723 section_num); 724 725 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 726 GFP_KERNEL | __GFP_NOWARN); 727 if (!v_addr) { 728 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 729 chunk_sz = PAGE_SIZE; 730 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 731 &p_addr, GFP_KERNEL); 732 if (!v_addr) 733 return -ENOMEM; 734 } 735 736 for (offset = 0; offset < section->len; offset += chunk_sz) { 737 u32 copy_size, dst_addr; 738 bool extended_addr = false; 739 740 copy_size = min_t(u32, chunk_sz, section->len - offset); 741 dst_addr = section->offset + offset; 742 743 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 744 dst_addr <= IWL_FW_MEM_EXTENDED_END) 745 extended_addr = true; 746 747 if (extended_addr) 748 iwl_set_bits_prph(trans, LMPM_CHICK, 749 LMPM_CHICK_EXTENDED_ADDR_SPACE); 750 751 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 752 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 753 copy_size); 754 755 if (extended_addr) 756 iwl_clear_bits_prph(trans, LMPM_CHICK, 757 LMPM_CHICK_EXTENDED_ADDR_SPACE); 758 759 if (ret) { 760 IWL_ERR(trans, 761 "Could not load the [%d] uCode section\n", 762 section_num); 763 break; 764 } 765 } 766 767 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 768 return ret; 769 } 770 771 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 772 const struct fw_img *image, 773 int cpu, 774 int *first_ucode_section) 775 { 776 int shift_param; 777 int i, ret = 0, sec_num = 0x1; 778 u32 val, last_read_idx = 0; 779 780 if (cpu == 1) { 781 shift_param = 0; 782 *first_ucode_section = 0; 783 } else { 784 shift_param = 16; 785 (*first_ucode_section)++; 786 } 787 788 for (i = *first_ucode_section; i < image->num_sec; i++) { 789 last_read_idx = i; 790 791 /* 792 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 793 * CPU1 to CPU2. 794 * PAGING_SEPARATOR_SECTION delimiter - separate between 795 * CPU2 non paged to CPU2 paging sec. 796 */ 797 if (!image->sec[i].data || 798 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 799 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 800 IWL_DEBUG_FW(trans, 801 "Break since Data not valid or Empty section, sec = %d\n", 802 i); 803 break; 804 } 805 806 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 807 if (ret) 808 return ret; 809 810 /* Notify ucode of loaded section number and status */ 811 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 812 val = val | (sec_num << shift_param); 813 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 814 815 sec_num = (sec_num << 1) | 0x1; 816 } 817 818 *first_ucode_section = last_read_idx; 819 820 iwl_enable_interrupts(trans); 821 822 if (trans->trans_cfg->gen2) { 823 if (cpu == 1) 824 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 825 0xFFFF); 826 else 827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 828 0xFFFFFFFF); 829 } else { 830 if (cpu == 1) 831 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 832 0xFFFF); 833 else 834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 835 0xFFFFFFFF); 836 } 837 838 return 0; 839 } 840 841 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 842 const struct fw_img *image, 843 int cpu, 844 int *first_ucode_section) 845 { 846 int i, ret = 0; 847 u32 last_read_idx = 0; 848 849 if (cpu == 1) 850 *first_ucode_section = 0; 851 else 852 (*first_ucode_section)++; 853 854 for (i = *first_ucode_section; i < image->num_sec; i++) { 855 last_read_idx = i; 856 857 /* 858 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 859 * CPU1 to CPU2. 860 * PAGING_SEPARATOR_SECTION delimiter - separate between 861 * CPU2 non paged to CPU2 paging sec. 862 */ 863 if (!image->sec[i].data || 864 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 865 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 866 IWL_DEBUG_FW(trans, 867 "Break since Data not valid or Empty section, sec = %d\n", 868 i); 869 break; 870 } 871 872 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 873 if (ret) 874 return ret; 875 } 876 877 *first_ucode_section = last_read_idx; 878 879 return 0; 880 } 881 882 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 883 { 884 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 885 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 886 &trans->dbg.fw_mon_cfg[alloc_id]; 887 struct iwl_dram_data *frag; 888 889 if (!iwl_trans_dbg_ini_valid(trans)) 890 return; 891 892 if (le32_to_cpu(fw_mon_cfg->buf_location) == 893 IWL_FW_INI_LOCATION_SRAM_PATH) { 894 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 895 /* set sram monitor by enabling bit 7 */ 896 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 897 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 898 899 return; 900 } 901 902 if (le32_to_cpu(fw_mon_cfg->buf_location) != 903 IWL_FW_INI_LOCATION_DRAM_PATH || 904 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 905 return; 906 907 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 908 909 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 910 alloc_id); 911 912 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 913 frag->physical >> MON_BUFF_SHIFT_VER2); 914 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 915 (frag->physical + frag->size - 256) >> 916 MON_BUFF_SHIFT_VER2); 917 } 918 919 void iwl_pcie_apply_destination(struct iwl_trans *trans) 920 { 921 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 922 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 923 int i; 924 925 if (iwl_trans_dbg_ini_valid(trans)) { 926 iwl_pcie_apply_destination_ini(trans); 927 return; 928 } 929 930 IWL_INFO(trans, "Applying debug destination %s\n", 931 get_fw_dbg_mode_string(dest->monitor_mode)); 932 933 if (dest->monitor_mode == EXTERNAL_MODE) 934 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 935 else 936 IWL_WARN(trans, "PCI should have external buffer debug\n"); 937 938 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 939 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 940 u32 val = le32_to_cpu(dest->reg_ops[i].val); 941 942 switch (dest->reg_ops[i].op) { 943 case CSR_ASSIGN: 944 iwl_write32(trans, addr, val); 945 break; 946 case CSR_SETBIT: 947 iwl_set_bit(trans, addr, BIT(val)); 948 break; 949 case CSR_CLEARBIT: 950 iwl_clear_bit(trans, addr, BIT(val)); 951 break; 952 case PRPH_ASSIGN: 953 iwl_write_prph(trans, addr, val); 954 break; 955 case PRPH_SETBIT: 956 iwl_set_bits_prph(trans, addr, BIT(val)); 957 break; 958 case PRPH_CLEARBIT: 959 iwl_clear_bits_prph(trans, addr, BIT(val)); 960 break; 961 case PRPH_BLOCKBIT: 962 if (iwl_read_prph(trans, addr) & BIT(val)) { 963 IWL_ERR(trans, 964 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 965 val, addr); 966 goto monitor; 967 } 968 break; 969 default: 970 IWL_ERR(trans, "FW debug - unknown OP %d\n", 971 dest->reg_ops[i].op); 972 break; 973 } 974 } 975 976 monitor: 977 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 978 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 979 fw_mon->physical >> dest->base_shift); 980 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 981 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 982 (fw_mon->physical + fw_mon->size - 983 256) >> dest->end_shift); 984 else 985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 986 (fw_mon->physical + fw_mon->size) >> 987 dest->end_shift); 988 } 989 } 990 991 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 992 const struct fw_img *image) 993 { 994 int ret = 0; 995 int first_ucode_section; 996 997 IWL_DEBUG_FW(trans, "working with %s CPU\n", 998 image->is_dual_cpus ? "Dual" : "Single"); 999 1000 /* load to FW the binary non secured sections of CPU1 */ 1001 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1002 if (ret) 1003 return ret; 1004 1005 if (image->is_dual_cpus) { 1006 /* set CPU2 header address */ 1007 iwl_write_prph(trans, 1008 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1009 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1010 1011 /* load to FW the binary sections of CPU2 */ 1012 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1013 &first_ucode_section); 1014 if (ret) 1015 return ret; 1016 } 1017 1018 if (iwl_pcie_dbg_on(trans)) 1019 iwl_pcie_apply_destination(trans); 1020 1021 iwl_enable_interrupts(trans); 1022 1023 /* release CPU reset */ 1024 iwl_write32(trans, CSR_RESET, 0); 1025 1026 return 0; 1027 } 1028 1029 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1030 const struct fw_img *image) 1031 { 1032 int ret = 0; 1033 int first_ucode_section; 1034 1035 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1036 image->is_dual_cpus ? "Dual" : "Single"); 1037 1038 if (iwl_pcie_dbg_on(trans)) 1039 iwl_pcie_apply_destination(trans); 1040 1041 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1042 iwl_read_prph(trans, WFPM_GP2)); 1043 1044 /* 1045 * Set default value. On resume reading the values that were 1046 * zeored can provide debug data on the resume flow. 1047 * This is for debugging only and has no functional impact. 1048 */ 1049 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1050 1051 /* configure the ucode to be ready to get the secured image */ 1052 /* release CPU reset */ 1053 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1054 1055 /* load to FW the binary Secured sections of CPU1 */ 1056 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1057 &first_ucode_section); 1058 if (ret) 1059 return ret; 1060 1061 /* load to FW the binary sections of CPU2 */ 1062 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1063 &first_ucode_section); 1064 } 1065 1066 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1067 { 1068 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1069 bool hw_rfkill = iwl_is_rfkill_set(trans); 1070 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1071 bool report; 1072 1073 if (hw_rfkill) { 1074 set_bit(STATUS_RFKILL_HW, &trans->status); 1075 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1076 } else { 1077 clear_bit(STATUS_RFKILL_HW, &trans->status); 1078 if (trans_pcie->opmode_down) 1079 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1080 } 1081 1082 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1083 1084 if (prev != report) 1085 iwl_trans_pcie_rf_kill(trans, report, false); 1086 1087 return hw_rfkill; 1088 } 1089 1090 struct iwl_causes_list { 1091 u16 mask_reg; 1092 u8 bit; 1093 u8 addr; 1094 }; 1095 1096 #define IWL_CAUSE(reg, mask) \ 1097 { \ 1098 .mask_reg = reg, \ 1099 .bit = ilog2(mask), \ 1100 .addr = ilog2(mask) + \ 1101 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1102 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1103 0xffff), /* causes overflow warning */ \ 1104 } 1105 1106 static const struct iwl_causes_list causes_list_common[] = { 1107 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 1108 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 1109 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 1110 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 1111 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 1112 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 1113 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 1114 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR), 1115 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 1116 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 1117 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 1118 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 1119 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 1120 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 1121 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 1122 }; 1123 1124 static const struct iwl_causes_list causes_list_pre_bz[] = { 1125 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1126 }; 1127 1128 static const struct iwl_causes_list causes_list_bz[] = { 1129 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1130 }; 1131 1132 static void iwl_pcie_map_list(struct iwl_trans *trans, 1133 const struct iwl_causes_list *causes, 1134 int arr_size, int val) 1135 { 1136 int i; 1137 1138 for (i = 0; i < arr_size; i++) { 1139 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1140 iwl_clear_bit(trans, causes[i].mask_reg, 1141 BIT(causes[i].bit)); 1142 } 1143 } 1144 1145 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1146 { 1147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1148 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1149 /* 1150 * Access all non RX causes and map them to the default irq. 1151 * In case we are missing at least one interrupt vector, 1152 * the first interrupt vector will serve non-RX and FBQ causes. 1153 */ 1154 iwl_pcie_map_list(trans, causes_list_common, 1155 ARRAY_SIZE(causes_list_common), val); 1156 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1157 iwl_pcie_map_list(trans, causes_list_bz, 1158 ARRAY_SIZE(causes_list_bz), val); 1159 else 1160 iwl_pcie_map_list(trans, causes_list_pre_bz, 1161 ARRAY_SIZE(causes_list_pre_bz), val); 1162 } 1163 1164 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1165 { 1166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1167 u32 offset = 1168 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1169 u32 val, idx; 1170 1171 /* 1172 * The first RX queue - fallback queue, which is designated for 1173 * management frame, command responses etc, is always mapped to the 1174 * first interrupt vector. The other RX queues are mapped to 1175 * the other (N - 2) interrupt vectors. 1176 */ 1177 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1178 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1179 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1180 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1181 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1182 } 1183 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1184 1185 val = MSIX_FH_INT_CAUSES_Q(0); 1186 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1187 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1188 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1189 1190 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1191 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1192 } 1193 1194 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1195 { 1196 struct iwl_trans *trans = trans_pcie->trans; 1197 1198 if (!trans_pcie->msix_enabled) { 1199 if (trans->trans_cfg->mq_rx_supported && 1200 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1201 iwl_write_umac_prph(trans, UREG_CHICK, 1202 UREG_CHICK_MSI_ENABLE); 1203 return; 1204 } 1205 /* 1206 * The IVAR table needs to be configured again after reset, 1207 * but if the device is disabled, we can't write to 1208 * prph. 1209 */ 1210 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1211 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1212 1213 /* 1214 * Each cause from the causes list above and the RX causes is 1215 * represented as a byte in the IVAR table. The first nibble 1216 * represents the bound interrupt vector of the cause, the second 1217 * represents no auto clear for this cause. This will be set if its 1218 * interrupt vector is bound to serve other causes. 1219 */ 1220 iwl_pcie_map_rx_causes(trans); 1221 1222 iwl_pcie_map_non_rx_causes(trans); 1223 } 1224 1225 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1226 { 1227 struct iwl_trans *trans = trans_pcie->trans; 1228 1229 iwl_pcie_conf_msix_hw(trans_pcie); 1230 1231 if (!trans_pcie->msix_enabled) 1232 return; 1233 1234 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1235 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1236 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1237 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1238 } 1239 1240 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq) 1241 { 1242 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1243 1244 lockdep_assert_held(&trans_pcie->mutex); 1245 1246 if (trans_pcie->is_down) 1247 return; 1248 1249 trans_pcie->is_down = true; 1250 1251 /* tell the device to stop sending interrupts */ 1252 iwl_disable_interrupts(trans); 1253 1254 /* device going down, Stop using ICT table */ 1255 iwl_pcie_disable_ict(trans); 1256 1257 /* 1258 * If a HW restart happens during firmware loading, 1259 * then the firmware loading might call this function 1260 * and later it might be called again due to the 1261 * restart. So don't process again if the device is 1262 * already dead. 1263 */ 1264 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1265 IWL_DEBUG_INFO(trans, 1266 "DEVICE_ENABLED bit was set and is now cleared\n"); 1267 if (!from_irq) 1268 iwl_pcie_synchronize_irqs(trans); 1269 iwl_pcie_rx_napi_sync(trans); 1270 iwl_pcie_tx_stop(trans); 1271 iwl_pcie_rx_stop(trans); 1272 1273 /* Power-down device's busmaster DMA clocks */ 1274 if (!trans->cfg->apmg_not_supported) { 1275 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1276 APMG_CLK_VAL_DMA_CLK_RQT); 1277 udelay(5); 1278 } 1279 } 1280 1281 /* Make sure (redundant) we've released our request to stay awake */ 1282 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1283 iwl_clear_bit(trans, CSR_GP_CNTRL, 1284 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1285 else 1286 iwl_clear_bit(trans, CSR_GP_CNTRL, 1287 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1288 1289 /* Stop the device, and put it in low power state */ 1290 iwl_pcie_apm_stop(trans, false); 1291 1292 /* re-take ownership to prevent other users from stealing the device */ 1293 iwl_trans_pcie_sw_reset(trans, true); 1294 1295 /* 1296 * Upon stop, the IVAR table gets erased, so msi-x won't 1297 * work. This causes a bug in RF-KILL flows, since the interrupt 1298 * that enables radio won't fire on the correct irq, and the 1299 * driver won't be able to handle the interrupt. 1300 * Configure the IVAR table again after reset. 1301 */ 1302 iwl_pcie_conf_msix_hw(trans_pcie); 1303 1304 /* 1305 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1306 * This is a bug in certain verions of the hardware. 1307 * Certain devices also keep sending HW RF kill interrupt all 1308 * the time, unless the interrupt is ACKed even if the interrupt 1309 * should be masked. Re-ACK all the interrupts here. 1310 */ 1311 iwl_disable_interrupts(trans); 1312 1313 /* clear all status bits */ 1314 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1315 clear_bit(STATUS_INT_ENABLED, &trans->status); 1316 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1317 1318 /* 1319 * Even if we stop the HW, we still want the RF kill 1320 * interrupt 1321 */ 1322 iwl_enable_rfkill_int(trans); 1323 } 1324 1325 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1326 { 1327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1328 1329 if (trans_pcie->msix_enabled) { 1330 int i; 1331 1332 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1333 synchronize_irq(trans_pcie->msix_entries[i].vector); 1334 } else { 1335 synchronize_irq(trans_pcie->pci_dev->irq); 1336 } 1337 } 1338 1339 int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1340 const struct fw_img *fw, bool run_in_rfkill) 1341 { 1342 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1343 bool hw_rfkill; 1344 int ret; 1345 1346 /* This may fail if AMT took ownership of the device */ 1347 if (iwl_pcie_prepare_card_hw(trans)) { 1348 IWL_WARN(trans, "Exit HW not ready\n"); 1349 return -EIO; 1350 } 1351 1352 iwl_enable_rfkill_int(trans); 1353 1354 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1355 1356 /* 1357 * We enabled the RF-Kill interrupt and the handler may very 1358 * well be running. Disable the interrupts to make sure no other 1359 * interrupt can be fired. 1360 */ 1361 iwl_disable_interrupts(trans); 1362 1363 /* Make sure it finished running */ 1364 iwl_pcie_synchronize_irqs(trans); 1365 1366 mutex_lock(&trans_pcie->mutex); 1367 1368 /* If platform's RF_KILL switch is NOT set to KILL */ 1369 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1370 if (hw_rfkill && !run_in_rfkill) { 1371 ret = -ERFKILL; 1372 goto out; 1373 } 1374 1375 /* Someone called stop_device, don't try to start_fw */ 1376 if (trans_pcie->is_down) { 1377 IWL_WARN(trans, 1378 "Can't start_fw since the HW hasn't been started\n"); 1379 ret = -EIO; 1380 goto out; 1381 } 1382 1383 /* make sure rfkill handshake bits are cleared */ 1384 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1385 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1386 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1387 1388 /* clear (again), then enable host interrupts */ 1389 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1390 1391 ret = iwl_pcie_nic_init(trans); 1392 if (ret) { 1393 IWL_ERR(trans, "Unable to init nic\n"); 1394 goto out; 1395 } 1396 1397 /* 1398 * Now, we load the firmware and don't want to be interrupted, even 1399 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1400 * FH_TX interrupt which is needed to load the firmware). If the 1401 * RF-Kill switch is toggled, we will find out after having loaded 1402 * the firmware and return the proper value to the caller. 1403 */ 1404 iwl_enable_fw_load_int(trans); 1405 1406 /* really make sure rfkill handshake bits are cleared */ 1407 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1408 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1409 1410 /* Load the given image to the HW */ 1411 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1412 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1413 else 1414 ret = iwl_pcie_load_given_ucode(trans, fw); 1415 1416 /* re-check RF-Kill state since we may have missed the interrupt */ 1417 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1418 if (hw_rfkill && !run_in_rfkill) 1419 ret = -ERFKILL; 1420 1421 out: 1422 mutex_unlock(&trans_pcie->mutex); 1423 return ret; 1424 } 1425 1426 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1427 { 1428 iwl_pcie_reset_ict(trans); 1429 iwl_pcie_tx_start(trans, scd_addr); 1430 } 1431 1432 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1433 bool was_in_rfkill) 1434 { 1435 bool hw_rfkill; 1436 1437 /* 1438 * Check again since the RF kill state may have changed while 1439 * all the interrupts were disabled, in this case we couldn't 1440 * receive the RF kill interrupt and update the state in the 1441 * op_mode. 1442 * Don't call the op_mode if the rkfill state hasn't changed. 1443 * This allows the op_mode to call stop_device from the rfkill 1444 * notification without endless recursion. Under very rare 1445 * circumstances, we might have a small recursion if the rfkill 1446 * state changed exactly now while we were called from stop_device. 1447 * This is very unlikely but can happen and is supported. 1448 */ 1449 hw_rfkill = iwl_is_rfkill_set(trans); 1450 if (hw_rfkill) { 1451 set_bit(STATUS_RFKILL_HW, &trans->status); 1452 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1453 } else { 1454 clear_bit(STATUS_RFKILL_HW, &trans->status); 1455 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1456 } 1457 if (hw_rfkill != was_in_rfkill) 1458 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false); 1459 } 1460 1461 void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1462 { 1463 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1464 bool was_in_rfkill; 1465 1466 iwl_op_mode_time_point(trans->op_mode, 1467 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1468 NULL); 1469 1470 mutex_lock(&trans_pcie->mutex); 1471 trans_pcie->opmode_down = true; 1472 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1473 _iwl_trans_pcie_stop_device(trans, false); 1474 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1475 mutex_unlock(&trans_pcie->mutex); 1476 } 1477 1478 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq) 1479 { 1480 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1481 IWL_TRANS_GET_PCIE_TRANS(trans); 1482 1483 lockdep_assert_held(&trans_pcie->mutex); 1484 1485 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1486 state ? "disabled" : "enabled"); 1487 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) && 1488 !WARN_ON(trans->trans_cfg->gen2)) 1489 _iwl_trans_pcie_stop_device(trans, from_irq); 1490 } 1491 1492 static void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1493 bool test, bool reset) 1494 { 1495 iwl_disable_interrupts(trans); 1496 1497 /* 1498 * in testing mode, the host stays awake and the 1499 * hardware won't be reset (not even partially) 1500 */ 1501 if (test) 1502 return; 1503 1504 iwl_pcie_disable_ict(trans); 1505 1506 iwl_pcie_synchronize_irqs(trans); 1507 1508 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1509 iwl_clear_bit(trans, CSR_GP_CNTRL, 1510 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1511 iwl_clear_bit(trans, CSR_GP_CNTRL, 1512 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 1513 } else { 1514 iwl_clear_bit(trans, CSR_GP_CNTRL, 1515 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1516 iwl_clear_bit(trans, CSR_GP_CNTRL, 1517 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1518 } 1519 1520 if (reset) { 1521 /* 1522 * reset TX queues -- some of their registers reset during S3 1523 * so if we don't reset everything here the D3 image would try 1524 * to execute some invalid memory upon resume 1525 */ 1526 iwl_trans_pcie_tx_reset(trans); 1527 } 1528 1529 iwl_pcie_set_pwr(trans, true); 1530 } 1531 1532 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1533 { 1534 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1535 int ret; 1536 1537 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1538 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1539 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1540 UREG_DOORBELL_TO_ISR6_RESUME); 1541 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1542 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1543 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1544 CSR_IPC_SLEEP_CONTROL_RESUME); 1545 else 1546 return 0; 1547 1548 ret = wait_event_timeout(trans_pcie->sx_waitq, 1549 trans_pcie->sx_complete, 2 * HZ); 1550 1551 /* Invalidate it toward next suspend or resume */ 1552 trans_pcie->sx_complete = false; 1553 1554 if (!ret) { 1555 IWL_ERR(trans, "Timeout %s D3\n", 1556 suspend ? "entering" : "exiting"); 1557 return -ETIMEDOUT; 1558 } 1559 1560 return 0; 1561 } 1562 1563 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset) 1564 { 1565 int ret; 1566 1567 if (!reset) 1568 /* Enable persistence mode to avoid reset */ 1569 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1570 CSR_HW_IF_CONFIG_REG_PERSISTENCE); 1571 1572 ret = iwl_pcie_d3_handshake(trans, true); 1573 if (ret) 1574 return ret; 1575 1576 iwl_pcie_d3_complete_suspend(trans, test, reset); 1577 1578 return 0; 1579 } 1580 1581 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1582 enum iwl_d3_status *status, 1583 bool test, bool reset) 1584 { 1585 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1586 u32 val; 1587 int ret; 1588 1589 if (test) { 1590 iwl_enable_interrupts(trans); 1591 *status = IWL_D3_STATUS_ALIVE; 1592 ret = 0; 1593 goto out; 1594 } 1595 1596 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1597 iwl_set_bit(trans, CSR_GP_CNTRL, 1598 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1599 else 1600 iwl_set_bit(trans, CSR_GP_CNTRL, 1601 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1602 1603 ret = iwl_finish_nic_init(trans); 1604 if (ret) 1605 return ret; 1606 1607 /* 1608 * Reconfigure IVAR table in case of MSIX or reset ict table in 1609 * MSI mode since HW reset erased it. 1610 * Also enables interrupts - none will happen as 1611 * the device doesn't know we're waking it up, only when 1612 * the opmode actually tells it after this call. 1613 */ 1614 iwl_pcie_conf_msix_hw(trans_pcie); 1615 if (!trans_pcie->msix_enabled) 1616 iwl_pcie_reset_ict(trans); 1617 iwl_enable_interrupts(trans); 1618 1619 iwl_pcie_set_pwr(trans, false); 1620 1621 if (!reset) { 1622 iwl_clear_bit(trans, CSR_GP_CNTRL, 1623 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1624 } else { 1625 iwl_trans_pcie_tx_reset(trans); 1626 1627 ret = iwl_pcie_rx_init(trans); 1628 if (ret) { 1629 IWL_ERR(trans, 1630 "Failed to resume the device (RX reset)\n"); 1631 return ret; 1632 } 1633 } 1634 1635 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1636 iwl_read_umac_prph(trans, WFPM_GP2)); 1637 1638 val = iwl_read32(trans, CSR_RESET); 1639 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1640 *status = IWL_D3_STATUS_RESET; 1641 else 1642 *status = IWL_D3_STATUS_ALIVE; 1643 1644 out: 1645 if (*status == IWL_D3_STATUS_ALIVE) 1646 ret = iwl_pcie_d3_handshake(trans, false); 1647 else 1648 trans->state = IWL_TRANS_NO_FW; 1649 1650 return ret; 1651 } 1652 1653 static void 1654 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1655 struct iwl_trans *trans, 1656 const struct iwl_cfg_trans_params *cfg_trans) 1657 { 1658 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1659 int max_irqs, num_irqs, i, ret; 1660 u16 pci_cmd; 1661 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1662 1663 if (!cfg_trans->mq_rx_supported) 1664 goto enable_msi; 1665 1666 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1667 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1668 1669 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1670 for (i = 0; i < max_irqs; i++) 1671 trans_pcie->msix_entries[i].entry = i; 1672 1673 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1674 MSIX_MIN_INTERRUPT_VECTORS, 1675 max_irqs); 1676 if (num_irqs < 0) { 1677 IWL_DEBUG_INFO(trans, 1678 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1679 num_irqs); 1680 goto enable_msi; 1681 } 1682 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1683 1684 IWL_DEBUG_INFO(trans, 1685 "MSI-X enabled. %d interrupt vectors were allocated\n", 1686 num_irqs); 1687 1688 /* 1689 * In case the OS provides fewer interrupts than requested, different 1690 * causes will share the same interrupt vector as follows: 1691 * One interrupt less: non rx causes shared with FBQ. 1692 * Two interrupts less: non rx causes shared with FBQ and RSS. 1693 * More than two interrupts: we will use fewer RSS queues. 1694 */ 1695 if (num_irqs <= max_irqs - 2) { 1696 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1697 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1698 IWL_SHARED_IRQ_FIRST_RSS; 1699 } else if (num_irqs == max_irqs - 1) { 1700 trans_pcie->trans->num_rx_queues = num_irqs; 1701 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1702 } else { 1703 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1704 } 1705 1706 IWL_DEBUG_INFO(trans, 1707 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1708 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1709 1710 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1711 1712 trans_pcie->alloc_vecs = num_irqs; 1713 trans_pcie->msix_enabled = true; 1714 return; 1715 1716 enable_msi: 1717 ret = pci_enable_msi(pdev); 1718 if (ret) { 1719 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1720 /* enable rfkill interrupt: hw bug w/a */ 1721 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1722 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1723 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1724 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1725 } 1726 } 1727 } 1728 1729 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1730 { 1731 #if defined(CONFIG_SMP) 1732 int iter_rx_q, i, ret, cpu, offset; 1733 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1734 1735 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1736 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1737 offset = 1 + i; 1738 for (; i < iter_rx_q ; i++) { 1739 /* 1740 * Get the cpu prior to the place to search 1741 * (i.e. return will be > i - 1). 1742 */ 1743 cpu = cpumask_next(i - offset, cpu_online_mask); 1744 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1745 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1746 &trans_pcie->affinity_mask[i]); 1747 if (ret) 1748 IWL_ERR(trans_pcie->trans, 1749 "Failed to set affinity mask for IRQ %d\n", 1750 trans_pcie->msix_entries[i].vector); 1751 } 1752 #endif 1753 } 1754 1755 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1756 struct iwl_trans_pcie *trans_pcie) 1757 { 1758 int i; 1759 1760 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1761 int ret; 1762 struct msix_entry *msix_entry; 1763 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1764 1765 if (!qname) 1766 return -ENOMEM; 1767 1768 msix_entry = &trans_pcie->msix_entries[i]; 1769 ret = devm_request_threaded_irq(&pdev->dev, 1770 msix_entry->vector, 1771 iwl_pcie_msix_isr, 1772 (i == trans_pcie->def_irq) ? 1773 iwl_pcie_irq_msix_handler : 1774 iwl_pcie_irq_rx_msix_handler, 1775 IRQF_SHARED, 1776 qname, 1777 msix_entry); 1778 if (ret) { 1779 IWL_ERR(trans_pcie->trans, 1780 "Error allocating IRQ %d\n", i); 1781 1782 return ret; 1783 } 1784 } 1785 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1786 1787 return 0; 1788 } 1789 1790 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1791 { 1792 u32 hpm, wprot; 1793 1794 switch (trans->trans_cfg->device_family) { 1795 case IWL_DEVICE_FAMILY_9000: 1796 wprot = PREG_PRPH_WPROT_9000; 1797 break; 1798 case IWL_DEVICE_FAMILY_22000: 1799 wprot = PREG_PRPH_WPROT_22000; 1800 break; 1801 default: 1802 return 0; 1803 } 1804 1805 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1806 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { 1807 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1808 1809 if (wprot_val & PREG_WFPM_ACCESS) { 1810 IWL_ERR(trans, 1811 "Error, can not clear persistence bit\n"); 1812 return -EPERM; 1813 } 1814 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1815 hpm & ~PERSISTENCE_BIT); 1816 } 1817 1818 return 0; 1819 } 1820 1821 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1822 { 1823 int ret; 1824 1825 ret = iwl_finish_nic_init(trans); 1826 if (ret < 0) 1827 return ret; 1828 1829 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1830 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1831 udelay(20); 1832 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1833 HPM_HIPM_GEN_CFG_CR_PG_EN | 1834 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1835 udelay(20); 1836 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1837 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1838 1839 return iwl_trans_pcie_sw_reset(trans, true); 1840 } 1841 1842 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1843 { 1844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1845 int err; 1846 1847 lockdep_assert_held(&trans_pcie->mutex); 1848 1849 err = iwl_pcie_prepare_card_hw(trans); 1850 if (err) { 1851 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1852 return err; 1853 } 1854 1855 err = iwl_trans_pcie_clear_persistence_bit(trans); 1856 if (err) 1857 return err; 1858 1859 err = iwl_trans_pcie_sw_reset(trans, true); 1860 if (err) 1861 return err; 1862 1863 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1864 trans->trans_cfg->integrated) { 1865 err = iwl_pcie_gen2_force_power_gating(trans); 1866 if (err) 1867 return err; 1868 } 1869 1870 err = iwl_pcie_apm_init(trans); 1871 if (err) 1872 return err; 1873 1874 iwl_pcie_init_msix(trans_pcie); 1875 1876 /* From now on, the op_mode will be kept updated about RF kill state */ 1877 iwl_enable_rfkill_int(trans); 1878 1879 trans_pcie->opmode_down = false; 1880 1881 /* Set is_down to false here so that...*/ 1882 trans_pcie->is_down = false; 1883 1884 /* ...rfkill can call stop_device and set it false if needed */ 1885 iwl_pcie_check_hw_rf_kill(trans); 1886 1887 return 0; 1888 } 1889 1890 int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1891 { 1892 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1893 int ret; 1894 1895 mutex_lock(&trans_pcie->mutex); 1896 ret = _iwl_trans_pcie_start_hw(trans); 1897 mutex_unlock(&trans_pcie->mutex); 1898 1899 return ret; 1900 } 1901 1902 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1903 { 1904 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1905 1906 mutex_lock(&trans_pcie->mutex); 1907 1908 /* disable interrupts - don't enable HW RF kill interrupt */ 1909 iwl_disable_interrupts(trans); 1910 1911 iwl_pcie_apm_stop(trans, true); 1912 1913 iwl_disable_interrupts(trans); 1914 1915 iwl_pcie_disable_ict(trans); 1916 1917 mutex_unlock(&trans_pcie->mutex); 1918 1919 iwl_pcie_synchronize_irqs(trans); 1920 } 1921 1922 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1923 { 1924 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1925 } 1926 1927 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1928 { 1929 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1930 } 1931 1932 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1933 { 1934 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1935 } 1936 1937 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1938 { 1939 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1940 return 0x00FFFFFF; 1941 else 1942 return 0x000FFFFF; 1943 } 1944 1945 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1946 { 1947 u32 mask = iwl_trans_pcie_prph_msk(trans); 1948 1949 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1950 ((reg & mask) | (3 << 24))); 1951 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1952 } 1953 1954 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val) 1955 { 1956 u32 mask = iwl_trans_pcie_prph_msk(trans); 1957 1958 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1959 ((addr & mask) | (3 << 24))); 1960 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1961 } 1962 1963 void iwl_trans_pcie_configure(struct iwl_trans *trans, 1964 const struct iwl_trans_config *trans_cfg) 1965 { 1966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1967 1968 /* free all first - we might be reconfigured for a different size */ 1969 iwl_pcie_free_rbs_pool(trans); 1970 1971 trans_pcie->txqs.cmd.q_id = trans_cfg->cmd_queue; 1972 trans_pcie->txqs.cmd.fifo = trans_cfg->cmd_fifo; 1973 trans_pcie->txqs.page_offs = trans_cfg->cb_data_offs; 1974 trans_pcie->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1975 trans_pcie->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 1976 1977 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1978 trans_pcie->n_no_reclaim_cmds = 0; 1979 else 1980 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1981 if (trans_pcie->n_no_reclaim_cmds) 1982 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1983 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1984 1985 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1986 trans_pcie->rx_page_order = 1987 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1988 trans_pcie->rx_buf_bytes = 1989 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1990 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1991 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1992 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1993 1994 trans_pcie->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1995 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1996 1997 trans->command_groups = trans_cfg->command_groups; 1998 trans->command_groups_size = trans_cfg->command_groups_size; 1999 2000 2001 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 2002 } 2003 2004 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 2005 struct device *dev) 2006 { 2007 u8 i; 2008 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 2009 2010 /* free DRAM payloads */ 2011 for (i = 0; i < dram_regions->n_regions; i++) { 2012 dma_free_coherent(dev, dram_regions->drams[i].size, 2013 dram_regions->drams[i].block, 2014 dram_regions->drams[i].physical); 2015 } 2016 dram_regions->n_regions = 0; 2017 2018 /* free DRAM addresses array */ 2019 if (desc_dram->block) { 2020 dma_free_coherent(dev, desc_dram->size, 2021 desc_dram->block, 2022 desc_dram->physical); 2023 } 2024 memset(desc_dram, 0, sizeof(*desc_dram)); 2025 } 2026 2027 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) 2028 { 2029 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); 2030 } 2031 2032 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) 2033 { 2034 struct iwl_cmd_header_wide bad_cmd = { 2035 .cmd = INVALID_WR_PTR_CMD, 2036 .group_id = DEBUG_GROUP, 2037 .sequence = cpu_to_le16(0xffff), 2038 .length = cpu_to_le16(0), 2039 .version = 0, 2040 }; 2041 int ret; 2042 2043 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, 2044 sizeof(bad_cmd)); 2045 if (ret) 2046 return ret; 2047 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); 2048 return 0; 2049 } 2050 2051 void iwl_trans_pcie_free(struct iwl_trans *trans) 2052 { 2053 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2054 int i; 2055 2056 iwl_pcie_synchronize_irqs(trans); 2057 2058 if (trans->trans_cfg->gen2) 2059 iwl_txq_gen2_tx_free(trans); 2060 else 2061 iwl_pcie_tx_free(trans); 2062 iwl_pcie_rx_free(trans); 2063 2064 if (trans_pcie->rba.alloc_wq) { 2065 destroy_workqueue(trans_pcie->rba.alloc_wq); 2066 trans_pcie->rba.alloc_wq = NULL; 2067 } 2068 2069 if (trans_pcie->msix_enabled) { 2070 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2071 irq_set_affinity_hint( 2072 trans_pcie->msix_entries[i].vector, 2073 NULL); 2074 } 2075 2076 trans_pcie->msix_enabled = false; 2077 } else { 2078 iwl_pcie_free_ict(trans); 2079 } 2080 2081 free_netdev(trans_pcie->napi_dev); 2082 2083 iwl_pcie_free_invalid_tx_cmd(trans); 2084 2085 iwl_pcie_free_fw_monitor(trans); 2086 2087 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, 2088 trans->dev); 2089 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, 2090 trans->dev); 2091 2092 mutex_destroy(&trans_pcie->mutex); 2093 2094 if (trans_pcie->txqs.tso_hdr_page) { 2095 for_each_possible_cpu(i) { 2096 struct iwl_tso_hdr_page *p = 2097 per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i); 2098 2099 if (p && p->page) 2100 __free_page(p->page); 2101 } 2102 2103 free_percpu(trans_pcie->txqs.tso_hdr_page); 2104 } 2105 2106 iwl_trans_free(trans); 2107 } 2108 2109 static union acpi_object * 2110 iwl_trans_pcie_call_prod_reset_dsm(struct pci_dev *pdev, u16 cmd, u16 value) 2111 { 2112 #ifdef CONFIG_ACPI 2113 struct iwl_dsm_internal_product_reset_cmd pldr_arg = { 2114 .cmd = cmd, 2115 .value = value, 2116 }; 2117 union acpi_object arg = { 2118 .buffer.type = ACPI_TYPE_BUFFER, 2119 .buffer.length = sizeof(pldr_arg), 2120 .buffer.pointer = (void *)&pldr_arg, 2121 }; 2122 static const guid_t dsm_guid = GUID_INIT(0x7266172C, 0x220B, 0x4B29, 2123 0x81, 0x4F, 0x75, 0xE4, 2124 0xDD, 0x26, 0xB5, 0xFD); 2125 2126 if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &dsm_guid, ACPI_DSM_REV, 2127 DSM_INTERNAL_FUNC_PRODUCT_RESET)) 2128 return ERR_PTR(-ENODEV); 2129 2130 return iwl_acpi_get_dsm_object(&pdev->dev, ACPI_DSM_REV, 2131 DSM_INTERNAL_FUNC_PRODUCT_RESET, 2132 &arg, &dsm_guid); 2133 #else 2134 return ERR_PTR(-EOPNOTSUPP); 2135 #endif 2136 } 2137 2138 void iwl_trans_pcie_check_product_reset_mode(struct pci_dev *pdev) 2139 { 2140 union acpi_object *res; 2141 2142 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2143 DSM_INTERNAL_PLDR_CMD_GET_MODE, 2144 0); 2145 if (IS_ERR(res)) 2146 return; 2147 2148 if (res->type != ACPI_TYPE_INTEGER) 2149 IWL_ERR_DEV(&pdev->dev, 2150 "unexpected return type from product reset DSM\n"); 2151 else 2152 IWL_DEBUG_DEV_POWER(&pdev->dev, 2153 "product reset mode is 0x%llx\n", 2154 res->integer.value); 2155 2156 ACPI_FREE(res); 2157 } 2158 2159 static void iwl_trans_pcie_set_product_reset(struct pci_dev *pdev, bool enable, 2160 bool integrated) 2161 { 2162 union acpi_object *res; 2163 u16 mode = enable ? DSM_INTERNAL_PLDR_MODE_EN_PROD_RESET : 0; 2164 2165 if (!integrated) 2166 mode |= DSM_INTERNAL_PLDR_MODE_EN_WIFI_FLR | 2167 DSM_INTERNAL_PLDR_MODE_EN_BT_OFF_ON; 2168 2169 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2170 DSM_INTERNAL_PLDR_CMD_SET_MODE, 2171 mode); 2172 if (IS_ERR(res)) { 2173 if (enable) 2174 IWL_ERR_DEV(&pdev->dev, 2175 "ACPI _DSM not available (%d), cannot do product reset\n", 2176 (int)PTR_ERR(res)); 2177 return; 2178 } 2179 2180 ACPI_FREE(res); 2181 IWL_DEBUG_DEV_POWER(&pdev->dev, "%sabled product reset via DSM\n", 2182 enable ? "En" : "Dis"); 2183 iwl_trans_pcie_check_product_reset_mode(pdev); 2184 } 2185 2186 void iwl_trans_pcie_check_product_reset_status(struct pci_dev *pdev) 2187 { 2188 union acpi_object *res; 2189 2190 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2191 DSM_INTERNAL_PLDR_CMD_GET_STATUS, 2192 0); 2193 if (IS_ERR(res)) 2194 return; 2195 2196 if (res->type != ACPI_TYPE_INTEGER) 2197 IWL_ERR_DEV(&pdev->dev, 2198 "unexpected return type from product reset DSM\n"); 2199 else 2200 IWL_DEBUG_DEV_POWER(&pdev->dev, 2201 "product reset status is 0x%llx\n", 2202 res->integer.value); 2203 2204 ACPI_FREE(res); 2205 } 2206 2207 static void iwl_trans_pcie_call_reset(struct pci_dev *pdev) 2208 { 2209 #ifdef CONFIG_ACPI 2210 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2211 union acpi_object *p, *ref; 2212 acpi_status status; 2213 int ret = -EINVAL; 2214 2215 status = acpi_evaluate_object(ACPI_HANDLE(&pdev->dev), 2216 "_PRR", NULL, &buffer); 2217 if (ACPI_FAILURE(status)) { 2218 IWL_DEBUG_DEV_POWER(&pdev->dev, "No _PRR method found\n"); 2219 goto out; 2220 } 2221 p = buffer.pointer; 2222 2223 if (p->type != ACPI_TYPE_PACKAGE || p->package.count != 1) { 2224 pci_err(pdev, "Bad _PRR return type\n"); 2225 goto out; 2226 } 2227 2228 ref = &p->package.elements[0]; 2229 if (ref->type != ACPI_TYPE_LOCAL_REFERENCE) { 2230 pci_err(pdev, "_PRR wasn't a reference\n"); 2231 goto out; 2232 } 2233 2234 status = acpi_evaluate_object(ref->reference.handle, 2235 "_RST", NULL, NULL); 2236 if (ACPI_FAILURE(status)) { 2237 pci_err(pdev, 2238 "Failed to call _RST on object returned by _PRR (%d)\n", 2239 status); 2240 goto out; 2241 } 2242 ret = 0; 2243 out: 2244 kfree(buffer.pointer); 2245 if (!ret) { 2246 IWL_DEBUG_DEV_POWER(&pdev->dev, "called _RST on _PRR object\n"); 2247 return; 2248 } 2249 IWL_DEBUG_DEV_POWER(&pdev->dev, 2250 "No BIOS support, using pci_reset_function()\n"); 2251 #endif 2252 pci_reset_function(pdev); 2253 } 2254 2255 struct iwl_trans_pcie_removal { 2256 struct pci_dev *pdev; 2257 struct work_struct work; 2258 enum iwl_reset_mode mode; 2259 bool integrated; 2260 }; 2261 2262 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2263 { 2264 struct iwl_trans_pcie_removal *removal = 2265 container_of(wk, struct iwl_trans_pcie_removal, work); 2266 struct pci_dev *pdev = removal->pdev; 2267 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2268 struct pci_bus *bus; 2269 2270 pci_lock_rescan_remove(); 2271 2272 bus = pdev->bus; 2273 /* in this case, something else already removed the device */ 2274 if (!bus) 2275 goto out; 2276 2277 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2278 2279 if (removal->mode == IWL_RESET_MODE_PROD_RESET) { 2280 struct pci_dev *bt = NULL; 2281 2282 if (!removal->integrated) { 2283 /* discrete devices have WiFi/BT at function 0/1 */ 2284 int slot = PCI_SLOT(pdev->devfn); 2285 int func = PCI_FUNC(pdev->devfn); 2286 2287 if (func == 0) 2288 bt = pci_get_slot(bus, PCI_DEVFN(slot, 1)); 2289 else 2290 pci_info(pdev, "Unexpected function %d\n", 2291 func); 2292 } else { 2293 /* on integrated we have to look up by ID (same bus) */ 2294 static const struct pci_device_id bt_device_ids[] = { 2295 #define BT_DEV(_id) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, _id) } 2296 BT_DEV(0xA876), /* LNL */ 2297 BT_DEV(0xE476), /* PTL-P */ 2298 BT_DEV(0xE376), /* PTL-H */ 2299 BT_DEV(0xD346), /* NVL-H */ 2300 BT_DEV(0x6E74), /* NVL-S */ 2301 BT_DEV(0x4D76), /* WCL */ 2302 BT_DEV(0xD246), /* RZL-H */ 2303 BT_DEV(0x6C46), /* RZL-M */ 2304 {} 2305 }; 2306 struct pci_dev *tmp = NULL; 2307 2308 for_each_pci_dev(tmp) { 2309 if (tmp->bus != bus) 2310 continue; 2311 2312 if (pci_match_id(bt_device_ids, tmp)) { 2313 bt = tmp; 2314 break; 2315 } 2316 } 2317 } 2318 2319 if (bt) { 2320 pci_info(bt, "Removal by WiFi due to product reset\n"); 2321 pci_stop_and_remove_bus_device(bt); 2322 pci_dev_put(bt); 2323 } 2324 } 2325 2326 iwl_trans_pcie_set_product_reset(pdev, 2327 removal->mode == 2328 IWL_RESET_MODE_PROD_RESET, 2329 removal->integrated); 2330 if (removal->mode >= IWL_RESET_MODE_FUNC_RESET) 2331 iwl_trans_pcie_call_reset(pdev); 2332 2333 pci_stop_and_remove_bus_device(pdev); 2334 pci_dev_put(pdev); 2335 2336 if (removal->mode >= IWL_RESET_MODE_RESCAN) { 2337 if (bus->parent) 2338 bus = bus->parent; 2339 pci_rescan_bus(bus); 2340 } 2341 2342 out: 2343 pci_unlock_rescan_remove(); 2344 2345 kfree(removal); 2346 module_put(THIS_MODULE); 2347 } 2348 2349 void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode) 2350 { 2351 struct iwl_trans_pcie_removal *removal; 2352 char _msg = 0, *msg = &_msg; 2353 2354 if (WARN_ON(mode < IWL_RESET_MODE_REMOVE_ONLY)) 2355 return; 2356 2357 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2358 return; 2359 2360 if (trans->me_present && mode == IWL_RESET_MODE_PROD_RESET) { 2361 mode = IWL_RESET_MODE_FUNC_RESET; 2362 if (trans->me_present < 0) 2363 msg = " instead of product reset as ME may be present"; 2364 else 2365 msg = " instead of product reset as ME is present"; 2366 } 2367 2368 IWL_INFO(trans, "scheduling reset (mode=%d%s)\n", mode, msg); 2369 2370 iwl_pcie_dump_csr(trans); 2371 2372 /* 2373 * get a module reference to avoid doing this 2374 * while unloading anyway and to avoid 2375 * scheduling a work with code that's being 2376 * removed. 2377 */ 2378 if (!try_module_get(THIS_MODULE)) { 2379 IWL_ERR(trans, 2380 "Module is being unloaded - abort\n"); 2381 return; 2382 } 2383 2384 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2385 if (!removal) { 2386 module_put(THIS_MODULE); 2387 return; 2388 } 2389 /* 2390 * we don't need to clear this flag, because 2391 * the trans will be freed and reallocated. 2392 */ 2393 set_bit(STATUS_TRANS_DEAD, &trans->status); 2394 2395 removal->pdev = to_pci_dev(trans->dev); 2396 removal->mode = mode; 2397 removal->integrated = trans->trans_cfg->integrated; 2398 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2399 pci_dev_get(removal->pdev); 2400 schedule_work(&removal->work); 2401 } 2402 EXPORT_SYMBOL(iwl_trans_pcie_reset); 2403 2404 /* 2405 * This version doesn't disable BHs but rather assumes they're 2406 * already disabled. 2407 */ 2408 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2409 { 2410 int ret; 2411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2412 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2413 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2414 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2415 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2416 2417 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2418 return false; 2419 2420 spin_lock(&trans_pcie->reg_lock); 2421 2422 if (trans_pcie->cmd_hold_nic_awake) 2423 goto out; 2424 2425 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2426 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2427 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2428 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2429 } 2430 2431 /* this bit wakes up the NIC */ 2432 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2433 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2434 udelay(2); 2435 2436 /* 2437 * These bits say the device is running, and should keep running for 2438 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2439 * but they do not indicate that embedded SRAM is restored yet; 2440 * HW with volatile SRAM must save/restore contents to/from 2441 * host DRAM when sleeping/waking for power-saving. 2442 * Each direction takes approximately 1/4 millisecond; with this 2443 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2444 * series of register accesses are expected (e.g. reading Event Log), 2445 * to keep device from sleeping. 2446 * 2447 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2448 * SRAM is okay/restored. We don't check that here because this call 2449 * is just for hardware register access; but GP1 MAC_SLEEP 2450 * check is a good idea before accessing the SRAM of HW with 2451 * volatile SRAM (e.g. reading Event Log). 2452 * 2453 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2454 * and do not save/restore SRAM when power cycling. 2455 */ 2456 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2457 if (unlikely(ret < 0)) { 2458 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2459 2460 WARN_ONCE(1, 2461 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2462 cntrl); 2463 2464 iwl_trans_pcie_dump_regs(trans); 2465 2466 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2467 iwl_trans_pcie_reset(trans, 2468 IWL_RESET_MODE_REMOVE_ONLY); 2469 else 2470 iwl_write32(trans, CSR_RESET, 2471 CSR_RESET_REG_FLAG_FORCE_NMI); 2472 2473 spin_unlock(&trans_pcie->reg_lock); 2474 return false; 2475 } 2476 2477 out: 2478 /* 2479 * Fool sparse by faking we release the lock - sparse will 2480 * track nic_access anyway. 2481 */ 2482 __release(&trans_pcie->reg_lock); 2483 return true; 2484 } 2485 2486 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2487 { 2488 bool ret; 2489 2490 local_bh_disable(); 2491 ret = __iwl_trans_pcie_grab_nic_access(trans); 2492 if (ret) { 2493 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2494 return ret; 2495 } 2496 local_bh_enable(); 2497 return false; 2498 } 2499 2500 void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2501 { 2502 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2503 2504 lockdep_assert_held(&trans_pcie->reg_lock); 2505 2506 /* 2507 * Fool sparse by faking we acquiring the lock - sparse will 2508 * track nic_access anyway. 2509 */ 2510 __acquire(&trans_pcie->reg_lock); 2511 2512 if (trans_pcie->cmd_hold_nic_awake) 2513 goto out; 2514 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2515 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2516 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2517 else 2518 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2519 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2520 /* 2521 * Above we read the CSR_GP_CNTRL register, which will flush 2522 * any previous writes, but we need the write that clears the 2523 * MAC_ACCESS_REQ bit to be performed before any other writes 2524 * scheduled on different CPUs (after we drop reg_lock). 2525 */ 2526 out: 2527 spin_unlock_bh(&trans_pcie->reg_lock); 2528 } 2529 2530 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2531 void *buf, int dwords) 2532 { 2533 #define IWL_MAX_HW_ERRS 5 2534 unsigned int num_consec_hw_errors = 0; 2535 int offs = 0; 2536 u32 *vals = buf; 2537 2538 while (offs < dwords) { 2539 /* limit the time we spin here under lock to 1/2s */ 2540 unsigned long end = jiffies + HZ / 2; 2541 bool resched = false; 2542 2543 if (iwl_trans_grab_nic_access(trans)) { 2544 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2545 addr + 4 * offs); 2546 2547 while (offs < dwords) { 2548 vals[offs] = iwl_read32(trans, 2549 HBUS_TARG_MEM_RDAT); 2550 2551 if (iwl_trans_is_hw_error_value(vals[offs])) 2552 num_consec_hw_errors++; 2553 else 2554 num_consec_hw_errors = 0; 2555 2556 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) { 2557 iwl_trans_release_nic_access(trans); 2558 return -EIO; 2559 } 2560 2561 offs++; 2562 2563 if (time_after(jiffies, end)) { 2564 resched = true; 2565 break; 2566 } 2567 } 2568 iwl_trans_release_nic_access(trans); 2569 2570 if (resched) 2571 cond_resched(); 2572 } else { 2573 return -EBUSY; 2574 } 2575 } 2576 2577 return 0; 2578 } 2579 2580 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2581 const void *buf, int dwords) 2582 { 2583 int offs, ret = 0; 2584 const u32 *vals = buf; 2585 2586 if (iwl_trans_grab_nic_access(trans)) { 2587 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2588 for (offs = 0; offs < dwords; offs++) 2589 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2590 vals ? vals[offs] : 0); 2591 iwl_trans_release_nic_access(trans); 2592 } else { 2593 ret = -EBUSY; 2594 } 2595 return ret; 2596 } 2597 2598 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2599 u32 *val) 2600 { 2601 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2602 ofs, val); 2603 } 2604 2605 #define IWL_FLUSH_WAIT_MS 2000 2606 2607 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2608 struct iwl_trans_rxq_dma_data *data) 2609 { 2610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2611 2612 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2613 return -EINVAL; 2614 2615 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2616 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2617 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2618 data->fr_bd_wid = 0; 2619 2620 return 0; 2621 } 2622 2623 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2624 { 2625 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2626 struct iwl_txq *txq; 2627 unsigned long now = jiffies; 2628 bool overflow_tx; 2629 u8 wr_ptr; 2630 2631 /* Make sure the NIC is still alive in the bus */ 2632 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2633 return -ENODEV; 2634 2635 if (!test_bit(txq_idx, trans_pcie->txqs.queue_used)) 2636 return -EINVAL; 2637 2638 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2639 txq = trans_pcie->txqs.txq[txq_idx]; 2640 2641 spin_lock_bh(&txq->lock); 2642 overflow_tx = txq->overflow_tx || 2643 !skb_queue_empty(&txq->overflow_q); 2644 spin_unlock_bh(&txq->lock); 2645 2646 wr_ptr = READ_ONCE(txq->write_ptr); 2647 2648 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2649 overflow_tx) && 2650 !time_after(jiffies, 2651 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2652 u8 write_ptr = READ_ONCE(txq->write_ptr); 2653 2654 /* 2655 * If write pointer moved during the wait, warn only 2656 * if the TX came from op mode. In case TX came from 2657 * trans layer (overflow TX) don't warn. 2658 */ 2659 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2660 "WR pointer moved while flushing %d -> %d\n", 2661 wr_ptr, write_ptr)) 2662 return -ETIMEDOUT; 2663 wr_ptr = write_ptr; 2664 2665 usleep_range(1000, 2000); 2666 2667 spin_lock_bh(&txq->lock); 2668 overflow_tx = txq->overflow_tx || 2669 !skb_queue_empty(&txq->overflow_q); 2670 spin_unlock_bh(&txq->lock); 2671 } 2672 2673 if (txq->read_ptr != txq->write_ptr) { 2674 IWL_ERR(trans, 2675 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2676 iwl_txq_log_scd_error(trans, txq); 2677 return -ETIMEDOUT; 2678 } 2679 2680 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2681 2682 return 0; 2683 } 2684 2685 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2686 { 2687 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2688 int cnt; 2689 int ret = 0; 2690 2691 /* waiting for all the tx frames complete might take a while */ 2692 for (cnt = 0; 2693 cnt < trans->trans_cfg->base_params->num_of_queues; 2694 cnt++) { 2695 2696 if (cnt == trans_pcie->txqs.cmd.q_id) 2697 continue; 2698 if (!test_bit(cnt, trans_pcie->txqs.queue_used)) 2699 continue; 2700 if (!(BIT(cnt) & txq_bm)) 2701 continue; 2702 2703 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2704 if (ret) 2705 break; 2706 } 2707 2708 return ret; 2709 } 2710 2711 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2712 u32 mask, u32 value) 2713 { 2714 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2715 2716 spin_lock_bh(&trans_pcie->reg_lock); 2717 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2718 spin_unlock_bh(&trans_pcie->reg_lock); 2719 } 2720 2721 static const char *get_csr_string(int cmd) 2722 { 2723 #define IWL_CMD(x) case x: return #x 2724 switch (cmd) { 2725 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2726 IWL_CMD(CSR_INT_COALESCING); 2727 IWL_CMD(CSR_INT); 2728 IWL_CMD(CSR_INT_MASK); 2729 IWL_CMD(CSR_FH_INT_STATUS); 2730 IWL_CMD(CSR_GPIO_IN); 2731 IWL_CMD(CSR_RESET); 2732 IWL_CMD(CSR_GP_CNTRL); 2733 IWL_CMD(CSR_HW_REV); 2734 IWL_CMD(CSR_EEPROM_REG); 2735 IWL_CMD(CSR_EEPROM_GP); 2736 IWL_CMD(CSR_OTP_GP_REG); 2737 IWL_CMD(CSR_GIO_REG); 2738 IWL_CMD(CSR_GP_UCODE_REG); 2739 IWL_CMD(CSR_GP_DRIVER_REG); 2740 IWL_CMD(CSR_UCODE_DRV_GP1); 2741 IWL_CMD(CSR_UCODE_DRV_GP2); 2742 IWL_CMD(CSR_LED_REG); 2743 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2744 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2745 IWL_CMD(CSR_ANA_PLL_CFG); 2746 IWL_CMD(CSR_HW_REV_WA_REG); 2747 IWL_CMD(CSR_MONITOR_STATUS_REG); 2748 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2749 default: 2750 return "UNKNOWN"; 2751 } 2752 #undef IWL_CMD 2753 } 2754 2755 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2756 { 2757 int i; 2758 static const u32 csr_tbl[] = { 2759 CSR_HW_IF_CONFIG_REG, 2760 CSR_INT_COALESCING, 2761 CSR_INT, 2762 CSR_INT_MASK, 2763 CSR_FH_INT_STATUS, 2764 CSR_GPIO_IN, 2765 CSR_RESET, 2766 CSR_GP_CNTRL, 2767 CSR_HW_REV, 2768 CSR_EEPROM_REG, 2769 CSR_EEPROM_GP, 2770 CSR_OTP_GP_REG, 2771 CSR_GIO_REG, 2772 CSR_GP_UCODE_REG, 2773 CSR_GP_DRIVER_REG, 2774 CSR_UCODE_DRV_GP1, 2775 CSR_UCODE_DRV_GP2, 2776 CSR_LED_REG, 2777 CSR_DRAM_INT_TBL_REG, 2778 CSR_GIO_CHICKEN_BITS, 2779 CSR_ANA_PLL_CFG, 2780 CSR_MONITOR_STATUS_REG, 2781 CSR_HW_REV_WA_REG, 2782 CSR_DBG_HPET_MEM_REG 2783 }; 2784 IWL_ERR(trans, "CSR values:\n"); 2785 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2786 "CSR_INT_PERIODIC_REG)\n"); 2787 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2788 IWL_ERR(trans, " %25s: 0X%08x\n", 2789 get_csr_string(csr_tbl[i]), 2790 iwl_read32(trans, csr_tbl[i])); 2791 } 2792 } 2793 2794 #ifdef CONFIG_IWLWIFI_DEBUGFS 2795 /* create and remove of files */ 2796 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2797 debugfs_create_file(#name, mode, parent, trans, \ 2798 &iwl_dbgfs_##name##_ops); \ 2799 } while (0) 2800 2801 /* file operation */ 2802 #define DEBUGFS_READ_FILE_OPS(name) \ 2803 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2804 .read = iwl_dbgfs_##name##_read, \ 2805 .open = simple_open, \ 2806 .llseek = generic_file_llseek, \ 2807 }; 2808 2809 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2810 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2811 .write = iwl_dbgfs_##name##_write, \ 2812 .open = simple_open, \ 2813 .llseek = generic_file_llseek, \ 2814 }; 2815 2816 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2817 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2818 .write = iwl_dbgfs_##name##_write, \ 2819 .read = iwl_dbgfs_##name##_read, \ 2820 .open = simple_open, \ 2821 .llseek = generic_file_llseek, \ 2822 }; 2823 2824 struct iwl_dbgfs_tx_queue_priv { 2825 struct iwl_trans *trans; 2826 }; 2827 2828 struct iwl_dbgfs_tx_queue_state { 2829 loff_t pos; 2830 }; 2831 2832 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2833 { 2834 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2835 struct iwl_dbgfs_tx_queue_state *state; 2836 2837 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2838 return NULL; 2839 2840 state = kmalloc(sizeof(*state), GFP_KERNEL); 2841 if (!state) 2842 return NULL; 2843 state->pos = *pos; 2844 return state; 2845 } 2846 2847 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2848 void *v, loff_t *pos) 2849 { 2850 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2851 struct iwl_dbgfs_tx_queue_state *state = v; 2852 2853 *pos = ++state->pos; 2854 2855 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2856 return NULL; 2857 2858 return state; 2859 } 2860 2861 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2862 { 2863 kfree(v); 2864 } 2865 2866 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2867 { 2868 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2869 struct iwl_dbgfs_tx_queue_state *state = v; 2870 struct iwl_trans *trans = priv->trans; 2871 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2872 struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos]; 2873 2874 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2875 (unsigned int)state->pos, 2876 !!test_bit(state->pos, trans_pcie->txqs.queue_used), 2877 !!test_bit(state->pos, trans_pcie->txqs.queue_stopped)); 2878 if (txq) 2879 seq_printf(seq, 2880 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2881 txq->read_ptr, txq->write_ptr, 2882 txq->need_update, txq->frozen, 2883 txq->n_window, txq->ampdu); 2884 else 2885 seq_puts(seq, "(unallocated)"); 2886 2887 if (state->pos == trans_pcie->txqs.cmd.q_id) 2888 seq_puts(seq, " (HCMD)"); 2889 seq_puts(seq, "\n"); 2890 2891 return 0; 2892 } 2893 2894 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2895 .start = iwl_dbgfs_tx_queue_seq_start, 2896 .next = iwl_dbgfs_tx_queue_seq_next, 2897 .stop = iwl_dbgfs_tx_queue_seq_stop, 2898 .show = iwl_dbgfs_tx_queue_seq_show, 2899 }; 2900 2901 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2902 { 2903 struct iwl_dbgfs_tx_queue_priv *priv; 2904 2905 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2906 sizeof(*priv)); 2907 2908 if (!priv) 2909 return -ENOMEM; 2910 2911 priv->trans = inode->i_private; 2912 return 0; 2913 } 2914 2915 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2916 char __user *user_buf, 2917 size_t count, loff_t *ppos) 2918 { 2919 struct iwl_trans *trans = file->private_data; 2920 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2921 char *buf; 2922 int pos = 0, i, ret; 2923 size_t bufsz; 2924 2925 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2926 2927 if (!trans_pcie->rxq) 2928 return -EAGAIN; 2929 2930 buf = kzalloc(bufsz, GFP_KERNEL); 2931 if (!buf) 2932 return -ENOMEM; 2933 2934 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2935 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2936 2937 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2938 i); 2939 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2940 rxq->read); 2941 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2942 rxq->write); 2943 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2944 rxq->write_actual); 2945 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2946 rxq->need_update); 2947 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2948 rxq->free_count); 2949 if (rxq->rb_stts) { 2950 u32 r = iwl_get_closed_rb_stts(trans, rxq); 2951 pos += scnprintf(buf + pos, bufsz - pos, 2952 "\tclosed_rb_num: %u\n", r); 2953 } else { 2954 pos += scnprintf(buf + pos, bufsz - pos, 2955 "\tclosed_rb_num: Not Allocated\n"); 2956 } 2957 } 2958 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2959 kfree(buf); 2960 2961 return ret; 2962 } 2963 2964 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2965 char __user *user_buf, 2966 size_t count, loff_t *ppos) 2967 { 2968 struct iwl_trans *trans = file->private_data; 2969 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2970 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2971 2972 int pos = 0; 2973 char *buf; 2974 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2975 ssize_t ret; 2976 2977 buf = kzalloc(bufsz, GFP_KERNEL); 2978 if (!buf) 2979 return -ENOMEM; 2980 2981 pos += scnprintf(buf + pos, bufsz - pos, 2982 "Interrupt Statistics Report:\n"); 2983 2984 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2985 isr_stats->hw); 2986 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2987 isr_stats->sw); 2988 if (isr_stats->sw || isr_stats->hw) { 2989 pos += scnprintf(buf + pos, bufsz - pos, 2990 "\tLast Restarting Code: 0x%X\n", 2991 isr_stats->err_code); 2992 } 2993 #ifdef CONFIG_IWLWIFI_DEBUG 2994 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2995 isr_stats->sch); 2996 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2997 isr_stats->alive); 2998 #endif 2999 pos += scnprintf(buf + pos, bufsz - pos, 3000 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 3001 3002 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 3003 isr_stats->ctkill); 3004 3005 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 3006 isr_stats->wakeup); 3007 3008 pos += scnprintf(buf + pos, bufsz - pos, 3009 "Rx command responses:\t\t %u\n", isr_stats->rx); 3010 3011 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 3012 isr_stats->tx); 3013 3014 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 3015 isr_stats->unhandled); 3016 3017 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 3018 kfree(buf); 3019 return ret; 3020 } 3021 3022 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 3023 const char __user *user_buf, 3024 size_t count, loff_t *ppos) 3025 { 3026 struct iwl_trans *trans = file->private_data; 3027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3028 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 3029 u32 reset_flag; 3030 int ret; 3031 3032 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 3033 if (ret) 3034 return ret; 3035 if (reset_flag == 0) 3036 memset(isr_stats, 0, sizeof(*isr_stats)); 3037 3038 return count; 3039 } 3040 3041 static ssize_t iwl_dbgfs_csr_write(struct file *file, 3042 const char __user *user_buf, 3043 size_t count, loff_t *ppos) 3044 { 3045 struct iwl_trans *trans = file->private_data; 3046 3047 iwl_pcie_dump_csr(trans); 3048 3049 return count; 3050 } 3051 3052 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 3053 char __user *user_buf, 3054 size_t count, loff_t *ppos) 3055 { 3056 struct iwl_trans *trans = file->private_data; 3057 char *buf = NULL; 3058 ssize_t ret; 3059 3060 ret = iwl_dump_fh(trans, &buf); 3061 if (ret < 0) 3062 return ret; 3063 if (!buf) 3064 return -EINVAL; 3065 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 3066 kfree(buf); 3067 return ret; 3068 } 3069 3070 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 3071 char __user *user_buf, 3072 size_t count, loff_t *ppos) 3073 { 3074 struct iwl_trans *trans = file->private_data; 3075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3076 char buf[100]; 3077 int pos; 3078 3079 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 3080 trans_pcie->debug_rfkill, 3081 !(iwl_read32(trans, CSR_GP_CNTRL) & 3082 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 3083 3084 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 3085 } 3086 3087 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 3088 const char __user *user_buf, 3089 size_t count, loff_t *ppos) 3090 { 3091 struct iwl_trans *trans = file->private_data; 3092 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3093 bool new_value; 3094 int ret; 3095 3096 ret = kstrtobool_from_user(user_buf, count, &new_value); 3097 if (ret) 3098 return ret; 3099 if (new_value == trans_pcie->debug_rfkill) 3100 return count; 3101 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 3102 trans_pcie->debug_rfkill, new_value); 3103 trans_pcie->debug_rfkill = new_value; 3104 iwl_pcie_handle_rfkill_irq(trans, false); 3105 3106 return count; 3107 } 3108 3109 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 3110 struct file *file) 3111 { 3112 struct iwl_trans *trans = inode->i_private; 3113 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3114 3115 if (!trans->dbg.dest_tlv || 3116 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 3117 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 3118 return -ENOENT; 3119 } 3120 3121 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 3122 return -EBUSY; 3123 3124 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 3125 return simple_open(inode, file); 3126 } 3127 3128 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 3129 struct file *file) 3130 { 3131 struct iwl_trans_pcie *trans_pcie = 3132 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 3133 3134 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 3135 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3136 return 0; 3137 } 3138 3139 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 3140 void *buf, ssize_t *size, 3141 ssize_t *bytes_copied) 3142 { 3143 ssize_t buf_size_left = count - *bytes_copied; 3144 3145 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 3146 if (*size > buf_size_left) 3147 *size = buf_size_left; 3148 3149 *size -= copy_to_user(user_buf, buf, *size); 3150 *bytes_copied += *size; 3151 3152 if (buf_size_left == *size) 3153 return true; 3154 return false; 3155 } 3156 3157 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 3158 char __user *user_buf, 3159 size_t count, loff_t *ppos) 3160 { 3161 struct iwl_trans *trans = file->private_data; 3162 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3163 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 3164 struct cont_rec *data = &trans_pcie->fw_mon_data; 3165 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 3166 ssize_t size, bytes_copied = 0; 3167 bool b_full; 3168 3169 if (trans->dbg.dest_tlv) { 3170 write_ptr_addr = 3171 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3172 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3173 } else { 3174 write_ptr_addr = MON_BUFF_WRPTR; 3175 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 3176 } 3177 3178 if (unlikely(!trans->dbg.rec_on)) 3179 return 0; 3180 3181 mutex_lock(&data->mutex); 3182 if (data->state == 3183 IWL_FW_MON_DBGFS_STATE_DISABLED) { 3184 mutex_unlock(&data->mutex); 3185 return 0; 3186 } 3187 3188 /* write_ptr position in bytes rather then DW */ 3189 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 3190 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 3191 3192 if (data->prev_wrap_cnt == wrap_cnt) { 3193 size = write_ptr - data->prev_wr_ptr; 3194 curr_buf = cpu_addr + data->prev_wr_ptr; 3195 b_full = iwl_write_to_user_buf(user_buf, count, 3196 curr_buf, &size, 3197 &bytes_copied); 3198 data->prev_wr_ptr += size; 3199 3200 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 3201 write_ptr < data->prev_wr_ptr) { 3202 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 3203 curr_buf = cpu_addr + data->prev_wr_ptr; 3204 b_full = iwl_write_to_user_buf(user_buf, count, 3205 curr_buf, &size, 3206 &bytes_copied); 3207 data->prev_wr_ptr += size; 3208 3209 if (!b_full) { 3210 size = write_ptr; 3211 b_full = iwl_write_to_user_buf(user_buf, count, 3212 cpu_addr, &size, 3213 &bytes_copied); 3214 data->prev_wr_ptr = size; 3215 data->prev_wrap_cnt++; 3216 } 3217 } else { 3218 if (data->prev_wrap_cnt == wrap_cnt - 1 && 3219 write_ptr > data->prev_wr_ptr) 3220 IWL_WARN(trans, 3221 "write pointer passed previous write pointer, start copying from the beginning\n"); 3222 else if (!unlikely(data->prev_wrap_cnt == 0 && 3223 data->prev_wr_ptr == 0)) 3224 IWL_WARN(trans, 3225 "monitor data is out of sync, start copying from the beginning\n"); 3226 3227 size = write_ptr; 3228 b_full = iwl_write_to_user_buf(user_buf, count, 3229 cpu_addr, &size, 3230 &bytes_copied); 3231 data->prev_wr_ptr = size; 3232 data->prev_wrap_cnt = wrap_cnt; 3233 } 3234 3235 mutex_unlock(&data->mutex); 3236 3237 return bytes_copied; 3238 } 3239 3240 static ssize_t iwl_dbgfs_rf_read(struct file *file, 3241 char __user *user_buf, 3242 size_t count, loff_t *ppos) 3243 { 3244 struct iwl_trans *trans = file->private_data; 3245 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3246 3247 if (!trans_pcie->rf_name[0]) 3248 return -ENODEV; 3249 3250 return simple_read_from_buffer(user_buf, count, ppos, 3251 trans_pcie->rf_name, 3252 strlen(trans_pcie->rf_name)); 3253 } 3254 3255 static ssize_t iwl_dbgfs_reset_write(struct file *file, 3256 const char __user *user_buf, 3257 size_t count, loff_t *ppos) 3258 { 3259 struct iwl_trans *trans = file->private_data; 3260 static const char * const modes[] = { 3261 [IWL_RESET_MODE_SW_RESET] = "n/a", 3262 [IWL_RESET_MODE_REPROBE] = "n/a", 3263 [IWL_RESET_MODE_REMOVE_ONLY] = "remove", 3264 [IWL_RESET_MODE_RESCAN] = "rescan", 3265 [IWL_RESET_MODE_FUNC_RESET] = "function", 3266 [IWL_RESET_MODE_PROD_RESET] = "product", 3267 }; 3268 char buf[10] = {}; 3269 int mode; 3270 3271 if (count > sizeof(buf) - 1) 3272 return -EINVAL; 3273 3274 if (copy_from_user(buf, user_buf, count)) 3275 return -EFAULT; 3276 3277 mode = sysfs_match_string(modes, buf); 3278 if (mode < 0) 3279 return mode; 3280 3281 if (mode < IWL_RESET_MODE_REMOVE_ONLY) 3282 return -EINVAL; 3283 3284 iwl_trans_pcie_reset(trans, mode); 3285 3286 return count; 3287 } 3288 3289 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3290 DEBUGFS_READ_FILE_OPS(fh_reg); 3291 DEBUGFS_READ_FILE_OPS(rx_queue); 3292 DEBUGFS_WRITE_FILE_OPS(csr); 3293 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3294 DEBUGFS_READ_FILE_OPS(rf); 3295 DEBUGFS_WRITE_FILE_OPS(reset); 3296 3297 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3298 .owner = THIS_MODULE, 3299 .open = iwl_dbgfs_tx_queue_open, 3300 .read = seq_read, 3301 .llseek = seq_lseek, 3302 .release = seq_release_private, 3303 }; 3304 3305 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3306 .read = iwl_dbgfs_monitor_data_read, 3307 .open = iwl_dbgfs_monitor_data_open, 3308 .release = iwl_dbgfs_monitor_data_release, 3309 }; 3310 3311 /* Create the debugfs files and directories */ 3312 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3313 { 3314 struct dentry *dir = trans->dbgfs_dir; 3315 3316 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3317 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3318 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3319 DEBUGFS_ADD_FILE(csr, dir, 0200); 3320 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3321 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3322 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3323 DEBUGFS_ADD_FILE(rf, dir, 0400); 3324 DEBUGFS_ADD_FILE(reset, dir, 0200); 3325 } 3326 3327 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3328 { 3329 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3330 struct cont_rec *data = &trans_pcie->fw_mon_data; 3331 3332 mutex_lock(&data->mutex); 3333 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3334 mutex_unlock(&data->mutex); 3335 } 3336 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3337 3338 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3339 { 3340 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3341 u32 cmdlen = 0; 3342 int i; 3343 3344 for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++) 3345 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3346 3347 return cmdlen; 3348 } 3349 3350 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3351 struct iwl_fw_error_dump_data **data, 3352 int allocated_rb_nums) 3353 { 3354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3355 int max_len = trans_pcie->rx_buf_bytes; 3356 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3357 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3358 u32 i, r, j, rb_len = 0; 3359 3360 spin_lock_bh(&rxq->lock); 3361 3362 r = iwl_get_closed_rb_stts(trans, rxq); 3363 3364 for (i = rxq->read, j = 0; 3365 i != r && j < allocated_rb_nums; 3366 i = (i + 1) & RX_QUEUE_MASK, j++) { 3367 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3368 struct iwl_fw_error_dump_rb *rb; 3369 3370 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3371 max_len, DMA_FROM_DEVICE); 3372 3373 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3374 3375 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3376 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3377 rb = (void *)(*data)->data; 3378 rb->index = cpu_to_le32(i); 3379 memcpy(rb->data, page_address(rxb->page), max_len); 3380 3381 *data = iwl_fw_error_next_data(*data); 3382 } 3383 3384 spin_unlock_bh(&rxq->lock); 3385 3386 return rb_len; 3387 } 3388 #define IWL_CSR_TO_DUMP (0x250) 3389 3390 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3391 struct iwl_fw_error_dump_data **data) 3392 { 3393 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3394 __le32 *val; 3395 int i; 3396 3397 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3398 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3399 val = (void *)(*data)->data; 3400 3401 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3402 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3403 3404 *data = iwl_fw_error_next_data(*data); 3405 3406 return csr_len; 3407 } 3408 3409 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3410 struct iwl_fw_error_dump_data **data) 3411 { 3412 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3413 __le32 *val; 3414 int i; 3415 3416 if (!iwl_trans_grab_nic_access(trans)) 3417 return 0; 3418 3419 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3420 (*data)->len = cpu_to_le32(fh_regs_len); 3421 val = (void *)(*data)->data; 3422 3423 if (!trans->trans_cfg->gen2) 3424 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3425 i += sizeof(u32)) 3426 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3427 else 3428 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3429 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3430 i += sizeof(u32)) 3431 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3432 i)); 3433 3434 iwl_trans_release_nic_access(trans); 3435 3436 *data = iwl_fw_error_next_data(*data); 3437 3438 return sizeof(**data) + fh_regs_len; 3439 } 3440 3441 static u32 3442 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3443 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3444 u32 monitor_len) 3445 { 3446 u32 buf_size_in_dwords = (monitor_len >> 2); 3447 u32 *buffer = (u32 *)fw_mon_data->data; 3448 u32 i; 3449 3450 if (!iwl_trans_grab_nic_access(trans)) 3451 return 0; 3452 3453 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3454 for (i = 0; i < buf_size_in_dwords; i++) 3455 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3456 MON_DMARB_RD_DATA_ADDR); 3457 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3458 3459 iwl_trans_release_nic_access(trans); 3460 3461 return monitor_len; 3462 } 3463 3464 static void 3465 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3466 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3467 { 3468 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3469 3470 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3471 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3472 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3473 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3474 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3475 } else if (trans->dbg.dest_tlv) { 3476 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3477 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3478 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3479 } else { 3480 base = MON_BUFF_BASE_ADDR; 3481 write_ptr = MON_BUFF_WRPTR; 3482 wrap_cnt = MON_BUFF_CYCLE_CNT; 3483 } 3484 3485 write_ptr_val = iwl_read_prph(trans, write_ptr); 3486 fw_mon_data->fw_mon_cycle_cnt = 3487 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3488 fw_mon_data->fw_mon_base_ptr = 3489 cpu_to_le32(iwl_read_prph(trans, base)); 3490 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3491 fw_mon_data->fw_mon_base_high_ptr = 3492 cpu_to_le32(iwl_read_prph(trans, base_high)); 3493 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3494 /* convert wrtPtr to DWs, to align with all HWs */ 3495 write_ptr_val >>= 2; 3496 } 3497 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3498 } 3499 3500 static u32 3501 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3502 struct iwl_fw_error_dump_data **data, 3503 u32 monitor_len) 3504 { 3505 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3506 u32 len = 0; 3507 3508 if (trans->dbg.dest_tlv || 3509 (fw_mon->size && 3510 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3511 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3512 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3513 3514 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3515 fw_mon_data = (void *)(*data)->data; 3516 3517 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3518 3519 len += sizeof(**data) + sizeof(*fw_mon_data); 3520 if (fw_mon->size) { 3521 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3522 monitor_len = fw_mon->size; 3523 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3524 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3525 /* 3526 * Update pointers to reflect actual values after 3527 * shifting 3528 */ 3529 if (trans->dbg.dest_tlv->version) { 3530 base = (iwl_read_prph(trans, base) & 3531 IWL_LDBG_M2S_BUF_BA_MSK) << 3532 trans->dbg.dest_tlv->base_shift; 3533 base *= IWL_M2S_UNIT_SIZE; 3534 base += trans->cfg->smem_offset; 3535 } else { 3536 base = iwl_read_prph(trans, base) << 3537 trans->dbg.dest_tlv->base_shift; 3538 } 3539 3540 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3541 monitor_len / sizeof(u32)); 3542 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3543 monitor_len = 3544 iwl_trans_pci_dump_marbh_monitor(trans, 3545 fw_mon_data, 3546 monitor_len); 3547 } else { 3548 /* Didn't match anything - output no monitor data */ 3549 monitor_len = 0; 3550 } 3551 3552 len += monitor_len; 3553 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3554 } 3555 3556 return len; 3557 } 3558 3559 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3560 { 3561 if (trans->dbg.fw_mon.size) { 3562 *len += sizeof(struct iwl_fw_error_dump_data) + 3563 sizeof(struct iwl_fw_error_dump_fw_mon) + 3564 trans->dbg.fw_mon.size; 3565 return trans->dbg.fw_mon.size; 3566 } else if (trans->dbg.dest_tlv) { 3567 u32 base, end, cfg_reg, monitor_len; 3568 3569 if (trans->dbg.dest_tlv->version == 1) { 3570 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3571 cfg_reg = iwl_read_prph(trans, cfg_reg); 3572 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3573 trans->dbg.dest_tlv->base_shift; 3574 base *= IWL_M2S_UNIT_SIZE; 3575 base += trans->cfg->smem_offset; 3576 3577 monitor_len = 3578 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3579 trans->dbg.dest_tlv->end_shift; 3580 monitor_len *= IWL_M2S_UNIT_SIZE; 3581 } else { 3582 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3583 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3584 3585 base = iwl_read_prph(trans, base) << 3586 trans->dbg.dest_tlv->base_shift; 3587 end = iwl_read_prph(trans, end) << 3588 trans->dbg.dest_tlv->end_shift; 3589 3590 /* Make "end" point to the actual end */ 3591 if (trans->trans_cfg->device_family >= 3592 IWL_DEVICE_FAMILY_8000 || 3593 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3594 end += (1 << trans->dbg.dest_tlv->end_shift); 3595 monitor_len = end - base; 3596 } 3597 *len += sizeof(struct iwl_fw_error_dump_data) + 3598 sizeof(struct iwl_fw_error_dump_fw_mon) + 3599 monitor_len; 3600 return monitor_len; 3601 } 3602 return 0; 3603 } 3604 3605 struct iwl_trans_dump_data * 3606 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask, 3607 const struct iwl_dump_sanitize_ops *sanitize_ops, 3608 void *sanitize_ctx) 3609 { 3610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3611 struct iwl_fw_error_dump_data *data; 3612 struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]; 3613 struct iwl_fw_error_dump_txcmd *txcmd; 3614 struct iwl_trans_dump_data *dump_data; 3615 u32 len, num_rbs = 0, monitor_len = 0; 3616 int i, ptr; 3617 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3618 !trans->trans_cfg->mq_rx_supported && 3619 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3620 3621 if (!dump_mask) 3622 return NULL; 3623 3624 /* transport dump header */ 3625 len = sizeof(*dump_data); 3626 3627 /* host commands */ 3628 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3629 len += sizeof(*data) + 3630 cmdq->n_window * (sizeof(*txcmd) + 3631 TFD_MAX_PAYLOAD_SIZE); 3632 3633 /* FW monitor */ 3634 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3635 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3636 3637 /* CSR registers */ 3638 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3639 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3640 3641 /* FH registers */ 3642 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3643 if (trans->trans_cfg->gen2) 3644 len += sizeof(*data) + 3645 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3646 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3647 else 3648 len += sizeof(*data) + 3649 (FH_MEM_UPPER_BOUND - 3650 FH_MEM_LOWER_BOUND); 3651 } 3652 3653 if (dump_rbs) { 3654 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3655 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3656 /* RBs */ 3657 num_rbs = iwl_get_closed_rb_stts(trans, rxq); 3658 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3659 len += num_rbs * (sizeof(*data) + 3660 sizeof(struct iwl_fw_error_dump_rb) + 3661 (PAGE_SIZE << trans_pcie->rx_page_order)); 3662 } 3663 3664 /* Paged memory for gen2 HW */ 3665 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3666 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3667 len += sizeof(*data) + 3668 sizeof(struct iwl_fw_error_dump_paging) + 3669 trans->init_dram.paging[i].size; 3670 3671 dump_data = vzalloc(len); 3672 if (!dump_data) 3673 return NULL; 3674 3675 len = 0; 3676 data = (void *)dump_data->data; 3677 3678 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3679 u16 tfd_size = trans_pcie->txqs.tfd.size; 3680 3681 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3682 txcmd = (void *)data->data; 3683 spin_lock_bh(&cmdq->lock); 3684 ptr = cmdq->write_ptr; 3685 for (i = 0; i < cmdq->n_window; i++) { 3686 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3687 u8 tfdidx; 3688 u32 caplen, cmdlen; 3689 3690 if (trans->trans_cfg->gen2) 3691 tfdidx = idx; 3692 else 3693 tfdidx = ptr; 3694 3695 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3696 (u8 *)cmdq->tfds + 3697 tfd_size * tfdidx); 3698 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3699 3700 if (cmdlen) { 3701 len += sizeof(*txcmd) + caplen; 3702 txcmd->cmdlen = cpu_to_le32(cmdlen); 3703 txcmd->caplen = cpu_to_le32(caplen); 3704 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3705 caplen); 3706 if (sanitize_ops && sanitize_ops->frob_hcmd) 3707 sanitize_ops->frob_hcmd(sanitize_ctx, 3708 txcmd->data, 3709 caplen); 3710 txcmd = (void *)((u8 *)txcmd->data + caplen); 3711 } 3712 3713 ptr = iwl_txq_dec_wrap(trans, ptr); 3714 } 3715 spin_unlock_bh(&cmdq->lock); 3716 3717 data->len = cpu_to_le32(len); 3718 len += sizeof(*data); 3719 data = iwl_fw_error_next_data(data); 3720 } 3721 3722 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3723 len += iwl_trans_pcie_dump_csr(trans, &data); 3724 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3725 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3726 if (dump_rbs) 3727 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3728 3729 /* Paged memory for gen2 HW */ 3730 if (trans->trans_cfg->gen2 && 3731 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3732 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3733 struct iwl_fw_error_dump_paging *paging; 3734 u32 page_len = trans->init_dram.paging[i].size; 3735 3736 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3737 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3738 paging = (void *)data->data; 3739 paging->index = cpu_to_le32(i); 3740 memcpy(paging->data, 3741 trans->init_dram.paging[i].block, page_len); 3742 data = iwl_fw_error_next_data(data); 3743 3744 len += sizeof(*data) + sizeof(*paging) + page_len; 3745 } 3746 } 3747 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3748 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3749 3750 dump_data->len = len; 3751 3752 return dump_data; 3753 } 3754 3755 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3756 { 3757 if (enable) 3758 iwl_enable_interrupts(trans); 3759 else 3760 iwl_disable_interrupts(trans); 3761 } 3762 3763 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3764 { 3765 u32 inta_addr, sw_err_bit; 3766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3767 3768 if (trans_pcie->msix_enabled) { 3769 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3770 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3771 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3772 else 3773 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3774 } else { 3775 inta_addr = CSR_INT; 3776 sw_err_bit = CSR_INT_BIT_SW_ERR; 3777 } 3778 3779 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3780 } 3781 3782 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3783 const struct pci_device_id *ent, 3784 const struct iwl_cfg_trans_params *cfg_trans) 3785 { 3786 struct iwl_trans_pcie *trans_pcie, **priv; 3787 struct iwl_trans *trans; 3788 int ret, addr_size; 3789 u32 bar0; 3790 3791 /* reassign our BAR 0 if invalid due to possible runtime PM races */ 3792 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0); 3793 if (bar0 == PCI_BASE_ADDRESS_MEM_TYPE_64) { 3794 ret = pci_assign_resource(pdev, 0); 3795 if (ret) 3796 return ERR_PTR(ret); 3797 } 3798 3799 ret = pcim_enable_device(pdev); 3800 if (ret) 3801 return ERR_PTR(ret); 3802 3803 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, 3804 cfg_trans); 3805 if (!trans) 3806 return ERR_PTR(-ENOMEM); 3807 3808 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3809 3810 if (trans->trans_cfg->gen2) { 3811 trans_pcie->txqs.tfd.addr_size = 64; 3812 trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS; 3813 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd); 3814 } else { 3815 trans_pcie->txqs.tfd.addr_size = 36; 3816 trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS; 3817 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd); 3818 } 3819 trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie); 3820 3821 /* Set a short watchdog for the command queue */ 3822 trans_pcie->txqs.cmd.wdg_timeout = IWL_DEF_WD_TIMEOUT; 3823 3824 trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3825 if (!trans_pcie->txqs.tso_hdr_page) { 3826 ret = -ENOMEM; 3827 goto out_free_trans; 3828 } 3829 3830 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3831 trans_pcie->txqs.bc_tbl_size = 3832 sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_BZ; 3833 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 3834 trans_pcie->txqs.bc_tbl_size = 3835 sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_AX210; 3836 else 3837 trans_pcie->txqs.bc_tbl_size = sizeof(struct iwlagn_scd_bc_tbl); 3838 /* 3839 * For gen2 devices, we use a single allocation for each byte-count 3840 * table, but they're pretty small (1k) so use a DMA pool that we 3841 * allocate here. 3842 */ 3843 if (trans->trans_cfg->gen2) { 3844 trans_pcie->txqs.bc_pool = 3845 dmam_pool_create("iwlwifi:bc", trans->dev, 3846 trans_pcie->txqs.bc_tbl_size, 3847 256, 0); 3848 if (!trans_pcie->txqs.bc_pool) { 3849 ret = -ENOMEM; 3850 goto out_free_tso; 3851 } 3852 } 3853 3854 /* Some things must not change even if the config does */ 3855 WARN_ON(trans_pcie->txqs.tfd.addr_size != 3856 (trans->trans_cfg->gen2 ? 64 : 36)); 3857 3858 /* Initialize NAPI here - it should be before registering to mac80211 3859 * in the opmode but after the HW struct is allocated. 3860 */ 3861 trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *)); 3862 if (!trans_pcie->napi_dev) { 3863 ret = -ENOMEM; 3864 goto out_free_tso; 3865 } 3866 /* The private struct in netdev is a pointer to struct iwl_trans_pcie */ 3867 priv = netdev_priv(trans_pcie->napi_dev); 3868 *priv = trans_pcie; 3869 3870 trans_pcie->trans = trans; 3871 trans_pcie->opmode_down = true; 3872 spin_lock_init(&trans_pcie->irq_lock); 3873 spin_lock_init(&trans_pcie->reg_lock); 3874 spin_lock_init(&trans_pcie->alloc_page_lock); 3875 mutex_init(&trans_pcie->mutex); 3876 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3877 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3878 init_waitqueue_head(&trans_pcie->imr_waitq); 3879 3880 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3881 WQ_HIGHPRI | WQ_UNBOUND, 0); 3882 if (!trans_pcie->rba.alloc_wq) { 3883 ret = -ENOMEM; 3884 goto out_free_ndev; 3885 } 3886 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3887 3888 trans_pcie->debug_rfkill = -1; 3889 3890 if (!cfg_trans->base_params->pcie_l1_allowed) { 3891 /* 3892 * W/A - seems to solve weird behavior. We need to remove this 3893 * if we don't want to stay in L1 all the time. This wastes a 3894 * lot of power. 3895 */ 3896 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3897 PCIE_LINK_STATE_L1 | 3898 PCIE_LINK_STATE_CLKPM); 3899 } 3900 3901 pci_set_master(pdev); 3902 3903 addr_size = trans_pcie->txqs.tfd.addr_size; 3904 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3905 if (ret) { 3906 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3907 /* both attempts failed: */ 3908 if (ret) { 3909 dev_err(&pdev->dev, "No suitable DMA available\n"); 3910 goto out_no_pci; 3911 } 3912 } 3913 3914 ret = pcim_request_all_regions(pdev, DRV_NAME); 3915 if (ret) { 3916 dev_err(&pdev->dev, "Requesting all PCI BARs failed.\n"); 3917 goto out_no_pci; 3918 } 3919 3920 trans_pcie->hw_base = pcim_iomap(pdev, 0, 0); 3921 if (!trans_pcie->hw_base) { 3922 dev_err(&pdev->dev, "Could not ioremap PCI BAR 0.\n"); 3923 ret = -ENODEV; 3924 goto out_no_pci; 3925 } 3926 3927 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3928 * PCI Tx retries from interfering with C3 CPU state */ 3929 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3930 3931 trans_pcie->pci_dev = pdev; 3932 iwl_disable_interrupts(trans); 3933 3934 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3935 if (trans->hw_rev == 0xffffffff) { 3936 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3937 ret = -EIO; 3938 goto out_no_pci; 3939 } 3940 3941 /* 3942 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3943 * changed, and now the revision step also includes bit 0-1 (no more 3944 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3945 * in the old format. 3946 */ 3947 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3948 trans->hw_rev_step = trans->hw_rev & 0xF; 3949 else 3950 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3951 3952 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3953 3954 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3955 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3956 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3957 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3958 3959 init_waitqueue_head(&trans_pcie->sx_waitq); 3960 3961 ret = iwl_pcie_alloc_invalid_tx_cmd(trans); 3962 if (ret) 3963 goto out_no_pci; 3964 3965 if (trans_pcie->msix_enabled) { 3966 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3967 if (ret) 3968 goto out_no_pci; 3969 } else { 3970 ret = iwl_pcie_alloc_ict(trans); 3971 if (ret) 3972 goto out_no_pci; 3973 3974 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3975 iwl_pcie_isr, 3976 iwl_pcie_irq_handler, 3977 IRQF_SHARED, DRV_NAME, trans); 3978 if (ret) { 3979 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3980 goto out_free_ict; 3981 } 3982 } 3983 3984 #ifdef CONFIG_IWLWIFI_DEBUGFS 3985 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3986 mutex_init(&trans_pcie->fw_mon_data.mutex); 3987 #endif 3988 3989 iwl_dbg_tlv_init(trans); 3990 3991 return trans; 3992 3993 out_free_ict: 3994 iwl_pcie_free_ict(trans); 3995 out_no_pci: 3996 destroy_workqueue(trans_pcie->rba.alloc_wq); 3997 out_free_ndev: 3998 free_netdev(trans_pcie->napi_dev); 3999 out_free_tso: 4000 free_percpu(trans_pcie->txqs.tso_hdr_page); 4001 out_free_trans: 4002 iwl_trans_free(trans); 4003 return ERR_PTR(ret); 4004 } 4005 4006 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 4007 u32 dst_addr, u64 src_addr, u32 byte_cnt) 4008 { 4009 iwl_write_prph(trans, IMR_UREG_CHICK, 4010 iwl_read_prph(trans, IMR_UREG_CHICK) | 4011 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 4012 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 4013 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 4014 (u32)(src_addr & 0xFFFFFFFF)); 4015 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 4016 iwl_get_dma_hi_addr(src_addr)); 4017 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 4018 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 4019 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 4020 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 4021 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 4022 } 4023 4024 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 4025 u32 dst_addr, u64 src_addr, u32 byte_cnt) 4026 { 4027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4028 int ret = -1; 4029 4030 trans_pcie->imr_status = IMR_D2S_REQUESTED; 4031 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 4032 ret = wait_event_timeout(trans_pcie->imr_waitq, 4033 trans_pcie->imr_status != 4034 IMR_D2S_REQUESTED, 5 * HZ); 4035 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 4036 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 4037 iwl_trans_pcie_dump_regs(trans); 4038 return -ETIMEDOUT; 4039 } 4040 trans_pcie->imr_status = IMR_D2S_IDLE; 4041 return 0; 4042 } 4043