1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 18 #include "iwl-drv.h" 19 #include "iwl-trans.h" 20 #include "iwl-csr.h" 21 #include "iwl-prph.h" 22 #include "iwl-scd.h" 23 #include "iwl-agn-hw.h" 24 #include "fw/error-dump.h" 25 #include "fw/dbg.h" 26 #include "fw/api/tx.h" 27 #include "mei/iwl-mei.h" 28 #include "internal.h" 29 #include "iwl-fh.h" 30 #include "iwl-context-info-gen3.h" 31 32 /* extended range in FW SRAM */ 33 #define IWL_FW_MEM_EXTENDED_START 0x40000 34 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35 36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37 { 38 #define PCI_DUMP_SIZE 352 39 #define PCI_MEM_DUMP_SIZE 64 40 #define PCI_PARENT_DUMP_SIZE 524 41 #define PREFIX_LEN 32 42 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43 struct pci_dev *pdev = trans_pcie->pci_dev; 44 u32 i, pos, alloc_size, *ptr, *buf; 45 char *prefix; 46 47 if (trans_pcie->pcie_dbg_dumped_once) 48 return; 49 50 /* Should be a multiple of 4 */ 51 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54 55 /* Alloc a max size buffer */ 56 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60 61 buf = kmalloc(alloc_size, GFP_ATOMIC); 62 if (!buf) 63 return; 64 prefix = (char *)buf + alloc_size - PREFIX_LEN; 65 66 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67 68 /* Print wifi device registers */ 69 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70 IWL_ERR(trans, "iwlwifi device config registers:\n"); 71 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72 if (pci_read_config_dword(pdev, i, ptr)) 73 goto err_read; 74 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75 76 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78 *ptr = iwl_read32(trans, i); 79 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80 81 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82 if (pos) { 83 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85 if (pci_read_config_dword(pdev, pos + i, ptr)) 86 goto err_read; 87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88 32, 4, buf, i, 0); 89 } 90 91 /* Print parent device registers next */ 92 if (!pdev->bus->self) 93 goto out; 94 95 pdev = pdev->bus->self; 96 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97 98 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99 pci_name(pdev)); 100 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101 if (pci_read_config_dword(pdev, i, ptr)) 102 goto err_read; 103 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104 105 /* Print root port AER registers */ 106 pos = 0; 107 pdev = pcie_find_root_port(pdev); 108 if (pdev) 109 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110 if (pos) { 111 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112 pci_name(pdev)); 113 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115 if (pci_read_config_dword(pdev, pos + i, ptr)) 116 goto err_read; 117 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118 4, buf, i, 0); 119 } 120 goto out; 121 122 err_read: 123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124 IWL_ERR(trans, "Read failed at 0x%X\n", i); 125 out: 126 trans_pcie->pcie_dbg_dumped_once = 1; 127 kfree(buf); 128 } 129 130 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 131 bool retake_ownership) 132 { 133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 135 iwl_set_bit(trans, CSR_GP_CNTRL, 136 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 137 usleep_range(10000, 20000); 138 } else { 139 iwl_set_bit(trans, CSR_RESET, 140 CSR_RESET_REG_FLAG_SW_RESET); 141 usleep_range(5000, 6000); 142 } 143 144 if (retake_ownership) 145 return iwl_pcie_prepare_card_hw(trans); 146 147 return 0; 148 } 149 150 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 151 { 152 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 153 154 if (!fw_mon->size) 155 return; 156 157 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 158 fw_mon->physical); 159 160 fw_mon->block = NULL; 161 fw_mon->physical = 0; 162 fw_mon->size = 0; 163 } 164 165 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 166 u8 max_power) 167 { 168 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 169 void *block = NULL; 170 dma_addr_t physical = 0; 171 u32 size = 0; 172 u8 power; 173 174 if (fw_mon->size) { 175 memset(fw_mon->block, 0, fw_mon->size); 176 return; 177 } 178 179 /* need at least 2 KiB, so stop at 11 */ 180 for (power = max_power; power >= 11; power--) { 181 size = BIT(power); 182 block = dma_alloc_coherent(trans->dev, size, &physical, 183 GFP_KERNEL | __GFP_NOWARN); 184 if (!block) 185 continue; 186 187 IWL_INFO(trans, 188 "Allocated 0x%08x bytes for firmware monitor.\n", 189 size); 190 break; 191 } 192 193 if (WARN_ON_ONCE(!block)) 194 return; 195 196 if (power != max_power) 197 IWL_ERR(trans, 198 "Sorry - debug buffer is only %luK while you requested %luK\n", 199 (unsigned long)BIT(power - 10), 200 (unsigned long)BIT(max_power - 10)); 201 202 fw_mon->block = block; 203 fw_mon->physical = physical; 204 fw_mon->size = size; 205 } 206 207 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 208 { 209 if (!max_power) { 210 /* default max_power is maximum */ 211 max_power = 26; 212 } else { 213 max_power += 11; 214 } 215 216 if (WARN(max_power > 26, 217 "External buffer size for monitor is too big %d, check the FW TLV\n", 218 max_power)) 219 return; 220 221 iwl_pcie_alloc_fw_monitor_block(trans, max_power); 222 } 223 224 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 225 { 226 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 227 ((reg & 0x0000ffff) | (2 << 28))); 228 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 229 } 230 231 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 232 { 233 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 234 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 235 ((reg & 0x0000ffff) | (3 << 28))); 236 } 237 238 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 239 { 240 if (trans->cfg->apmg_not_supported) 241 return; 242 243 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 244 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 245 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 246 ~APMG_PS_CTRL_MSK_PWR_SRC); 247 else 248 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 249 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 250 ~APMG_PS_CTRL_MSK_PWR_SRC); 251 } 252 253 /* PCI registers */ 254 #define PCI_CFG_RETRY_TIMEOUT 0x041 255 256 void iwl_pcie_apm_config(struct iwl_trans *trans) 257 { 258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 259 u16 lctl; 260 u16 cap; 261 262 /* 263 * L0S states have been found to be unstable with our devices 264 * and in newer hardware they are not officially supported at 265 * all, so we must always set the L0S_DISABLED bit. 266 */ 267 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 268 269 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 270 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 271 272 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 273 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 274 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 275 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 276 trans->ltr_enabled ? "En" : "Dis"); 277 } 278 279 /* 280 * Start up NIC's basic functionality after it has been reset 281 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 282 * NOTE: This does not load uCode nor start the embedded processor 283 */ 284 static int iwl_pcie_apm_init(struct iwl_trans *trans) 285 { 286 int ret; 287 288 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 289 290 /* 291 * Use "set_bit" below rather than "write", to preserve any hardware 292 * bits already set by default after reset. 293 */ 294 295 /* Disable L0S exit timer (platform NMI Work/Around) */ 296 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 297 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 298 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 299 300 /* 301 * Disable L0s without affecting L1; 302 * don't wait for ICH L0s (ICH bug W/A) 303 */ 304 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 305 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 306 307 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 308 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 309 310 /* 311 * Enable HAP INTA (interrupt from management bus) to 312 * wake device's PCI Express link L1a -> L0s 313 */ 314 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 315 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 316 317 iwl_pcie_apm_config(trans); 318 319 /* Configure analog phase-lock-loop before activating to D0A */ 320 if (trans->trans_cfg->base_params->pll_cfg) 321 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 322 323 ret = iwl_finish_nic_init(trans); 324 if (ret) 325 return ret; 326 327 if (trans->cfg->host_interrupt_operation_mode) { 328 /* 329 * This is a bit of an abuse - This is needed for 7260 / 3160 330 * only check host_interrupt_operation_mode even if this is 331 * not related to host_interrupt_operation_mode. 332 * 333 * Enable the oscillator to count wake up time for L1 exit. This 334 * consumes slightly more power (100uA) - but allows to be sure 335 * that we wake up from L1 on time. 336 * 337 * This looks weird: read twice the same register, discard the 338 * value, set a bit, and yet again, read that same register 339 * just to discard the value. But that's the way the hardware 340 * seems to like it. 341 */ 342 iwl_read_prph(trans, OSC_CLK); 343 iwl_read_prph(trans, OSC_CLK); 344 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 345 iwl_read_prph(trans, OSC_CLK); 346 iwl_read_prph(trans, OSC_CLK); 347 } 348 349 /* 350 * Enable DMA clock and wait for it to stabilize. 351 * 352 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 353 * bits do not disable clocks. This preserves any hardware 354 * bits already set by default in "CLK_CTRL_REG" after reset. 355 */ 356 if (!trans->cfg->apmg_not_supported) { 357 iwl_write_prph(trans, APMG_CLK_EN_REG, 358 APMG_CLK_VAL_DMA_CLK_RQT); 359 udelay(20); 360 361 /* Disable L1-Active */ 362 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 363 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 364 365 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 366 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 367 APMG_RTC_INT_STT_RFKILL); 368 } 369 370 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 371 372 return 0; 373 } 374 375 /* 376 * Enable LP XTAL to avoid HW bug where device may consume much power if 377 * FW is not loaded after device reset. LP XTAL is disabled by default 378 * after device HW reset. Do it only if XTAL is fed by internal source. 379 * Configure device's "persistence" mode to avoid resetting XTAL again when 380 * SHRD_HW_RST occurs in S3. 381 */ 382 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 383 { 384 int ret; 385 u32 apmg_gp1_reg; 386 u32 apmg_xtal_cfg_reg; 387 u32 dl_cfg_reg; 388 389 /* Force XTAL ON */ 390 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 391 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 392 393 ret = iwl_trans_pcie_sw_reset(trans, true); 394 395 if (!ret) 396 ret = iwl_finish_nic_init(trans); 397 398 if (WARN_ON(ret)) { 399 /* Release XTAL ON request */ 400 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 401 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 402 return; 403 } 404 405 /* 406 * Clear "disable persistence" to avoid LP XTAL resetting when 407 * SHRD_HW_RST is applied in S3. 408 */ 409 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 410 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 411 412 /* 413 * Force APMG XTAL to be active to prevent its disabling by HW 414 * caused by APMG idle state. 415 */ 416 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 417 SHR_APMG_XTAL_CFG_REG); 418 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 419 apmg_xtal_cfg_reg | 420 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 421 422 ret = iwl_trans_pcie_sw_reset(trans, true); 423 if (ret) 424 IWL_ERR(trans, 425 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 426 427 /* Enable LP XTAL by indirect access through CSR */ 428 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 429 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 430 SHR_APMG_GP1_WF_XTAL_LP_EN | 431 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 432 433 /* Clear delay line clock power up */ 434 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 435 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 436 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 437 438 /* 439 * Enable persistence mode to avoid LP XTAL resetting when 440 * SHRD_HW_RST is applied in S3. 441 */ 442 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 443 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 444 445 /* 446 * Clear "initialization complete" bit to move adapter from 447 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 448 */ 449 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 450 451 /* Activates XTAL resources monitor */ 452 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 453 CSR_MONITOR_XTAL_RESOURCES); 454 455 /* Release XTAL ON request */ 456 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 457 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 458 udelay(10); 459 460 /* Release APMG XTAL */ 461 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 462 apmg_xtal_cfg_reg & 463 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 464 } 465 466 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 467 { 468 int ret; 469 470 /* stop device's busmaster DMA activity */ 471 472 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 473 iwl_set_bit(trans, CSR_GP_CNTRL, 474 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 475 476 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 477 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 478 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 479 100); 480 usleep_range(10000, 20000); 481 } else { 482 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 483 484 ret = iwl_poll_bit(trans, CSR_RESET, 485 CSR_RESET_REG_FLAG_MASTER_DISABLED, 486 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 487 } 488 489 if (ret < 0) 490 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 491 492 IWL_DEBUG_INFO(trans, "stop master\n"); 493 } 494 495 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 496 { 497 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 498 499 if (op_mode_leave) { 500 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 501 iwl_pcie_apm_init(trans); 502 503 /* inform ME that we are leaving */ 504 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 505 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 506 APMG_PCIDEV_STT_VAL_WAKE_ME); 507 else if (trans->trans_cfg->device_family >= 508 IWL_DEVICE_FAMILY_8000) { 509 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 510 CSR_RESET_LINK_PWR_MGMT_DISABLED); 511 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 512 CSR_HW_IF_CONFIG_REG_PREPARE | 513 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 514 mdelay(1); 515 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 516 CSR_RESET_LINK_PWR_MGMT_DISABLED); 517 } 518 mdelay(5); 519 } 520 521 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 522 523 /* Stop device's DMA activity */ 524 iwl_pcie_apm_stop_master(trans); 525 526 if (trans->cfg->lp_xtal_workaround) { 527 iwl_pcie_apm_lp_xtal_enable(trans); 528 return; 529 } 530 531 iwl_trans_pcie_sw_reset(trans, false); 532 533 /* 534 * Clear "initialization complete" bit to move adapter from 535 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 536 */ 537 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 538 } 539 540 static int iwl_pcie_nic_init(struct iwl_trans *trans) 541 { 542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 543 int ret; 544 545 /* nic_init */ 546 spin_lock_bh(&trans_pcie->irq_lock); 547 ret = iwl_pcie_apm_init(trans); 548 spin_unlock_bh(&trans_pcie->irq_lock); 549 550 if (ret) 551 return ret; 552 553 iwl_pcie_set_pwr(trans, false); 554 555 iwl_op_mode_nic_config(trans->op_mode); 556 557 /* Allocate the RX queue, or reset if it is already allocated */ 558 ret = iwl_pcie_rx_init(trans); 559 if (ret) 560 return ret; 561 562 /* Allocate or reset and init all Tx and Command queues */ 563 if (iwl_pcie_tx_init(trans)) { 564 iwl_pcie_rx_free(trans); 565 return -ENOMEM; 566 } 567 568 if (trans->trans_cfg->base_params->shadow_reg_enable) { 569 /* enable shadow regs in HW */ 570 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 571 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 572 } 573 574 return 0; 575 } 576 577 #define HW_READY_TIMEOUT (50) 578 579 /* Note: returns poll_bit return value, which is >= 0 if success */ 580 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 581 { 582 int ret; 583 584 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 585 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 586 587 /* See if we got it */ 588 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 589 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 590 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 591 HW_READY_TIMEOUT); 592 593 if (ret >= 0) 594 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 595 596 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 597 return ret; 598 } 599 600 /* Note: returns standard 0/-ERROR code */ 601 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 602 { 603 int ret; 604 int iter; 605 606 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 607 608 ret = iwl_pcie_set_hw_ready(trans); 609 /* If the card is ready, exit 0 */ 610 if (ret >= 0) { 611 trans->csme_own = false; 612 return 0; 613 } 614 615 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 616 CSR_RESET_LINK_PWR_MGMT_DISABLED); 617 usleep_range(1000, 2000); 618 619 for (iter = 0; iter < 10; iter++) { 620 int t = 0; 621 622 /* If HW is not ready, prepare the conditions to check again */ 623 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 624 CSR_HW_IF_CONFIG_REG_PREPARE); 625 626 do { 627 ret = iwl_pcie_set_hw_ready(trans); 628 if (ret >= 0) { 629 trans->csme_own = false; 630 return 0; 631 } 632 633 if (iwl_mei_is_connected()) { 634 IWL_DEBUG_INFO(trans, 635 "Couldn't prepare the card but SAP is connected\n"); 636 trans->csme_own = true; 637 if (trans->trans_cfg->device_family != 638 IWL_DEVICE_FAMILY_9000) 639 IWL_ERR(trans, 640 "SAP not supported for this NIC family\n"); 641 642 return -EBUSY; 643 } 644 645 usleep_range(200, 1000); 646 t += 200; 647 } while (t < 150000); 648 msleep(25); 649 } 650 651 IWL_ERR(trans, "Couldn't prepare the card\n"); 652 653 return ret; 654 } 655 656 /* 657 * ucode 658 */ 659 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 660 u32 dst_addr, dma_addr_t phy_addr, 661 u32 byte_cnt) 662 { 663 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 664 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 665 666 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 667 dst_addr); 668 669 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 670 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 671 672 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 673 (iwl_get_dma_hi_addr(phy_addr) 674 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 675 676 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 677 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 678 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 679 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 680 681 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 682 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 683 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 684 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 685 } 686 687 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 688 u32 dst_addr, dma_addr_t phy_addr, 689 u32 byte_cnt) 690 { 691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 692 int ret; 693 694 trans_pcie->ucode_write_complete = false; 695 696 if (!iwl_trans_grab_nic_access(trans)) 697 return -EIO; 698 699 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 700 byte_cnt); 701 iwl_trans_release_nic_access(trans); 702 703 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 704 trans_pcie->ucode_write_complete, 5 * HZ); 705 if (!ret) { 706 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 707 iwl_trans_pcie_dump_regs(trans); 708 return -ETIMEDOUT; 709 } 710 711 return 0; 712 } 713 714 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 715 const struct fw_desc *section) 716 { 717 u8 *v_addr; 718 dma_addr_t p_addr; 719 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 720 int ret = 0; 721 722 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 723 section_num); 724 725 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 726 GFP_KERNEL | __GFP_NOWARN); 727 if (!v_addr) { 728 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 729 chunk_sz = PAGE_SIZE; 730 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 731 &p_addr, GFP_KERNEL); 732 if (!v_addr) 733 return -ENOMEM; 734 } 735 736 for (offset = 0; offset < section->len; offset += chunk_sz) { 737 u32 copy_size, dst_addr; 738 bool extended_addr = false; 739 740 copy_size = min_t(u32, chunk_sz, section->len - offset); 741 dst_addr = section->offset + offset; 742 743 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 744 dst_addr <= IWL_FW_MEM_EXTENDED_END) 745 extended_addr = true; 746 747 if (extended_addr) 748 iwl_set_bits_prph(trans, LMPM_CHICK, 749 LMPM_CHICK_EXTENDED_ADDR_SPACE); 750 751 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 752 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 753 copy_size); 754 755 if (extended_addr) 756 iwl_clear_bits_prph(trans, LMPM_CHICK, 757 LMPM_CHICK_EXTENDED_ADDR_SPACE); 758 759 if (ret) { 760 IWL_ERR(trans, 761 "Could not load the [%d] uCode section\n", 762 section_num); 763 break; 764 } 765 } 766 767 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 768 return ret; 769 } 770 771 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 772 const struct fw_img *image, 773 int cpu, 774 int *first_ucode_section) 775 { 776 int shift_param; 777 int i, ret = 0, sec_num = 0x1; 778 u32 val, last_read_idx = 0; 779 780 if (cpu == 1) { 781 shift_param = 0; 782 *first_ucode_section = 0; 783 } else { 784 shift_param = 16; 785 (*first_ucode_section)++; 786 } 787 788 for (i = *first_ucode_section; i < image->num_sec; i++) { 789 last_read_idx = i; 790 791 /* 792 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 793 * CPU1 to CPU2. 794 * PAGING_SEPARATOR_SECTION delimiter - separate between 795 * CPU2 non paged to CPU2 paging sec. 796 */ 797 if (!image->sec[i].data || 798 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 799 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 800 IWL_DEBUG_FW(trans, 801 "Break since Data not valid or Empty section, sec = %d\n", 802 i); 803 break; 804 } 805 806 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 807 if (ret) 808 return ret; 809 810 /* Notify ucode of loaded section number and status */ 811 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 812 val = val | (sec_num << shift_param); 813 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 814 815 sec_num = (sec_num << 1) | 0x1; 816 } 817 818 *first_ucode_section = last_read_idx; 819 820 iwl_enable_interrupts(trans); 821 822 if (trans->trans_cfg->gen2) { 823 if (cpu == 1) 824 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 825 0xFFFF); 826 else 827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 828 0xFFFFFFFF); 829 } else { 830 if (cpu == 1) 831 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 832 0xFFFF); 833 else 834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 835 0xFFFFFFFF); 836 } 837 838 return 0; 839 } 840 841 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 842 const struct fw_img *image, 843 int cpu, 844 int *first_ucode_section) 845 { 846 int i, ret = 0; 847 u32 last_read_idx = 0; 848 849 if (cpu == 1) 850 *first_ucode_section = 0; 851 else 852 (*first_ucode_section)++; 853 854 for (i = *first_ucode_section; i < image->num_sec; i++) { 855 last_read_idx = i; 856 857 /* 858 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 859 * CPU1 to CPU2. 860 * PAGING_SEPARATOR_SECTION delimiter - separate between 861 * CPU2 non paged to CPU2 paging sec. 862 */ 863 if (!image->sec[i].data || 864 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 865 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 866 IWL_DEBUG_FW(trans, 867 "Break since Data not valid or Empty section, sec = %d\n", 868 i); 869 break; 870 } 871 872 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 873 if (ret) 874 return ret; 875 } 876 877 *first_ucode_section = last_read_idx; 878 879 return 0; 880 } 881 882 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 883 { 884 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 885 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 886 &trans->dbg.fw_mon_cfg[alloc_id]; 887 struct iwl_dram_data *frag; 888 889 if (!iwl_trans_dbg_ini_valid(trans)) 890 return; 891 892 if (le32_to_cpu(fw_mon_cfg->buf_location) == 893 IWL_FW_INI_LOCATION_SRAM_PATH) { 894 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 895 /* set sram monitor by enabling bit 7 */ 896 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 897 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 898 899 return; 900 } 901 902 if (le32_to_cpu(fw_mon_cfg->buf_location) != 903 IWL_FW_INI_LOCATION_DRAM_PATH || 904 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 905 return; 906 907 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 908 909 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 910 alloc_id); 911 912 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 913 frag->physical >> MON_BUFF_SHIFT_VER2); 914 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 915 (frag->physical + frag->size - 256) >> 916 MON_BUFF_SHIFT_VER2); 917 } 918 919 void iwl_pcie_apply_destination(struct iwl_trans *trans) 920 { 921 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 922 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 923 int i; 924 925 if (iwl_trans_dbg_ini_valid(trans)) { 926 iwl_pcie_apply_destination_ini(trans); 927 return; 928 } 929 930 IWL_INFO(trans, "Applying debug destination %s\n", 931 get_fw_dbg_mode_string(dest->monitor_mode)); 932 933 if (dest->monitor_mode == EXTERNAL_MODE) 934 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 935 else 936 IWL_WARN(trans, "PCI should have external buffer debug\n"); 937 938 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 939 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 940 u32 val = le32_to_cpu(dest->reg_ops[i].val); 941 942 switch (dest->reg_ops[i].op) { 943 case CSR_ASSIGN: 944 iwl_write32(trans, addr, val); 945 break; 946 case CSR_SETBIT: 947 iwl_set_bit(trans, addr, BIT(val)); 948 break; 949 case CSR_CLEARBIT: 950 iwl_clear_bit(trans, addr, BIT(val)); 951 break; 952 case PRPH_ASSIGN: 953 iwl_write_prph(trans, addr, val); 954 break; 955 case PRPH_SETBIT: 956 iwl_set_bits_prph(trans, addr, BIT(val)); 957 break; 958 case PRPH_CLEARBIT: 959 iwl_clear_bits_prph(trans, addr, BIT(val)); 960 break; 961 case PRPH_BLOCKBIT: 962 if (iwl_read_prph(trans, addr) & BIT(val)) { 963 IWL_ERR(trans, 964 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 965 val, addr); 966 goto monitor; 967 } 968 break; 969 default: 970 IWL_ERR(trans, "FW debug - unknown OP %d\n", 971 dest->reg_ops[i].op); 972 break; 973 } 974 } 975 976 monitor: 977 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 978 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 979 fw_mon->physical >> dest->base_shift); 980 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 981 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 982 (fw_mon->physical + fw_mon->size - 983 256) >> dest->end_shift); 984 else 985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 986 (fw_mon->physical + fw_mon->size) >> 987 dest->end_shift); 988 } 989 } 990 991 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 992 const struct fw_img *image) 993 { 994 int ret = 0; 995 int first_ucode_section; 996 997 IWL_DEBUG_FW(trans, "working with %s CPU\n", 998 image->is_dual_cpus ? "Dual" : "Single"); 999 1000 /* load to FW the binary non secured sections of CPU1 */ 1001 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1002 if (ret) 1003 return ret; 1004 1005 if (image->is_dual_cpus) { 1006 /* set CPU2 header address */ 1007 iwl_write_prph(trans, 1008 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1009 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1010 1011 /* load to FW the binary sections of CPU2 */ 1012 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1013 &first_ucode_section); 1014 if (ret) 1015 return ret; 1016 } 1017 1018 if (iwl_pcie_dbg_on(trans)) 1019 iwl_pcie_apply_destination(trans); 1020 1021 iwl_enable_interrupts(trans); 1022 1023 /* release CPU reset */ 1024 iwl_write32(trans, CSR_RESET, 0); 1025 1026 return 0; 1027 } 1028 1029 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1030 const struct fw_img *image) 1031 { 1032 int ret = 0; 1033 int first_ucode_section; 1034 1035 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1036 image->is_dual_cpus ? "Dual" : "Single"); 1037 1038 if (iwl_pcie_dbg_on(trans)) 1039 iwl_pcie_apply_destination(trans); 1040 1041 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1042 iwl_read_prph(trans, WFPM_GP2)); 1043 1044 /* 1045 * Set default value. On resume reading the values that were 1046 * zeored can provide debug data on the resume flow. 1047 * This is for debugging only and has no functional impact. 1048 */ 1049 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1050 1051 /* configure the ucode to be ready to get the secured image */ 1052 /* release CPU reset */ 1053 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1054 1055 /* load to FW the binary Secured sections of CPU1 */ 1056 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1057 &first_ucode_section); 1058 if (ret) 1059 return ret; 1060 1061 /* load to FW the binary sections of CPU2 */ 1062 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1063 &first_ucode_section); 1064 } 1065 1066 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1067 { 1068 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1069 bool hw_rfkill = iwl_is_rfkill_set(trans); 1070 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1071 bool report; 1072 1073 if (hw_rfkill) { 1074 set_bit(STATUS_RFKILL_HW, &trans->status); 1075 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1076 } else { 1077 clear_bit(STATUS_RFKILL_HW, &trans->status); 1078 if (trans_pcie->opmode_down) 1079 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1080 } 1081 1082 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1083 1084 if (prev != report) 1085 iwl_trans_pcie_rf_kill(trans, report); 1086 1087 return hw_rfkill; 1088 } 1089 1090 struct iwl_causes_list { 1091 u16 mask_reg; 1092 u8 bit; 1093 u8 addr; 1094 }; 1095 1096 #define IWL_CAUSE(reg, mask) \ 1097 { \ 1098 .mask_reg = reg, \ 1099 .bit = ilog2(mask), \ 1100 .addr = ilog2(mask) + \ 1101 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1102 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1103 0xffff), /* causes overflow warning */ \ 1104 } 1105 1106 static const struct iwl_causes_list causes_list_common[] = { 1107 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 1108 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 1109 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 1110 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 1111 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 1112 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 1113 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 1114 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR), 1115 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 1116 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 1117 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 1118 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 1119 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 1120 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 1121 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 1122 }; 1123 1124 static const struct iwl_causes_list causes_list_pre_bz[] = { 1125 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1126 }; 1127 1128 static const struct iwl_causes_list causes_list_bz[] = { 1129 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1130 }; 1131 1132 static void iwl_pcie_map_list(struct iwl_trans *trans, 1133 const struct iwl_causes_list *causes, 1134 int arr_size, int val) 1135 { 1136 int i; 1137 1138 for (i = 0; i < arr_size; i++) { 1139 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1140 iwl_clear_bit(trans, causes[i].mask_reg, 1141 BIT(causes[i].bit)); 1142 } 1143 } 1144 1145 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1146 { 1147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1148 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1149 /* 1150 * Access all non RX causes and map them to the default irq. 1151 * In case we are missing at least one interrupt vector, 1152 * the first interrupt vector will serve non-RX and FBQ causes. 1153 */ 1154 iwl_pcie_map_list(trans, causes_list_common, 1155 ARRAY_SIZE(causes_list_common), val); 1156 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1157 iwl_pcie_map_list(trans, causes_list_bz, 1158 ARRAY_SIZE(causes_list_bz), val); 1159 else 1160 iwl_pcie_map_list(trans, causes_list_pre_bz, 1161 ARRAY_SIZE(causes_list_pre_bz), val); 1162 } 1163 1164 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1165 { 1166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1167 u32 offset = 1168 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1169 u32 val, idx; 1170 1171 /* 1172 * The first RX queue - fallback queue, which is designated for 1173 * management frame, command responses etc, is always mapped to the 1174 * first interrupt vector. The other RX queues are mapped to 1175 * the other (N - 2) interrupt vectors. 1176 */ 1177 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1178 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1179 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1180 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1181 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1182 } 1183 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1184 1185 val = MSIX_FH_INT_CAUSES_Q(0); 1186 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1187 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1188 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1189 1190 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1191 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1192 } 1193 1194 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1195 { 1196 struct iwl_trans *trans = trans_pcie->trans; 1197 1198 if (!trans_pcie->msix_enabled) { 1199 if (trans->trans_cfg->mq_rx_supported && 1200 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1201 iwl_write_umac_prph(trans, UREG_CHICK, 1202 UREG_CHICK_MSI_ENABLE); 1203 return; 1204 } 1205 /* 1206 * The IVAR table needs to be configured again after reset, 1207 * but if the device is disabled, we can't write to 1208 * prph. 1209 */ 1210 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1211 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1212 1213 /* 1214 * Each cause from the causes list above and the RX causes is 1215 * represented as a byte in the IVAR table. The first nibble 1216 * represents the bound interrupt vector of the cause, the second 1217 * represents no auto clear for this cause. This will be set if its 1218 * interrupt vector is bound to serve other causes. 1219 */ 1220 iwl_pcie_map_rx_causes(trans); 1221 1222 iwl_pcie_map_non_rx_causes(trans); 1223 } 1224 1225 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1226 { 1227 struct iwl_trans *trans = trans_pcie->trans; 1228 1229 iwl_pcie_conf_msix_hw(trans_pcie); 1230 1231 if (!trans_pcie->msix_enabled) 1232 return; 1233 1234 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1235 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1236 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1237 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1238 } 1239 1240 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1241 { 1242 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1243 1244 lockdep_assert_held(&trans_pcie->mutex); 1245 1246 if (trans_pcie->is_down) 1247 return; 1248 1249 trans_pcie->is_down = true; 1250 1251 /* tell the device to stop sending interrupts */ 1252 iwl_disable_interrupts(trans); 1253 1254 /* device going down, Stop using ICT table */ 1255 iwl_pcie_disable_ict(trans); 1256 1257 /* 1258 * If a HW restart happens during firmware loading, 1259 * then the firmware loading might call this function 1260 * and later it might be called again due to the 1261 * restart. So don't process again if the device is 1262 * already dead. 1263 */ 1264 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1265 IWL_DEBUG_INFO(trans, 1266 "DEVICE_ENABLED bit was set and is now cleared\n"); 1267 iwl_pcie_rx_napi_sync(trans); 1268 iwl_pcie_tx_stop(trans); 1269 iwl_pcie_rx_stop(trans); 1270 1271 /* Power-down device's busmaster DMA clocks */ 1272 if (!trans->cfg->apmg_not_supported) { 1273 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1274 APMG_CLK_VAL_DMA_CLK_RQT); 1275 udelay(5); 1276 } 1277 } 1278 1279 /* Make sure (redundant) we've released our request to stay awake */ 1280 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1281 iwl_clear_bit(trans, CSR_GP_CNTRL, 1282 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1283 else 1284 iwl_clear_bit(trans, CSR_GP_CNTRL, 1285 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1286 1287 /* Stop the device, and put it in low power state */ 1288 iwl_pcie_apm_stop(trans, false); 1289 1290 /* re-take ownership to prevent other users from stealing the device */ 1291 iwl_trans_pcie_sw_reset(trans, true); 1292 1293 /* 1294 * Upon stop, the IVAR table gets erased, so msi-x won't 1295 * work. This causes a bug in RF-KILL flows, since the interrupt 1296 * that enables radio won't fire on the correct irq, and the 1297 * driver won't be able to handle the interrupt. 1298 * Configure the IVAR table again after reset. 1299 */ 1300 iwl_pcie_conf_msix_hw(trans_pcie); 1301 1302 /* 1303 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1304 * This is a bug in certain verions of the hardware. 1305 * Certain devices also keep sending HW RF kill interrupt all 1306 * the time, unless the interrupt is ACKed even if the interrupt 1307 * should be masked. Re-ACK all the interrupts here. 1308 */ 1309 iwl_disable_interrupts(trans); 1310 1311 /* clear all status bits */ 1312 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1313 clear_bit(STATUS_INT_ENABLED, &trans->status); 1314 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1315 1316 /* 1317 * Even if we stop the HW, we still want the RF kill 1318 * interrupt 1319 */ 1320 iwl_enable_rfkill_int(trans); 1321 } 1322 1323 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1324 { 1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1326 1327 if (trans_pcie->msix_enabled) { 1328 int i; 1329 1330 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1331 synchronize_irq(trans_pcie->msix_entries[i].vector); 1332 } else { 1333 synchronize_irq(trans_pcie->pci_dev->irq); 1334 } 1335 } 1336 1337 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1338 const struct fw_img *fw, bool run_in_rfkill) 1339 { 1340 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1341 bool hw_rfkill; 1342 int ret; 1343 1344 /* This may fail if AMT took ownership of the device */ 1345 if (iwl_pcie_prepare_card_hw(trans)) { 1346 IWL_WARN(trans, "Exit HW not ready\n"); 1347 return -EIO; 1348 } 1349 1350 iwl_enable_rfkill_int(trans); 1351 1352 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1353 1354 /* 1355 * We enabled the RF-Kill interrupt and the handler may very 1356 * well be running. Disable the interrupts to make sure no other 1357 * interrupt can be fired. 1358 */ 1359 iwl_disable_interrupts(trans); 1360 1361 /* Make sure it finished running */ 1362 iwl_pcie_synchronize_irqs(trans); 1363 1364 mutex_lock(&trans_pcie->mutex); 1365 1366 /* If platform's RF_KILL switch is NOT set to KILL */ 1367 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1368 if (hw_rfkill && !run_in_rfkill) { 1369 ret = -ERFKILL; 1370 goto out; 1371 } 1372 1373 /* Someone called stop_device, don't try to start_fw */ 1374 if (trans_pcie->is_down) { 1375 IWL_WARN(trans, 1376 "Can't start_fw since the HW hasn't been started\n"); 1377 ret = -EIO; 1378 goto out; 1379 } 1380 1381 /* make sure rfkill handshake bits are cleared */ 1382 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1383 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1384 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1385 1386 /* clear (again), then enable host interrupts */ 1387 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1388 1389 ret = iwl_pcie_nic_init(trans); 1390 if (ret) { 1391 IWL_ERR(trans, "Unable to init nic\n"); 1392 goto out; 1393 } 1394 1395 /* 1396 * Now, we load the firmware and don't want to be interrupted, even 1397 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1398 * FH_TX interrupt which is needed to load the firmware). If the 1399 * RF-Kill switch is toggled, we will find out after having loaded 1400 * the firmware and return the proper value to the caller. 1401 */ 1402 iwl_enable_fw_load_int(trans); 1403 1404 /* really make sure rfkill handshake bits are cleared */ 1405 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1406 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1407 1408 /* Load the given image to the HW */ 1409 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1410 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1411 else 1412 ret = iwl_pcie_load_given_ucode(trans, fw); 1413 1414 /* re-check RF-Kill state since we may have missed the interrupt */ 1415 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1416 if (hw_rfkill && !run_in_rfkill) 1417 ret = -ERFKILL; 1418 1419 out: 1420 mutex_unlock(&trans_pcie->mutex); 1421 return ret; 1422 } 1423 1424 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1425 { 1426 iwl_pcie_reset_ict(trans); 1427 iwl_pcie_tx_start(trans, scd_addr); 1428 } 1429 1430 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1431 bool was_in_rfkill) 1432 { 1433 bool hw_rfkill; 1434 1435 /* 1436 * Check again since the RF kill state may have changed while 1437 * all the interrupts were disabled, in this case we couldn't 1438 * receive the RF kill interrupt and update the state in the 1439 * op_mode. 1440 * Don't call the op_mode if the rkfill state hasn't changed. 1441 * This allows the op_mode to call stop_device from the rfkill 1442 * notification without endless recursion. Under very rare 1443 * circumstances, we might have a small recursion if the rfkill 1444 * state changed exactly now while we were called from stop_device. 1445 * This is very unlikely but can happen and is supported. 1446 */ 1447 hw_rfkill = iwl_is_rfkill_set(trans); 1448 if (hw_rfkill) { 1449 set_bit(STATUS_RFKILL_HW, &trans->status); 1450 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1451 } else { 1452 clear_bit(STATUS_RFKILL_HW, &trans->status); 1453 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1454 } 1455 if (hw_rfkill != was_in_rfkill) 1456 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1457 } 1458 1459 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1460 { 1461 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1462 bool was_in_rfkill; 1463 1464 iwl_op_mode_time_point(trans->op_mode, 1465 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1466 NULL); 1467 1468 mutex_lock(&trans_pcie->mutex); 1469 trans_pcie->opmode_down = true; 1470 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1471 _iwl_trans_pcie_stop_device(trans); 1472 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1473 mutex_unlock(&trans_pcie->mutex); 1474 } 1475 1476 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1477 { 1478 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1479 IWL_TRANS_GET_PCIE_TRANS(trans); 1480 1481 lockdep_assert_held(&trans_pcie->mutex); 1482 1483 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1484 state ? "disabled" : "enabled"); 1485 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1486 if (trans->trans_cfg->gen2) 1487 _iwl_trans_pcie_gen2_stop_device(trans); 1488 else 1489 _iwl_trans_pcie_stop_device(trans); 1490 } 1491 } 1492 1493 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1494 bool test, bool reset) 1495 { 1496 iwl_disable_interrupts(trans); 1497 1498 /* 1499 * in testing mode, the host stays awake and the 1500 * hardware won't be reset (not even partially) 1501 */ 1502 if (test) 1503 return; 1504 1505 iwl_pcie_disable_ict(trans); 1506 1507 iwl_pcie_synchronize_irqs(trans); 1508 1509 iwl_clear_bit(trans, CSR_GP_CNTRL, 1510 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1511 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1512 1513 if (reset) { 1514 /* 1515 * reset TX queues -- some of their registers reset during S3 1516 * so if we don't reset everything here the D3 image would try 1517 * to execute some invalid memory upon resume 1518 */ 1519 iwl_trans_pcie_tx_reset(trans); 1520 } 1521 1522 iwl_pcie_set_pwr(trans, true); 1523 } 1524 1525 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1526 { 1527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1528 int ret; 1529 1530 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1531 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1532 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1533 UREG_DOORBELL_TO_ISR6_RESUME); 1534 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1535 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1536 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1537 CSR_IPC_SLEEP_CONTROL_RESUME); 1538 else 1539 return 0; 1540 1541 ret = wait_event_timeout(trans_pcie->sx_waitq, 1542 trans_pcie->sx_complete, 2 * HZ); 1543 1544 /* Invalidate it toward next suspend or resume */ 1545 trans_pcie->sx_complete = false; 1546 1547 if (!ret) { 1548 IWL_ERR(trans, "Timeout %s D3\n", 1549 suspend ? "entering" : "exiting"); 1550 return -ETIMEDOUT; 1551 } 1552 1553 return 0; 1554 } 1555 1556 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1557 bool reset) 1558 { 1559 int ret; 1560 1561 if (!reset) 1562 /* Enable persistence mode to avoid reset */ 1563 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1564 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1565 1566 ret = iwl_pcie_d3_handshake(trans, true); 1567 if (ret) 1568 return ret; 1569 1570 iwl_pcie_d3_complete_suspend(trans, test, reset); 1571 1572 return 0; 1573 } 1574 1575 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1576 enum iwl_d3_status *status, 1577 bool test, bool reset) 1578 { 1579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1580 u32 val; 1581 int ret; 1582 1583 if (test) { 1584 iwl_enable_interrupts(trans); 1585 *status = IWL_D3_STATUS_ALIVE; 1586 ret = 0; 1587 goto out; 1588 } 1589 1590 iwl_set_bit(trans, CSR_GP_CNTRL, 1591 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1592 1593 ret = iwl_finish_nic_init(trans); 1594 if (ret) 1595 return ret; 1596 1597 /* 1598 * Reconfigure IVAR table in case of MSIX or reset ict table in 1599 * MSI mode since HW reset erased it. 1600 * Also enables interrupts - none will happen as 1601 * the device doesn't know we're waking it up, only when 1602 * the opmode actually tells it after this call. 1603 */ 1604 iwl_pcie_conf_msix_hw(trans_pcie); 1605 if (!trans_pcie->msix_enabled) 1606 iwl_pcie_reset_ict(trans); 1607 iwl_enable_interrupts(trans); 1608 1609 iwl_pcie_set_pwr(trans, false); 1610 1611 if (!reset) { 1612 iwl_clear_bit(trans, CSR_GP_CNTRL, 1613 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1614 } else { 1615 iwl_trans_pcie_tx_reset(trans); 1616 1617 ret = iwl_pcie_rx_init(trans); 1618 if (ret) { 1619 IWL_ERR(trans, 1620 "Failed to resume the device (RX reset)\n"); 1621 return ret; 1622 } 1623 } 1624 1625 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1626 iwl_read_umac_prph(trans, WFPM_GP2)); 1627 1628 val = iwl_read32(trans, CSR_RESET); 1629 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1630 *status = IWL_D3_STATUS_RESET; 1631 else 1632 *status = IWL_D3_STATUS_ALIVE; 1633 1634 out: 1635 if (*status == IWL_D3_STATUS_ALIVE) 1636 ret = iwl_pcie_d3_handshake(trans, false); 1637 1638 return ret; 1639 } 1640 1641 static void 1642 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1643 struct iwl_trans *trans, 1644 const struct iwl_cfg_trans_params *cfg_trans) 1645 { 1646 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1647 int max_irqs, num_irqs, i, ret; 1648 u16 pci_cmd; 1649 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1650 1651 if (!cfg_trans->mq_rx_supported) 1652 goto enable_msi; 1653 1654 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1655 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1656 1657 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1658 for (i = 0; i < max_irqs; i++) 1659 trans_pcie->msix_entries[i].entry = i; 1660 1661 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1662 MSIX_MIN_INTERRUPT_VECTORS, 1663 max_irqs); 1664 if (num_irqs < 0) { 1665 IWL_DEBUG_INFO(trans, 1666 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1667 num_irqs); 1668 goto enable_msi; 1669 } 1670 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1671 1672 IWL_DEBUG_INFO(trans, 1673 "MSI-X enabled. %d interrupt vectors were allocated\n", 1674 num_irqs); 1675 1676 /* 1677 * In case the OS provides fewer interrupts than requested, different 1678 * causes will share the same interrupt vector as follows: 1679 * One interrupt less: non rx causes shared with FBQ. 1680 * Two interrupts less: non rx causes shared with FBQ and RSS. 1681 * More than two interrupts: we will use fewer RSS queues. 1682 */ 1683 if (num_irqs <= max_irqs - 2) { 1684 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1685 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1686 IWL_SHARED_IRQ_FIRST_RSS; 1687 } else if (num_irqs == max_irqs - 1) { 1688 trans_pcie->trans->num_rx_queues = num_irqs; 1689 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1690 } else { 1691 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1692 } 1693 1694 IWL_DEBUG_INFO(trans, 1695 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1696 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1697 1698 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1699 1700 trans_pcie->alloc_vecs = num_irqs; 1701 trans_pcie->msix_enabled = true; 1702 return; 1703 1704 enable_msi: 1705 ret = pci_enable_msi(pdev); 1706 if (ret) { 1707 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1708 /* enable rfkill interrupt: hw bug w/a */ 1709 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1710 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1711 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1712 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1713 } 1714 } 1715 } 1716 1717 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1718 { 1719 int iter_rx_q, i, ret, cpu, offset; 1720 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1721 1722 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1723 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1724 offset = 1 + i; 1725 for (; i < iter_rx_q ; i++) { 1726 /* 1727 * Get the cpu prior to the place to search 1728 * (i.e. return will be > i - 1). 1729 */ 1730 cpu = cpumask_next(i - offset, cpu_online_mask); 1731 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1732 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1733 &trans_pcie->affinity_mask[i]); 1734 if (ret) 1735 IWL_ERR(trans_pcie->trans, 1736 "Failed to set affinity mask for IRQ %d\n", 1737 trans_pcie->msix_entries[i].vector); 1738 } 1739 } 1740 1741 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1742 struct iwl_trans_pcie *trans_pcie) 1743 { 1744 int i; 1745 1746 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1747 int ret; 1748 struct msix_entry *msix_entry; 1749 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1750 1751 if (!qname) 1752 return -ENOMEM; 1753 1754 msix_entry = &trans_pcie->msix_entries[i]; 1755 ret = devm_request_threaded_irq(&pdev->dev, 1756 msix_entry->vector, 1757 iwl_pcie_msix_isr, 1758 (i == trans_pcie->def_irq) ? 1759 iwl_pcie_irq_msix_handler : 1760 iwl_pcie_irq_rx_msix_handler, 1761 IRQF_SHARED, 1762 qname, 1763 msix_entry); 1764 if (ret) { 1765 IWL_ERR(trans_pcie->trans, 1766 "Error allocating IRQ %d\n", i); 1767 1768 return ret; 1769 } 1770 } 1771 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1772 1773 return 0; 1774 } 1775 1776 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1777 { 1778 u32 hpm, wprot; 1779 1780 switch (trans->trans_cfg->device_family) { 1781 case IWL_DEVICE_FAMILY_9000: 1782 wprot = PREG_PRPH_WPROT_9000; 1783 break; 1784 case IWL_DEVICE_FAMILY_22000: 1785 wprot = PREG_PRPH_WPROT_22000; 1786 break; 1787 default: 1788 return 0; 1789 } 1790 1791 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1792 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { 1793 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1794 1795 if (wprot_val & PREG_WFPM_ACCESS) { 1796 IWL_ERR(trans, 1797 "Error, can not clear persistence bit\n"); 1798 return -EPERM; 1799 } 1800 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1801 hpm & ~PERSISTENCE_BIT); 1802 } 1803 1804 return 0; 1805 } 1806 1807 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1808 { 1809 int ret; 1810 1811 ret = iwl_finish_nic_init(trans); 1812 if (ret < 0) 1813 return ret; 1814 1815 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1816 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1817 udelay(20); 1818 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1819 HPM_HIPM_GEN_CFG_CR_PG_EN | 1820 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1821 udelay(20); 1822 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1823 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1824 1825 return iwl_trans_pcie_sw_reset(trans, true); 1826 } 1827 1828 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1829 { 1830 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1831 int err; 1832 1833 lockdep_assert_held(&trans_pcie->mutex); 1834 1835 err = iwl_pcie_prepare_card_hw(trans); 1836 if (err) { 1837 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1838 return err; 1839 } 1840 1841 err = iwl_trans_pcie_clear_persistence_bit(trans); 1842 if (err) 1843 return err; 1844 1845 err = iwl_trans_pcie_sw_reset(trans, true); 1846 if (err) 1847 return err; 1848 1849 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1850 trans->trans_cfg->integrated) { 1851 err = iwl_pcie_gen2_force_power_gating(trans); 1852 if (err) 1853 return err; 1854 } 1855 1856 err = iwl_pcie_apm_init(trans); 1857 if (err) 1858 return err; 1859 1860 iwl_pcie_init_msix(trans_pcie); 1861 1862 /* From now on, the op_mode will be kept updated about RF kill state */ 1863 iwl_enable_rfkill_int(trans); 1864 1865 trans_pcie->opmode_down = false; 1866 1867 /* Set is_down to false here so that...*/ 1868 trans_pcie->is_down = false; 1869 1870 /* ...rfkill can call stop_device and set it false if needed */ 1871 iwl_pcie_check_hw_rf_kill(trans); 1872 1873 return 0; 1874 } 1875 1876 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1877 { 1878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1879 int ret; 1880 1881 mutex_lock(&trans_pcie->mutex); 1882 ret = _iwl_trans_pcie_start_hw(trans); 1883 mutex_unlock(&trans_pcie->mutex); 1884 1885 return ret; 1886 } 1887 1888 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1889 { 1890 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1891 1892 mutex_lock(&trans_pcie->mutex); 1893 1894 /* disable interrupts - don't enable HW RF kill interrupt */ 1895 iwl_disable_interrupts(trans); 1896 1897 iwl_pcie_apm_stop(trans, true); 1898 1899 iwl_disable_interrupts(trans); 1900 1901 iwl_pcie_disable_ict(trans); 1902 1903 mutex_unlock(&trans_pcie->mutex); 1904 1905 iwl_pcie_synchronize_irqs(trans); 1906 } 1907 1908 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1909 { 1910 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1911 } 1912 1913 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1914 { 1915 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1916 } 1917 1918 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1919 { 1920 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1921 } 1922 1923 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1924 { 1925 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1926 return 0x00FFFFFF; 1927 else 1928 return 0x000FFFFF; 1929 } 1930 1931 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1932 { 1933 u32 mask = iwl_trans_pcie_prph_msk(trans); 1934 1935 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1936 ((reg & mask) | (3 << 24))); 1937 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1938 } 1939 1940 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1941 u32 val) 1942 { 1943 u32 mask = iwl_trans_pcie_prph_msk(trans); 1944 1945 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1946 ((addr & mask) | (3 << 24))); 1947 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1948 } 1949 1950 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1951 const struct iwl_trans_config *trans_cfg) 1952 { 1953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1954 1955 /* free all first - we might be reconfigured for a different size */ 1956 iwl_pcie_free_rbs_pool(trans); 1957 1958 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 1959 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 1960 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1961 trans->txqs.page_offs = trans_cfg->cb_data_offs; 1962 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1963 trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 1964 1965 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1966 trans_pcie->n_no_reclaim_cmds = 0; 1967 else 1968 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1969 if (trans_pcie->n_no_reclaim_cmds) 1970 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1971 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1972 1973 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1974 trans_pcie->rx_page_order = 1975 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1976 trans_pcie->rx_buf_bytes = 1977 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1978 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1979 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1980 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1981 1982 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1983 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1984 1985 trans->command_groups = trans_cfg->command_groups; 1986 trans->command_groups_size = trans_cfg->command_groups_size; 1987 1988 /* Initialize NAPI here - it should be before registering to mac80211 1989 * in the opmode but after the HW struct is allocated. 1990 * As this function may be called again in some corner cases don't 1991 * do anything if NAPI was already initialized. 1992 */ 1993 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1994 init_dummy_netdev(&trans_pcie->napi_dev); 1995 1996 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1997 } 1998 1999 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 2000 struct device *dev) 2001 { 2002 u8 i; 2003 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 2004 2005 /* free DRAM payloads */ 2006 for (i = 0; i < dram_regions->n_regions; i++) { 2007 dma_free_coherent(dev, dram_regions->drams[i].size, 2008 dram_regions->drams[i].block, 2009 dram_regions->drams[i].physical); 2010 } 2011 dram_regions->n_regions = 0; 2012 2013 /* free DRAM addresses array */ 2014 if (desc_dram->block) { 2015 dma_free_coherent(dev, desc_dram->size, 2016 desc_dram->block, 2017 desc_dram->physical); 2018 } 2019 memset(desc_dram, 0, sizeof(*desc_dram)); 2020 } 2021 2022 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) 2023 { 2024 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); 2025 } 2026 2027 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) 2028 { 2029 struct iwl_cmd_header_wide bad_cmd = { 2030 .cmd = INVALID_WR_PTR_CMD, 2031 .group_id = DEBUG_GROUP, 2032 .sequence = cpu_to_le16(0xffff), 2033 .length = cpu_to_le16(0), 2034 .version = 0, 2035 }; 2036 int ret; 2037 2038 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, 2039 sizeof(bad_cmd)); 2040 if (ret) 2041 return ret; 2042 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); 2043 return 0; 2044 } 2045 2046 void iwl_trans_pcie_free(struct iwl_trans *trans) 2047 { 2048 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2049 int i; 2050 2051 iwl_pcie_synchronize_irqs(trans); 2052 2053 if (trans->trans_cfg->gen2) 2054 iwl_txq_gen2_tx_free(trans); 2055 else 2056 iwl_pcie_tx_free(trans); 2057 iwl_pcie_rx_free(trans); 2058 2059 if (trans_pcie->rba.alloc_wq) { 2060 destroy_workqueue(trans_pcie->rba.alloc_wq); 2061 trans_pcie->rba.alloc_wq = NULL; 2062 } 2063 2064 if (trans_pcie->msix_enabled) { 2065 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2066 irq_set_affinity_hint( 2067 trans_pcie->msix_entries[i].vector, 2068 NULL); 2069 } 2070 2071 trans_pcie->msix_enabled = false; 2072 } else { 2073 iwl_pcie_free_ict(trans); 2074 } 2075 2076 iwl_pcie_free_invalid_tx_cmd(trans); 2077 2078 iwl_pcie_free_fw_monitor(trans); 2079 2080 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, 2081 trans->dev); 2082 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, 2083 trans->dev); 2084 2085 mutex_destroy(&trans_pcie->mutex); 2086 iwl_trans_free(trans); 2087 } 2088 2089 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2090 { 2091 if (state) 2092 set_bit(STATUS_TPOWER_PMI, &trans->status); 2093 else 2094 clear_bit(STATUS_TPOWER_PMI, &trans->status); 2095 } 2096 2097 struct iwl_trans_pcie_removal { 2098 struct pci_dev *pdev; 2099 struct work_struct work; 2100 bool rescan; 2101 }; 2102 2103 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2104 { 2105 struct iwl_trans_pcie_removal *removal = 2106 container_of(wk, struct iwl_trans_pcie_removal, work); 2107 struct pci_dev *pdev = removal->pdev; 2108 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2109 struct pci_bus *bus = pdev->bus; 2110 2111 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2112 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2113 pci_lock_rescan_remove(); 2114 pci_dev_put(pdev); 2115 pci_stop_and_remove_bus_device(pdev); 2116 if (removal->rescan && bus) { 2117 if (bus->parent) 2118 bus = bus->parent; 2119 pci_rescan_bus(bus); 2120 } 2121 pci_unlock_rescan_remove(); 2122 2123 kfree(removal); 2124 module_put(THIS_MODULE); 2125 } 2126 2127 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) 2128 { 2129 struct iwl_trans_pcie_removal *removal; 2130 2131 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2132 return; 2133 2134 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2135 2136 /* 2137 * get a module reference to avoid doing this 2138 * while unloading anyway and to avoid 2139 * scheduling a work with code that's being 2140 * removed. 2141 */ 2142 if (!try_module_get(THIS_MODULE)) { 2143 IWL_ERR(trans, 2144 "Module is being unloaded - abort\n"); 2145 return; 2146 } 2147 2148 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2149 if (!removal) { 2150 module_put(THIS_MODULE); 2151 return; 2152 } 2153 /* 2154 * we don't need to clear this flag, because 2155 * the trans will be freed and reallocated. 2156 */ 2157 set_bit(STATUS_TRANS_DEAD, &trans->status); 2158 2159 removal->pdev = to_pci_dev(trans->dev); 2160 removal->rescan = rescan; 2161 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2162 pci_dev_get(removal->pdev); 2163 schedule_work(&removal->work); 2164 } 2165 EXPORT_SYMBOL(iwl_trans_pcie_remove); 2166 2167 /* 2168 * This version doesn't disable BHs but rather assumes they're 2169 * already disabled. 2170 */ 2171 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2172 { 2173 int ret; 2174 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2175 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2176 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2177 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2178 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2179 2180 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2181 return false; 2182 2183 spin_lock(&trans_pcie->reg_lock); 2184 2185 if (trans_pcie->cmd_hold_nic_awake) 2186 goto out; 2187 2188 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2189 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2190 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2191 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2192 } 2193 2194 /* this bit wakes up the NIC */ 2195 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2196 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2197 udelay(2); 2198 2199 /* 2200 * These bits say the device is running, and should keep running for 2201 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2202 * but they do not indicate that embedded SRAM is restored yet; 2203 * HW with volatile SRAM must save/restore contents to/from 2204 * host DRAM when sleeping/waking for power-saving. 2205 * Each direction takes approximately 1/4 millisecond; with this 2206 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2207 * series of register accesses are expected (e.g. reading Event Log), 2208 * to keep device from sleeping. 2209 * 2210 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2211 * SRAM is okay/restored. We don't check that here because this call 2212 * is just for hardware register access; but GP1 MAC_SLEEP 2213 * check is a good idea before accessing the SRAM of HW with 2214 * volatile SRAM (e.g. reading Event Log). 2215 * 2216 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2217 * and do not save/restore SRAM when power cycling. 2218 */ 2219 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2220 if (unlikely(ret < 0)) { 2221 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2222 2223 WARN_ONCE(1, 2224 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2225 cntrl); 2226 2227 iwl_trans_pcie_dump_regs(trans); 2228 2229 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2230 iwl_trans_pcie_remove(trans, false); 2231 else 2232 iwl_write32(trans, CSR_RESET, 2233 CSR_RESET_REG_FLAG_FORCE_NMI); 2234 2235 spin_unlock(&trans_pcie->reg_lock); 2236 return false; 2237 } 2238 2239 out: 2240 /* 2241 * Fool sparse by faking we release the lock - sparse will 2242 * track nic_access anyway. 2243 */ 2244 __release(&trans_pcie->reg_lock); 2245 return true; 2246 } 2247 2248 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2249 { 2250 bool ret; 2251 2252 local_bh_disable(); 2253 ret = __iwl_trans_pcie_grab_nic_access(trans); 2254 if (ret) { 2255 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2256 return ret; 2257 } 2258 local_bh_enable(); 2259 return false; 2260 } 2261 2262 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2263 { 2264 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2265 2266 lockdep_assert_held(&trans_pcie->reg_lock); 2267 2268 /* 2269 * Fool sparse by faking we acquiring the lock - sparse will 2270 * track nic_access anyway. 2271 */ 2272 __acquire(&trans_pcie->reg_lock); 2273 2274 if (trans_pcie->cmd_hold_nic_awake) 2275 goto out; 2276 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2277 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2278 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2279 else 2280 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2281 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2282 /* 2283 * Above we read the CSR_GP_CNTRL register, which will flush 2284 * any previous writes, but we need the write that clears the 2285 * MAC_ACCESS_REQ bit to be performed before any other writes 2286 * scheduled on different CPUs (after we drop reg_lock). 2287 */ 2288 out: 2289 spin_unlock_bh(&trans_pcie->reg_lock); 2290 } 2291 2292 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2293 void *buf, int dwords) 2294 { 2295 #define IWL_MAX_HW_ERRS 5 2296 unsigned int num_consec_hw_errors = 0; 2297 int offs = 0; 2298 u32 *vals = buf; 2299 2300 while (offs < dwords) { 2301 /* limit the time we spin here under lock to 1/2s */ 2302 unsigned long end = jiffies + HZ / 2; 2303 bool resched = false; 2304 2305 if (iwl_trans_grab_nic_access(trans)) { 2306 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2307 addr + 4 * offs); 2308 2309 while (offs < dwords) { 2310 vals[offs] = iwl_read32(trans, 2311 HBUS_TARG_MEM_RDAT); 2312 2313 if (iwl_trans_is_hw_error_value(vals[offs])) 2314 num_consec_hw_errors++; 2315 else 2316 num_consec_hw_errors = 0; 2317 2318 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) { 2319 iwl_trans_release_nic_access(trans); 2320 return -EIO; 2321 } 2322 2323 offs++; 2324 2325 if (time_after(jiffies, end)) { 2326 resched = true; 2327 break; 2328 } 2329 } 2330 iwl_trans_release_nic_access(trans); 2331 2332 if (resched) 2333 cond_resched(); 2334 } else { 2335 return -EBUSY; 2336 } 2337 } 2338 2339 return 0; 2340 } 2341 2342 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2343 const void *buf, int dwords) 2344 { 2345 int offs, ret = 0; 2346 const u32 *vals = buf; 2347 2348 if (iwl_trans_grab_nic_access(trans)) { 2349 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2350 for (offs = 0; offs < dwords; offs++) 2351 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2352 vals ? vals[offs] : 0); 2353 iwl_trans_release_nic_access(trans); 2354 } else { 2355 ret = -EBUSY; 2356 } 2357 return ret; 2358 } 2359 2360 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2361 u32 *val) 2362 { 2363 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2364 ofs, val); 2365 } 2366 2367 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2368 { 2369 int i; 2370 2371 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2372 struct iwl_txq *txq = trans->txqs.txq[i]; 2373 2374 if (i == trans->txqs.cmd.q_id) 2375 continue; 2376 2377 spin_lock_bh(&txq->lock); 2378 2379 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2380 txq->block--; 2381 if (!txq->block) { 2382 iwl_write32(trans, HBUS_TARG_WRPTR, 2383 txq->write_ptr | (i << 8)); 2384 } 2385 } else if (block) { 2386 txq->block++; 2387 } 2388 2389 spin_unlock_bh(&txq->lock); 2390 } 2391 } 2392 2393 #define IWL_FLUSH_WAIT_MS 2000 2394 2395 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2396 struct iwl_trans_rxq_dma_data *data) 2397 { 2398 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2399 2400 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2401 return -EINVAL; 2402 2403 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2404 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2405 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2406 data->fr_bd_wid = 0; 2407 2408 return 0; 2409 } 2410 2411 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2412 { 2413 struct iwl_txq *txq; 2414 unsigned long now = jiffies; 2415 bool overflow_tx; 2416 u8 wr_ptr; 2417 2418 /* Make sure the NIC is still alive in the bus */ 2419 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2420 return -ENODEV; 2421 2422 if (!test_bit(txq_idx, trans->txqs.queue_used)) 2423 return -EINVAL; 2424 2425 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2426 txq = trans->txqs.txq[txq_idx]; 2427 2428 spin_lock_bh(&txq->lock); 2429 overflow_tx = txq->overflow_tx || 2430 !skb_queue_empty(&txq->overflow_q); 2431 spin_unlock_bh(&txq->lock); 2432 2433 wr_ptr = READ_ONCE(txq->write_ptr); 2434 2435 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2436 overflow_tx) && 2437 !time_after(jiffies, 2438 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2439 u8 write_ptr = READ_ONCE(txq->write_ptr); 2440 2441 /* 2442 * If write pointer moved during the wait, warn only 2443 * if the TX came from op mode. In case TX came from 2444 * trans layer (overflow TX) don't warn. 2445 */ 2446 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2447 "WR pointer moved while flushing %d -> %d\n", 2448 wr_ptr, write_ptr)) 2449 return -ETIMEDOUT; 2450 wr_ptr = write_ptr; 2451 2452 usleep_range(1000, 2000); 2453 2454 spin_lock_bh(&txq->lock); 2455 overflow_tx = txq->overflow_tx || 2456 !skb_queue_empty(&txq->overflow_q); 2457 spin_unlock_bh(&txq->lock); 2458 } 2459 2460 if (txq->read_ptr != txq->write_ptr) { 2461 IWL_ERR(trans, 2462 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2463 iwl_txq_log_scd_error(trans, txq); 2464 return -ETIMEDOUT; 2465 } 2466 2467 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2468 2469 return 0; 2470 } 2471 2472 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2473 { 2474 int cnt; 2475 int ret = 0; 2476 2477 /* waiting for all the tx frames complete might take a while */ 2478 for (cnt = 0; 2479 cnt < trans->trans_cfg->base_params->num_of_queues; 2480 cnt++) { 2481 2482 if (cnt == trans->txqs.cmd.q_id) 2483 continue; 2484 if (!test_bit(cnt, trans->txqs.queue_used)) 2485 continue; 2486 if (!(BIT(cnt) & txq_bm)) 2487 continue; 2488 2489 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2490 if (ret) 2491 break; 2492 } 2493 2494 return ret; 2495 } 2496 2497 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2498 u32 mask, u32 value) 2499 { 2500 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2501 2502 spin_lock_bh(&trans_pcie->reg_lock); 2503 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2504 spin_unlock_bh(&trans_pcie->reg_lock); 2505 } 2506 2507 static const char *get_csr_string(int cmd) 2508 { 2509 #define IWL_CMD(x) case x: return #x 2510 switch (cmd) { 2511 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2512 IWL_CMD(CSR_INT_COALESCING); 2513 IWL_CMD(CSR_INT); 2514 IWL_CMD(CSR_INT_MASK); 2515 IWL_CMD(CSR_FH_INT_STATUS); 2516 IWL_CMD(CSR_GPIO_IN); 2517 IWL_CMD(CSR_RESET); 2518 IWL_CMD(CSR_GP_CNTRL); 2519 IWL_CMD(CSR_HW_REV); 2520 IWL_CMD(CSR_EEPROM_REG); 2521 IWL_CMD(CSR_EEPROM_GP); 2522 IWL_CMD(CSR_OTP_GP_REG); 2523 IWL_CMD(CSR_GIO_REG); 2524 IWL_CMD(CSR_GP_UCODE_REG); 2525 IWL_CMD(CSR_GP_DRIVER_REG); 2526 IWL_CMD(CSR_UCODE_DRV_GP1); 2527 IWL_CMD(CSR_UCODE_DRV_GP2); 2528 IWL_CMD(CSR_LED_REG); 2529 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2530 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2531 IWL_CMD(CSR_ANA_PLL_CFG); 2532 IWL_CMD(CSR_HW_REV_WA_REG); 2533 IWL_CMD(CSR_MONITOR_STATUS_REG); 2534 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2535 default: 2536 return "UNKNOWN"; 2537 } 2538 #undef IWL_CMD 2539 } 2540 2541 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2542 { 2543 int i; 2544 static const u32 csr_tbl[] = { 2545 CSR_HW_IF_CONFIG_REG, 2546 CSR_INT_COALESCING, 2547 CSR_INT, 2548 CSR_INT_MASK, 2549 CSR_FH_INT_STATUS, 2550 CSR_GPIO_IN, 2551 CSR_RESET, 2552 CSR_GP_CNTRL, 2553 CSR_HW_REV, 2554 CSR_EEPROM_REG, 2555 CSR_EEPROM_GP, 2556 CSR_OTP_GP_REG, 2557 CSR_GIO_REG, 2558 CSR_GP_UCODE_REG, 2559 CSR_GP_DRIVER_REG, 2560 CSR_UCODE_DRV_GP1, 2561 CSR_UCODE_DRV_GP2, 2562 CSR_LED_REG, 2563 CSR_DRAM_INT_TBL_REG, 2564 CSR_GIO_CHICKEN_BITS, 2565 CSR_ANA_PLL_CFG, 2566 CSR_MONITOR_STATUS_REG, 2567 CSR_HW_REV_WA_REG, 2568 CSR_DBG_HPET_MEM_REG 2569 }; 2570 IWL_ERR(trans, "CSR values:\n"); 2571 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2572 "CSR_INT_PERIODIC_REG)\n"); 2573 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2574 IWL_ERR(trans, " %25s: 0X%08x\n", 2575 get_csr_string(csr_tbl[i]), 2576 iwl_read32(trans, csr_tbl[i])); 2577 } 2578 } 2579 2580 #ifdef CONFIG_IWLWIFI_DEBUGFS 2581 /* create and remove of files */ 2582 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2583 debugfs_create_file(#name, mode, parent, trans, \ 2584 &iwl_dbgfs_##name##_ops); \ 2585 } while (0) 2586 2587 /* file operation */ 2588 #define DEBUGFS_READ_FILE_OPS(name) \ 2589 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2590 .read = iwl_dbgfs_##name##_read, \ 2591 .open = simple_open, \ 2592 .llseek = generic_file_llseek, \ 2593 }; 2594 2595 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2596 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2597 .write = iwl_dbgfs_##name##_write, \ 2598 .open = simple_open, \ 2599 .llseek = generic_file_llseek, \ 2600 }; 2601 2602 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2603 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2604 .write = iwl_dbgfs_##name##_write, \ 2605 .read = iwl_dbgfs_##name##_read, \ 2606 .open = simple_open, \ 2607 .llseek = generic_file_llseek, \ 2608 }; 2609 2610 struct iwl_dbgfs_tx_queue_priv { 2611 struct iwl_trans *trans; 2612 }; 2613 2614 struct iwl_dbgfs_tx_queue_state { 2615 loff_t pos; 2616 }; 2617 2618 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2619 { 2620 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2621 struct iwl_dbgfs_tx_queue_state *state; 2622 2623 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2624 return NULL; 2625 2626 state = kmalloc(sizeof(*state), GFP_KERNEL); 2627 if (!state) 2628 return NULL; 2629 state->pos = *pos; 2630 return state; 2631 } 2632 2633 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2634 void *v, loff_t *pos) 2635 { 2636 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2637 struct iwl_dbgfs_tx_queue_state *state = v; 2638 2639 *pos = ++state->pos; 2640 2641 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2642 return NULL; 2643 2644 return state; 2645 } 2646 2647 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2648 { 2649 kfree(v); 2650 } 2651 2652 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2653 { 2654 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2655 struct iwl_dbgfs_tx_queue_state *state = v; 2656 struct iwl_trans *trans = priv->trans; 2657 struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2658 2659 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2660 (unsigned int)state->pos, 2661 !!test_bit(state->pos, trans->txqs.queue_used), 2662 !!test_bit(state->pos, trans->txqs.queue_stopped)); 2663 if (txq) 2664 seq_printf(seq, 2665 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2666 txq->read_ptr, txq->write_ptr, 2667 txq->need_update, txq->frozen, 2668 txq->n_window, txq->ampdu); 2669 else 2670 seq_puts(seq, "(unallocated)"); 2671 2672 if (state->pos == trans->txqs.cmd.q_id) 2673 seq_puts(seq, " (HCMD)"); 2674 seq_puts(seq, "\n"); 2675 2676 return 0; 2677 } 2678 2679 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2680 .start = iwl_dbgfs_tx_queue_seq_start, 2681 .next = iwl_dbgfs_tx_queue_seq_next, 2682 .stop = iwl_dbgfs_tx_queue_seq_stop, 2683 .show = iwl_dbgfs_tx_queue_seq_show, 2684 }; 2685 2686 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2687 { 2688 struct iwl_dbgfs_tx_queue_priv *priv; 2689 2690 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2691 sizeof(*priv)); 2692 2693 if (!priv) 2694 return -ENOMEM; 2695 2696 priv->trans = inode->i_private; 2697 return 0; 2698 } 2699 2700 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2701 char __user *user_buf, 2702 size_t count, loff_t *ppos) 2703 { 2704 struct iwl_trans *trans = file->private_data; 2705 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2706 char *buf; 2707 int pos = 0, i, ret; 2708 size_t bufsz; 2709 2710 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2711 2712 if (!trans_pcie->rxq) 2713 return -EAGAIN; 2714 2715 buf = kzalloc(bufsz, GFP_KERNEL); 2716 if (!buf) 2717 return -ENOMEM; 2718 2719 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2720 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2721 2722 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2723 i); 2724 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2725 rxq->read); 2726 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2727 rxq->write); 2728 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2729 rxq->write_actual); 2730 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2731 rxq->need_update); 2732 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2733 rxq->free_count); 2734 if (rxq->rb_stts) { 2735 u32 r = iwl_get_closed_rb_stts(trans, rxq); 2736 pos += scnprintf(buf + pos, bufsz - pos, 2737 "\tclosed_rb_num: %u\n", r); 2738 } else { 2739 pos += scnprintf(buf + pos, bufsz - pos, 2740 "\tclosed_rb_num: Not Allocated\n"); 2741 } 2742 } 2743 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2744 kfree(buf); 2745 2746 return ret; 2747 } 2748 2749 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2750 char __user *user_buf, 2751 size_t count, loff_t *ppos) 2752 { 2753 struct iwl_trans *trans = file->private_data; 2754 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2755 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2756 2757 int pos = 0; 2758 char *buf; 2759 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2760 ssize_t ret; 2761 2762 buf = kzalloc(bufsz, GFP_KERNEL); 2763 if (!buf) 2764 return -ENOMEM; 2765 2766 pos += scnprintf(buf + pos, bufsz - pos, 2767 "Interrupt Statistics Report:\n"); 2768 2769 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2770 isr_stats->hw); 2771 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2772 isr_stats->sw); 2773 if (isr_stats->sw || isr_stats->hw) { 2774 pos += scnprintf(buf + pos, bufsz - pos, 2775 "\tLast Restarting Code: 0x%X\n", 2776 isr_stats->err_code); 2777 } 2778 #ifdef CONFIG_IWLWIFI_DEBUG 2779 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2780 isr_stats->sch); 2781 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2782 isr_stats->alive); 2783 #endif 2784 pos += scnprintf(buf + pos, bufsz - pos, 2785 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2786 2787 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2788 isr_stats->ctkill); 2789 2790 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2791 isr_stats->wakeup); 2792 2793 pos += scnprintf(buf + pos, bufsz - pos, 2794 "Rx command responses:\t\t %u\n", isr_stats->rx); 2795 2796 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2797 isr_stats->tx); 2798 2799 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2800 isr_stats->unhandled); 2801 2802 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2803 kfree(buf); 2804 return ret; 2805 } 2806 2807 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2808 const char __user *user_buf, 2809 size_t count, loff_t *ppos) 2810 { 2811 struct iwl_trans *trans = file->private_data; 2812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2813 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2814 u32 reset_flag; 2815 int ret; 2816 2817 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2818 if (ret) 2819 return ret; 2820 if (reset_flag == 0) 2821 memset(isr_stats, 0, sizeof(*isr_stats)); 2822 2823 return count; 2824 } 2825 2826 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2827 const char __user *user_buf, 2828 size_t count, loff_t *ppos) 2829 { 2830 struct iwl_trans *trans = file->private_data; 2831 2832 iwl_pcie_dump_csr(trans); 2833 2834 return count; 2835 } 2836 2837 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2838 char __user *user_buf, 2839 size_t count, loff_t *ppos) 2840 { 2841 struct iwl_trans *trans = file->private_data; 2842 char *buf = NULL; 2843 ssize_t ret; 2844 2845 ret = iwl_dump_fh(trans, &buf); 2846 if (ret < 0) 2847 return ret; 2848 if (!buf) 2849 return -EINVAL; 2850 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2851 kfree(buf); 2852 return ret; 2853 } 2854 2855 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2856 char __user *user_buf, 2857 size_t count, loff_t *ppos) 2858 { 2859 struct iwl_trans *trans = file->private_data; 2860 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2861 char buf[100]; 2862 int pos; 2863 2864 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2865 trans_pcie->debug_rfkill, 2866 !(iwl_read32(trans, CSR_GP_CNTRL) & 2867 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2868 2869 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2870 } 2871 2872 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2873 const char __user *user_buf, 2874 size_t count, loff_t *ppos) 2875 { 2876 struct iwl_trans *trans = file->private_data; 2877 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2878 bool new_value; 2879 int ret; 2880 2881 ret = kstrtobool_from_user(user_buf, count, &new_value); 2882 if (ret) 2883 return ret; 2884 if (new_value == trans_pcie->debug_rfkill) 2885 return count; 2886 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2887 trans_pcie->debug_rfkill, new_value); 2888 trans_pcie->debug_rfkill = new_value; 2889 iwl_pcie_handle_rfkill_irq(trans); 2890 2891 return count; 2892 } 2893 2894 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2895 struct file *file) 2896 { 2897 struct iwl_trans *trans = inode->i_private; 2898 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2899 2900 if (!trans->dbg.dest_tlv || 2901 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2902 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2903 return -ENOENT; 2904 } 2905 2906 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2907 return -EBUSY; 2908 2909 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2910 return simple_open(inode, file); 2911 } 2912 2913 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2914 struct file *file) 2915 { 2916 struct iwl_trans_pcie *trans_pcie = 2917 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2918 2919 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2920 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2921 return 0; 2922 } 2923 2924 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2925 void *buf, ssize_t *size, 2926 ssize_t *bytes_copied) 2927 { 2928 ssize_t buf_size_left = count - *bytes_copied; 2929 2930 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2931 if (*size > buf_size_left) 2932 *size = buf_size_left; 2933 2934 *size -= copy_to_user(user_buf, buf, *size); 2935 *bytes_copied += *size; 2936 2937 if (buf_size_left == *size) 2938 return true; 2939 return false; 2940 } 2941 2942 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2943 char __user *user_buf, 2944 size_t count, loff_t *ppos) 2945 { 2946 struct iwl_trans *trans = file->private_data; 2947 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2948 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2949 struct cont_rec *data = &trans_pcie->fw_mon_data; 2950 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2951 ssize_t size, bytes_copied = 0; 2952 bool b_full; 2953 2954 if (trans->dbg.dest_tlv) { 2955 write_ptr_addr = 2956 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2957 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2958 } else { 2959 write_ptr_addr = MON_BUFF_WRPTR; 2960 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2961 } 2962 2963 if (unlikely(!trans->dbg.rec_on)) 2964 return 0; 2965 2966 mutex_lock(&data->mutex); 2967 if (data->state == 2968 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2969 mutex_unlock(&data->mutex); 2970 return 0; 2971 } 2972 2973 /* write_ptr position in bytes rather then DW */ 2974 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2975 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2976 2977 if (data->prev_wrap_cnt == wrap_cnt) { 2978 size = write_ptr - data->prev_wr_ptr; 2979 curr_buf = cpu_addr + data->prev_wr_ptr; 2980 b_full = iwl_write_to_user_buf(user_buf, count, 2981 curr_buf, &size, 2982 &bytes_copied); 2983 data->prev_wr_ptr += size; 2984 2985 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2986 write_ptr < data->prev_wr_ptr) { 2987 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2988 curr_buf = cpu_addr + data->prev_wr_ptr; 2989 b_full = iwl_write_to_user_buf(user_buf, count, 2990 curr_buf, &size, 2991 &bytes_copied); 2992 data->prev_wr_ptr += size; 2993 2994 if (!b_full) { 2995 size = write_ptr; 2996 b_full = iwl_write_to_user_buf(user_buf, count, 2997 cpu_addr, &size, 2998 &bytes_copied); 2999 data->prev_wr_ptr = size; 3000 data->prev_wrap_cnt++; 3001 } 3002 } else { 3003 if (data->prev_wrap_cnt == wrap_cnt - 1 && 3004 write_ptr > data->prev_wr_ptr) 3005 IWL_WARN(trans, 3006 "write pointer passed previous write pointer, start copying from the beginning\n"); 3007 else if (!unlikely(data->prev_wrap_cnt == 0 && 3008 data->prev_wr_ptr == 0)) 3009 IWL_WARN(trans, 3010 "monitor data is out of sync, start copying from the beginning\n"); 3011 3012 size = write_ptr; 3013 b_full = iwl_write_to_user_buf(user_buf, count, 3014 cpu_addr, &size, 3015 &bytes_copied); 3016 data->prev_wr_ptr = size; 3017 data->prev_wrap_cnt = wrap_cnt; 3018 } 3019 3020 mutex_unlock(&data->mutex); 3021 3022 return bytes_copied; 3023 } 3024 3025 static ssize_t iwl_dbgfs_rf_read(struct file *file, 3026 char __user *user_buf, 3027 size_t count, loff_t *ppos) 3028 { 3029 struct iwl_trans *trans = file->private_data; 3030 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3031 3032 if (!trans_pcie->rf_name[0]) 3033 return -ENODEV; 3034 3035 return simple_read_from_buffer(user_buf, count, ppos, 3036 trans_pcie->rf_name, 3037 strlen(trans_pcie->rf_name)); 3038 } 3039 3040 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3041 DEBUGFS_READ_FILE_OPS(fh_reg); 3042 DEBUGFS_READ_FILE_OPS(rx_queue); 3043 DEBUGFS_WRITE_FILE_OPS(csr); 3044 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3045 DEBUGFS_READ_FILE_OPS(rf); 3046 3047 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3048 .owner = THIS_MODULE, 3049 .open = iwl_dbgfs_tx_queue_open, 3050 .read = seq_read, 3051 .llseek = seq_lseek, 3052 .release = seq_release_private, 3053 }; 3054 3055 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3056 .read = iwl_dbgfs_monitor_data_read, 3057 .open = iwl_dbgfs_monitor_data_open, 3058 .release = iwl_dbgfs_monitor_data_release, 3059 }; 3060 3061 /* Create the debugfs files and directories */ 3062 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3063 { 3064 struct dentry *dir = trans->dbgfs_dir; 3065 3066 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3067 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3068 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3069 DEBUGFS_ADD_FILE(csr, dir, 0200); 3070 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3071 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3072 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3073 DEBUGFS_ADD_FILE(rf, dir, 0400); 3074 } 3075 3076 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3077 { 3078 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3079 struct cont_rec *data = &trans_pcie->fw_mon_data; 3080 3081 mutex_lock(&data->mutex); 3082 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3083 mutex_unlock(&data->mutex); 3084 } 3085 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3086 3087 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3088 { 3089 u32 cmdlen = 0; 3090 int i; 3091 3092 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 3093 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3094 3095 return cmdlen; 3096 } 3097 3098 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3099 struct iwl_fw_error_dump_data **data, 3100 int allocated_rb_nums) 3101 { 3102 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3103 int max_len = trans_pcie->rx_buf_bytes; 3104 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3105 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3106 u32 i, r, j, rb_len = 0; 3107 3108 spin_lock(&rxq->lock); 3109 3110 r = iwl_get_closed_rb_stts(trans, rxq); 3111 3112 for (i = rxq->read, j = 0; 3113 i != r && j < allocated_rb_nums; 3114 i = (i + 1) & RX_QUEUE_MASK, j++) { 3115 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3116 struct iwl_fw_error_dump_rb *rb; 3117 3118 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3119 max_len, DMA_FROM_DEVICE); 3120 3121 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3122 3123 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3124 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3125 rb = (void *)(*data)->data; 3126 rb->index = cpu_to_le32(i); 3127 memcpy(rb->data, page_address(rxb->page), max_len); 3128 3129 *data = iwl_fw_error_next_data(*data); 3130 } 3131 3132 spin_unlock(&rxq->lock); 3133 3134 return rb_len; 3135 } 3136 #define IWL_CSR_TO_DUMP (0x250) 3137 3138 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3139 struct iwl_fw_error_dump_data **data) 3140 { 3141 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3142 __le32 *val; 3143 int i; 3144 3145 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3146 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3147 val = (void *)(*data)->data; 3148 3149 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3150 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3151 3152 *data = iwl_fw_error_next_data(*data); 3153 3154 return csr_len; 3155 } 3156 3157 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3158 struct iwl_fw_error_dump_data **data) 3159 { 3160 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3161 __le32 *val; 3162 int i; 3163 3164 if (!iwl_trans_grab_nic_access(trans)) 3165 return 0; 3166 3167 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3168 (*data)->len = cpu_to_le32(fh_regs_len); 3169 val = (void *)(*data)->data; 3170 3171 if (!trans->trans_cfg->gen2) 3172 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3173 i += sizeof(u32)) 3174 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3175 else 3176 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3177 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3178 i += sizeof(u32)) 3179 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3180 i)); 3181 3182 iwl_trans_release_nic_access(trans); 3183 3184 *data = iwl_fw_error_next_data(*data); 3185 3186 return sizeof(**data) + fh_regs_len; 3187 } 3188 3189 static u32 3190 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3191 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3192 u32 monitor_len) 3193 { 3194 u32 buf_size_in_dwords = (monitor_len >> 2); 3195 u32 *buffer = (u32 *)fw_mon_data->data; 3196 u32 i; 3197 3198 if (!iwl_trans_grab_nic_access(trans)) 3199 return 0; 3200 3201 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3202 for (i = 0; i < buf_size_in_dwords; i++) 3203 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3204 MON_DMARB_RD_DATA_ADDR); 3205 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3206 3207 iwl_trans_release_nic_access(trans); 3208 3209 return monitor_len; 3210 } 3211 3212 static void 3213 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3214 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3215 { 3216 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3217 3218 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3219 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3220 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3221 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3222 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3223 } else if (trans->dbg.dest_tlv) { 3224 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3225 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3226 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3227 } else { 3228 base = MON_BUFF_BASE_ADDR; 3229 write_ptr = MON_BUFF_WRPTR; 3230 wrap_cnt = MON_BUFF_CYCLE_CNT; 3231 } 3232 3233 write_ptr_val = iwl_read_prph(trans, write_ptr); 3234 fw_mon_data->fw_mon_cycle_cnt = 3235 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3236 fw_mon_data->fw_mon_base_ptr = 3237 cpu_to_le32(iwl_read_prph(trans, base)); 3238 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3239 fw_mon_data->fw_mon_base_high_ptr = 3240 cpu_to_le32(iwl_read_prph(trans, base_high)); 3241 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3242 /* convert wrtPtr to DWs, to align with all HWs */ 3243 write_ptr_val >>= 2; 3244 } 3245 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3246 } 3247 3248 static u32 3249 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3250 struct iwl_fw_error_dump_data **data, 3251 u32 monitor_len) 3252 { 3253 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3254 u32 len = 0; 3255 3256 if (trans->dbg.dest_tlv || 3257 (fw_mon->size && 3258 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3259 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3260 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3261 3262 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3263 fw_mon_data = (void *)(*data)->data; 3264 3265 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3266 3267 len += sizeof(**data) + sizeof(*fw_mon_data); 3268 if (fw_mon->size) { 3269 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3270 monitor_len = fw_mon->size; 3271 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3272 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3273 /* 3274 * Update pointers to reflect actual values after 3275 * shifting 3276 */ 3277 if (trans->dbg.dest_tlv->version) { 3278 base = (iwl_read_prph(trans, base) & 3279 IWL_LDBG_M2S_BUF_BA_MSK) << 3280 trans->dbg.dest_tlv->base_shift; 3281 base *= IWL_M2S_UNIT_SIZE; 3282 base += trans->cfg->smem_offset; 3283 } else { 3284 base = iwl_read_prph(trans, base) << 3285 trans->dbg.dest_tlv->base_shift; 3286 } 3287 3288 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3289 monitor_len / sizeof(u32)); 3290 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3291 monitor_len = 3292 iwl_trans_pci_dump_marbh_monitor(trans, 3293 fw_mon_data, 3294 monitor_len); 3295 } else { 3296 /* Didn't match anything - output no monitor data */ 3297 monitor_len = 0; 3298 } 3299 3300 len += monitor_len; 3301 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3302 } 3303 3304 return len; 3305 } 3306 3307 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3308 { 3309 if (trans->dbg.fw_mon.size) { 3310 *len += sizeof(struct iwl_fw_error_dump_data) + 3311 sizeof(struct iwl_fw_error_dump_fw_mon) + 3312 trans->dbg.fw_mon.size; 3313 return trans->dbg.fw_mon.size; 3314 } else if (trans->dbg.dest_tlv) { 3315 u32 base, end, cfg_reg, monitor_len; 3316 3317 if (trans->dbg.dest_tlv->version == 1) { 3318 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3319 cfg_reg = iwl_read_prph(trans, cfg_reg); 3320 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3321 trans->dbg.dest_tlv->base_shift; 3322 base *= IWL_M2S_UNIT_SIZE; 3323 base += trans->cfg->smem_offset; 3324 3325 monitor_len = 3326 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3327 trans->dbg.dest_tlv->end_shift; 3328 monitor_len *= IWL_M2S_UNIT_SIZE; 3329 } else { 3330 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3331 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3332 3333 base = iwl_read_prph(trans, base) << 3334 trans->dbg.dest_tlv->base_shift; 3335 end = iwl_read_prph(trans, end) << 3336 trans->dbg.dest_tlv->end_shift; 3337 3338 /* Make "end" point to the actual end */ 3339 if (trans->trans_cfg->device_family >= 3340 IWL_DEVICE_FAMILY_8000 || 3341 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3342 end += (1 << trans->dbg.dest_tlv->end_shift); 3343 monitor_len = end - base; 3344 } 3345 *len += sizeof(struct iwl_fw_error_dump_data) + 3346 sizeof(struct iwl_fw_error_dump_fw_mon) + 3347 monitor_len; 3348 return monitor_len; 3349 } 3350 return 0; 3351 } 3352 3353 static struct iwl_trans_dump_data * 3354 iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3355 u32 dump_mask, 3356 const struct iwl_dump_sanitize_ops *sanitize_ops, 3357 void *sanitize_ctx) 3358 { 3359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3360 struct iwl_fw_error_dump_data *data; 3361 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3362 struct iwl_fw_error_dump_txcmd *txcmd; 3363 struct iwl_trans_dump_data *dump_data; 3364 u32 len, num_rbs = 0, monitor_len = 0; 3365 int i, ptr; 3366 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3367 !trans->trans_cfg->mq_rx_supported && 3368 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3369 3370 if (!dump_mask) 3371 return NULL; 3372 3373 /* transport dump header */ 3374 len = sizeof(*dump_data); 3375 3376 /* host commands */ 3377 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3378 len += sizeof(*data) + 3379 cmdq->n_window * (sizeof(*txcmd) + 3380 TFD_MAX_PAYLOAD_SIZE); 3381 3382 /* FW monitor */ 3383 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3384 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3385 3386 /* CSR registers */ 3387 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3388 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3389 3390 /* FH registers */ 3391 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3392 if (trans->trans_cfg->gen2) 3393 len += sizeof(*data) + 3394 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3395 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3396 else 3397 len += sizeof(*data) + 3398 (FH_MEM_UPPER_BOUND - 3399 FH_MEM_LOWER_BOUND); 3400 } 3401 3402 if (dump_rbs) { 3403 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3404 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3405 /* RBs */ 3406 num_rbs = iwl_get_closed_rb_stts(trans, rxq); 3407 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3408 len += num_rbs * (sizeof(*data) + 3409 sizeof(struct iwl_fw_error_dump_rb) + 3410 (PAGE_SIZE << trans_pcie->rx_page_order)); 3411 } 3412 3413 /* Paged memory for gen2 HW */ 3414 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3415 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3416 len += sizeof(*data) + 3417 sizeof(struct iwl_fw_error_dump_paging) + 3418 trans->init_dram.paging[i].size; 3419 3420 dump_data = vzalloc(len); 3421 if (!dump_data) 3422 return NULL; 3423 3424 len = 0; 3425 data = (void *)dump_data->data; 3426 3427 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3428 u16 tfd_size = trans->txqs.tfd.size; 3429 3430 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3431 txcmd = (void *)data->data; 3432 spin_lock_bh(&cmdq->lock); 3433 ptr = cmdq->write_ptr; 3434 for (i = 0; i < cmdq->n_window; i++) { 3435 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3436 u8 tfdidx; 3437 u32 caplen, cmdlen; 3438 3439 if (trans->trans_cfg->gen2) 3440 tfdidx = idx; 3441 else 3442 tfdidx = ptr; 3443 3444 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3445 (u8 *)cmdq->tfds + 3446 tfd_size * tfdidx); 3447 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3448 3449 if (cmdlen) { 3450 len += sizeof(*txcmd) + caplen; 3451 txcmd->cmdlen = cpu_to_le32(cmdlen); 3452 txcmd->caplen = cpu_to_le32(caplen); 3453 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3454 caplen); 3455 if (sanitize_ops && sanitize_ops->frob_hcmd) 3456 sanitize_ops->frob_hcmd(sanitize_ctx, 3457 txcmd->data, 3458 caplen); 3459 txcmd = (void *)((u8 *)txcmd->data + caplen); 3460 } 3461 3462 ptr = iwl_txq_dec_wrap(trans, ptr); 3463 } 3464 spin_unlock_bh(&cmdq->lock); 3465 3466 data->len = cpu_to_le32(len); 3467 len += sizeof(*data); 3468 data = iwl_fw_error_next_data(data); 3469 } 3470 3471 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3472 len += iwl_trans_pcie_dump_csr(trans, &data); 3473 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3474 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3475 if (dump_rbs) 3476 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3477 3478 /* Paged memory for gen2 HW */ 3479 if (trans->trans_cfg->gen2 && 3480 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3481 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3482 struct iwl_fw_error_dump_paging *paging; 3483 u32 page_len = trans->init_dram.paging[i].size; 3484 3485 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3486 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3487 paging = (void *)data->data; 3488 paging->index = cpu_to_le32(i); 3489 memcpy(paging->data, 3490 trans->init_dram.paging[i].block, page_len); 3491 data = iwl_fw_error_next_data(data); 3492 3493 len += sizeof(*data) + sizeof(*paging) + page_len; 3494 } 3495 } 3496 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3497 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3498 3499 dump_data->len = len; 3500 3501 return dump_data; 3502 } 3503 3504 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3505 { 3506 if (enable) 3507 iwl_enable_interrupts(trans); 3508 else 3509 iwl_disable_interrupts(trans); 3510 } 3511 3512 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3513 { 3514 u32 inta_addr, sw_err_bit; 3515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3516 3517 if (trans_pcie->msix_enabled) { 3518 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3519 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3520 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3521 else 3522 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3523 } else { 3524 inta_addr = CSR_INT; 3525 sw_err_bit = CSR_INT_BIT_SW_ERR; 3526 } 3527 3528 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3529 } 3530 3531 #define IWL_TRANS_COMMON_OPS \ 3532 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3533 .write8 = iwl_trans_pcie_write8, \ 3534 .write32 = iwl_trans_pcie_write32, \ 3535 .read32 = iwl_trans_pcie_read32, \ 3536 .read_prph = iwl_trans_pcie_read_prph, \ 3537 .write_prph = iwl_trans_pcie_write_prph, \ 3538 .read_mem = iwl_trans_pcie_read_mem, \ 3539 .write_mem = iwl_trans_pcie_write_mem, \ 3540 .read_config32 = iwl_trans_pcie_read_config32, \ 3541 .configure = iwl_trans_pcie_configure, \ 3542 .set_pmi = iwl_trans_pcie_set_pmi, \ 3543 .sw_reset = iwl_trans_pcie_sw_reset, \ 3544 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3545 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3546 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3547 .dump_data = iwl_trans_pcie_dump_data, \ 3548 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3549 .d3_resume = iwl_trans_pcie_d3_resume, \ 3550 .interrupts = iwl_trans_pci_interrupts, \ 3551 .sync_nmi = iwl_trans_pcie_sync_nmi, \ 3552 .imr_dma_data = iwl_trans_pcie_copy_imr \ 3553 3554 static const struct iwl_trans_ops trans_ops_pcie = { 3555 IWL_TRANS_COMMON_OPS, 3556 .start_hw = iwl_trans_pcie_start_hw, 3557 .fw_alive = iwl_trans_pcie_fw_alive, 3558 .start_fw = iwl_trans_pcie_start_fw, 3559 .stop_device = iwl_trans_pcie_stop_device, 3560 3561 .send_cmd = iwl_pcie_enqueue_hcmd, 3562 3563 .tx = iwl_trans_pcie_tx, 3564 .reclaim = iwl_txq_reclaim, 3565 3566 .txq_disable = iwl_trans_pcie_txq_disable, 3567 .txq_enable = iwl_trans_pcie_txq_enable, 3568 3569 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3570 3571 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3572 3573 .freeze_txq_timer = iwl_trans_txq_freeze_timer, 3574 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3575 #ifdef CONFIG_IWLWIFI_DEBUGFS 3576 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3577 #endif 3578 }; 3579 3580 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3581 IWL_TRANS_COMMON_OPS, 3582 .start_hw = iwl_trans_pcie_start_hw, 3583 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3584 .start_fw = iwl_trans_pcie_gen2_start_fw, 3585 .stop_device = iwl_trans_pcie_gen2_stop_device, 3586 3587 .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3588 3589 .tx = iwl_txq_gen2_tx, 3590 .reclaim = iwl_txq_reclaim, 3591 3592 .set_q_ptrs = iwl_txq_set_q_ptrs, 3593 3594 .txq_alloc = iwl_txq_dyn_alloc, 3595 .txq_free = iwl_txq_dyn_free, 3596 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3597 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3598 .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm, 3599 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3600 .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power, 3601 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3602 #ifdef CONFIG_IWLWIFI_DEBUGFS 3603 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3604 #endif 3605 }; 3606 3607 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3608 const struct pci_device_id *ent, 3609 const struct iwl_cfg_trans_params *cfg_trans) 3610 { 3611 struct iwl_trans_pcie *trans_pcie; 3612 struct iwl_trans *trans; 3613 int ret, addr_size; 3614 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3615 void __iomem * const *table; 3616 u32 bar0; 3617 3618 if (!cfg_trans->gen2) 3619 ops = &trans_ops_pcie; 3620 3621 /* reassign our BAR 0 if invalid due to possible runtime PM races */ 3622 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0); 3623 if (bar0 == PCI_BASE_ADDRESS_MEM_TYPE_64) { 3624 ret = pci_assign_resource(pdev, 0); 3625 if (ret) 3626 return ERR_PTR(ret); 3627 } 3628 3629 ret = pcim_enable_device(pdev); 3630 if (ret) 3631 return ERR_PTR(ret); 3632 3633 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3634 cfg_trans); 3635 if (!trans) 3636 return ERR_PTR(-ENOMEM); 3637 3638 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3639 3640 trans_pcie->trans = trans; 3641 trans_pcie->opmode_down = true; 3642 spin_lock_init(&trans_pcie->irq_lock); 3643 spin_lock_init(&trans_pcie->reg_lock); 3644 spin_lock_init(&trans_pcie->alloc_page_lock); 3645 mutex_init(&trans_pcie->mutex); 3646 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3647 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3648 init_waitqueue_head(&trans_pcie->imr_waitq); 3649 3650 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3651 WQ_HIGHPRI | WQ_UNBOUND, 0); 3652 if (!trans_pcie->rba.alloc_wq) { 3653 ret = -ENOMEM; 3654 goto out_free_trans; 3655 } 3656 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3657 3658 trans_pcie->debug_rfkill = -1; 3659 3660 if (!cfg_trans->base_params->pcie_l1_allowed) { 3661 /* 3662 * W/A - seems to solve weird behavior. We need to remove this 3663 * if we don't want to stay in L1 all the time. This wastes a 3664 * lot of power. 3665 */ 3666 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3667 PCIE_LINK_STATE_L1 | 3668 PCIE_LINK_STATE_CLKPM); 3669 } 3670 3671 pci_set_master(pdev); 3672 3673 addr_size = trans->txqs.tfd.addr_size; 3674 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3675 if (ret) { 3676 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3677 /* both attempts failed: */ 3678 if (ret) { 3679 dev_err(&pdev->dev, "No suitable DMA available\n"); 3680 goto out_no_pci; 3681 } 3682 } 3683 3684 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3685 if (ret) { 3686 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3687 goto out_no_pci; 3688 } 3689 3690 table = pcim_iomap_table(pdev); 3691 if (!table) { 3692 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3693 ret = -ENOMEM; 3694 goto out_no_pci; 3695 } 3696 3697 trans_pcie->hw_base = table[0]; 3698 if (!trans_pcie->hw_base) { 3699 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3700 ret = -ENODEV; 3701 goto out_no_pci; 3702 } 3703 3704 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3705 * PCI Tx retries from interfering with C3 CPU state */ 3706 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3707 3708 trans_pcie->pci_dev = pdev; 3709 iwl_disable_interrupts(trans); 3710 3711 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3712 if (trans->hw_rev == 0xffffffff) { 3713 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3714 ret = -EIO; 3715 goto out_no_pci; 3716 } 3717 3718 /* 3719 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3720 * changed, and now the revision step also includes bit 0-1 (no more 3721 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3722 * in the old format. 3723 */ 3724 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3725 trans->hw_rev_step = trans->hw_rev & 0xF; 3726 else 3727 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3728 3729 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3730 3731 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3732 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3733 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3734 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3735 3736 init_waitqueue_head(&trans_pcie->sx_waitq); 3737 3738 ret = iwl_pcie_alloc_invalid_tx_cmd(trans); 3739 if (ret) 3740 goto out_no_pci; 3741 3742 if (trans_pcie->msix_enabled) { 3743 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3744 if (ret) 3745 goto out_no_pci; 3746 } else { 3747 ret = iwl_pcie_alloc_ict(trans); 3748 if (ret) 3749 goto out_no_pci; 3750 3751 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3752 iwl_pcie_isr, 3753 iwl_pcie_irq_handler, 3754 IRQF_SHARED, DRV_NAME, trans); 3755 if (ret) { 3756 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3757 goto out_free_ict; 3758 } 3759 } 3760 3761 #ifdef CONFIG_IWLWIFI_DEBUGFS 3762 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3763 mutex_init(&trans_pcie->fw_mon_data.mutex); 3764 #endif 3765 3766 iwl_dbg_tlv_init(trans); 3767 3768 return trans; 3769 3770 out_free_ict: 3771 iwl_pcie_free_ict(trans); 3772 out_no_pci: 3773 destroy_workqueue(trans_pcie->rba.alloc_wq); 3774 out_free_trans: 3775 iwl_trans_free(trans); 3776 return ERR_PTR(ret); 3777 } 3778 3779 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3780 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3781 { 3782 iwl_write_prph(trans, IMR_UREG_CHICK, 3783 iwl_read_prph(trans, IMR_UREG_CHICK) | 3784 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3785 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3786 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3787 (u32)(src_addr & 0xFFFFFFFF)); 3788 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3789 iwl_get_dma_hi_addr(src_addr)); 3790 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3791 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3792 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3793 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3794 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3795 } 3796 3797 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3798 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3799 { 3800 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3801 int ret = -1; 3802 3803 trans_pcie->imr_status = IMR_D2S_REQUESTED; 3804 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3805 ret = wait_event_timeout(trans_pcie->imr_waitq, 3806 trans_pcie->imr_status != 3807 IMR_D2S_REQUESTED, 5 * HZ); 3808 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3809 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3810 iwl_trans_pcie_dump_regs(trans); 3811 return -ETIMEDOUT; 3812 } 3813 trans_pcie->imr_status = IMR_D2S_IDLE; 3814 return 0; 3815 } 3816