xref: /linux/drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c (revision 40f6e94d873fe29bd5d987f53772eb8d968b8103)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2007-2015, 2018-2024 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
6  */
7 #include <linux/pci.h>
8 #include <linux/interrupt.h>
9 #include <linux/debugfs.h>
10 #include <linux/sched.h>
11 #include <linux/bitops.h>
12 #include <linux/gfp.h>
13 #include <linux/vmalloc.h>
14 #include <linux/module.h>
15 #include <linux/wait.h>
16 #include <linux/seq_file.h>
17 
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
25 #include "fw/dbg.h"
26 #include "fw/api/tx.h"
27 #include "fw/acpi.h"
28 #include "fw/api/tx.h"
29 #include "mei/iwl-mei.h"
30 #include "internal.h"
31 #include "iwl-fh.h"
32 #include "pcie/iwl-context-info-v2.h"
33 #include "pcie/utils.h"
34 
35 #define IWL_HOST_MON_BLOCK_PEMON	0x00
36 #define IWL_HOST_MON_BLOCK_HIPM		0x22
37 
38 #define IWL_HOST_MON_BLOCK_PEMON_VEC0	0x00
39 #define IWL_HOST_MON_BLOCK_PEMON_VEC1	0x01
40 #define IWL_HOST_MON_BLOCK_PEMON_WFPM	0x06
41 
42 static void iwl_dump_host_monitor_block(struct iwl_trans *trans,
43 					u32 block, u32 vec, u32 iter)
44 {
45 	int i;
46 
47 	IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec);
48 	iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec);
49 	for (i = 0; i < iter; i++)
50 		IWL_ERR(trans, "    value [iter %d]: 0x%08x\n",
51 			i, iwl_read32(trans, CSR_MONITOR_STATUS_REG));
52 }
53 
54 static void iwl_pcie_dump_host_monitor(struct iwl_trans *trans)
55 {
56 	switch (trans->mac_cfg->device_family) {
57 	case IWL_DEVICE_FAMILY_22000:
58 	case IWL_DEVICE_FAMILY_AX210:
59 		IWL_ERR(trans, "CSR_RESET = 0x%x\n",
60 			iwl_read32(trans, CSR_RESET));
61 		iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
62 					    IWL_HOST_MON_BLOCK_PEMON_VEC0, 15);
63 		iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
64 					    IWL_HOST_MON_BLOCK_PEMON_VEC1, 15);
65 		iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
66 					    IWL_HOST_MON_BLOCK_PEMON_WFPM, 15);
67 		iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_HIPM,
68 					    IWL_HOST_MON_BLOCK_PEMON_VEC0, 1);
69 		break;
70 	default:
71 		return;
72 	}
73 }
74 
75 /* extended range in FW SRAM */
76 #define IWL_FW_MEM_EXTENDED_START	0x40000
77 #define IWL_FW_MEM_EXTENDED_END		0x57FFF
78 
79 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership)
80 {
81 	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
82 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
83 		iwl_set_bit(trans, CSR_GP_CNTRL,
84 			    CSR_GP_CNTRL_REG_FLAG_SW_RESET);
85 		usleep_range(10000, 20000);
86 	} else {
87 		iwl_set_bit(trans, CSR_RESET,
88 			    CSR_RESET_REG_FLAG_SW_RESET);
89 		usleep_range(5000, 6000);
90 	}
91 
92 	if (retake_ownership)
93 		return iwl_pcie_prepare_card_hw(trans);
94 
95 	return 0;
96 }
97 
98 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
99 {
100 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
101 
102 	if (!fw_mon->size)
103 		return;
104 
105 	dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
106 			  fw_mon->physical);
107 
108 	fw_mon->block = NULL;
109 	fw_mon->physical = 0;
110 	fw_mon->size = 0;
111 }
112 
113 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
114 					    u8 max_power)
115 {
116 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
117 	void *block = NULL;
118 	dma_addr_t physical = 0;
119 	u32 size = 0;
120 	u8 power;
121 
122 	if (fw_mon->size) {
123 		memset(fw_mon->block, 0, fw_mon->size);
124 		return;
125 	}
126 
127 	/* need at least 2 KiB, so stop at 11 */
128 	for (power = max_power; power >= 11; power--) {
129 		size = BIT(power);
130 		block = dma_alloc_coherent(trans->dev, size, &physical,
131 					   GFP_KERNEL | __GFP_NOWARN);
132 		if (!block)
133 			continue;
134 
135 		IWL_INFO(trans,
136 			 "Allocated 0x%08x bytes for firmware monitor.\n",
137 			 size);
138 		break;
139 	}
140 
141 	if (WARN_ON_ONCE(!block))
142 		return;
143 
144 	if (power != max_power)
145 		IWL_ERR(trans,
146 			"Sorry - debug buffer is only %luK while you requested %luK\n",
147 			(unsigned long)BIT(power - 10),
148 			(unsigned long)BIT(max_power - 10));
149 
150 	fw_mon->block = block;
151 	fw_mon->physical = physical;
152 	fw_mon->size = size;
153 }
154 
155 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
156 {
157 	if (!max_power) {
158 		/* default max_power is maximum */
159 		max_power = 26;
160 	} else {
161 		max_power += 11;
162 	}
163 
164 	if (WARN(max_power > 26,
165 		 "External buffer size for monitor is too big %d, check the FW TLV\n",
166 		 max_power))
167 		return;
168 
169 	iwl_pcie_alloc_fw_monitor_block(trans, max_power);
170 }
171 
172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173 {
174 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 		    ((reg & 0x0000ffff) | (2 << 28)));
176 	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177 }
178 
179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180 {
181 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 		    ((reg & 0x0000ffff) | (3 << 28)));
184 }
185 
186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
187 {
188 	if (trans->mac_cfg->base->apmg_not_supported)
189 		return;
190 
191 	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
195 	else
196 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
199 }
200 
201 /* PCI registers */
202 #define PCI_CFG_RETRY_TIMEOUT	0x041
203 
204 void iwl_pcie_apm_config(struct iwl_trans *trans)
205 {
206 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
207 	u16 lctl;
208 	u16 cap;
209 
210 	/*
211 	 * L0S states have been found to be unstable with our devices
212 	 * and in newer hardware they are not officially supported at
213 	 * all, so we must always set the L0S_DISABLED bit.
214 	 */
215 	iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
216 
217 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
218 	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
219 
220 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
221 	trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
222 	IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
223 			(lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
224 			trans->ltr_enabled ? "En" : "Dis");
225 }
226 
227 /*
228  * Start up NIC's basic functionality after it has been reset
229  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
230  * NOTE:  This does not load uCode nor start the embedded processor
231  */
232 static int iwl_pcie_apm_init(struct iwl_trans *trans)
233 {
234 	int ret;
235 
236 	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
237 
238 	/*
239 	 * Use "set_bit" below rather than "write", to preserve any hardware
240 	 * bits already set by default after reset.
241 	 */
242 
243 	/* Disable L0S exit timer (platform NMI Work/Around) */
244 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000)
245 		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
246 			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
247 
248 	/*
249 	 * Disable L0s without affecting L1;
250 	 *  don't wait for ICH L0s (ICH bug W/A)
251 	 */
252 	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
253 		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
254 
255 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
256 	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
257 
258 	/*
259 	 * Enable HAP INTA (interrupt from management bus) to
260 	 * wake device's PCI Express link L1a -> L0s
261 	 */
262 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
263 		    CSR_HW_IF_CONFIG_REG_HAP_WAKE);
264 
265 	iwl_pcie_apm_config(trans);
266 
267 	/* Configure analog phase-lock-loop before activating to D0A */
268 	if (trans->mac_cfg->base->pll_cfg)
269 		iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
270 
271 	ret = iwl_finish_nic_init(trans);
272 	if (ret)
273 		return ret;
274 
275 	if (trans->cfg->host_interrupt_operation_mode) {
276 		/*
277 		 * This is a bit of an abuse - This is needed for 7260 / 3160
278 		 * only check host_interrupt_operation_mode even if this is
279 		 * not related to host_interrupt_operation_mode.
280 		 *
281 		 * Enable the oscillator to count wake up time for L1 exit. This
282 		 * consumes slightly more power (100uA) - but allows to be sure
283 		 * that we wake up from L1 on time.
284 		 *
285 		 * This looks weird: read twice the same register, discard the
286 		 * value, set a bit, and yet again, read that same register
287 		 * just to discard the value. But that's the way the hardware
288 		 * seems to like it.
289 		 */
290 		iwl_read_prph(trans, OSC_CLK);
291 		iwl_read_prph(trans, OSC_CLK);
292 		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
293 		iwl_read_prph(trans, OSC_CLK);
294 		iwl_read_prph(trans, OSC_CLK);
295 	}
296 
297 	/*
298 	 * Enable DMA clock and wait for it to stabilize.
299 	 *
300 	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
301 	 * bits do not disable clocks.  This preserves any hardware
302 	 * bits already set by default in "CLK_CTRL_REG" after reset.
303 	 */
304 	if (!trans->mac_cfg->base->apmg_not_supported) {
305 		iwl_write_prph(trans, APMG_CLK_EN_REG,
306 			       APMG_CLK_VAL_DMA_CLK_RQT);
307 		udelay(20);
308 
309 		/* Disable L1-Active */
310 		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
311 				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
312 
313 		/* Clear the interrupt in APMG if the NIC is in RFKILL */
314 		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
315 			       APMG_RTC_INT_STT_RFKILL);
316 	}
317 
318 	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
319 
320 	return 0;
321 }
322 
323 /*
324  * Enable LP XTAL to avoid HW bug where device may consume much power if
325  * FW is not loaded after device reset. LP XTAL is disabled by default
326  * after device HW reset. Do it only if XTAL is fed by internal source.
327  * Configure device's "persistence" mode to avoid resetting XTAL again when
328  * SHRD_HW_RST occurs in S3.
329  */
330 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
331 {
332 	int ret;
333 	u32 apmg_gp1_reg;
334 	u32 apmg_xtal_cfg_reg;
335 	u32 dl_cfg_reg;
336 
337 	/* Force XTAL ON */
338 	iwl_trans_set_bit(trans, CSR_GP_CNTRL,
339 			  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
340 
341 	ret = iwl_trans_pcie_sw_reset(trans, true);
342 
343 	if (!ret)
344 		ret = iwl_finish_nic_init(trans);
345 
346 	if (WARN_ON(ret)) {
347 		/* Release XTAL ON request */
348 		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
349 				    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
350 		return;
351 	}
352 
353 	/*
354 	 * Clear "disable persistence" to avoid LP XTAL resetting when
355 	 * SHRD_HW_RST is applied in S3.
356 	 */
357 	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
358 				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);
359 
360 	/*
361 	 * Force APMG XTAL to be active to prevent its disabling by HW
362 	 * caused by APMG idle state.
363 	 */
364 	apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
365 						    SHR_APMG_XTAL_CFG_REG);
366 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
367 				 apmg_xtal_cfg_reg |
368 				 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
369 
370 	ret = iwl_trans_pcie_sw_reset(trans, true);
371 	if (ret)
372 		IWL_ERR(trans,
373 			"iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n");
374 
375 	/* Enable LP XTAL by indirect access through CSR */
376 	apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
377 	iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
378 				 SHR_APMG_GP1_WF_XTAL_LP_EN |
379 				 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
380 
381 	/* Clear delay line clock power up */
382 	dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
383 	iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
384 				 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
385 
386 	/*
387 	 * Enable persistence mode to avoid LP XTAL resetting when
388 	 * SHRD_HW_RST is applied in S3.
389 	 */
390 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
391 		    CSR_HW_IF_CONFIG_REG_PERSISTENCE);
392 
393 	/*
394 	 * Clear "initialization complete" bit to move adapter from
395 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
396 	 */
397 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
398 
399 	/* Activates XTAL resources monitor */
400 	iwl_trans_set_bit(trans, CSR_MONITOR_CFG_REG,
401 			  CSR_MONITOR_XTAL_RESOURCES);
402 
403 	/* Release XTAL ON request */
404 	iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
405 			    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
406 	udelay(10);
407 
408 	/* Release APMG XTAL */
409 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
410 				 apmg_xtal_cfg_reg &
411 				 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
412 }
413 
414 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
415 {
416 	int ret;
417 
418 	/* stop device's busmaster DMA activity */
419 
420 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
421 		iwl_set_bit(trans, CSR_GP_CNTRL,
422 			    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
423 
424 		ret = iwl_poll_bits(trans, CSR_GP_CNTRL,
425 				    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
426 				    100);
427 		usleep_range(10000, 20000);
428 	} else {
429 		iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
430 
431 		ret = iwl_poll_bits(trans, CSR_RESET,
432 				    CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
433 	}
434 
435 	if (ret)
436 		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
437 
438 	IWL_DEBUG_INFO(trans, "stop master\n");
439 }
440 
441 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
442 {
443 	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
444 
445 	if (op_mode_leave) {
446 		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
447 			iwl_pcie_apm_init(trans);
448 
449 		/* inform ME that we are leaving */
450 		if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000)
451 			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
452 					  APMG_PCIDEV_STT_VAL_WAKE_ME);
453 		else if (trans->mac_cfg->device_family >=
454 			 IWL_DEVICE_FAMILY_8000) {
455 			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
456 				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
457 			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
458 				    CSR_HW_IF_CONFIG_REG_WAKE_ME |
459 				    CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
460 			mdelay(1);
461 			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
462 				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
463 		}
464 		mdelay(5);
465 	}
466 
467 	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
468 
469 	/* Stop device's DMA activity */
470 	iwl_pcie_apm_stop_master(trans);
471 
472 	if (trans->cfg->lp_xtal_workaround) {
473 		iwl_pcie_apm_lp_xtal_enable(trans);
474 		return;
475 	}
476 
477 	iwl_trans_pcie_sw_reset(trans, false);
478 
479 	/*
480 	 * Clear "initialization complete" bit to move adapter from
481 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
482 	 */
483 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
484 }
485 
486 static int iwl_pcie_nic_init(struct iwl_trans *trans)
487 {
488 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
489 	int ret;
490 
491 	/* nic_init */
492 	spin_lock_bh(&trans_pcie->irq_lock);
493 	ret = iwl_pcie_apm_init(trans);
494 	spin_unlock_bh(&trans_pcie->irq_lock);
495 
496 	if (ret)
497 		return ret;
498 
499 	iwl_pcie_set_pwr(trans, false);
500 
501 	iwl_op_mode_nic_config(trans->op_mode);
502 
503 	/* Allocate the RX queue, or reset if it is already allocated */
504 	ret = iwl_pcie_rx_init(trans);
505 	if (ret)
506 		return ret;
507 
508 	/* Allocate or reset and init all Tx and Command queues */
509 	if (iwl_pcie_tx_init(trans)) {
510 		iwl_pcie_rx_free(trans);
511 		return -ENOMEM;
512 	}
513 
514 	if (trans->mac_cfg->base->shadow_reg_enable) {
515 		/* enable shadow regs in HW */
516 		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
517 		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
518 	}
519 
520 	return 0;
521 }
522 
523 #define HW_READY_TIMEOUT (50)
524 
525 /* Note: returns poll_bit return value, which is >= 0 if success */
526 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
527 {
528 	int ret;
529 
530 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
531 		    CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);
532 
533 	/* See if we got it */
534 	ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
535 			    CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
536 			    HW_READY_TIMEOUT);
537 
538 	if (!ret)
539 		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
540 
541 	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret ? " not" : "");
542 	return ret;
543 }
544 
545 /* Note: returns standard 0/-ERROR code */
546 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
547 {
548 	int ret;
549 	int iter;
550 
551 	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
552 
553 	ret = iwl_pcie_set_hw_ready(trans);
554 	/* If the card is ready, exit 0 */
555 	if (!ret) {
556 		trans->csme_own = false;
557 		return 0;
558 	}
559 
560 	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
561 		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
562 	usleep_range(1000, 2000);
563 
564 	for (iter = 0; iter < 10; iter++) {
565 		int t = 0;
566 
567 		/* If HW is not ready, prepare the conditions to check again */
568 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
569 			    CSR_HW_IF_CONFIG_REG_WAKE_ME);
570 
571 		do {
572 			ret = iwl_pcie_set_hw_ready(trans);
573 			if (!ret) {
574 				trans->csme_own = false;
575 				return 0;
576 			}
577 
578 			if (iwl_mei_is_connected()) {
579 				IWL_DEBUG_INFO(trans,
580 					       "Couldn't prepare the card but SAP is connected\n");
581 				trans->csme_own = true;
582 				if (trans->mac_cfg->device_family !=
583 				    IWL_DEVICE_FAMILY_9000)
584 					IWL_ERR(trans,
585 						"SAP not supported for this NIC family\n");
586 
587 				return -EBUSY;
588 			}
589 
590 			usleep_range(200, 1000);
591 			t += 200;
592 		} while (t < 150000);
593 		msleep(25);
594 	}
595 
596 	IWL_ERR(trans, "Couldn't prepare the card\n");
597 
598 	return ret;
599 }
600 
601 /*
602  * ucode
603  */
604 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
605 					    u32 dst_addr, dma_addr_t phy_addr,
606 					    u32 byte_cnt)
607 {
608 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
609 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
610 
611 	iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
612 		    dst_addr);
613 
614 	iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
615 		    phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
616 
617 	iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
618 		    (iwl_get_dma_hi_addr(phy_addr)
619 			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
620 
621 	iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
622 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
623 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
624 		    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
625 
626 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
627 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
628 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
629 		    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
630 }
631 
632 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
633 					u32 dst_addr, dma_addr_t phy_addr,
634 					u32 byte_cnt)
635 {
636 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
637 	int ret;
638 
639 	trans_pcie->ucode_write_complete = false;
640 
641 	if (!iwl_trans_grab_nic_access(trans))
642 		return -EIO;
643 
644 	iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
645 					byte_cnt);
646 	iwl_trans_release_nic_access(trans);
647 
648 	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
649 				 trans_pcie->ucode_write_complete, 5 * HZ);
650 	if (!ret) {
651 		IWL_ERR(trans, "Failed to load firmware chunk!\n");
652 		iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev);
653 		return -ETIMEDOUT;
654 	}
655 
656 	return 0;
657 }
658 
659 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
660 			    const struct fw_desc *section)
661 {
662 	u8 *v_addr;
663 	dma_addr_t p_addr;
664 	u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
665 	int ret = 0;
666 
667 	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
668 		     section_num);
669 
670 	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
671 				    GFP_KERNEL | __GFP_NOWARN);
672 	if (!v_addr) {
673 		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
674 		chunk_sz = PAGE_SIZE;
675 		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
676 					    &p_addr, GFP_KERNEL);
677 		if (!v_addr)
678 			return -ENOMEM;
679 	}
680 
681 	for (offset = 0; offset < section->len; offset += chunk_sz) {
682 		u32 copy_size, dst_addr;
683 		bool extended_addr = false;
684 
685 		copy_size = min_t(u32, chunk_sz, section->len - offset);
686 		dst_addr = section->offset + offset;
687 
688 		if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
689 		    dst_addr <= IWL_FW_MEM_EXTENDED_END)
690 			extended_addr = true;
691 
692 		if (extended_addr)
693 			iwl_set_bits_prph(trans, LMPM_CHICK,
694 					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
695 
696 		memcpy(v_addr, (const u8 *)section->data + offset, copy_size);
697 		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
698 						   copy_size);
699 
700 		if (extended_addr)
701 			iwl_clear_bits_prph(trans, LMPM_CHICK,
702 					    LMPM_CHICK_EXTENDED_ADDR_SPACE);
703 
704 		if (ret) {
705 			IWL_ERR(trans,
706 				"Could not load the [%d] uCode section\n",
707 				section_num);
708 			break;
709 		}
710 	}
711 
712 	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
713 	return ret;
714 }
715 
716 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
717 					   const struct fw_img *image,
718 					   int cpu,
719 					   int *first_ucode_section)
720 {
721 	int shift_param;
722 	int i, ret = 0, sec_num = 0x1;
723 	u32 val, last_read_idx = 0;
724 
725 	if (cpu == 1) {
726 		shift_param = 0;
727 		*first_ucode_section = 0;
728 	} else {
729 		shift_param = 16;
730 		(*first_ucode_section)++;
731 	}
732 
733 	for (i = *first_ucode_section; i < image->num_sec; i++) {
734 		last_read_idx = i;
735 
736 		/*
737 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
738 		 * CPU1 to CPU2.
739 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
740 		 * CPU2 non paged to CPU2 paging sec.
741 		 */
742 		if (!image->sec[i].data ||
743 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
744 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
745 			IWL_DEBUG_FW(trans,
746 				     "Break since Data not valid or Empty section, sec = %d\n",
747 				     i);
748 			break;
749 		}
750 
751 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
752 		if (ret)
753 			return ret;
754 
755 		/* Notify ucode of loaded section number and status */
756 		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
757 		val = val | (sec_num << shift_param);
758 		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
759 
760 		sec_num = (sec_num << 1) | 0x1;
761 	}
762 
763 	*first_ucode_section = last_read_idx;
764 
765 	iwl_enable_interrupts(trans);
766 
767 	if (trans->mac_cfg->gen2) {
768 		if (cpu == 1)
769 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
770 				       0xFFFF);
771 		else
772 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
773 				       0xFFFFFFFF);
774 	} else {
775 		if (cpu == 1)
776 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
777 					   0xFFFF);
778 		else
779 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
780 					   0xFFFFFFFF);
781 	}
782 
783 	return 0;
784 }
785 
786 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
787 				      const struct fw_img *image,
788 				      int cpu,
789 				      int *first_ucode_section)
790 {
791 	int i, ret = 0;
792 	u32 last_read_idx = 0;
793 
794 	if (cpu == 1)
795 		*first_ucode_section = 0;
796 	else
797 		(*first_ucode_section)++;
798 
799 	for (i = *first_ucode_section; i < image->num_sec; i++) {
800 		last_read_idx = i;
801 
802 		/*
803 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
804 		 * CPU1 to CPU2.
805 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
806 		 * CPU2 non paged to CPU2 paging sec.
807 		 */
808 		if (!image->sec[i].data ||
809 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
810 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
811 			IWL_DEBUG_FW(trans,
812 				     "Break since Data not valid or Empty section, sec = %d\n",
813 				     i);
814 			break;
815 		}
816 
817 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
818 		if (ret)
819 			return ret;
820 	}
821 
822 	*first_ucode_section = last_read_idx;
823 
824 	return 0;
825 }
826 
827 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
828 {
829 	enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
830 	struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
831 		&trans->dbg.fw_mon_cfg[alloc_id];
832 	struct iwl_dram_data *frag;
833 
834 	if (!iwl_trans_dbg_ini_valid(trans))
835 		return;
836 
837 	if (le32_to_cpu(fw_mon_cfg->buf_location) ==
838 	    IWL_FW_INI_LOCATION_SRAM_PATH) {
839 		IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
840 		/* set sram monitor by enabling bit 7 */
841 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
842 			    CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
843 
844 		return;
845 	}
846 
847 	if (le32_to_cpu(fw_mon_cfg->buf_location) !=
848 	    IWL_FW_INI_LOCATION_DRAM_PATH ||
849 	    !trans->dbg.fw_mon_ini[alloc_id].num_frags)
850 		return;
851 
852 	frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
853 
854 	IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
855 		     alloc_id);
856 
857 	iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
858 			    frag->physical >> MON_BUFF_SHIFT_VER2);
859 	iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
860 			    (frag->physical + frag->size - 256) >>
861 			    MON_BUFF_SHIFT_VER2);
862 }
863 
864 void iwl_pcie_apply_destination(struct iwl_trans *trans)
865 {
866 	const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
867 	const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
868 	int i;
869 
870 	if (iwl_trans_dbg_ini_valid(trans)) {
871 		iwl_pcie_apply_destination_ini(trans);
872 		return;
873 	}
874 
875 	IWL_INFO(trans, "Applying debug destination %s\n",
876 		 get_fw_dbg_mode_string(dest->monitor_mode));
877 
878 	if (dest->monitor_mode == EXTERNAL_MODE)
879 		iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
880 	else
881 		IWL_WARN(trans, "PCI should have external buffer debug\n");
882 
883 	for (i = 0; i < trans->dbg.n_dest_reg; i++) {
884 		u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
885 		u32 val = le32_to_cpu(dest->reg_ops[i].val);
886 
887 		switch (dest->reg_ops[i].op) {
888 		case CSR_ASSIGN:
889 			iwl_write32(trans, addr, val);
890 			break;
891 		case CSR_SETBIT:
892 			iwl_set_bit(trans, addr, BIT(val));
893 			break;
894 		case CSR_CLEARBIT:
895 			iwl_clear_bit(trans, addr, BIT(val));
896 			break;
897 		case PRPH_ASSIGN:
898 			iwl_write_prph(trans, addr, val);
899 			break;
900 		case PRPH_SETBIT:
901 			iwl_set_bits_prph(trans, addr, BIT(val));
902 			break;
903 		case PRPH_CLEARBIT:
904 			iwl_clear_bits_prph(trans, addr, BIT(val));
905 			break;
906 		case PRPH_BLOCKBIT:
907 			if (iwl_read_prph(trans, addr) & BIT(val)) {
908 				IWL_ERR(trans,
909 					"BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
910 					val, addr);
911 				goto monitor;
912 			}
913 			break;
914 		default:
915 			IWL_ERR(trans, "FW debug - unknown OP %d\n",
916 				dest->reg_ops[i].op);
917 			break;
918 		}
919 	}
920 
921 monitor:
922 	if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
923 		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
924 			       fw_mon->physical >> dest->base_shift);
925 		if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
926 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
927 				       (fw_mon->physical + fw_mon->size -
928 					256) >> dest->end_shift);
929 		else
930 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
931 				       (fw_mon->physical + fw_mon->size) >>
932 				       dest->end_shift);
933 	}
934 }
935 
936 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
937 				const struct fw_img *image)
938 {
939 	int ret = 0;
940 	int first_ucode_section;
941 
942 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
943 		     image->is_dual_cpus ? "Dual" : "Single");
944 
945 	/* load to FW the binary non secured sections of CPU1 */
946 	ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
947 	if (ret)
948 		return ret;
949 
950 	if (image->is_dual_cpus) {
951 		/* set CPU2 header address */
952 		iwl_write_prph(trans,
953 			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
954 			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
955 
956 		/* load to FW the binary sections of CPU2 */
957 		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
958 						 &first_ucode_section);
959 		if (ret)
960 			return ret;
961 	}
962 
963 	if (iwl_pcie_dbg_on(trans))
964 		iwl_pcie_apply_destination(trans);
965 
966 	iwl_enable_interrupts(trans);
967 
968 	/* release CPU reset */
969 	iwl_write32(trans, CSR_RESET, 0);
970 
971 	return 0;
972 }
973 
974 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
975 					  const struct fw_img *image)
976 {
977 	int ret = 0;
978 	int first_ucode_section;
979 
980 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
981 		     image->is_dual_cpus ? "Dual" : "Single");
982 
983 	if (iwl_pcie_dbg_on(trans))
984 		iwl_pcie_apply_destination(trans);
985 
986 	IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
987 			iwl_read_prph(trans, WFPM_GP2));
988 
989 	/*
990 	 * Set default value. On resume reading the values that were
991 	 * zeored can provide debug data on the resume flow.
992 	 * This is for debugging only and has no functional impact.
993 	 */
994 	iwl_write_prph(trans, WFPM_GP2, 0x01010101);
995 
996 	/* configure the ucode to be ready to get the secured image */
997 	/* release CPU reset */
998 	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
999 
1000 	/* load to FW the binary Secured sections of CPU1 */
1001 	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1002 					      &first_ucode_section);
1003 	if (ret)
1004 		return ret;
1005 
1006 	/* load to FW the binary sections of CPU2 */
1007 	return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1008 					       &first_ucode_section);
1009 }
1010 
1011 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1012 {
1013 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1014 	bool hw_rfkill = iwl_is_rfkill_set(trans);
1015 	bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1016 	bool report;
1017 
1018 	if (hw_rfkill) {
1019 		set_bit(STATUS_RFKILL_HW, &trans->status);
1020 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1021 	} else {
1022 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1023 		if (trans_pcie->opmode_down)
1024 			clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1025 	}
1026 
1027 	report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1028 
1029 	if (prev != report)
1030 		iwl_trans_pcie_rf_kill(trans, report, false);
1031 
1032 	return hw_rfkill;
1033 }
1034 
1035 struct iwl_causes_list {
1036 	u16 mask_reg;
1037 	u8 bit;
1038 	u8 addr;
1039 };
1040 
1041 #define IWL_CAUSE(reg, mask)						\
1042 	{								\
1043 		.mask_reg = reg,					\
1044 		.bit = ilog2(mask),					\
1045 		.addr = ilog2(mask) +					\
1046 			((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 :	\
1047 			 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 :	\
1048 			 0xffff),	/* causes overflow warning */	\
1049 	}
1050 
1051 static const struct iwl_causes_list causes_list_common[] = {
1052 	IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM),
1053 	IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM),
1054 	IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D),
1055 	IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR),
1056 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE),
1057 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP),
1058 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE),
1059 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR),
1060 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL),
1061 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL),
1062 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC),
1063 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD),
1064 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX),
1065 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR),
1066 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP),
1067 };
1068 
1069 static const struct iwl_causes_list causes_list_pre_bz[] = {
1070 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR),
1071 };
1072 
1073 static const struct iwl_causes_list causes_list_bz[] = {
1074 	IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ),
1075 };
1076 
1077 static void iwl_pcie_map_list(struct iwl_trans *trans,
1078 			      const struct iwl_causes_list *causes,
1079 			      int arr_size, int val)
1080 {
1081 	int i;
1082 
1083 	for (i = 0; i < arr_size; i++) {
1084 		iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1085 		iwl_clear_bit(trans, causes[i].mask_reg,
1086 			      BIT(causes[i].bit));
1087 	}
1088 }
1089 
1090 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1091 {
1092 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1093 	int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1094 	/*
1095 	 * Access all non RX causes and map them to the default irq.
1096 	 * In case we are missing at least one interrupt vector,
1097 	 * the first interrupt vector will serve non-RX and FBQ causes.
1098 	 */
1099 	iwl_pcie_map_list(trans, causes_list_common,
1100 			  ARRAY_SIZE(causes_list_common), val);
1101 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1102 		iwl_pcie_map_list(trans, causes_list_bz,
1103 				  ARRAY_SIZE(causes_list_bz), val);
1104 	else
1105 		iwl_pcie_map_list(trans, causes_list_pre_bz,
1106 				  ARRAY_SIZE(causes_list_pre_bz), val);
1107 }
1108 
1109 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1110 {
1111 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1112 	u32 offset =
1113 		trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1114 	u32 val, idx;
1115 
1116 	/*
1117 	 * The first RX queue - fallback queue, which is designated for
1118 	 * management frame, command responses etc, is always mapped to the
1119 	 * first interrupt vector. The other RX queues are mapped to
1120 	 * the other (N - 2) interrupt vectors.
1121 	 */
1122 	val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1123 	for (idx = 1; idx < trans->info.num_rxqs; idx++) {
1124 		iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1125 			   MSIX_FH_INT_CAUSES_Q(idx - offset));
1126 		val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1127 	}
1128 	iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1129 
1130 	val = MSIX_FH_INT_CAUSES_Q(0);
1131 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1132 		val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1133 	iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1134 
1135 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1136 		iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1137 }
1138 
1139 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1140 {
1141 	struct iwl_trans *trans = trans_pcie->trans;
1142 
1143 	if (!trans_pcie->msix_enabled) {
1144 		if (trans->mac_cfg->mq_rx_supported &&
1145 		    test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1146 			iwl_write_umac_prph(trans, UREG_CHICK,
1147 					    UREG_CHICK_MSI_ENABLE);
1148 		return;
1149 	}
1150 	/*
1151 	 * The IVAR table needs to be configured again after reset,
1152 	 * but if the device is disabled, we can't write to
1153 	 * prph.
1154 	 */
1155 	if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1156 		iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1157 
1158 	/*
1159 	 * Each cause from the causes list above and the RX causes is
1160 	 * represented as a byte in the IVAR table. The first nibble
1161 	 * represents the bound interrupt vector of the cause, the second
1162 	 * represents no auto clear for this cause. This will be set if its
1163 	 * interrupt vector is bound to serve other causes.
1164 	 */
1165 	iwl_pcie_map_rx_causes(trans);
1166 
1167 	iwl_pcie_map_non_rx_causes(trans);
1168 }
1169 
1170 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1171 {
1172 	struct iwl_trans *trans = trans_pcie->trans;
1173 
1174 	iwl_pcie_conf_msix_hw(trans_pcie);
1175 
1176 	if (!trans_pcie->msix_enabled)
1177 		return;
1178 
1179 	trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1180 	trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1181 	trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1182 	trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1183 }
1184 
1185 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq)
1186 {
1187 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1188 
1189 	lockdep_assert_held(&trans_pcie->mutex);
1190 
1191 	if (trans_pcie->is_down)
1192 		return;
1193 
1194 	trans_pcie->is_down = true;
1195 
1196 	/* tell the device to stop sending interrupts */
1197 	iwl_disable_interrupts(trans);
1198 
1199 	/* device going down, Stop using ICT table */
1200 	iwl_pcie_disable_ict(trans);
1201 
1202 	/*
1203 	 * If a HW restart happens during firmware loading,
1204 	 * then the firmware loading might call this function
1205 	 * and later it might be called again due to the
1206 	 * restart. So don't process again if the device is
1207 	 * already dead.
1208 	 */
1209 	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1210 		IWL_DEBUG_INFO(trans,
1211 			       "DEVICE_ENABLED bit was set and is now cleared\n");
1212 		if (!from_irq)
1213 			iwl_pcie_synchronize_irqs(trans);
1214 		iwl_pcie_rx_napi_sync(trans);
1215 		iwl_pcie_tx_stop(trans);
1216 		iwl_pcie_rx_stop(trans);
1217 
1218 		/* Power-down device's busmaster DMA clocks */
1219 		if (!trans->mac_cfg->base->apmg_not_supported) {
1220 			iwl_write_prph(trans, APMG_CLK_DIS_REG,
1221 				       APMG_CLK_VAL_DMA_CLK_RQT);
1222 			udelay(5);
1223 		}
1224 	}
1225 
1226 	/* Make sure (redundant) we've released our request to stay awake */
1227 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1228 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1229 			      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1230 	else
1231 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1232 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1233 
1234 	/* Stop the device, and put it in low power state */
1235 	iwl_pcie_apm_stop(trans, false);
1236 
1237 	/* re-take ownership to prevent other users from stealing the device */
1238 	iwl_trans_pcie_sw_reset(trans, true);
1239 
1240 	/*
1241 	 * Upon stop, the IVAR table gets erased, so msi-x won't
1242 	 * work. This causes a bug in RF-KILL flows, since the interrupt
1243 	 * that enables radio won't fire on the correct irq, and the
1244 	 * driver won't be able to handle the interrupt.
1245 	 * Configure the IVAR table again after reset.
1246 	 */
1247 	iwl_pcie_conf_msix_hw(trans_pcie);
1248 
1249 	/*
1250 	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1251 	 * This is a bug in certain verions of the hardware.
1252 	 * Certain devices also keep sending HW RF kill interrupt all
1253 	 * the time, unless the interrupt is ACKed even if the interrupt
1254 	 * should be masked. Re-ACK all the interrupts here.
1255 	 */
1256 	iwl_disable_interrupts(trans);
1257 
1258 	/* clear all status bits */
1259 	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1260 	clear_bit(STATUS_INT_ENABLED, &trans->status);
1261 	clear_bit(STATUS_TPOWER_PMI, &trans->status);
1262 
1263 	/*
1264 	 * Even if we stop the HW, we still want the RF kill
1265 	 * interrupt
1266 	 */
1267 	iwl_enable_rfkill_int(trans);
1268 }
1269 
1270 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1271 {
1272 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1273 
1274 	if (trans_pcie->msix_enabled) {
1275 		int i;
1276 
1277 		for (i = 0; i < trans_pcie->alloc_vecs; i++)
1278 			synchronize_irq(trans_pcie->msix_entries[i].vector);
1279 	} else {
1280 		synchronize_irq(trans_pcie->pci_dev->irq);
1281 	}
1282 }
1283 
1284 int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1285 			    const struct iwl_fw *fw,
1286 			    const struct fw_img *img,
1287 			    bool run_in_rfkill)
1288 {
1289 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1290 	bool hw_rfkill;
1291 	int ret;
1292 
1293 	/* This may fail if AMT took ownership of the device */
1294 	if (iwl_pcie_prepare_card_hw(trans)) {
1295 		IWL_WARN(trans, "Exit HW not ready\n");
1296 		return -EIO;
1297 	}
1298 
1299 	iwl_enable_rfkill_int(trans);
1300 
1301 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1302 
1303 	/*
1304 	 * We enabled the RF-Kill interrupt and the handler may very
1305 	 * well be running. Disable the interrupts to make sure no other
1306 	 * interrupt can be fired.
1307 	 */
1308 	iwl_disable_interrupts(trans);
1309 
1310 	/* Make sure it finished running */
1311 	iwl_pcie_synchronize_irqs(trans);
1312 
1313 	mutex_lock(&trans_pcie->mutex);
1314 
1315 	/* If platform's RF_KILL switch is NOT set to KILL */
1316 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1317 	if (hw_rfkill && !run_in_rfkill) {
1318 		ret = -ERFKILL;
1319 		goto out;
1320 	}
1321 
1322 	/* Someone called stop_device, don't try to start_fw */
1323 	if (trans_pcie->is_down) {
1324 		IWL_WARN(trans,
1325 			 "Can't start_fw since the HW hasn't been started\n");
1326 		ret = -EIO;
1327 		goto out;
1328 	}
1329 
1330 	/* make sure rfkill handshake bits are cleared */
1331 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1332 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1333 		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1334 
1335 	/* clear (again), then enable host interrupts */
1336 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1337 
1338 	ret = iwl_pcie_nic_init(trans);
1339 	if (ret) {
1340 		IWL_ERR(trans, "Unable to init nic\n");
1341 		goto out;
1342 	}
1343 
1344 	/*
1345 	 * Now, we load the firmware and don't want to be interrupted, even
1346 	 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1347 	 * FH_TX interrupt which is needed to load the firmware). If the
1348 	 * RF-Kill switch is toggled, we will find out after having loaded
1349 	 * the firmware and return the proper value to the caller.
1350 	 */
1351 	iwl_enable_fw_load_int(trans);
1352 
1353 	/* really make sure rfkill handshake bits are cleared */
1354 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1355 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1356 
1357 	/* Load the given image to the HW */
1358 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1359 		ret = iwl_pcie_load_given_ucode_8000(trans, img);
1360 	else
1361 		ret = iwl_pcie_load_given_ucode(trans, img);
1362 
1363 	/* re-check RF-Kill state since we may have missed the interrupt */
1364 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1365 	if (hw_rfkill && !run_in_rfkill)
1366 		ret = -ERFKILL;
1367 
1368 out:
1369 	mutex_unlock(&trans_pcie->mutex);
1370 	return ret;
1371 }
1372 
1373 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1374 {
1375 	iwl_pcie_reset_ict(trans);
1376 	iwl_pcie_tx_start(trans);
1377 }
1378 
1379 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1380 				       bool was_in_rfkill)
1381 {
1382 	bool hw_rfkill;
1383 
1384 	/*
1385 	 * Check again since the RF kill state may have changed while
1386 	 * all the interrupts were disabled, in this case we couldn't
1387 	 * receive the RF kill interrupt and update the state in the
1388 	 * op_mode.
1389 	 * Don't call the op_mode if the rkfill state hasn't changed.
1390 	 * This allows the op_mode to call stop_device from the rfkill
1391 	 * notification without endless recursion. Under very rare
1392 	 * circumstances, we might have a small recursion if the rfkill
1393 	 * state changed exactly now while we were called from stop_device.
1394 	 * This is very unlikely but can happen and is supported.
1395 	 */
1396 	hw_rfkill = iwl_is_rfkill_set(trans);
1397 	if (hw_rfkill) {
1398 		set_bit(STATUS_RFKILL_HW, &trans->status);
1399 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1400 	} else {
1401 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1402 		clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1403 	}
1404 	if (hw_rfkill != was_in_rfkill)
1405 		iwl_trans_pcie_rf_kill(trans, hw_rfkill, false);
1406 }
1407 
1408 void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1409 {
1410 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1411 	bool was_in_rfkill;
1412 
1413 	iwl_op_mode_time_point(trans->op_mode,
1414 			       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
1415 			       NULL);
1416 
1417 	mutex_lock(&trans_pcie->mutex);
1418 	trans_pcie->opmode_down = true;
1419 	was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1420 	_iwl_trans_pcie_stop_device(trans, false);
1421 	iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1422 	mutex_unlock(&trans_pcie->mutex);
1423 }
1424 
1425 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq)
1426 {
1427 	struct iwl_trans_pcie __maybe_unused *trans_pcie =
1428 		IWL_TRANS_GET_PCIE_TRANS(trans);
1429 
1430 	lockdep_assert_held(&trans_pcie->mutex);
1431 
1432 	IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1433 		 state ? "disabled" : "enabled");
1434 	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) &&
1435 	    !WARN_ON(trans->mac_cfg->gen2))
1436 		_iwl_trans_pcie_stop_device(trans, from_irq);
1437 }
1438 
1439 static void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1440 					 bool reset)
1441 {
1442 	iwl_disable_interrupts(trans);
1443 
1444 	iwl_pcie_disable_ict(trans);
1445 
1446 	iwl_pcie_synchronize_irqs(trans);
1447 
1448 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
1449 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1450 			      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1451 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1452 			      CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
1453 	} else {
1454 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1455 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1456 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1457 			      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1458 	}
1459 
1460 	if (reset) {
1461 		/*
1462 		 * reset TX queues -- some of their registers reset during S3
1463 		 * so if we don't reset everything here the D3 image would try
1464 		 * to execute some invalid memory upon resume
1465 		 */
1466 		iwl_trans_pcie_tx_reset(trans);
1467 	}
1468 
1469 	iwl_pcie_set_pwr(trans, true);
1470 }
1471 
1472 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)
1473 {
1474 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1475 	int ret;
1476 
1477 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
1478 		return 0;
1479 
1480 	trans_pcie->sx_state = IWL_SX_WAITING;
1481 
1482 	if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
1483 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1484 				    suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :
1485 					      UREG_DOORBELL_TO_ISR6_RESUME);
1486 	else
1487 		iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
1488 			    suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :
1489 				      CSR_IPC_SLEEP_CONTROL_RESUME);
1490 
1491 	ret = wait_event_timeout(trans_pcie->sx_waitq,
1492 				 trans_pcie->sx_state != IWL_SX_WAITING,
1493 				 2 * HZ);
1494 	if (!ret) {
1495 		IWL_ERR(trans, "Timeout %s D3\n",
1496 			suspend ? "entering" : "exiting");
1497 		ret = -ETIMEDOUT;
1498 	} else {
1499 		ret = 0;
1500 	}
1501 
1502 	if (trans_pcie->sx_state == IWL_SX_ERROR) {
1503 		IWL_ERR(trans, "FW error while %s D3\n",
1504 			suspend ? "entering" : "exiting");
1505 		ret = -EIO;
1506 	}
1507 
1508 	/* Invalidate it toward next suspend or resume */
1509 	trans_pcie->sx_state = IWL_SX_INVALID;
1510 
1511 	return ret;
1512 }
1513 
1514 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool reset)
1515 {
1516 	int ret;
1517 
1518 	if (!reset)
1519 		/* Enable persistence mode to avoid reset */
1520 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1521 			    CSR_HW_IF_CONFIG_REG_PERSISTENCE);
1522 
1523 	ret = iwl_pcie_d3_handshake(trans, true);
1524 	if (ret)
1525 		return ret;
1526 
1527 	iwl_pcie_d3_complete_suspend(trans, reset);
1528 
1529 	return 0;
1530 }
1531 
1532 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1533 			     bool reset)
1534 {
1535 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1536 	u32 val;
1537 	int ret;
1538 
1539 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1540 		iwl_set_bit(trans, CSR_GP_CNTRL,
1541 			    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1542 	else
1543 		iwl_set_bit(trans, CSR_GP_CNTRL,
1544 			    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1545 
1546 	ret = iwl_finish_nic_init(trans);
1547 	if (ret) {
1548 		IWL_ERR(trans, "Failed to init nic upon resume. err = %d\n",
1549 			ret);
1550 		return ret;
1551 	}
1552 
1553 	/*
1554 	 * Reconfigure IVAR table in case of MSIX or reset ict table in
1555 	 * MSI mode since HW reset erased it.
1556 	 * Also enables interrupts - none will happen as
1557 	 * the device doesn't know we're waking it up, only when
1558 	 * the opmode actually tells it after this call.
1559 	 */
1560 	iwl_pcie_conf_msix_hw(trans_pcie);
1561 	if (!trans_pcie->msix_enabled)
1562 		iwl_pcie_reset_ict(trans);
1563 	iwl_enable_interrupts(trans);
1564 
1565 	iwl_pcie_set_pwr(trans, false);
1566 
1567 	if (!reset) {
1568 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1569 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1570 	} else {
1571 		iwl_trans_pcie_tx_reset(trans);
1572 
1573 		ret = iwl_pcie_rx_init(trans);
1574 		if (ret) {
1575 			IWL_ERR(trans,
1576 				"Failed to resume the device (RX reset)\n");
1577 			return ret;
1578 		}
1579 	}
1580 
1581 	IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1582 			iwl_read_umac_prph(trans, WFPM_GP2));
1583 
1584 	val = iwl_read32(trans, CSR_RESET);
1585 	if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
1586 		IWL_INFO(trans, "Device was reset during suspend\n");
1587 		trans->state = IWL_TRANS_NO_FW;
1588 		return -ENOENT;
1589 	}
1590 
1591 	return iwl_pcie_d3_handshake(trans, false);
1592 }
1593 
1594 static void
1595 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1596 			    struct iwl_trans *trans,
1597 			    const struct iwl_mac_cfg *mac_cfg,
1598 			    struct iwl_trans_info *info)
1599 {
1600 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1601 	int max_irqs, num_irqs, i, ret;
1602 	u16 pci_cmd;
1603 	u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1604 
1605 	if (!mac_cfg->mq_rx_supported)
1606 		goto enable_msi;
1607 
1608 	if (mac_cfg->device_family <= IWL_DEVICE_FAMILY_9000)
1609 		max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1610 
1611 	max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1612 	for (i = 0; i < max_irqs; i++)
1613 		trans_pcie->msix_entries[i].entry = i;
1614 
1615 	num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1616 					 MSIX_MIN_INTERRUPT_VECTORS,
1617 					 max_irqs);
1618 	if (num_irqs < 0) {
1619 		IWL_DEBUG_INFO(trans,
1620 			       "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1621 			       num_irqs);
1622 		goto enable_msi;
1623 	}
1624 	trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1625 
1626 	IWL_DEBUG_INFO(trans,
1627 		       "MSI-X enabled. %d interrupt vectors were allocated\n",
1628 		       num_irqs);
1629 
1630 	/*
1631 	 * In case the OS provides fewer interrupts than requested, different
1632 	 * causes will share the same interrupt vector as follows:
1633 	 * One interrupt less: non rx causes shared with FBQ.
1634 	 * Two interrupts less: non rx causes shared with FBQ and RSS.
1635 	 * More than two interrupts: we will use fewer RSS queues.
1636 	 */
1637 	if (num_irqs <= max_irqs - 2) {
1638 		info->num_rxqs = num_irqs + 1;
1639 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1640 			IWL_SHARED_IRQ_FIRST_RSS;
1641 	} else if (num_irqs == max_irqs - 1) {
1642 		info->num_rxqs = num_irqs;
1643 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1644 	} else {
1645 		info->num_rxqs = num_irqs - 1;
1646 	}
1647 
1648 	IWL_DEBUG_INFO(trans,
1649 		       "MSI-X enabled with rx queues %d, vec mask 0x%x\n",
1650 		       info->num_rxqs, trans_pcie->shared_vec_mask);
1651 
1652 	WARN_ON(info->num_rxqs > IWL_MAX_RX_HW_QUEUES);
1653 
1654 	trans_pcie->alloc_vecs = num_irqs;
1655 	trans_pcie->msix_enabled = true;
1656 	return;
1657 
1658 enable_msi:
1659 	info->num_rxqs = 1;
1660 	ret = pci_enable_msi(pdev);
1661 	if (ret) {
1662 		dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1663 		/* enable rfkill interrupt: hw bug w/a */
1664 		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1665 		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1666 			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1667 			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1668 		}
1669 	}
1670 }
1671 
1672 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans,
1673 				      struct iwl_trans_info *info)
1674 {
1675 #if defined(CONFIG_SMP)
1676 	int iter_rx_q, i, ret, cpu, offset;
1677 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1678 
1679 	i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1680 	iter_rx_q = info->num_rxqs - 1 + i;
1681 	offset = 1 + i;
1682 	for (; i < iter_rx_q ; i++) {
1683 		/*
1684 		 * Get the cpu prior to the place to search
1685 		 * (i.e. return will be > i - 1).
1686 		 */
1687 		cpu = cpumask_next(i - offset, cpu_online_mask);
1688 		cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1689 		ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1690 					    &trans_pcie->affinity_mask[i]);
1691 		if (ret)
1692 			IWL_ERR(trans_pcie->trans,
1693 				"Failed to set affinity mask for IRQ %d\n",
1694 				trans_pcie->msix_entries[i].vector);
1695 	}
1696 #endif
1697 }
1698 
1699 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1700 				      struct iwl_trans_pcie *trans_pcie,
1701 				      struct iwl_trans_info *info)
1702 {
1703 	int i;
1704 
1705 	for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1706 		int ret;
1707 		struct msix_entry *msix_entry;
1708 		const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1709 
1710 		if (!qname)
1711 			return -ENOMEM;
1712 
1713 		msix_entry = &trans_pcie->msix_entries[i];
1714 		ret = devm_request_threaded_irq(&pdev->dev,
1715 						msix_entry->vector,
1716 						iwl_pcie_msix_isr,
1717 						(i == trans_pcie->def_irq) ?
1718 						iwl_pcie_irq_msix_handler :
1719 						iwl_pcie_irq_rx_msix_handler,
1720 						IRQF_SHARED,
1721 						qname,
1722 						msix_entry);
1723 		if (ret) {
1724 			IWL_ERR(trans_pcie->trans,
1725 				"Error allocating IRQ %d\n", i);
1726 
1727 			return ret;
1728 		}
1729 	}
1730 	iwl_pcie_irq_set_affinity(trans_pcie->trans, info);
1731 
1732 	return 0;
1733 }
1734 
1735 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1736 {
1737 	u32 hpm, wprot;
1738 
1739 	switch (trans->mac_cfg->device_family) {
1740 	case IWL_DEVICE_FAMILY_9000:
1741 		wprot = PREG_PRPH_WPROT_9000;
1742 		break;
1743 	case IWL_DEVICE_FAMILY_22000:
1744 		wprot = PREG_PRPH_WPROT_22000;
1745 		break;
1746 	default:
1747 		return 0;
1748 	}
1749 
1750 	hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1751 	if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {
1752 		u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1753 
1754 		if (wprot_val & PREG_WFPM_ACCESS) {
1755 			IWL_ERR(trans,
1756 				"Error, can not clear persistence bit\n");
1757 			return -EPERM;
1758 		}
1759 		iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1760 					    hpm & ~PERSISTENCE_BIT);
1761 	}
1762 
1763 	return 0;
1764 }
1765 
1766 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1767 {
1768 	int ret;
1769 
1770 	ret = iwl_finish_nic_init(trans);
1771 	if (ret < 0)
1772 		return ret;
1773 
1774 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1775 			  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1776 	udelay(20);
1777 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1778 			  HPM_HIPM_GEN_CFG_CR_PG_EN |
1779 			  HPM_HIPM_GEN_CFG_CR_SLP_EN);
1780 	udelay(20);
1781 	iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1782 			    HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1783 
1784 	return iwl_trans_pcie_sw_reset(trans, true);
1785 }
1786 
1787 int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1788 {
1789 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1790 	int err;
1791 
1792 	lockdep_assert_held(&trans_pcie->mutex);
1793 
1794 	err = iwl_pcie_prepare_card_hw(trans);
1795 	if (err) {
1796 		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1797 		return err;
1798 	}
1799 
1800 	err = iwl_trans_pcie_clear_persistence_bit(trans);
1801 	if (err)
1802 		return err;
1803 
1804 	err = iwl_trans_pcie_sw_reset(trans, true);
1805 	if (err)
1806 		return err;
1807 
1808 	if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1809 	    trans->mac_cfg->integrated) {
1810 		err = iwl_pcie_gen2_force_power_gating(trans);
1811 		if (err)
1812 			return err;
1813 	}
1814 
1815 	err = iwl_pcie_apm_init(trans);
1816 	if (err)
1817 		return err;
1818 
1819 	iwl_pcie_init_msix(trans_pcie);
1820 
1821 	/* From now on, the op_mode will be kept updated about RF kill state */
1822 	iwl_enable_rfkill_int(trans);
1823 
1824 	trans_pcie->opmode_down = false;
1825 
1826 	/* Set is_down to false here so that...*/
1827 	trans_pcie->is_down = false;
1828 
1829 	/* ...rfkill can call stop_device and set it false if needed */
1830 	iwl_pcie_check_hw_rf_kill(trans);
1831 
1832 	return 0;
1833 }
1834 
1835 int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1836 {
1837 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1838 	int ret;
1839 
1840 	mutex_lock(&trans_pcie->mutex);
1841 	ret = _iwl_trans_pcie_start_hw(trans);
1842 	mutex_unlock(&trans_pcie->mutex);
1843 
1844 	return ret;
1845 }
1846 
1847 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1848 {
1849 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1850 
1851 	mutex_lock(&trans_pcie->mutex);
1852 
1853 	/* disable interrupts - don't enable HW RF kill interrupt */
1854 	iwl_disable_interrupts(trans);
1855 
1856 	iwl_pcie_apm_stop(trans, true);
1857 
1858 	iwl_disable_interrupts(trans);
1859 
1860 	iwl_pcie_disable_ict(trans);
1861 
1862 	mutex_unlock(&trans_pcie->mutex);
1863 
1864 	iwl_pcie_synchronize_irqs(trans);
1865 }
1866 
1867 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1868 {
1869 	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1870 }
1871 
1872 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1873 {
1874 	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1875 }
1876 
1877 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1878 {
1879 	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1880 }
1881 
1882 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1883 {
1884 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1885 		return 0x00FFFFFF;
1886 	else
1887 		return 0x000FFFFF;
1888 }
1889 
1890 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1891 {
1892 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1893 
1894 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1895 			       ((reg & mask) | (3 << 24)));
1896 	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1897 }
1898 
1899 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
1900 {
1901 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1902 
1903 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1904 			       ((addr & mask) | (3 << 24)));
1905 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1906 }
1907 
1908 void iwl_pcie_gen1_2_op_mode_enter(struct iwl_trans *trans)
1909 {
1910 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1911 
1912 	/* free all first - we might be reconfigured for a different size */
1913 	iwl_pcie_free_rbs_pool(trans);
1914 
1915 	trans_pcie->rx_page_order =
1916 		iwl_trans_get_rb_size_order(trans->conf.rx_buf_size);
1917 	trans_pcie->rx_buf_bytes =
1918 		iwl_trans_get_rb_size(trans->conf.rx_buf_size);
1919 }
1920 
1921 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
1922 					   struct device *dev)
1923 {
1924 	u8 i;
1925 	struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
1926 
1927 	/* free DRAM payloads */
1928 	for (i = 0; i < dram_regions->n_regions; i++) {
1929 		dma_free_coherent(dev, dram_regions->drams[i].size,
1930 				  dram_regions->drams[i].block,
1931 				  dram_regions->drams[i].physical);
1932 	}
1933 	dram_regions->n_regions = 0;
1934 
1935 	/* free DRAM addresses array */
1936 	if (desc_dram->block) {
1937 		dma_free_coherent(dev, desc_dram->size,
1938 				  desc_dram->block,
1939 				  desc_dram->physical);
1940 	}
1941 	memset(desc_dram, 0, sizeof(*desc_dram));
1942 }
1943 
1944 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans)
1945 {
1946 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1947 
1948 	iwl_pcie_free_dma_ptr(trans, &trans_pcie->invalid_tx_cmd);
1949 }
1950 
1951 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans)
1952 {
1953 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1954 	struct iwl_cmd_header_wide bad_cmd = {
1955 		.cmd = INVALID_WR_PTR_CMD,
1956 		.group_id = DEBUG_GROUP,
1957 		.sequence = cpu_to_le16(0xffff),
1958 		.length = cpu_to_le16(0),
1959 		.version = 0,
1960 	};
1961 	int ret;
1962 
1963 	ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->invalid_tx_cmd,
1964 				     sizeof(bad_cmd));
1965 	if (ret)
1966 		return ret;
1967 	memcpy(trans_pcie->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd));
1968 	return 0;
1969 }
1970 
1971 void iwl_trans_pcie_free(struct iwl_trans *trans)
1972 {
1973 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1974 	int i;
1975 
1976 	iwl_pcie_synchronize_irqs(trans);
1977 
1978 	if (trans->mac_cfg->gen2)
1979 		iwl_txq_gen2_tx_free(trans);
1980 	else
1981 		iwl_pcie_tx_free(trans);
1982 	iwl_pcie_rx_free(trans);
1983 
1984 	if (trans_pcie->rba.alloc_wq) {
1985 		destroy_workqueue(trans_pcie->rba.alloc_wq);
1986 		trans_pcie->rba.alloc_wq = NULL;
1987 	}
1988 
1989 	if (trans_pcie->msix_enabled) {
1990 		for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1991 			irq_set_affinity_hint(
1992 				trans_pcie->msix_entries[i].vector,
1993 				NULL);
1994 		}
1995 
1996 		trans_pcie->msix_enabled = false;
1997 	} else {
1998 		iwl_pcie_free_ict(trans);
1999 	}
2000 
2001 	free_netdev(trans_pcie->napi_dev);
2002 
2003 	iwl_pcie_free_invalid_tx_cmd(trans);
2004 
2005 	iwl_pcie_free_fw_monitor(trans);
2006 
2007 	iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data,
2008 					      trans->dev);
2009 	iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data,
2010 					      trans->dev);
2011 
2012 	mutex_destroy(&trans_pcie->mutex);
2013 
2014 	if (trans_pcie->txqs.tso_hdr_page) {
2015 		for_each_possible_cpu(i) {
2016 			struct iwl_tso_hdr_page *p =
2017 				per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i);
2018 
2019 			if (p && p->page)
2020 				__free_page(p->page);
2021 		}
2022 
2023 		free_percpu(trans_pcie->txqs.tso_hdr_page);
2024 	}
2025 
2026 	kmem_cache_destroy(trans_pcie->dev_cmd_pool);
2027 	iwl_trans_free(trans);
2028 }
2029 
2030 static union acpi_object *
2031 iwl_trans_pcie_call_prod_reset_dsm(struct pci_dev *pdev, u16 cmd, u16 value)
2032 {
2033 #ifdef CONFIG_ACPI
2034 	struct iwl_dsm_internal_product_reset_cmd pldr_arg = {
2035 		.cmd = cmd,
2036 		.value = value,
2037 	};
2038 	union acpi_object arg = {
2039 		.buffer.type = ACPI_TYPE_BUFFER,
2040 		.buffer.length = sizeof(pldr_arg),
2041 		.buffer.pointer = (void *)&pldr_arg,
2042 	};
2043 	static const guid_t dsm_guid = GUID_INIT(0x7266172C, 0x220B, 0x4B29,
2044 						 0x81, 0x4F, 0x75, 0xE4,
2045 						 0xDD, 0x26, 0xB5, 0xFD);
2046 
2047 	if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &dsm_guid, ACPI_DSM_REV,
2048 			    DSM_INTERNAL_FUNC_PRODUCT_RESET))
2049 		return ERR_PTR(-ENODEV);
2050 
2051 	return iwl_acpi_get_dsm_object(&pdev->dev, ACPI_DSM_REV,
2052 				       DSM_INTERNAL_FUNC_PRODUCT_RESET,
2053 				       &arg, &dsm_guid);
2054 #else
2055 	return ERR_PTR(-EOPNOTSUPP);
2056 #endif
2057 }
2058 
2059 void iwl_trans_pcie_check_product_reset_mode(struct pci_dev *pdev)
2060 {
2061 	union acpi_object *res;
2062 
2063 	res = iwl_trans_pcie_call_prod_reset_dsm(pdev,
2064 						 DSM_INTERNAL_PLDR_CMD_GET_MODE,
2065 						 0);
2066 	if (IS_ERR(res))
2067 		return;
2068 
2069 	if (res->type != ACPI_TYPE_INTEGER)
2070 		IWL_ERR_DEV(&pdev->dev,
2071 			    "unexpected return type from product reset DSM\n");
2072 	else
2073 		IWL_DEBUG_DEV_POWER(&pdev->dev,
2074 				    "product reset mode is 0x%llx\n",
2075 				    res->integer.value);
2076 
2077 	ACPI_FREE(res);
2078 }
2079 
2080 static void iwl_trans_pcie_set_product_reset(struct pci_dev *pdev, bool enable,
2081 					     bool integrated)
2082 {
2083 	union acpi_object *res;
2084 	u16 mode = enable ? DSM_INTERNAL_PLDR_MODE_EN_PROD_RESET : 0;
2085 
2086 	if (!integrated)
2087 		mode |= DSM_INTERNAL_PLDR_MODE_EN_WIFI_FLR |
2088 			DSM_INTERNAL_PLDR_MODE_EN_BT_OFF_ON;
2089 
2090 	res = iwl_trans_pcie_call_prod_reset_dsm(pdev,
2091 						 DSM_INTERNAL_PLDR_CMD_SET_MODE,
2092 						 mode);
2093 	if (IS_ERR(res)) {
2094 		if (enable)
2095 			IWL_ERR_DEV(&pdev->dev,
2096 				    "ACPI _DSM not available (%d), cannot do product reset\n",
2097 				    (int)PTR_ERR(res));
2098 		return;
2099 	}
2100 
2101 	ACPI_FREE(res);
2102 	IWL_DEBUG_DEV_POWER(&pdev->dev, "%sabled product reset via DSM\n",
2103 			    enable ? "En" : "Dis");
2104 	iwl_trans_pcie_check_product_reset_mode(pdev);
2105 }
2106 
2107 void iwl_trans_pcie_check_product_reset_status(struct pci_dev *pdev)
2108 {
2109 	union acpi_object *res;
2110 
2111 	res = iwl_trans_pcie_call_prod_reset_dsm(pdev,
2112 						 DSM_INTERNAL_PLDR_CMD_GET_STATUS,
2113 						 0);
2114 	if (IS_ERR(res))
2115 		return;
2116 
2117 	if (res->type != ACPI_TYPE_INTEGER)
2118 		IWL_ERR_DEV(&pdev->dev,
2119 			    "unexpected return type from product reset DSM\n");
2120 	else
2121 		IWL_DEBUG_DEV_POWER(&pdev->dev,
2122 				    "product reset status is 0x%llx\n",
2123 				    res->integer.value);
2124 
2125 	ACPI_FREE(res);
2126 }
2127 
2128 static void iwl_trans_pcie_call_reset(struct pci_dev *pdev)
2129 {
2130 #ifdef CONFIG_ACPI
2131 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2132 	union acpi_object *p, *ref;
2133 	acpi_status status;
2134 	int ret = -EINVAL;
2135 
2136 	status = acpi_evaluate_object(ACPI_HANDLE(&pdev->dev),
2137 				      "_PRR", NULL, &buffer);
2138 	if (ACPI_FAILURE(status)) {
2139 		IWL_DEBUG_DEV_POWER(&pdev->dev, "No _PRR method found\n");
2140 		goto out;
2141 	}
2142 	p = buffer.pointer;
2143 
2144 	if (p->type != ACPI_TYPE_PACKAGE || p->package.count != 1) {
2145 		pci_err(pdev, "Bad _PRR return type\n");
2146 		goto out;
2147 	}
2148 
2149 	ref = &p->package.elements[0];
2150 	if (ref->type != ACPI_TYPE_LOCAL_REFERENCE) {
2151 		pci_err(pdev, "_PRR wasn't a reference\n");
2152 		goto out;
2153 	}
2154 
2155 	status = acpi_evaluate_object(ref->reference.handle,
2156 				      "_RST", NULL, NULL);
2157 	if (ACPI_FAILURE(status)) {
2158 		pci_err(pdev,
2159 			"Failed to call _RST on object returned by _PRR (%d)\n",
2160 			status);
2161 		goto out;
2162 	}
2163 	ret = 0;
2164 out:
2165 	kfree(buffer.pointer);
2166 	if (!ret) {
2167 		IWL_DEBUG_DEV_POWER(&pdev->dev, "called _RST on _PRR object\n");
2168 		return;
2169 	}
2170 	IWL_DEBUG_DEV_POWER(&pdev->dev,
2171 			    "No BIOS support, using pci_reset_function()\n");
2172 #endif
2173 	pci_reset_function(pdev);
2174 }
2175 
2176 struct iwl_trans_pcie_removal {
2177 	struct pci_dev *pdev;
2178 	struct work_struct work;
2179 	enum iwl_reset_mode mode;
2180 	bool integrated;
2181 };
2182 
2183 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2184 {
2185 	struct iwl_trans_pcie_removal *removal =
2186 		container_of(wk, struct iwl_trans_pcie_removal, work);
2187 	struct pci_dev *pdev = removal->pdev;
2188 	static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2189 	struct pci_bus *bus;
2190 
2191 	pci_lock_rescan_remove();
2192 
2193 	bus = pdev->bus;
2194 	/* in this case, something else already removed the device */
2195 	if (!bus)
2196 		goto out;
2197 
2198 	kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2199 
2200 	if (removal->mode == IWL_RESET_MODE_PROD_RESET) {
2201 		struct pci_dev *bt = NULL;
2202 
2203 		if (!removal->integrated) {
2204 			/* discrete devices have WiFi/BT at function 0/1 */
2205 			int slot = PCI_SLOT(pdev->devfn);
2206 			int func = PCI_FUNC(pdev->devfn);
2207 
2208 			if (func == 0)
2209 				bt = pci_get_slot(bus, PCI_DEVFN(slot, 1));
2210 			else
2211 				pci_info(pdev, "Unexpected function %d\n",
2212 					 func);
2213 		} else {
2214 			/* on integrated we have to look up by ID (same bus) */
2215 			static const struct pci_device_id bt_device_ids[] = {
2216 #define BT_DEV(_id) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, _id) }
2217 				BT_DEV(0xA876), /* LNL */
2218 				BT_DEV(0xE476), /* PTL-P */
2219 				BT_DEV(0xE376), /* PTL-H */
2220 				BT_DEV(0xD346), /* NVL-H */
2221 				BT_DEV(0x6E74), /* NVL-S */
2222 				BT_DEV(0x4D76), /* WCL */
2223 				BT_DEV(0xD246), /* RZL-H */
2224 				BT_DEV(0x6C46), /* RZL-M */
2225 				{}
2226 			};
2227 			struct pci_dev *tmp = NULL;
2228 
2229 			for_each_pci_dev(tmp) {
2230 				if (tmp->bus != bus)
2231 					continue;
2232 
2233 				if (pci_match_id(bt_device_ids, tmp)) {
2234 					bt = tmp;
2235 					break;
2236 				}
2237 			}
2238 		}
2239 
2240 		if (bt) {
2241 			pci_info(bt, "Removal by WiFi due to product reset\n");
2242 			pci_stop_and_remove_bus_device(bt);
2243 			pci_dev_put(bt);
2244 		}
2245 	}
2246 
2247 	iwl_trans_pcie_set_product_reset(pdev,
2248 					 removal->mode ==
2249 						IWL_RESET_MODE_PROD_RESET,
2250 					 removal->integrated);
2251 	if (removal->mode >= IWL_RESET_MODE_FUNC_RESET)
2252 		iwl_trans_pcie_call_reset(pdev);
2253 
2254 	pci_stop_and_remove_bus_device(pdev);
2255 	pci_dev_put(pdev);
2256 
2257 	if (removal->mode >= IWL_RESET_MODE_RESCAN) {
2258 		if (bus->parent)
2259 			bus = bus->parent;
2260 		pci_rescan_bus(bus);
2261 	}
2262 
2263 out:
2264 	pci_unlock_rescan_remove();
2265 
2266 	kfree(removal);
2267 	module_put(THIS_MODULE);
2268 }
2269 
2270 void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)
2271 {
2272 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2273 	struct iwl_trans_pcie_removal *removal;
2274 	char _msg = 0, *msg = &_msg;
2275 
2276 	if (WARN_ON(mode < IWL_RESET_MODE_REMOVE_ONLY ||
2277 		    mode == IWL_RESET_MODE_BACKOFF))
2278 		return;
2279 
2280 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2281 		return;
2282 
2283 	if (trans_pcie->me_present && mode == IWL_RESET_MODE_PROD_RESET) {
2284 		mode = IWL_RESET_MODE_FUNC_RESET;
2285 		if (trans_pcie->me_present < 0)
2286 			msg = " instead of product reset as ME may be present";
2287 		else
2288 			msg = " instead of product reset as ME is present";
2289 	}
2290 
2291 	IWL_INFO(trans, "scheduling reset (mode=%d%s)\n", mode, msg);
2292 
2293 	iwl_pcie_dump_csr(trans);
2294 
2295 	/*
2296 	 * get a module reference to avoid doing this
2297 	 * while unloading anyway and to avoid
2298 	 * scheduling a work with code that's being
2299 	 * removed.
2300 	 */
2301 	if (!try_module_get(THIS_MODULE)) {
2302 		IWL_ERR(trans,
2303 			"Module is being unloaded - abort\n");
2304 		return;
2305 	}
2306 
2307 	removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2308 	if (!removal) {
2309 		module_put(THIS_MODULE);
2310 		return;
2311 	}
2312 	/*
2313 	 * we don't need to clear this flag, because
2314 	 * the trans will be freed and reallocated.
2315 	 */
2316 	set_bit(STATUS_TRANS_DEAD, &trans->status);
2317 
2318 	removal->pdev = to_pci_dev(trans->dev);
2319 	removal->mode = mode;
2320 	removal->integrated = trans->mac_cfg->integrated;
2321 	INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2322 	pci_dev_get(removal->pdev);
2323 	schedule_work(&removal->work);
2324 }
2325 EXPORT_SYMBOL(iwl_trans_pcie_reset);
2326 
2327 /*
2328  * This version doesn't disable BHs but rather assumes they're
2329  * already disabled.
2330  */
2331 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
2332 {
2333 	int ret;
2334 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2335 	u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;
2336 	u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2337 		   CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;
2338 	u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;
2339 
2340 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2341 		return false;
2342 
2343 	spin_lock(&trans_pcie->reg_lock);
2344 
2345 	if (trans_pcie->cmd_hold_nic_awake)
2346 		goto out;
2347 
2348 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2349 		write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;
2350 		mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2351 		poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2352 	}
2353 
2354 	/* this bit wakes up the NIC */
2355 	iwl_trans_set_bit(trans, CSR_GP_CNTRL, write);
2356 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2357 		udelay(2);
2358 
2359 	/*
2360 	 * These bits say the device is running, and should keep running for
2361 	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2362 	 * but they do not indicate that embedded SRAM is restored yet;
2363 	 * HW with volatile SRAM must save/restore contents to/from
2364 	 * host DRAM when sleeping/waking for power-saving.
2365 	 * Each direction takes approximately 1/4 millisecond; with this
2366 	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2367 	 * series of register accesses are expected (e.g. reading Event Log),
2368 	 * to keep device from sleeping.
2369 	 *
2370 	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2371 	 * SRAM is okay/restored.  We don't check that here because this call
2372 	 * is just for hardware register access; but GP1 MAC_SLEEP
2373 	 * check is a good idea before accessing the SRAM of HW with
2374 	 * volatile SRAM (e.g. reading Event Log).
2375 	 *
2376 	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2377 	 * and do not save/restore SRAM when power cycling.
2378 	 */
2379 	ret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);
2380 	if (unlikely(ret)) {
2381 		u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2382 
2383 		if (silent) {
2384 			spin_unlock(&trans_pcie->reg_lock);
2385 			return false;
2386 		}
2387 
2388 		WARN_ONCE(1,
2389 			  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2390 			  cntrl);
2391 
2392 		iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev);
2393 
2394 		if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U)
2395 			iwl_trans_pcie_reset(trans,
2396 					     IWL_RESET_MODE_REMOVE_ONLY);
2397 		else
2398 			iwl_write32(trans, CSR_RESET,
2399 				    CSR_RESET_REG_FLAG_FORCE_NMI);
2400 
2401 		spin_unlock(&trans_pcie->reg_lock);
2402 		return false;
2403 	}
2404 
2405 out:
2406 	/*
2407 	 * Fool sparse by faking we release the lock - sparse will
2408 	 * track nic_access anyway.
2409 	 */
2410 	__release(&trans_pcie->reg_lock);
2411 	return true;
2412 }
2413 
2414 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2415 {
2416 	bool ret;
2417 
2418 	local_bh_disable();
2419 	ret = __iwl_trans_pcie_grab_nic_access(trans, false);
2420 	if (ret) {
2421 		/* keep BHs disabled until iwl_trans_pcie_release_nic_access */
2422 		return ret;
2423 	}
2424 	local_bh_enable();
2425 	return false;
2426 }
2427 
2428 void __releases(nic_access_nobh)
2429 iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
2430 {
2431 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2432 
2433 	lockdep_assert_held(&trans_pcie->reg_lock);
2434 
2435 	/*
2436 	 * Fool sparse by faking we acquiring the lock - sparse will
2437 	 * track nic_access anyway.
2438 	 */
2439 	__acquire(&trans_pcie->reg_lock);
2440 
2441 	if (trans_pcie->cmd_hold_nic_awake)
2442 		goto out;
2443 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2444 		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
2445 				    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
2446 	else
2447 		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
2448 				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2449 	/*
2450 	 * Above we read the CSR_GP_CNTRL register, which will flush
2451 	 * any previous writes, but we need the write that clears the
2452 	 * MAC_ACCESS_REQ bit to be performed before any other writes
2453 	 * scheduled on different CPUs (after we drop reg_lock).
2454 	 */
2455 out:
2456 	__release(nic_access_nobh);
2457 	spin_unlock_bh(&trans_pcie->reg_lock);
2458 }
2459 
2460 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2461 			    void *buf, int dwords)
2462 {
2463 #define IWL_MAX_HW_ERRS 5
2464 	unsigned int num_consec_hw_errors = 0;
2465 	int offs = 0;
2466 	u32 *vals = buf;
2467 
2468 	while (offs < dwords) {
2469 		/* limit the time we spin here under lock to 1/2s */
2470 		unsigned long end = jiffies + HZ / 2;
2471 		bool resched = false;
2472 
2473 		if (iwl_trans_grab_nic_access(trans)) {
2474 			iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2475 				    addr + 4 * offs);
2476 
2477 			while (offs < dwords) {
2478 				vals[offs] = iwl_read32(trans,
2479 							HBUS_TARG_MEM_RDAT);
2480 
2481 				if (iwl_trans_is_hw_error_value(vals[offs]))
2482 					num_consec_hw_errors++;
2483 				else
2484 					num_consec_hw_errors = 0;
2485 
2486 				if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) {
2487 					iwl_trans_release_nic_access(trans);
2488 					return -EIO;
2489 				}
2490 
2491 				offs++;
2492 
2493 				if (time_after(jiffies, end)) {
2494 					resched = true;
2495 					break;
2496 				}
2497 			}
2498 			iwl_trans_release_nic_access(trans);
2499 
2500 			if (resched)
2501 				cond_resched();
2502 		} else {
2503 			return -EBUSY;
2504 		}
2505 	}
2506 
2507 	return 0;
2508 }
2509 
2510 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2511 				 u32 *val)
2512 {
2513 	return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2514 				     ofs, val);
2515 }
2516 
2517 #define IWL_FLUSH_WAIT_MS	2000
2518 
2519 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2520 				struct iwl_trans_rxq_dma_data *data)
2521 {
2522 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2523 
2524 	if (queue >= trans->info.num_rxqs || !trans_pcie->rxq)
2525 		return -EINVAL;
2526 
2527 	data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2528 	data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2529 	data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2530 	data->fr_bd_wid = 0;
2531 
2532 	return 0;
2533 }
2534 
2535 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2536 {
2537 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2538 	struct iwl_txq *txq;
2539 	unsigned long now = jiffies;
2540 	bool overflow_tx;
2541 	u8 wr_ptr;
2542 
2543 	/* Make sure the NIC is still alive in the bus */
2544 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2545 		return -ENODEV;
2546 
2547 	if (!test_bit(txq_idx, trans_pcie->txqs.queue_used))
2548 		return -EINVAL;
2549 
2550 	IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2551 	txq = trans_pcie->txqs.txq[txq_idx];
2552 
2553 	spin_lock_bh(&txq->lock);
2554 	overflow_tx = txq->overflow_tx ||
2555 		      !skb_queue_empty(&txq->overflow_q);
2556 	spin_unlock_bh(&txq->lock);
2557 
2558 	wr_ptr = READ_ONCE(txq->write_ptr);
2559 
2560 	while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2561 		overflow_tx) &&
2562 	       !time_after(jiffies,
2563 			   now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2564 		u8 write_ptr = READ_ONCE(txq->write_ptr);
2565 
2566 		/*
2567 		 * If write pointer moved during the wait, warn only
2568 		 * if the TX came from op mode. In case TX came from
2569 		 * trans layer (overflow TX) don't warn.
2570 		 */
2571 		if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2572 			      "WR pointer moved while flushing %d -> %d\n",
2573 			      wr_ptr, write_ptr))
2574 			return -ETIMEDOUT;
2575 		wr_ptr = write_ptr;
2576 
2577 		usleep_range(1000, 2000);
2578 
2579 		spin_lock_bh(&txq->lock);
2580 		overflow_tx = txq->overflow_tx ||
2581 			      !skb_queue_empty(&txq->overflow_q);
2582 		spin_unlock_bh(&txq->lock);
2583 	}
2584 
2585 	if (txq->read_ptr != txq->write_ptr) {
2586 		IWL_ERR(trans,
2587 			"fail to flush all tx fifo queues Q %d\n", txq_idx);
2588 		iwl_txq_log_scd_error(trans, txq);
2589 		return -ETIMEDOUT;
2590 	}
2591 
2592 	IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2593 
2594 	return 0;
2595 }
2596 
2597 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2598 {
2599 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2600 	int cnt;
2601 	int ret = 0;
2602 
2603 	/* waiting for all the tx frames complete might take a while */
2604 	for (cnt = 0;
2605 	     cnt < trans->mac_cfg->base->num_of_queues;
2606 	     cnt++) {
2607 
2608 		if (cnt == trans->conf.cmd_queue)
2609 			continue;
2610 		if (!test_bit(cnt, trans_pcie->txqs.queue_used))
2611 			continue;
2612 		if (!(BIT(cnt) & txq_bm))
2613 			continue;
2614 
2615 		ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2616 		if (ret)
2617 			break;
2618 	}
2619 
2620 	return ret;
2621 }
2622 
2623 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2624 				  u32 mask, u32 value)
2625 {
2626 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2627 
2628 	spin_lock_bh(&trans_pcie->reg_lock);
2629 	_iwl_trans_set_bits_mask(trans, reg, mask, value);
2630 	spin_unlock_bh(&trans_pcie->reg_lock);
2631 }
2632 
2633 static const char *get_csr_string(int cmd)
2634 {
2635 #define IWL_CMD(x) case x: return #x
2636 	switch (cmd) {
2637 	IWL_CMD(CSR_HW_IF_CONFIG_REG);
2638 	IWL_CMD(CSR_INT_COALESCING);
2639 	IWL_CMD(CSR_INT);
2640 	IWL_CMD(CSR_INT_MASK);
2641 	IWL_CMD(CSR_FH_INT_STATUS);
2642 	IWL_CMD(CSR_GPIO_IN);
2643 	IWL_CMD(CSR_RESET);
2644 	IWL_CMD(CSR_GP_CNTRL);
2645 	IWL_CMD(CSR_HW_REV);
2646 	IWL_CMD(CSR_EEPROM_REG);
2647 	IWL_CMD(CSR_EEPROM_GP);
2648 	IWL_CMD(CSR_OTP_GP_REG);
2649 	IWL_CMD(CSR_GIO_REG);
2650 	IWL_CMD(CSR_GP_UCODE_REG);
2651 	IWL_CMD(CSR_GP_DRIVER_REG);
2652 	IWL_CMD(CSR_UCODE_DRV_GP1);
2653 	IWL_CMD(CSR_UCODE_DRV_GP2);
2654 	IWL_CMD(CSR_LED_REG);
2655 	IWL_CMD(CSR_DRAM_INT_TBL_REG);
2656 	IWL_CMD(CSR_GIO_CHICKEN_BITS);
2657 	IWL_CMD(CSR_ANA_PLL_CFG);
2658 	IWL_CMD(CSR_HW_REV_WA_REG);
2659 	IWL_CMD(CSR_MONITOR_STATUS_REG);
2660 	IWL_CMD(CSR_DBG_HPET_MEM_REG);
2661 	default:
2662 		return "UNKNOWN";
2663 	}
2664 #undef IWL_CMD
2665 }
2666 
2667 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2668 {
2669 	int i;
2670 	static const u32 csr_tbl[] = {
2671 		CSR_HW_IF_CONFIG_REG,
2672 		CSR_INT_COALESCING,
2673 		CSR_INT,
2674 		CSR_INT_MASK,
2675 		CSR_FH_INT_STATUS,
2676 		CSR_GPIO_IN,
2677 		CSR_RESET,
2678 		CSR_GP_CNTRL,
2679 		CSR_HW_REV,
2680 		CSR_EEPROM_REG,
2681 		CSR_EEPROM_GP,
2682 		CSR_OTP_GP_REG,
2683 		CSR_GIO_REG,
2684 		CSR_GP_UCODE_REG,
2685 		CSR_GP_DRIVER_REG,
2686 		CSR_UCODE_DRV_GP1,
2687 		CSR_UCODE_DRV_GP2,
2688 		CSR_LED_REG,
2689 		CSR_DRAM_INT_TBL_REG,
2690 		CSR_GIO_CHICKEN_BITS,
2691 		CSR_ANA_PLL_CFG,
2692 		CSR_MONITOR_STATUS_REG,
2693 		CSR_HW_REV_WA_REG,
2694 		CSR_DBG_HPET_MEM_REG
2695 	};
2696 	IWL_ERR(trans, "CSR values:\n");
2697 	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2698 		"CSR_INT_PERIODIC_REG)\n");
2699 	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2700 		IWL_ERR(trans, "  %25s: 0X%08x\n",
2701 			get_csr_string(csr_tbl[i]),
2702 			iwl_read32(trans, csr_tbl[i]));
2703 	}
2704 }
2705 
2706 #ifdef CONFIG_IWLWIFI_DEBUGFS
2707 /* create and remove of files */
2708 #define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
2709 	debugfs_create_file(#name, mode, parent, trans,			\
2710 			    &iwl_dbgfs_##name##_ops);			\
2711 } while (0)
2712 
2713 /* file operation */
2714 #define DEBUGFS_READ_FILE_OPS(name)					\
2715 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2716 	.read = iwl_dbgfs_##name##_read,				\
2717 	.open = simple_open,						\
2718 	.llseek = generic_file_llseek,					\
2719 };
2720 
2721 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2722 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2723 	.write = iwl_dbgfs_##name##_write,                              \
2724 	.open = simple_open,						\
2725 	.llseek = generic_file_llseek,					\
2726 };
2727 
2728 #define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
2729 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2730 	.write = iwl_dbgfs_##name##_write,				\
2731 	.read = iwl_dbgfs_##name##_read,				\
2732 	.open = simple_open,						\
2733 	.llseek = generic_file_llseek,					\
2734 };
2735 
2736 struct iwl_dbgfs_tx_queue_priv {
2737 	struct iwl_trans *trans;
2738 };
2739 
2740 struct iwl_dbgfs_tx_queue_state {
2741 	loff_t pos;
2742 };
2743 
2744 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2745 {
2746 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2747 	struct iwl_dbgfs_tx_queue_state *state;
2748 
2749 	if (*pos >= priv->trans->mac_cfg->base->num_of_queues)
2750 		return NULL;
2751 
2752 	state = kmalloc(sizeof(*state), GFP_KERNEL);
2753 	if (!state)
2754 		return NULL;
2755 	state->pos = *pos;
2756 	return state;
2757 }
2758 
2759 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2760 					 void *v, loff_t *pos)
2761 {
2762 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2763 	struct iwl_dbgfs_tx_queue_state *state = v;
2764 
2765 	*pos = ++state->pos;
2766 
2767 	if (*pos >= priv->trans->mac_cfg->base->num_of_queues)
2768 		return NULL;
2769 
2770 	return state;
2771 }
2772 
2773 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2774 {
2775 	kfree(v);
2776 }
2777 
2778 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2779 {
2780 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2781 	struct iwl_dbgfs_tx_queue_state *state = v;
2782 	struct iwl_trans *trans = priv->trans;
2783 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2784 	struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos];
2785 
2786 	seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2787 		   (unsigned int)state->pos,
2788 		   !!test_bit(state->pos, trans_pcie->txqs.queue_used),
2789 		   !!test_bit(state->pos, trans_pcie->txqs.queue_stopped));
2790 	if (txq)
2791 		seq_printf(seq,
2792 			   "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2793 			   txq->read_ptr, txq->write_ptr,
2794 			   txq->need_update, txq->frozen,
2795 			   txq->n_window, txq->ampdu);
2796 	else
2797 		seq_puts(seq, "(unallocated)");
2798 
2799 	if (state->pos == trans->conf.cmd_queue)
2800 		seq_puts(seq, " (HCMD)");
2801 	seq_puts(seq, "\n");
2802 
2803 	return 0;
2804 }
2805 
2806 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2807 	.start = iwl_dbgfs_tx_queue_seq_start,
2808 	.next = iwl_dbgfs_tx_queue_seq_next,
2809 	.stop = iwl_dbgfs_tx_queue_seq_stop,
2810 	.show = iwl_dbgfs_tx_queue_seq_show,
2811 };
2812 
2813 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2814 {
2815 	struct iwl_dbgfs_tx_queue_priv *priv;
2816 
2817 	priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2818 				  sizeof(*priv));
2819 
2820 	if (!priv)
2821 		return -ENOMEM;
2822 
2823 	priv->trans = inode->i_private;
2824 	return 0;
2825 }
2826 
2827 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2828 				       char __user *user_buf,
2829 				       size_t count, loff_t *ppos)
2830 {
2831 	struct iwl_trans *trans = file->private_data;
2832 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2833 	char *buf;
2834 	int pos = 0, i, ret;
2835 	size_t bufsz;
2836 
2837 	bufsz = sizeof(char) * 121 * trans->info.num_rxqs;
2838 
2839 	if (!trans_pcie->rxq)
2840 		return -EAGAIN;
2841 
2842 	buf = kzalloc(bufsz, GFP_KERNEL);
2843 	if (!buf)
2844 		return -ENOMEM;
2845 
2846 	for (i = 0; i < trans->info.num_rxqs && pos < bufsz; i++) {
2847 		struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2848 
2849 		spin_lock_bh(&rxq->lock);
2850 
2851 		pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2852 				 i);
2853 		pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2854 				 rxq->read);
2855 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2856 				 rxq->write);
2857 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2858 				 rxq->write_actual);
2859 		pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2860 				 rxq->need_update);
2861 		pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2862 				 rxq->free_count);
2863 		if (rxq->rb_stts) {
2864 			u32 r =	iwl_get_closed_rb_stts(trans, rxq);
2865 			pos += scnprintf(buf + pos, bufsz - pos,
2866 					 "\tclosed_rb_num: %u\n", r);
2867 		} else {
2868 			pos += scnprintf(buf + pos, bufsz - pos,
2869 					 "\tclosed_rb_num: Not Allocated\n");
2870 		}
2871 		spin_unlock_bh(&rxq->lock);
2872 	}
2873 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2874 	kfree(buf);
2875 
2876 	return ret;
2877 }
2878 
2879 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2880 					char __user *user_buf,
2881 					size_t count, loff_t *ppos)
2882 {
2883 	struct iwl_trans *trans = file->private_data;
2884 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2885 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2886 
2887 	int pos = 0;
2888 	char *buf;
2889 	int bufsz = 24 * 64; /* 24 items * 64 char per item */
2890 	ssize_t ret;
2891 
2892 	buf = kzalloc(bufsz, GFP_KERNEL);
2893 	if (!buf)
2894 		return -ENOMEM;
2895 
2896 	pos += scnprintf(buf + pos, bufsz - pos,
2897 			"Interrupt Statistics Report:\n");
2898 
2899 	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2900 		isr_stats->hw);
2901 	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2902 		isr_stats->sw);
2903 	if (isr_stats->sw || isr_stats->hw) {
2904 		pos += scnprintf(buf + pos, bufsz - pos,
2905 			"\tLast Restarting Code:  0x%X\n",
2906 			isr_stats->err_code);
2907 	}
2908 #ifdef CONFIG_IWLWIFI_DEBUG
2909 	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2910 		isr_stats->sch);
2911 	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2912 		isr_stats->alive);
2913 #endif
2914 	pos += scnprintf(buf + pos, bufsz - pos,
2915 		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2916 
2917 	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2918 		isr_stats->ctkill);
2919 
2920 	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2921 		isr_stats->wakeup);
2922 
2923 	pos += scnprintf(buf + pos, bufsz - pos,
2924 		"Rx command responses:\t\t %u\n", isr_stats->rx);
2925 
2926 	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2927 		isr_stats->tx);
2928 
2929 	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2930 		isr_stats->unhandled);
2931 
2932 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2933 	kfree(buf);
2934 	return ret;
2935 }
2936 
2937 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2938 					 const char __user *user_buf,
2939 					 size_t count, loff_t *ppos)
2940 {
2941 	struct iwl_trans *trans = file->private_data;
2942 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2943 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2944 	u32 reset_flag;
2945 	int ret;
2946 
2947 	ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2948 	if (ret)
2949 		return ret;
2950 	if (reset_flag == 0)
2951 		memset(isr_stats, 0, sizeof(*isr_stats));
2952 
2953 	return count;
2954 }
2955 
2956 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2957 				   const char __user *user_buf,
2958 				   size_t count, loff_t *ppos)
2959 {
2960 	struct iwl_trans *trans = file->private_data;
2961 
2962 	iwl_pcie_dump_csr(trans);
2963 
2964 	return count;
2965 }
2966 
2967 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2968 				     char __user *user_buf,
2969 				     size_t count, loff_t *ppos)
2970 {
2971 	struct iwl_trans *trans = file->private_data;
2972 	char *buf = NULL;
2973 	ssize_t ret;
2974 
2975 	ret = iwl_dump_fh(trans, &buf);
2976 	if (ret < 0)
2977 		return ret;
2978 	if (!buf)
2979 		return -EINVAL;
2980 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2981 	kfree(buf);
2982 	return ret;
2983 }
2984 
2985 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2986 				     char __user *user_buf,
2987 				     size_t count, loff_t *ppos)
2988 {
2989 	struct iwl_trans *trans = file->private_data;
2990 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2991 	char buf[100];
2992 	int pos;
2993 
2994 	pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2995 			trans_pcie->debug_rfkill,
2996 			!(iwl_read32(trans, CSR_GP_CNTRL) &
2997 				CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2998 
2999 	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
3000 }
3001 
3002 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
3003 				      const char __user *user_buf,
3004 				      size_t count, loff_t *ppos)
3005 {
3006 	struct iwl_trans *trans = file->private_data;
3007 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3008 	bool new_value;
3009 	int ret;
3010 
3011 	ret = kstrtobool_from_user(user_buf, count, &new_value);
3012 	if (ret)
3013 		return ret;
3014 	if (new_value == trans_pcie->debug_rfkill)
3015 		return count;
3016 	IWL_WARN(trans, "changing debug rfkill %d->%d\n",
3017 		 trans_pcie->debug_rfkill, new_value);
3018 	trans_pcie->debug_rfkill = new_value;
3019 	iwl_pcie_handle_rfkill_irq(trans, false);
3020 
3021 	return count;
3022 }
3023 
3024 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
3025 				       struct file *file)
3026 {
3027 	struct iwl_trans *trans = inode->i_private;
3028 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3029 
3030 	if (!trans->dbg.dest_tlv ||
3031 	    trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
3032 		IWL_ERR(trans, "Debug destination is not set to DRAM\n");
3033 		return -ENOENT;
3034 	}
3035 
3036 	if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
3037 		return -EBUSY;
3038 
3039 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
3040 	return simple_open(inode, file);
3041 }
3042 
3043 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
3044 					  struct file *file)
3045 {
3046 	struct iwl_trans_pcie *trans_pcie =
3047 		IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
3048 
3049 	if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
3050 		trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3051 	return 0;
3052 }
3053 
3054 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
3055 				  void *buf, ssize_t *size,
3056 				  ssize_t *bytes_copied)
3057 {
3058 	ssize_t buf_size_left = count - *bytes_copied;
3059 
3060 	buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
3061 	if (*size > buf_size_left)
3062 		*size = buf_size_left;
3063 
3064 	*size -= copy_to_user(user_buf, buf, *size);
3065 	*bytes_copied += *size;
3066 
3067 	if (buf_size_left == *size)
3068 		return true;
3069 	return false;
3070 }
3071 
3072 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
3073 					   char __user *user_buf,
3074 					   size_t count, loff_t *ppos)
3075 {
3076 	struct iwl_trans *trans = file->private_data;
3077 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3078 	u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
3079 	struct cont_rec *data = &trans_pcie->fw_mon_data;
3080 	u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
3081 	ssize_t size, bytes_copied = 0;
3082 	bool b_full;
3083 
3084 	if (trans->dbg.dest_tlv) {
3085 		write_ptr_addr =
3086 			le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3087 		wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3088 	} else {
3089 		write_ptr_addr = MON_BUFF_WRPTR;
3090 		wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
3091 	}
3092 
3093 	if (unlikely(!trans->dbg.rec_on))
3094 		return 0;
3095 
3096 	mutex_lock(&data->mutex);
3097 	if (data->state ==
3098 	    IWL_FW_MON_DBGFS_STATE_DISABLED) {
3099 		mutex_unlock(&data->mutex);
3100 		return 0;
3101 	}
3102 
3103 	/* write_ptr position in bytes rather then DW */
3104 	write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
3105 	wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
3106 
3107 	if (data->prev_wrap_cnt == wrap_cnt) {
3108 		size = write_ptr - data->prev_wr_ptr;
3109 		curr_buf = cpu_addr + data->prev_wr_ptr;
3110 		b_full = iwl_write_to_user_buf(user_buf, count,
3111 					       curr_buf, &size,
3112 					       &bytes_copied);
3113 		data->prev_wr_ptr += size;
3114 
3115 	} else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
3116 		   write_ptr < data->prev_wr_ptr) {
3117 		size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
3118 		curr_buf = cpu_addr + data->prev_wr_ptr;
3119 		b_full = iwl_write_to_user_buf(user_buf, count,
3120 					       curr_buf, &size,
3121 					       &bytes_copied);
3122 		data->prev_wr_ptr += size;
3123 
3124 		if (!b_full) {
3125 			size = write_ptr;
3126 			b_full = iwl_write_to_user_buf(user_buf, count,
3127 						       cpu_addr, &size,
3128 						       &bytes_copied);
3129 			data->prev_wr_ptr = size;
3130 			data->prev_wrap_cnt++;
3131 		}
3132 	} else {
3133 		if (data->prev_wrap_cnt == wrap_cnt - 1 &&
3134 		    write_ptr > data->prev_wr_ptr)
3135 			IWL_WARN(trans,
3136 				 "write pointer passed previous write pointer, start copying from the beginning\n");
3137 		else if (!unlikely(data->prev_wrap_cnt == 0 &&
3138 				   data->prev_wr_ptr == 0))
3139 			IWL_WARN(trans,
3140 				 "monitor data is out of sync, start copying from the beginning\n");
3141 
3142 		size = write_ptr;
3143 		b_full = iwl_write_to_user_buf(user_buf, count,
3144 					       cpu_addr, &size,
3145 					       &bytes_copied);
3146 		data->prev_wr_ptr = size;
3147 		data->prev_wrap_cnt = wrap_cnt;
3148 	}
3149 
3150 	mutex_unlock(&data->mutex);
3151 
3152 	return bytes_copied;
3153 }
3154 
3155 static ssize_t iwl_dbgfs_rf_read(struct file *file,
3156 				 char __user *user_buf,
3157 				 size_t count, loff_t *ppos)
3158 {
3159 	struct iwl_trans *trans = file->private_data;
3160 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3161 
3162 	if (!trans_pcie->rf_name[0])
3163 		return -ENODEV;
3164 
3165 	return simple_read_from_buffer(user_buf, count, ppos,
3166 				       trans_pcie->rf_name,
3167 				       strlen(trans_pcie->rf_name));
3168 }
3169 
3170 static ssize_t iwl_dbgfs_reset_write(struct file *file,
3171 				     const char __user *user_buf,
3172 				     size_t count, loff_t *ppos)
3173 {
3174 	struct iwl_trans *trans = file->private_data;
3175 	static const char * const modes[] = {
3176 		[IWL_RESET_MODE_SW_RESET] = "sw",
3177 		[IWL_RESET_MODE_REPROBE] = "reprobe",
3178 		[IWL_RESET_MODE_TOP_RESET] = "top",
3179 		[IWL_RESET_MODE_REMOVE_ONLY] = "remove",
3180 		[IWL_RESET_MODE_RESCAN] = "rescan",
3181 		[IWL_RESET_MODE_FUNC_RESET] = "function",
3182 		[IWL_RESET_MODE_PROD_RESET] = "product",
3183 	};
3184 	char buf[10] = {};
3185 	int mode;
3186 
3187 	if (count > sizeof(buf) - 1)
3188 		return -EINVAL;
3189 
3190 	if (copy_from_user(buf, user_buf, count))
3191 		return -EFAULT;
3192 
3193 	mode = sysfs_match_string(modes, buf);
3194 	if (mode < 0)
3195 		return mode;
3196 
3197 	if (mode < IWL_RESET_MODE_REMOVE_ONLY) {
3198 		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
3199 			return -EINVAL;
3200 		if (mode == IWL_RESET_MODE_TOP_RESET) {
3201 			if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_SC)
3202 				return -EINVAL;
3203 			trans->request_top_reset = 1;
3204 		}
3205 		iwl_op_mode_nic_error(trans->op_mode, IWL_ERR_TYPE_DEBUGFS);
3206 		iwl_trans_schedule_reset(trans, IWL_ERR_TYPE_DEBUGFS);
3207 		return count;
3208 	}
3209 
3210 	iwl_trans_pcie_reset(trans, mode);
3211 
3212 	return count;
3213 }
3214 
3215 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
3216 DEBUGFS_READ_FILE_OPS(fh_reg);
3217 DEBUGFS_READ_FILE_OPS(rx_queue);
3218 DEBUGFS_WRITE_FILE_OPS(csr);
3219 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
3220 DEBUGFS_READ_FILE_OPS(rf);
3221 DEBUGFS_WRITE_FILE_OPS(reset);
3222 
3223 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
3224 	.owner = THIS_MODULE,
3225 	.open = iwl_dbgfs_tx_queue_open,
3226 	.read = seq_read,
3227 	.llseek = seq_lseek,
3228 	.release = seq_release_private,
3229 };
3230 
3231 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
3232 	.read = iwl_dbgfs_monitor_data_read,
3233 	.open = iwl_dbgfs_monitor_data_open,
3234 	.release = iwl_dbgfs_monitor_data_release,
3235 };
3236 
3237 /* Create the debugfs files and directories */
3238 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
3239 {
3240 	struct dentry *dir = trans->dbgfs_dir;
3241 
3242 	DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
3243 	DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
3244 	DEBUGFS_ADD_FILE(interrupt, dir, 0600);
3245 	DEBUGFS_ADD_FILE(csr, dir, 0200);
3246 	DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
3247 	DEBUGFS_ADD_FILE(rfkill, dir, 0600);
3248 	DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
3249 	DEBUGFS_ADD_FILE(rf, dir, 0400);
3250 	DEBUGFS_ADD_FILE(reset, dir, 0200);
3251 }
3252 
3253 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
3254 {
3255 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3256 	struct cont_rec *data = &trans_pcie->fw_mon_data;
3257 
3258 	mutex_lock(&data->mutex);
3259 	data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
3260 	mutex_unlock(&data->mutex);
3261 }
3262 #endif /*CONFIG_IWLWIFI_DEBUGFS */
3263 
3264 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
3265 {
3266 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3267 	u32 cmdlen = 0;
3268 	int i;
3269 
3270 	for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++)
3271 		cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
3272 
3273 	return cmdlen;
3274 }
3275 
3276 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3277 				   struct iwl_fw_error_dump_data **data,
3278 				   int allocated_rb_nums)
3279 {
3280 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3281 	int max_len = trans_pcie->rx_buf_bytes;
3282 	/* Dump RBs is supported only for pre-9000 devices (1 queue) */
3283 	struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3284 	u32 i, r, j, rb_len = 0;
3285 
3286 	spin_lock_bh(&rxq->lock);
3287 
3288 	r = iwl_get_closed_rb_stts(trans, rxq);
3289 
3290 	for (i = rxq->read, j = 0;
3291 	     i != r && j < allocated_rb_nums;
3292 	     i = (i + 1) & RX_QUEUE_MASK, j++) {
3293 		struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3294 		struct iwl_fw_error_dump_rb *rb;
3295 
3296 		dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
3297 					max_len, DMA_FROM_DEVICE);
3298 
3299 		rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3300 
3301 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3302 		(*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3303 		rb = (void *)(*data)->data;
3304 		rb->index = cpu_to_le32(i);
3305 		memcpy(rb->data, page_address(rxb->page), max_len);
3306 
3307 		*data = iwl_fw_error_next_data(*data);
3308 	}
3309 
3310 	spin_unlock_bh(&rxq->lock);
3311 
3312 	return rb_len;
3313 }
3314 #define IWL_CSR_TO_DUMP (0x250)
3315 
3316 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3317 				   struct iwl_fw_error_dump_data **data)
3318 {
3319 	u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3320 	__le32 *val;
3321 	int i;
3322 
3323 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3324 	(*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3325 	val = (void *)(*data)->data;
3326 
3327 	for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3328 		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3329 
3330 	*data = iwl_fw_error_next_data(*data);
3331 
3332 	return csr_len;
3333 }
3334 
3335 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3336 				       struct iwl_fw_error_dump_data **data)
3337 {
3338 	u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3339 	__le32 *val;
3340 	int i;
3341 
3342 	if (!iwl_trans_grab_nic_access(trans))
3343 		return 0;
3344 
3345 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3346 	(*data)->len = cpu_to_le32(fh_regs_len);
3347 	val = (void *)(*data)->data;
3348 
3349 	if (!trans->mac_cfg->gen2)
3350 		for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3351 		     i += sizeof(u32))
3352 			*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3353 	else
3354 		for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3355 		     i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3356 		     i += sizeof(u32))
3357 			*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3358 								      i));
3359 
3360 	iwl_trans_release_nic_access(trans);
3361 
3362 	*data = iwl_fw_error_next_data(*data);
3363 
3364 	return sizeof(**data) + fh_regs_len;
3365 }
3366 
3367 static u32
3368 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3369 				 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3370 				 u32 monitor_len)
3371 {
3372 	u32 buf_size_in_dwords = (monitor_len >> 2);
3373 	u32 *buffer = (u32 *)fw_mon_data->data;
3374 	u32 i;
3375 
3376 	if (!iwl_trans_grab_nic_access(trans))
3377 		return 0;
3378 
3379 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3380 	for (i = 0; i < buf_size_in_dwords; i++)
3381 		buffer[i] = iwl_read_umac_prph_no_grab(trans,
3382 						       MON_DMARB_RD_DATA_ADDR);
3383 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3384 
3385 	iwl_trans_release_nic_access(trans);
3386 
3387 	return monitor_len;
3388 }
3389 
3390 static void
3391 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3392 			     struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3393 {
3394 	u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3395 
3396 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3397 		base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3398 		base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3399 		write_ptr = DBGC_CUR_DBGBUF_STATUS;
3400 		wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3401 	} else if (trans->dbg.dest_tlv) {
3402 		write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3403 		wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3404 		base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3405 	} else {
3406 		base = MON_BUFF_BASE_ADDR;
3407 		write_ptr = MON_BUFF_WRPTR;
3408 		wrap_cnt = MON_BUFF_CYCLE_CNT;
3409 	}
3410 
3411 	write_ptr_val = iwl_read_prph(trans, write_ptr);
3412 	fw_mon_data->fw_mon_cycle_cnt =
3413 		cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3414 	fw_mon_data->fw_mon_base_ptr =
3415 		cpu_to_le32(iwl_read_prph(trans, base));
3416 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3417 		fw_mon_data->fw_mon_base_high_ptr =
3418 			cpu_to_le32(iwl_read_prph(trans, base_high));
3419 		write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3420 		/* convert wrtPtr to DWs, to align with all HWs */
3421 		write_ptr_val >>= 2;
3422 	}
3423 	fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3424 }
3425 
3426 static u32
3427 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3428 			    struct iwl_fw_error_dump_data **data,
3429 			    u32 monitor_len)
3430 {
3431 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3432 	u32 len = 0;
3433 
3434 	if (trans->dbg.dest_tlv ||
3435 	    (fw_mon->size &&
3436 	     (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3437 	      trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3438 		struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3439 
3440 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3441 		fw_mon_data = (void *)(*data)->data;
3442 
3443 		iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3444 
3445 		len += sizeof(**data) + sizeof(*fw_mon_data);
3446 		if (fw_mon->size) {
3447 			memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3448 			monitor_len = fw_mon->size;
3449 		} else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3450 			u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3451 			/*
3452 			 * Update pointers to reflect actual values after
3453 			 * shifting
3454 			 */
3455 			if (trans->dbg.dest_tlv->version) {
3456 				base = (iwl_read_prph(trans, base) &
3457 					IWL_LDBG_M2S_BUF_BA_MSK) <<
3458 				       trans->dbg.dest_tlv->base_shift;
3459 				base *= IWL_M2S_UNIT_SIZE;
3460 				base += trans->mac_cfg->base->smem_offset;
3461 			} else {
3462 				base = iwl_read_prph(trans, base) <<
3463 				       trans->dbg.dest_tlv->base_shift;
3464 			}
3465 
3466 			iwl_trans_pcie_read_mem(trans, base, fw_mon_data->data,
3467 						monitor_len / sizeof(u32));
3468 		} else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3469 			monitor_len =
3470 				iwl_trans_pci_dump_marbh_monitor(trans,
3471 								 fw_mon_data,
3472 								 monitor_len);
3473 		} else {
3474 			/* Didn't match anything - output no monitor data */
3475 			monitor_len = 0;
3476 		}
3477 
3478 		len += monitor_len;
3479 		(*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3480 	}
3481 
3482 	return len;
3483 }
3484 
3485 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3486 {
3487 	if (trans->dbg.fw_mon.size) {
3488 		*len += sizeof(struct iwl_fw_error_dump_data) +
3489 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3490 			trans->dbg.fw_mon.size;
3491 		return trans->dbg.fw_mon.size;
3492 	} else if (trans->dbg.dest_tlv) {
3493 		u32 base, end, cfg_reg, monitor_len;
3494 
3495 		if (trans->dbg.dest_tlv->version == 1) {
3496 			cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3497 			cfg_reg = iwl_read_prph(trans, cfg_reg);
3498 			base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3499 				trans->dbg.dest_tlv->base_shift;
3500 			base *= IWL_M2S_UNIT_SIZE;
3501 			base += trans->mac_cfg->base->smem_offset;
3502 
3503 			monitor_len =
3504 				(cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3505 				trans->dbg.dest_tlv->end_shift;
3506 			monitor_len *= IWL_M2S_UNIT_SIZE;
3507 		} else {
3508 			base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3509 			end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3510 
3511 			base = iwl_read_prph(trans, base) <<
3512 			       trans->dbg.dest_tlv->base_shift;
3513 			end = iwl_read_prph(trans, end) <<
3514 			      trans->dbg.dest_tlv->end_shift;
3515 
3516 			/* Make "end" point to the actual end */
3517 			if (trans->mac_cfg->device_family >=
3518 			    IWL_DEVICE_FAMILY_8000 ||
3519 			    trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3520 				end += (1 << trans->dbg.dest_tlv->end_shift);
3521 			monitor_len = end - base;
3522 		}
3523 		*len += sizeof(struct iwl_fw_error_dump_data) +
3524 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3525 			monitor_len;
3526 		return monitor_len;
3527 	}
3528 	return 0;
3529 }
3530 
3531 struct iwl_trans_dump_data *
3532 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,
3533 			 const struct iwl_dump_sanitize_ops *sanitize_ops,
3534 			 void *sanitize_ctx)
3535 {
3536 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3537 	struct iwl_fw_error_dump_data *data;
3538 	struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans->conf.cmd_queue];
3539 	struct iwl_fw_error_dump_txcmd *txcmd;
3540 	struct iwl_trans_dump_data *dump_data;
3541 	u32 len, num_rbs = 0, monitor_len = 0;
3542 	int i, ptr;
3543 	bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3544 			!trans->mac_cfg->mq_rx_supported &&
3545 			dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3546 
3547 	if (!dump_mask)
3548 		return NULL;
3549 
3550 	/* transport dump header */
3551 	len = sizeof(*dump_data);
3552 
3553 	/* host commands */
3554 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3555 		len += sizeof(*data) +
3556 			cmdq->n_window * (sizeof(*txcmd) +
3557 					  TFD_MAX_PAYLOAD_SIZE);
3558 
3559 	/* FW monitor */
3560 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3561 		monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3562 
3563 	/* CSR registers */
3564 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3565 		len += sizeof(*data) + IWL_CSR_TO_DUMP;
3566 
3567 	/* FH registers */
3568 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3569 		if (trans->mac_cfg->gen2)
3570 			len += sizeof(*data) +
3571 			       (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3572 				iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3573 		else
3574 			len += sizeof(*data) +
3575 			       (FH_MEM_UPPER_BOUND -
3576 				FH_MEM_LOWER_BOUND);
3577 	}
3578 
3579 	if (dump_rbs) {
3580 		/* Dump RBs is supported only for pre-9000 devices (1 queue) */
3581 		struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3582 		/* RBs */
3583 		spin_lock_bh(&rxq->lock);
3584 		num_rbs = iwl_get_closed_rb_stts(trans, rxq);
3585 		num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3586 		spin_unlock_bh(&rxq->lock);
3587 
3588 		len += num_rbs * (sizeof(*data) +
3589 				  sizeof(struct iwl_fw_error_dump_rb) +
3590 				  (PAGE_SIZE << trans_pcie->rx_page_order));
3591 	}
3592 
3593 	/* Paged memory for gen2 HW */
3594 	if (trans->mac_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3595 		for (i = 0; i < trans->init_dram.paging_cnt; i++)
3596 			len += sizeof(*data) +
3597 			       sizeof(struct iwl_fw_error_dump_paging) +
3598 			       trans->init_dram.paging[i].size;
3599 
3600 	dump_data = vzalloc(len);
3601 	if (!dump_data)
3602 		return NULL;
3603 
3604 	len = 0;
3605 	data = (void *)dump_data->data;
3606 
3607 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3608 		u16 tfd_size = trans_pcie->txqs.tfd.size;
3609 
3610 		data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3611 		txcmd = (void *)data->data;
3612 		spin_lock_bh(&cmdq->lock);
3613 		ptr = cmdq->write_ptr;
3614 		for (i = 0; i < cmdq->n_window; i++) {
3615 			u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
3616 			u8 tfdidx;
3617 			u32 caplen, cmdlen;
3618 
3619 			if (trans->mac_cfg->gen2)
3620 				tfdidx = idx;
3621 			else
3622 				tfdidx = ptr;
3623 
3624 			cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3625 							   (u8 *)cmdq->tfds +
3626 							   tfd_size * tfdidx);
3627 			caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3628 
3629 			if (cmdlen) {
3630 				len += sizeof(*txcmd) + caplen;
3631 				txcmd->cmdlen = cpu_to_le32(cmdlen);
3632 				txcmd->caplen = cpu_to_le32(caplen);
3633 				memcpy(txcmd->data, cmdq->entries[idx].cmd,
3634 				       caplen);
3635 				if (sanitize_ops && sanitize_ops->frob_hcmd)
3636 					sanitize_ops->frob_hcmd(sanitize_ctx,
3637 								txcmd->data,
3638 								caplen);
3639 				txcmd = (void *)((u8 *)txcmd->data + caplen);
3640 			}
3641 
3642 			ptr = iwl_txq_dec_wrap(trans, ptr);
3643 		}
3644 		spin_unlock_bh(&cmdq->lock);
3645 
3646 		data->len = cpu_to_le32(len);
3647 		len += sizeof(*data);
3648 		data = iwl_fw_error_next_data(data);
3649 	}
3650 
3651 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3652 		len += iwl_trans_pcie_dump_csr(trans, &data);
3653 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3654 		len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3655 	if (dump_rbs)
3656 		len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3657 
3658 	/* Paged memory for gen2 HW */
3659 	if (trans->mac_cfg->gen2 &&
3660 	    dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3661 		for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3662 			struct iwl_fw_error_dump_paging *paging;
3663 			u32 page_len = trans->init_dram.paging[i].size;
3664 
3665 			data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3666 			data->len = cpu_to_le32(sizeof(*paging) + page_len);
3667 			paging = (void *)data->data;
3668 			paging->index = cpu_to_le32(i);
3669 			memcpy(paging->data,
3670 			       trans->init_dram.paging[i].block, page_len);
3671 			data = iwl_fw_error_next_data(data);
3672 
3673 			len += sizeof(*data) + sizeof(*paging) + page_len;
3674 		}
3675 	}
3676 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3677 		len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3678 
3679 	dump_data->len = len;
3680 
3681 	return dump_data;
3682 }
3683 
3684 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
3685 {
3686 	if (enable)
3687 		iwl_enable_interrupts(trans);
3688 	else
3689 		iwl_disable_interrupts(trans);
3690 }
3691 
3692 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3693 {
3694 	u32 inta_addr, sw_err_bit;
3695 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3696 
3697 	if (trans_pcie->msix_enabled) {
3698 		inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3699 		if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3700 			sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
3701 		else
3702 			sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3703 	} else {
3704 		inta_addr = CSR_INT;
3705 		sw_err_bit = CSR_INT_BIT_SW_ERR;
3706 	}
3707 
3708 	iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
3709 }
3710 
3711 static int iwl_trans_pcie_alloc_txcmd_pool(struct iwl_trans *trans)
3712 {
3713 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3714 	unsigned int txcmd_size, txcmd_align;
3715 
3716 	if (!trans->mac_cfg->gen2) {
3717 		txcmd_size = sizeof(struct iwl_tx_cmd_v6);
3718 		txcmd_align = sizeof(void *);
3719 	} else if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
3720 		txcmd_size = sizeof(struct iwl_tx_cmd_v9);
3721 		txcmd_align = 64;
3722 	} else {
3723 		txcmd_size = sizeof(struct iwl_tx_cmd);
3724 		txcmd_align = 128;
3725 	}
3726 
3727 	txcmd_size += sizeof(struct iwl_cmd_header);
3728 	txcmd_size += 36; /* biggest possible 802.11 header */
3729 
3730 	/* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */
3731 	if (WARN_ON((trans->mac_cfg->gen2 && txcmd_size >= txcmd_align)))
3732 		return -EINVAL;
3733 
3734 	snprintf(trans_pcie->dev_cmd_pool_name,
3735 		 sizeof(trans_pcie->dev_cmd_pool_name),
3736 		 "iwl_cmd_pool:%s", dev_name(trans->dev));
3737 
3738 	trans_pcie->dev_cmd_pool =
3739 		kmem_cache_create(trans_pcie->dev_cmd_pool_name,
3740 				  txcmd_size, txcmd_align,
3741 				  SLAB_HWCACHE_ALIGN, NULL);
3742 	if (!trans_pcie->dev_cmd_pool)
3743 		return -ENOMEM;
3744 
3745 	return 0;
3746 }
3747 
3748 static struct iwl_trans *
3749 iwl_trans_pcie_alloc(struct pci_dev *pdev,
3750 		     const struct iwl_mac_cfg *mac_cfg,
3751 		     struct iwl_trans_info *info, u8 __iomem *hw_base)
3752 {
3753 	struct iwl_trans_pcie *trans_pcie, **priv;
3754 	struct iwl_trans *trans;
3755 	unsigned int bc_tbl_n_entries;
3756 	int ret, addr_size;
3757 
3758 	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev,
3759 				mac_cfg);
3760 	if (!trans)
3761 		return ERR_PTR(-ENOMEM);
3762 
3763 	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3764 
3765 	trans_pcie->hw_base = hw_base;
3766 
3767 	/* Initialize the wait queue for commands */
3768 	init_waitqueue_head(&trans_pcie->wait_command_queue);
3769 
3770 	ret = iwl_trans_pcie_alloc_txcmd_pool(trans);
3771 	if (ret)
3772 		goto out_free_trans;
3773 
3774 	if (trans->mac_cfg->gen2) {
3775 		trans_pcie->txqs.tfd.addr_size = 64;
3776 		trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS;
3777 		trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd);
3778 	} else {
3779 		trans_pcie->txqs.tfd.addr_size = 36;
3780 		trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS;
3781 		trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd);
3782 	}
3783 
3784 	trans_pcie->supported_dma_mask = (u32)DMA_BIT_MASK(12);
3785 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
3786 		trans_pcie->supported_dma_mask = (u32)DMA_BIT_MASK(11);
3787 
3788 	info->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie);
3789 
3790 	trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3791 	if (!trans_pcie->txqs.tso_hdr_page) {
3792 		ret = -ENOMEM;
3793 		goto out_free_txcmd_pool;
3794 	}
3795 
3796 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3797 		bc_tbl_n_entries = TFD_QUEUE_BC_SIZE_BZ;
3798 	else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
3799 		bc_tbl_n_entries = TFD_QUEUE_BC_SIZE_AX210;
3800 	else
3801 		bc_tbl_n_entries = TFD_QUEUE_BC_SIZE;
3802 
3803 	trans_pcie->txqs.bc_tbl_size =
3804 		sizeof(struct iwl_bc_tbl_entry) * bc_tbl_n_entries;
3805 	/*
3806 	 * For gen2 devices, we use a single allocation for each byte-count
3807 	 * table, but they're pretty small (1k) so use a DMA pool that we
3808 	 * allocate here.
3809 	 */
3810 	if (trans->mac_cfg->gen2) {
3811 		trans_pcie->txqs.bc_pool =
3812 			dmam_pool_create("iwlwifi:bc", trans->dev,
3813 					 trans_pcie->txqs.bc_tbl_size,
3814 					 256, 0);
3815 		if (!trans_pcie->txqs.bc_pool) {
3816 			ret = -ENOMEM;
3817 			goto out_free_tso;
3818 		}
3819 	}
3820 
3821 	/* Some things must not change even if the config does */
3822 	WARN_ON(trans_pcie->txqs.tfd.addr_size !=
3823 		(trans->mac_cfg->gen2 ? 64 : 36));
3824 
3825 	/* Initialize NAPI here - it should be before registering to mac80211
3826 	 * in the opmode but after the HW struct is allocated.
3827 	 */
3828 	trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *));
3829 	if (!trans_pcie->napi_dev) {
3830 		ret = -ENOMEM;
3831 		goto out_free_tso;
3832 	}
3833 	/* The private struct in netdev is a pointer to struct iwl_trans_pcie */
3834 	priv = netdev_priv(trans_pcie->napi_dev);
3835 	*priv = trans_pcie;
3836 
3837 	trans_pcie->trans = trans;
3838 	trans_pcie->opmode_down = true;
3839 	spin_lock_init(&trans_pcie->irq_lock);
3840 	spin_lock_init(&trans_pcie->reg_lock);
3841 	spin_lock_init(&trans_pcie->alloc_page_lock);
3842 	mutex_init(&trans_pcie->mutex);
3843 	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3844 	init_waitqueue_head(&trans_pcie->fw_reset_waitq);
3845 	init_waitqueue_head(&trans_pcie->imr_waitq);
3846 
3847 	trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3848 						   WQ_HIGHPRI | WQ_UNBOUND, 0);
3849 	if (!trans_pcie->rba.alloc_wq) {
3850 		ret = -ENOMEM;
3851 		goto out_free_ndev;
3852 	}
3853 	INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3854 
3855 	trans_pcie->debug_rfkill = -1;
3856 
3857 	if (!mac_cfg->base->pcie_l1_allowed) {
3858 		/*
3859 		 * W/A - seems to solve weird behavior. We need to remove this
3860 		 * if we don't want to stay in L1 all the time. This wastes a
3861 		 * lot of power.
3862 		 */
3863 		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3864 				       PCIE_LINK_STATE_L1 |
3865 				       PCIE_LINK_STATE_CLKPM);
3866 	}
3867 
3868 	addr_size = trans_pcie->txqs.tfd.addr_size;
3869 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));
3870 	if (ret) {
3871 		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3872 		/* both attempts failed: */
3873 		if (ret) {
3874 			dev_err(&pdev->dev, "No suitable DMA available\n");
3875 			goto out_no_pci;
3876 		}
3877 	}
3878 
3879 	/* We disable the RETRY_TIMEOUT register (0x41) to keep
3880 	 * PCI Tx retries from interfering with C3 CPU state */
3881 	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3882 
3883 	trans_pcie->pci_dev = pdev;
3884 	iwl_disable_interrupts(trans);
3885 
3886 	/*
3887 	 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3888 	 * changed, and now the revision step also includes bit 0-1 (no more
3889 	 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3890 	 * in the old format.
3891 	 */
3892 	if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
3893 		info->hw_rev_step = info->hw_rev & 0xF;
3894 	else
3895 		info->hw_rev_step = (info->hw_rev & 0xC) >> 2;
3896 
3897 	IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", info->hw_rev);
3898 
3899 	iwl_pcie_set_interrupt_capa(pdev, trans, mac_cfg, info);
3900 
3901 	init_waitqueue_head(&trans_pcie->sx_waitq);
3902 
3903 	ret = iwl_pcie_alloc_invalid_tx_cmd(trans);
3904 	if (ret)
3905 		goto out_no_pci;
3906 
3907 	if (trans_pcie->msix_enabled) {
3908 		ret = iwl_pcie_init_msix_handler(pdev, trans_pcie, info);
3909 		if (ret)
3910 			goto out_no_pci;
3911 	 } else {
3912 		ret = iwl_pcie_alloc_ict(trans);
3913 		if (ret)
3914 			goto out_no_pci;
3915 
3916 		ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3917 						iwl_pcie_isr,
3918 						iwl_pcie_irq_handler,
3919 						IRQF_SHARED, DRV_NAME, trans);
3920 		if (ret) {
3921 			IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3922 			goto out_free_ict;
3923 		}
3924 	 }
3925 
3926 #ifdef CONFIG_IWLWIFI_DEBUGFS
3927 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3928 	mutex_init(&trans_pcie->fw_mon_data.mutex);
3929 #endif
3930 
3931 	iwl_dbg_tlv_init(trans);
3932 
3933 	return trans;
3934 
3935 out_free_ict:
3936 	iwl_pcie_free_ict(trans);
3937 out_no_pci:
3938 	destroy_workqueue(trans_pcie->rba.alloc_wq);
3939 out_free_ndev:
3940 	free_netdev(trans_pcie->napi_dev);
3941 out_free_tso:
3942 	free_percpu(trans_pcie->txqs.tso_hdr_page);
3943 out_free_txcmd_pool:
3944 	kmem_cache_destroy(trans_pcie->dev_cmd_pool);
3945 out_free_trans:
3946 	iwl_trans_free(trans);
3947 	return ERR_PTR(ret);
3948 }
3949 
3950 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
3951 				u32 dst_addr, u64 src_addr, u32 byte_cnt)
3952 {
3953 	iwl_write_prph(trans, IMR_UREG_CHICK,
3954 		       iwl_read_prph(trans, IMR_UREG_CHICK) |
3955 		       IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);
3956 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
3957 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
3958 		       (u32)(src_addr & 0xFFFFFFFF));
3959 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
3960 		       iwl_get_dma_hi_addr(src_addr));
3961 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
3962 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
3963 		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |
3964 		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |
3965 		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);
3966 }
3967 
3968 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
3969 			    u32 dst_addr, u64 src_addr, u32 byte_cnt)
3970 {
3971 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3972 	int ret = -1;
3973 
3974 	trans_pcie->imr_status = IMR_D2S_REQUESTED;
3975 	iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt);
3976 	ret = wait_event_timeout(trans_pcie->imr_waitq,
3977 				 trans_pcie->imr_status !=
3978 				 IMR_D2S_REQUESTED, 5 * HZ);
3979 	if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) {
3980 		IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n");
3981 		iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev);
3982 		return -ETIMEDOUT;
3983 	}
3984 	trans_pcie->imr_status = IMR_D2S_IDLE;
3985 	return 0;
3986 }
3987 
3988 /*
3989  * Read rf id and cdb info from prph register and store it
3990  */
3991 static void get_crf_id(struct iwl_trans *iwl_trans,
3992 		       struct iwl_trans_info *info)
3993 {
3994 	u32 sd_reg_ver_addr;
3995 	u32 hw_wfpm_id;
3996 	u32 val = 0;
3997 	u8 step;
3998 
3999 	if (iwl_trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
4000 		sd_reg_ver_addr = SD_REG_VER_GEN2;
4001 	else
4002 		sd_reg_ver_addr = SD_REG_VER;
4003 
4004 	/* Enable access to peripheral registers */
4005 	val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);
4006 	val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;
4007 	iwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);
4008 
4009 	/* Read crf info */
4010 	info->hw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr);
4011 
4012 	/* Read cnv info */
4013 	info->hw_cnv_id = iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP);
4014 
4015 	/* For BZ-W, take B step also when A step is indicated */
4016 	if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W)
4017 		step = SILICON_B_STEP;
4018 
4019 	/* In BZ, the MAC step must be read from the CNVI aux register */
4020 	if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ) {
4021 		step = CNVI_AUX_MISC_CHIP_MAC_STEP(info->hw_cnv_id);
4022 
4023 		/* For BZ-U, take B step also when A step is indicated */
4024 		if ((CNVI_AUX_MISC_CHIP_PROD_TYPE(info->hw_cnv_id) ==
4025 		    CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U) &&
4026 		    step == SILICON_A_STEP)
4027 			step = SILICON_B_STEP;
4028 	}
4029 
4030 	if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ ||
4031 	    CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W) {
4032 		info->hw_rev_step = step;
4033 		info->hw_rev |= step;
4034 	}
4035 
4036 	/* Read cdb info (also contains the jacket info if needed in the future */
4037 	hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);
4038 
4039 	IWL_INFO(iwl_trans, "Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\n",
4040 		 info->hw_crf_id, info->hw_cnv_id, hw_wfpm_id);
4041 }
4042 
4043 /*
4044  * In case that there is no OTP on the NIC, map the rf id and cdb info
4045  * from the prph registers.
4046  */
4047 static int map_crf_id(struct iwl_trans *iwl_trans,
4048 		      struct iwl_trans_info *info)
4049 {
4050 	int ret = 0;
4051 	u32 val = info->hw_crf_id;
4052 	u32 step_id = REG_CRF_ID_STEP(val);
4053 	u32 slave_id = REG_CRF_ID_SLAVE(val);
4054 	u32 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans,
4055 						    WFPM_OTP_CFG1_ADDR);
4056 	u32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(hw_wfpm_id);
4057 
4058 	/* Map between crf id to rf id */
4059 	switch (REG_CRF_ID_TYPE(val)) {
4060 	case REG_CRF_ID_TYPE_JF_1:
4061 		info->hw_rf_id = (IWL_CFG_RF_TYPE_JF1 << 12);
4062 		break;
4063 	case REG_CRF_ID_TYPE_JF_2:
4064 		info->hw_rf_id = (IWL_CFG_RF_TYPE_JF2 << 12);
4065 		break;
4066 	case REG_CRF_ID_TYPE_HR_NONE_CDB_1X1:
4067 		info->hw_rf_id = (IWL_CFG_RF_TYPE_HR1 << 12);
4068 		break;
4069 	case REG_CRF_ID_TYPE_HR_NONE_CDB:
4070 		info->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12);
4071 		break;
4072 	case REG_CRF_ID_TYPE_HR_CDB:
4073 		info->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12);
4074 		break;
4075 	case REG_CRF_ID_TYPE_GF:
4076 		info->hw_rf_id = (IWL_CFG_RF_TYPE_GF << 12);
4077 		break;
4078 	case REG_CRF_ID_TYPE_FM:
4079 		info->hw_rf_id = (IWL_CFG_RF_TYPE_FM << 12);
4080 		break;
4081 	case REG_CRF_ID_TYPE_WHP:
4082 		info->hw_rf_id = (IWL_CFG_RF_TYPE_WH << 12);
4083 		break;
4084 	case REG_CRF_ID_TYPE_PE:
4085 		info->hw_rf_id = (IWL_CFG_RF_TYPE_PE << 12);
4086 		break;
4087 	default:
4088 		ret = -EIO;
4089 		IWL_ERR(iwl_trans,
4090 			"Can't find a correct rfid for crf id 0x%x\n",
4091 			REG_CRF_ID_TYPE(val));
4092 		goto out;
4093 	}
4094 
4095 	/* Set Step-id */
4096 	info->hw_rf_id |= (step_id << 8);
4097 
4098 	/* Set CDB capabilities */
4099 	if (cdb_id_wfpm || slave_id) {
4100 		info->hw_rf_id += BIT(28);
4101 		IWL_INFO(iwl_trans, "Adding cdb to rf id\n");
4102 	}
4103 
4104 	IWL_INFO(iwl_trans,
4105 		 "Detected rf-type 0x%x step-id 0x%x slave-id 0x%x from crf id 0x%x\n",
4106 		 REG_CRF_ID_TYPE(val), step_id, slave_id, info->hw_rf_id);
4107 	IWL_INFO(iwl_trans,
4108 		 "Detected cdb-id 0x%x from wfpm id 0x%x\n",
4109 		 cdb_id_wfpm, hw_wfpm_id);
4110 out:
4111 	return ret;
4112 }
4113 
4114 static void iwl_pcie_recheck_me_status(struct work_struct *wk)
4115 {
4116 	struct iwl_trans_pcie *trans_pcie = container_of(wk,
4117 							 typeof(*trans_pcie),
4118 							 me_recheck_wk.work);
4119 	u32 val;
4120 
4121 	val = iwl_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG);
4122 	trans_pcie->me_present = !!(val & CSR_HW_IF_CONFIG_REG_IAMT_UP);
4123 }
4124 
4125 static void iwl_pcie_check_me_status(struct iwl_trans *trans)
4126 {
4127 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4128 	u32 val;
4129 
4130 	trans_pcie->me_present = -1;
4131 
4132 	INIT_DELAYED_WORK(&trans_pcie->me_recheck_wk,
4133 			  iwl_pcie_recheck_me_status);
4134 
4135 	/* we don't have a good way of determining this until BZ */
4136 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
4137 		return;
4138 
4139 	val = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);
4140 	if (val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_KNOWN) {
4141 		trans_pcie->me_present =
4142 			!!(val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_PRESENT);
4143 		return;
4144 	}
4145 
4146 	val = iwl_read32(trans, CSR_HW_IF_CONFIG_REG);
4147 	if (val & (CSR_HW_IF_CONFIG_REG_ME_OWN |
4148 		   CSR_HW_IF_CONFIG_REG_IAMT_UP)) {
4149 		trans_pcie->me_present = 1;
4150 		return;
4151 	}
4152 
4153 	/* recheck again later, ME might still be initializing */
4154 	schedule_delayed_work(&trans_pcie->me_recheck_wk, HZ);
4155 }
4156 
4157 int iwl_pci_gen1_2_probe(struct pci_dev *pdev,
4158 			 const struct pci_device_id *ent,
4159 			 const struct iwl_mac_cfg *mac_cfg,
4160 			 u8 __iomem *hw_base, u32 hw_rev)
4161 {
4162 	const struct iwl_dev_info *dev_info;
4163 	struct iwl_trans_info info = {
4164 		.hw_id = (pdev->device << 16) + pdev->subsystem_device,
4165 		.hw_rev = hw_rev,
4166 	};
4167 	struct iwl_trans *iwl_trans;
4168 	struct iwl_trans_pcie *trans_pcie;
4169 	int ret;
4170 
4171 	iwl_trans = iwl_trans_pcie_alloc(pdev, mac_cfg, &info, hw_base);
4172 	if (IS_ERR(iwl_trans))
4173 		return PTR_ERR(iwl_trans);
4174 
4175 	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
4176 
4177 	iwl_trans_pcie_check_product_reset_status(pdev);
4178 	iwl_trans_pcie_check_product_reset_mode(pdev);
4179 
4180 	/* set the things we know so far for the grab NIC access */
4181 	iwl_trans_set_info(iwl_trans, &info);
4182 
4183 	/*
4184 	 * Let's try to grab NIC access early here. Sometimes, NICs may
4185 	 * fail to initialize, and if that happens it's better if we see
4186 	 * issues early on (and can reprobe, per the logic inside), than
4187 	 * first trying to load the firmware etc. and potentially only
4188 	 * detecting any problems when the first interface is brought up.
4189 	 */
4190 	ret = iwl_pcie_prepare_card_hw(iwl_trans);
4191 	if (!ret) {
4192 		ret = iwl_finish_nic_init(iwl_trans);
4193 		if (ret)
4194 			goto out_free_trans;
4195 		if (iwl_trans_grab_nic_access(iwl_trans)) {
4196 			get_crf_id(iwl_trans, &info);
4197 			/* all good */
4198 			iwl_trans_release_nic_access(iwl_trans);
4199 		} else {
4200 			ret = -EIO;
4201 			goto out_free_trans;
4202 		}
4203 	}
4204 
4205 	info.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID);
4206 
4207 	/*
4208 	 * The RF_ID is set to zero in blank OTP so read version to
4209 	 * extract the RF_ID.
4210 	 * This is relevant only for family 9000 and up.
4211 	 */
4212 	if (iwl_trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_9000 &&
4213 	    !CSR_HW_RFID_TYPE(info.hw_rf_id) && map_crf_id(iwl_trans, &info)) {
4214 		ret = -EINVAL;
4215 		goto out_free_trans;
4216 	}
4217 
4218 	IWL_INFO(iwl_trans, "PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n",
4219 		 pdev->device, pdev->subsystem_device,
4220 		 info.hw_rev, info.hw_rf_id);
4221 
4222 	dev_info = iwl_pci_find_dev_info(pdev->device, pdev->subsystem_device,
4223 					 CSR_HW_RFID_TYPE(info.hw_rf_id),
4224 					 CSR_HW_RFID_IS_CDB(info.hw_rf_id),
4225 					 IWL_SUBDEVICE_RF_ID(pdev->subsystem_device),
4226 					 IWL_SUBDEVICE_BW_LIM(pdev->subsystem_device),
4227 					 !iwl_trans->mac_cfg->integrated);
4228 	if (dev_info) {
4229 		iwl_trans->cfg = dev_info->cfg;
4230 		info.name = dev_info->name;
4231 	}
4232 
4233 #if IS_ENABLED(CONFIG_IWLMVM)
4234 
4235 	/*
4236 	 * special-case 7265D, it has the same PCI IDs.
4237 	 *
4238 	 * Note that because we already pass the cfg to the transport above,
4239 	 * all the parameters that the transport uses must, until that is
4240 	 * changed, be identical to the ones in the 7265D configuration.
4241 	 */
4242 	if (iwl_trans->cfg == &iwl7265_cfg &&
4243 	    (info.hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_7265D)
4244 		iwl_trans->cfg = &iwl7265d_cfg;
4245 #endif
4246 	if (!iwl_trans->cfg) {
4247 		pr_err("No config found for PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n",
4248 		       pdev->device, pdev->subsystem_device,
4249 		       info.hw_rev, info.hw_rf_id);
4250 		ret = -EINVAL;
4251 		goto out_free_trans;
4252 	}
4253 
4254 	IWL_INFO(iwl_trans, "Detected %s\n", info.name);
4255 
4256 	if (iwl_trans->mac_cfg->mq_rx_supported) {
4257 		if (WARN_ON(!iwl_trans->cfg->num_rbds)) {
4258 			ret = -EINVAL;
4259 			goto out_free_trans;
4260 		}
4261 		trans_pcie->num_rx_bufs = iwl_trans_get_num_rbds(iwl_trans);
4262 	} else {
4263 		trans_pcie->num_rx_bufs = RX_QUEUE_SIZE;
4264 	}
4265 
4266 	if (!iwl_trans->mac_cfg->integrated) {
4267 		u16 link_status;
4268 
4269 		pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &link_status);
4270 
4271 		info.pcie_link_speed =
4272 			u16_get_bits(link_status, PCI_EXP_LNKSTA_CLS);
4273 	}
4274 
4275 	iwl_trans_set_info(iwl_trans, &info);
4276 
4277 	pci_set_drvdata(pdev, iwl_trans);
4278 
4279 	iwl_pcie_check_me_status(iwl_trans);
4280 
4281 	/* try to get ownership so that we'll know if we don't own it */
4282 	iwl_pcie_prepare_card_hw(iwl_trans);
4283 
4284 	iwl_trans->drv = iwl_drv_start(iwl_trans);
4285 
4286 	if (IS_ERR(iwl_trans->drv)) {
4287 		ret = PTR_ERR(iwl_trans->drv);
4288 		goto out_free_trans;
4289 	}
4290 
4291 	/* register transport layer debugfs here */
4292 	iwl_trans_pcie_dbgfs_register(iwl_trans);
4293 
4294 	return 0;
4295 
4296 out_free_trans:
4297 	iwl_trans_pcie_free(iwl_trans);
4298 	return ret;
4299 }
4300 
4301 void iwl_pcie_gen1_2_remove(struct iwl_trans *trans)
4302 {
4303 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4304 
4305 	cancel_delayed_work_sync(&trans_pcie->me_recheck_wk);
4306 
4307 	iwl_drv_stop(trans->drv);
4308 
4309 	iwl_trans_pcie_free(trans);
4310 }
4311 
4312 int iwl_pcie_gen1_2_finish_nic_init(struct iwl_trans *trans)
4313 {
4314 	const struct iwl_mac_cfg *mac_cfg = trans->mac_cfg;
4315 	u32 poll_ready;
4316 	int err;
4317 
4318 	if (mac_cfg->bisr_workaround) {
4319 		/* ensure the TOP FSM isn't still in previous reset */
4320 		mdelay(2);
4321 	}
4322 
4323 	/*
4324 	 * Set "initialization complete" bit to move adapter from
4325 	 * D0U* --> D0A* (powered-up active) state.
4326 	 */
4327 	if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
4328 		iwl_set_bit(trans, CSR_GP_CNTRL,
4329 			    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ |
4330 			    CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
4331 		poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
4332 	} else {
4333 		iwl_set_bit(trans, CSR_GP_CNTRL,
4334 			    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4335 		poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY;
4336 	}
4337 
4338 	if (mac_cfg->device_family == IWL_DEVICE_FAMILY_8000)
4339 		udelay(2);
4340 
4341 	/*
4342 	 * Wait for clock stabilization; once stabilized, access to
4343 	 * device-internal resources is supported, e.g. iwl_write_prph()
4344 	 * and accesses to uCode SRAM.
4345 	 */
4346 	err = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);
4347 	if (err < 0) {
4348 		IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
4349 
4350 		iwl_pcie_dump_host_monitor(trans);
4351 	}
4352 
4353 	if (mac_cfg->bisr_workaround) {
4354 		/* ensure BISR shift has finished */
4355 		udelay(200);
4356 	}
4357 
4358 	return err;
4359 }
4360