1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 18 #include "iwl-drv.h" 19 #include "iwl-trans.h" 20 #include "iwl-csr.h" 21 #include "iwl-prph.h" 22 #include "iwl-scd.h" 23 #include "iwl-agn-hw.h" 24 #include "fw/error-dump.h" 25 #include "fw/dbg.h" 26 #include "fw/api/tx.h" 27 #include "fw/acpi.h" 28 #include "fw/api/tx.h" 29 #include "mei/iwl-mei.h" 30 #include "internal.h" 31 #include "iwl-fh.h" 32 #include "pcie/iwl-context-info-v2.h" 33 #include "pcie/utils.h" 34 35 #define IWL_HOST_MON_BLOCK_PEMON 0x00 36 #define IWL_HOST_MON_BLOCK_HIPM 0x22 37 38 #define IWL_HOST_MON_BLOCK_PEMON_VEC0 0x00 39 #define IWL_HOST_MON_BLOCK_PEMON_VEC1 0x01 40 #define IWL_HOST_MON_BLOCK_PEMON_WFPM 0x06 41 42 static void iwl_dump_host_monitor_block(struct iwl_trans *trans, 43 u32 block, u32 vec, u32 iter) 44 { 45 int i; 46 47 IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec); 48 iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec); 49 for (i = 0; i < iter; i++) 50 IWL_ERR(trans, " value [iter %d]: 0x%08x\n", 51 i, iwl_read32(trans, CSR_MONITOR_STATUS_REG)); 52 } 53 54 static void iwl_pcie_dump_host_monitor(struct iwl_trans *trans) 55 { 56 switch (trans->mac_cfg->device_family) { 57 case IWL_DEVICE_FAMILY_22000: 58 case IWL_DEVICE_FAMILY_AX210: 59 IWL_ERR(trans, "CSR_RESET = 0x%x\n", 60 iwl_read32(trans, CSR_RESET)); 61 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, 62 IWL_HOST_MON_BLOCK_PEMON_VEC0, 15); 63 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, 64 IWL_HOST_MON_BLOCK_PEMON_VEC1, 15); 65 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, 66 IWL_HOST_MON_BLOCK_PEMON_WFPM, 15); 67 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_HIPM, 68 IWL_HOST_MON_BLOCK_PEMON_VEC0, 1); 69 break; 70 default: 71 return; 72 } 73 } 74 75 /* extended range in FW SRAM */ 76 #define IWL_FW_MEM_EXTENDED_START 0x40000 77 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 78 79 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership) 80 { 81 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 82 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 83 iwl_set_bit(trans, CSR_GP_CNTRL, 84 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 85 usleep_range(10000, 20000); 86 } else { 87 iwl_set_bit(trans, CSR_RESET, 88 CSR_RESET_REG_FLAG_SW_RESET); 89 usleep_range(5000, 6000); 90 } 91 92 if (retake_ownership) 93 return iwl_pcie_prepare_card_hw(trans); 94 95 return 0; 96 } 97 98 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 99 { 100 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 101 102 if (!fw_mon->size) 103 return; 104 105 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 106 fw_mon->physical); 107 108 fw_mon->block = NULL; 109 fw_mon->physical = 0; 110 fw_mon->size = 0; 111 } 112 113 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 114 u8 max_power) 115 { 116 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 117 void *block = NULL; 118 dma_addr_t physical = 0; 119 u32 size = 0; 120 u8 power; 121 122 if (fw_mon->size) { 123 memset(fw_mon->block, 0, fw_mon->size); 124 return; 125 } 126 127 /* need at least 2 KiB, so stop at 11 */ 128 for (power = max_power; power >= 11; power--) { 129 size = BIT(power); 130 block = dma_alloc_coherent(trans->dev, size, &physical, 131 GFP_KERNEL | __GFP_NOWARN); 132 if (!block) 133 continue; 134 135 IWL_INFO(trans, 136 "Allocated 0x%08x bytes for firmware monitor.\n", 137 size); 138 break; 139 } 140 141 if (WARN_ON_ONCE(!block)) 142 return; 143 144 if (power != max_power) 145 IWL_ERR(trans, 146 "Sorry - debug buffer is only %luK while you requested %luK\n", 147 (unsigned long)BIT(power - 10), 148 (unsigned long)BIT(max_power - 10)); 149 150 fw_mon->block = block; 151 fw_mon->physical = physical; 152 fw_mon->size = size; 153 } 154 155 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 156 { 157 if (!max_power) { 158 /* default max_power is maximum */ 159 max_power = 26; 160 } else { 161 max_power += 11; 162 } 163 164 if (WARN(max_power > 26, 165 "External buffer size for monitor is too big %d, check the FW TLV\n", 166 max_power)) 167 return; 168 169 iwl_pcie_alloc_fw_monitor_block(trans, max_power); 170 } 171 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 173 { 174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 175 ((reg & 0x0000ffff) | (2 << 28))); 176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 177 } 178 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 180 { 181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 183 ((reg & 0x0000ffff) | (3 << 28))); 184 } 185 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 187 { 188 if (trans->mac_cfg->base->apmg_not_supported) 189 return; 190 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 194 ~APMG_PS_CTRL_MSK_PWR_SRC); 195 else 196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 198 ~APMG_PS_CTRL_MSK_PWR_SRC); 199 } 200 201 /* PCI registers */ 202 #define PCI_CFG_RETRY_TIMEOUT 0x041 203 204 void iwl_pcie_apm_config(struct iwl_trans *trans) 205 { 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 207 u16 lctl; 208 u16 cap; 209 210 /* 211 * L0S states have been found to be unstable with our devices 212 * and in newer hardware they are not officially supported at 213 * all, so we must always set the L0S_DISABLED bit. 214 */ 215 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 216 217 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 218 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 219 220 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 221 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 222 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 223 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 224 trans->ltr_enabled ? "En" : "Dis"); 225 } 226 227 /* 228 * Start up NIC's basic functionality after it has been reset 229 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 230 * NOTE: This does not load uCode nor start the embedded processor 231 */ 232 static int iwl_pcie_apm_init(struct iwl_trans *trans) 233 { 234 int ret; 235 236 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 237 238 /* 239 * Use "set_bit" below rather than "write", to preserve any hardware 240 * bits already set by default after reset. 241 */ 242 243 /* Disable L0S exit timer (platform NMI Work/Around) */ 244 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000) 245 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 246 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 247 248 /* 249 * Disable L0s without affecting L1; 250 * don't wait for ICH L0s (ICH bug W/A) 251 */ 252 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 253 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 254 255 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 256 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 257 258 /* 259 * Enable HAP INTA (interrupt from management bus) to 260 * wake device's PCI Express link L1a -> L0s 261 */ 262 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 263 CSR_HW_IF_CONFIG_REG_HAP_WAKE); 264 265 iwl_pcie_apm_config(trans); 266 267 /* Configure analog phase-lock-loop before activating to D0A */ 268 if (trans->mac_cfg->base->pll_cfg) 269 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 270 271 ret = iwl_finish_nic_init(trans); 272 if (ret) 273 return ret; 274 275 if (trans->cfg->host_interrupt_operation_mode) { 276 /* 277 * This is a bit of an abuse - This is needed for 7260 / 3160 278 * only check host_interrupt_operation_mode even if this is 279 * not related to host_interrupt_operation_mode. 280 * 281 * Enable the oscillator to count wake up time for L1 exit. This 282 * consumes slightly more power (100uA) - but allows to be sure 283 * that we wake up from L1 on time. 284 * 285 * This looks weird: read twice the same register, discard the 286 * value, set a bit, and yet again, read that same register 287 * just to discard the value. But that's the way the hardware 288 * seems to like it. 289 */ 290 iwl_read_prph(trans, OSC_CLK); 291 iwl_read_prph(trans, OSC_CLK); 292 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 293 iwl_read_prph(trans, OSC_CLK); 294 iwl_read_prph(trans, OSC_CLK); 295 } 296 297 /* 298 * Enable DMA clock and wait for it to stabilize. 299 * 300 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 301 * bits do not disable clocks. This preserves any hardware 302 * bits already set by default in "CLK_CTRL_REG" after reset. 303 */ 304 if (!trans->mac_cfg->base->apmg_not_supported) { 305 iwl_write_prph(trans, APMG_CLK_EN_REG, 306 APMG_CLK_VAL_DMA_CLK_RQT); 307 udelay(20); 308 309 /* Disable L1-Active */ 310 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 311 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 312 313 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 314 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 315 APMG_RTC_INT_STT_RFKILL); 316 } 317 318 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 319 320 return 0; 321 } 322 323 /* 324 * Enable LP XTAL to avoid HW bug where device may consume much power if 325 * FW is not loaded after device reset. LP XTAL is disabled by default 326 * after device HW reset. Do it only if XTAL is fed by internal source. 327 * Configure device's "persistence" mode to avoid resetting XTAL again when 328 * SHRD_HW_RST occurs in S3. 329 */ 330 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 331 { 332 int ret; 333 u32 apmg_gp1_reg; 334 u32 apmg_xtal_cfg_reg; 335 u32 dl_cfg_reg; 336 337 /* Force XTAL ON */ 338 iwl_trans_set_bit(trans, CSR_GP_CNTRL, 339 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 340 341 ret = iwl_trans_pcie_sw_reset(trans, true); 342 343 if (!ret) 344 ret = iwl_finish_nic_init(trans); 345 346 if (WARN_ON(ret)) { 347 /* Release XTAL ON request */ 348 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 349 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 350 return; 351 } 352 353 /* 354 * Clear "disable persistence" to avoid LP XTAL resetting when 355 * SHRD_HW_RST is applied in S3. 356 */ 357 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 358 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 359 360 /* 361 * Force APMG XTAL to be active to prevent its disabling by HW 362 * caused by APMG idle state. 363 */ 364 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 365 SHR_APMG_XTAL_CFG_REG); 366 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 367 apmg_xtal_cfg_reg | 368 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 369 370 ret = iwl_trans_pcie_sw_reset(trans, true); 371 if (ret) 372 IWL_ERR(trans, 373 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 374 375 /* Enable LP XTAL by indirect access through CSR */ 376 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 377 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 378 SHR_APMG_GP1_WF_XTAL_LP_EN | 379 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 380 381 /* Clear delay line clock power up */ 382 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 383 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 384 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 385 386 /* 387 * Enable persistence mode to avoid LP XTAL resetting when 388 * SHRD_HW_RST is applied in S3. 389 */ 390 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 391 CSR_HW_IF_CONFIG_REG_PERSISTENCE); 392 393 /* 394 * Clear "initialization complete" bit to move adapter from 395 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 396 */ 397 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 398 399 /* Activates XTAL resources monitor */ 400 iwl_trans_set_bit(trans, CSR_MONITOR_CFG_REG, 401 CSR_MONITOR_XTAL_RESOURCES); 402 403 /* Release XTAL ON request */ 404 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 405 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 406 udelay(10); 407 408 /* Release APMG XTAL */ 409 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 410 apmg_xtal_cfg_reg & 411 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 412 } 413 414 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 415 { 416 int ret; 417 418 /* stop device's busmaster DMA activity */ 419 420 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 421 iwl_set_bit(trans, CSR_GP_CNTRL, 422 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 423 424 ret = iwl_poll_bits(trans, CSR_GP_CNTRL, 425 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 426 100); 427 usleep_range(10000, 20000); 428 } else { 429 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 430 431 ret = iwl_poll_bits(trans, CSR_RESET, 432 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 433 } 434 435 if (ret) 436 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 437 438 IWL_DEBUG_INFO(trans, "stop master\n"); 439 } 440 441 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 442 { 443 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 444 445 if (op_mode_leave) { 446 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 447 iwl_pcie_apm_init(trans); 448 449 /* inform ME that we are leaving */ 450 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) 451 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 452 APMG_PCIDEV_STT_VAL_WAKE_ME); 453 else if (trans->mac_cfg->device_family >= 454 IWL_DEVICE_FAMILY_8000) { 455 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 456 CSR_RESET_LINK_PWR_MGMT_DISABLED); 457 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 458 CSR_HW_IF_CONFIG_REG_WAKE_ME | 459 CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN); 460 mdelay(1); 461 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 462 CSR_RESET_LINK_PWR_MGMT_DISABLED); 463 } 464 mdelay(5); 465 } 466 467 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 468 469 /* Stop device's DMA activity */ 470 iwl_pcie_apm_stop_master(trans); 471 472 if (trans->cfg->lp_xtal_workaround) { 473 iwl_pcie_apm_lp_xtal_enable(trans); 474 return; 475 } 476 477 iwl_trans_pcie_sw_reset(trans, false); 478 479 /* 480 * Clear "initialization complete" bit to move adapter from 481 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 482 */ 483 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 484 } 485 486 static int iwl_pcie_nic_init(struct iwl_trans *trans) 487 { 488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 489 int ret; 490 491 /* nic_init */ 492 spin_lock_bh(&trans_pcie->irq_lock); 493 ret = iwl_pcie_apm_init(trans); 494 spin_unlock_bh(&trans_pcie->irq_lock); 495 496 if (ret) 497 return ret; 498 499 iwl_pcie_set_pwr(trans, false); 500 501 iwl_op_mode_nic_config(trans->op_mode); 502 503 /* Allocate the RX queue, or reset if it is already allocated */ 504 ret = iwl_pcie_rx_init(trans); 505 if (ret) 506 return ret; 507 508 /* Allocate or reset and init all Tx and Command queues */ 509 if (iwl_pcie_tx_init(trans)) { 510 iwl_pcie_rx_free(trans); 511 return -ENOMEM; 512 } 513 514 if (trans->mac_cfg->base->shadow_reg_enable) { 515 /* enable shadow regs in HW */ 516 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 517 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 518 } 519 520 return 0; 521 } 522 523 #define HW_READY_TIMEOUT (50) 524 525 /* Note: returns poll_bit return value, which is >= 0 if success */ 526 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 527 { 528 int ret; 529 530 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 531 CSR_HW_IF_CONFIG_REG_PCI_OWN_SET); 532 533 /* See if we got it */ 534 ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG, 535 CSR_HW_IF_CONFIG_REG_PCI_OWN_SET, 536 HW_READY_TIMEOUT); 537 538 if (!ret) 539 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 540 541 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret ? " not" : ""); 542 return ret; 543 } 544 545 /* Note: returns standard 0/-ERROR code */ 546 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 547 { 548 int ret; 549 int iter; 550 551 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 552 553 ret = iwl_pcie_set_hw_ready(trans); 554 /* If the card is ready, exit 0 */ 555 if (!ret) { 556 trans->csme_own = false; 557 return 0; 558 } 559 560 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 561 CSR_RESET_LINK_PWR_MGMT_DISABLED); 562 usleep_range(1000, 2000); 563 564 for (iter = 0; iter < 10; iter++) { 565 int t = 0; 566 567 /* If HW is not ready, prepare the conditions to check again */ 568 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 569 CSR_HW_IF_CONFIG_REG_WAKE_ME); 570 571 do { 572 ret = iwl_pcie_set_hw_ready(trans); 573 if (!ret) { 574 trans->csme_own = false; 575 return 0; 576 } 577 578 if (iwl_mei_is_connected()) { 579 IWL_DEBUG_INFO(trans, 580 "Couldn't prepare the card but SAP is connected\n"); 581 trans->csme_own = true; 582 if (trans->mac_cfg->device_family != 583 IWL_DEVICE_FAMILY_9000) 584 IWL_ERR(trans, 585 "SAP not supported for this NIC family\n"); 586 587 return -EBUSY; 588 } 589 590 usleep_range(200, 1000); 591 t += 200; 592 } while (t < 150000); 593 msleep(25); 594 } 595 596 IWL_ERR(trans, "Couldn't prepare the card\n"); 597 598 return ret; 599 } 600 601 /* 602 * ucode 603 */ 604 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 605 u32 dst_addr, dma_addr_t phy_addr, 606 u32 byte_cnt) 607 { 608 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 609 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 610 611 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 612 dst_addr); 613 614 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 615 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 616 617 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 618 (iwl_get_dma_hi_addr(phy_addr) 619 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 620 621 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 622 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 623 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 624 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 625 626 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 627 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 628 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 629 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 630 } 631 632 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 633 u32 dst_addr, dma_addr_t phy_addr, 634 u32 byte_cnt) 635 { 636 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 637 int ret; 638 639 trans_pcie->ucode_write_complete = false; 640 641 if (!iwl_trans_grab_nic_access(trans)) 642 return -EIO; 643 644 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 645 byte_cnt); 646 iwl_trans_release_nic_access(trans); 647 648 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 649 trans_pcie->ucode_write_complete, 5 * HZ); 650 if (!ret) { 651 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 652 iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev); 653 return -ETIMEDOUT; 654 } 655 656 return 0; 657 } 658 659 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 660 const struct fw_desc *section) 661 { 662 u8 *v_addr; 663 dma_addr_t p_addr; 664 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 665 int ret = 0; 666 667 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 668 section_num); 669 670 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 671 GFP_KERNEL | __GFP_NOWARN); 672 if (!v_addr) { 673 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 674 chunk_sz = PAGE_SIZE; 675 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 676 &p_addr, GFP_KERNEL); 677 if (!v_addr) 678 return -ENOMEM; 679 } 680 681 for (offset = 0; offset < section->len; offset += chunk_sz) { 682 u32 copy_size, dst_addr; 683 bool extended_addr = false; 684 685 copy_size = min_t(u32, chunk_sz, section->len - offset); 686 dst_addr = section->offset + offset; 687 688 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 689 dst_addr <= IWL_FW_MEM_EXTENDED_END) 690 extended_addr = true; 691 692 if (extended_addr) 693 iwl_set_bits_prph(trans, LMPM_CHICK, 694 LMPM_CHICK_EXTENDED_ADDR_SPACE); 695 696 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 697 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 698 copy_size); 699 700 if (extended_addr) 701 iwl_clear_bits_prph(trans, LMPM_CHICK, 702 LMPM_CHICK_EXTENDED_ADDR_SPACE); 703 704 if (ret) { 705 IWL_ERR(trans, 706 "Could not load the [%d] uCode section\n", 707 section_num); 708 break; 709 } 710 } 711 712 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 713 return ret; 714 } 715 716 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 717 const struct fw_img *image, 718 int cpu, 719 int *first_ucode_section) 720 { 721 int shift_param; 722 int i, ret = 0, sec_num = 0x1; 723 u32 val, last_read_idx = 0; 724 725 if (cpu == 1) { 726 shift_param = 0; 727 *first_ucode_section = 0; 728 } else { 729 shift_param = 16; 730 (*first_ucode_section)++; 731 } 732 733 for (i = *first_ucode_section; i < image->num_sec; i++) { 734 last_read_idx = i; 735 736 /* 737 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 738 * CPU1 to CPU2. 739 * PAGING_SEPARATOR_SECTION delimiter - separate between 740 * CPU2 non paged to CPU2 paging sec. 741 */ 742 if (!image->sec[i].data || 743 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 744 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 745 IWL_DEBUG_FW(trans, 746 "Break since Data not valid or Empty section, sec = %d\n", 747 i); 748 break; 749 } 750 751 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 752 if (ret) 753 return ret; 754 755 /* Notify ucode of loaded section number and status */ 756 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 757 val = val | (sec_num << shift_param); 758 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 759 760 sec_num = (sec_num << 1) | 0x1; 761 } 762 763 *first_ucode_section = last_read_idx; 764 765 iwl_enable_interrupts(trans); 766 767 if (trans->mac_cfg->gen2) { 768 if (cpu == 1) 769 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 770 0xFFFF); 771 else 772 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 773 0xFFFFFFFF); 774 } else { 775 if (cpu == 1) 776 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 777 0xFFFF); 778 else 779 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 780 0xFFFFFFFF); 781 } 782 783 return 0; 784 } 785 786 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 787 const struct fw_img *image, 788 int cpu, 789 int *first_ucode_section) 790 { 791 int i, ret = 0; 792 u32 last_read_idx = 0; 793 794 if (cpu == 1) 795 *first_ucode_section = 0; 796 else 797 (*first_ucode_section)++; 798 799 for (i = *first_ucode_section; i < image->num_sec; i++) { 800 last_read_idx = i; 801 802 /* 803 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 804 * CPU1 to CPU2. 805 * PAGING_SEPARATOR_SECTION delimiter - separate between 806 * CPU2 non paged to CPU2 paging sec. 807 */ 808 if (!image->sec[i].data || 809 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 810 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 811 IWL_DEBUG_FW(trans, 812 "Break since Data not valid or Empty section, sec = %d\n", 813 i); 814 break; 815 } 816 817 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 818 if (ret) 819 return ret; 820 } 821 822 *first_ucode_section = last_read_idx; 823 824 return 0; 825 } 826 827 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 828 { 829 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 830 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 831 &trans->dbg.fw_mon_cfg[alloc_id]; 832 struct iwl_dram_data *frag; 833 834 if (!iwl_trans_dbg_ini_valid(trans)) 835 return; 836 837 if (le32_to_cpu(fw_mon_cfg->buf_location) == 838 IWL_FW_INI_LOCATION_SRAM_PATH) { 839 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 840 /* set sram monitor by enabling bit 7 */ 841 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 842 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 843 844 return; 845 } 846 847 if (le32_to_cpu(fw_mon_cfg->buf_location) != 848 IWL_FW_INI_LOCATION_DRAM_PATH || 849 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 850 return; 851 852 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 853 854 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 855 alloc_id); 856 857 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 858 frag->physical >> MON_BUFF_SHIFT_VER2); 859 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 860 (frag->physical + frag->size - 256) >> 861 MON_BUFF_SHIFT_VER2); 862 } 863 864 void iwl_pcie_apply_destination(struct iwl_trans *trans) 865 { 866 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 867 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 868 int i; 869 870 if (iwl_trans_dbg_ini_valid(trans)) { 871 iwl_pcie_apply_destination_ini(trans); 872 return; 873 } 874 875 IWL_INFO(trans, "Applying debug destination %s\n", 876 get_fw_dbg_mode_string(dest->monitor_mode)); 877 878 if (dest->monitor_mode == EXTERNAL_MODE) 879 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 880 else 881 IWL_WARN(trans, "PCI should have external buffer debug\n"); 882 883 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 884 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 885 u32 val = le32_to_cpu(dest->reg_ops[i].val); 886 887 switch (dest->reg_ops[i].op) { 888 case CSR_ASSIGN: 889 iwl_write32(trans, addr, val); 890 break; 891 case CSR_SETBIT: 892 iwl_set_bit(trans, addr, BIT(val)); 893 break; 894 case CSR_CLEARBIT: 895 iwl_clear_bit(trans, addr, BIT(val)); 896 break; 897 case PRPH_ASSIGN: 898 iwl_write_prph(trans, addr, val); 899 break; 900 case PRPH_SETBIT: 901 iwl_set_bits_prph(trans, addr, BIT(val)); 902 break; 903 case PRPH_CLEARBIT: 904 iwl_clear_bits_prph(trans, addr, BIT(val)); 905 break; 906 case PRPH_BLOCKBIT: 907 if (iwl_read_prph(trans, addr) & BIT(val)) { 908 IWL_ERR(trans, 909 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 910 val, addr); 911 goto monitor; 912 } 913 break; 914 default: 915 IWL_ERR(trans, "FW debug - unknown OP %d\n", 916 dest->reg_ops[i].op); 917 break; 918 } 919 } 920 921 monitor: 922 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 923 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 924 fw_mon->physical >> dest->base_shift); 925 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 926 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 927 (fw_mon->physical + fw_mon->size - 928 256) >> dest->end_shift); 929 else 930 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 931 (fw_mon->physical + fw_mon->size) >> 932 dest->end_shift); 933 } 934 } 935 936 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 937 const struct fw_img *image) 938 { 939 int ret = 0; 940 int first_ucode_section; 941 942 IWL_DEBUG_FW(trans, "working with %s CPU\n", 943 image->is_dual_cpus ? "Dual" : "Single"); 944 945 /* load to FW the binary non secured sections of CPU1 */ 946 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 947 if (ret) 948 return ret; 949 950 if (image->is_dual_cpus) { 951 /* set CPU2 header address */ 952 iwl_write_prph(trans, 953 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 954 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 955 956 /* load to FW the binary sections of CPU2 */ 957 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 958 &first_ucode_section); 959 if (ret) 960 return ret; 961 } 962 963 if (iwl_pcie_dbg_on(trans)) 964 iwl_pcie_apply_destination(trans); 965 966 iwl_enable_interrupts(trans); 967 968 /* release CPU reset */ 969 iwl_write32(trans, CSR_RESET, 0); 970 971 return 0; 972 } 973 974 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 975 const struct fw_img *image) 976 { 977 int ret = 0; 978 int first_ucode_section; 979 980 IWL_DEBUG_FW(trans, "working with %s CPU\n", 981 image->is_dual_cpus ? "Dual" : "Single"); 982 983 if (iwl_pcie_dbg_on(trans)) 984 iwl_pcie_apply_destination(trans); 985 986 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 987 iwl_read_prph(trans, WFPM_GP2)); 988 989 /* 990 * Set default value. On resume reading the values that were 991 * zeored can provide debug data on the resume flow. 992 * This is for debugging only and has no functional impact. 993 */ 994 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 995 996 /* configure the ucode to be ready to get the secured image */ 997 /* release CPU reset */ 998 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 999 1000 /* load to FW the binary Secured sections of CPU1 */ 1001 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1002 &first_ucode_section); 1003 if (ret) 1004 return ret; 1005 1006 /* load to FW the binary sections of CPU2 */ 1007 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1008 &first_ucode_section); 1009 } 1010 1011 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1012 { 1013 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1014 bool hw_rfkill = iwl_is_rfkill_set(trans); 1015 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1016 bool report; 1017 1018 if (hw_rfkill) { 1019 set_bit(STATUS_RFKILL_HW, &trans->status); 1020 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1021 } else { 1022 clear_bit(STATUS_RFKILL_HW, &trans->status); 1023 if (trans_pcie->opmode_down) 1024 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1025 } 1026 1027 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1028 1029 if (prev != report) 1030 iwl_trans_pcie_rf_kill(trans, report, false); 1031 1032 return hw_rfkill; 1033 } 1034 1035 struct iwl_causes_list { 1036 u16 mask_reg; 1037 u8 bit; 1038 u8 addr; 1039 }; 1040 1041 #define IWL_CAUSE(reg, mask) \ 1042 { \ 1043 .mask_reg = reg, \ 1044 .bit = ilog2(mask), \ 1045 .addr = ilog2(mask) + \ 1046 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1047 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1048 0xffff), /* causes overflow warning */ \ 1049 } 1050 1051 static const struct iwl_causes_list causes_list_common[] = { 1052 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 1053 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 1054 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 1055 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 1056 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 1057 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 1058 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 1059 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR), 1060 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 1061 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 1062 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 1063 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 1064 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 1065 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 1066 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 1067 }; 1068 1069 static const struct iwl_causes_list causes_list_pre_bz[] = { 1070 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1071 }; 1072 1073 static const struct iwl_causes_list causes_list_bz[] = { 1074 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1075 }; 1076 1077 static void iwl_pcie_map_list(struct iwl_trans *trans, 1078 const struct iwl_causes_list *causes, 1079 int arr_size, int val) 1080 { 1081 int i; 1082 1083 for (i = 0; i < arr_size; i++) { 1084 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1085 iwl_clear_bit(trans, causes[i].mask_reg, 1086 BIT(causes[i].bit)); 1087 } 1088 } 1089 1090 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1091 { 1092 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1093 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1094 /* 1095 * Access all non RX causes and map them to the default irq. 1096 * In case we are missing at least one interrupt vector, 1097 * the first interrupt vector will serve non-RX and FBQ causes. 1098 */ 1099 iwl_pcie_map_list(trans, causes_list_common, 1100 ARRAY_SIZE(causes_list_common), val); 1101 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1102 iwl_pcie_map_list(trans, causes_list_bz, 1103 ARRAY_SIZE(causes_list_bz), val); 1104 else 1105 iwl_pcie_map_list(trans, causes_list_pre_bz, 1106 ARRAY_SIZE(causes_list_pre_bz), val); 1107 } 1108 1109 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1110 { 1111 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1112 u32 offset = 1113 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1114 u32 val, idx; 1115 1116 /* 1117 * The first RX queue - fallback queue, which is designated for 1118 * management frame, command responses etc, is always mapped to the 1119 * first interrupt vector. The other RX queues are mapped to 1120 * the other (N - 2) interrupt vectors. 1121 */ 1122 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1123 for (idx = 1; idx < trans->info.num_rxqs; idx++) { 1124 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1125 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1126 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1127 } 1128 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1129 1130 val = MSIX_FH_INT_CAUSES_Q(0); 1131 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1132 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1133 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1134 1135 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1136 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1137 } 1138 1139 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1140 { 1141 struct iwl_trans *trans = trans_pcie->trans; 1142 1143 if (!trans_pcie->msix_enabled) { 1144 if (trans->mac_cfg->mq_rx_supported && 1145 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1146 iwl_write_umac_prph(trans, UREG_CHICK, 1147 UREG_CHICK_MSI_ENABLE); 1148 return; 1149 } 1150 /* 1151 * The IVAR table needs to be configured again after reset, 1152 * but if the device is disabled, we can't write to 1153 * prph. 1154 */ 1155 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1156 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1157 1158 /* 1159 * Each cause from the causes list above and the RX causes is 1160 * represented as a byte in the IVAR table. The first nibble 1161 * represents the bound interrupt vector of the cause, the second 1162 * represents no auto clear for this cause. This will be set if its 1163 * interrupt vector is bound to serve other causes. 1164 */ 1165 iwl_pcie_map_rx_causes(trans); 1166 1167 iwl_pcie_map_non_rx_causes(trans); 1168 } 1169 1170 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1171 { 1172 struct iwl_trans *trans = trans_pcie->trans; 1173 1174 iwl_pcie_conf_msix_hw(trans_pcie); 1175 1176 if (!trans_pcie->msix_enabled) 1177 return; 1178 1179 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1180 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1181 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1182 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1183 } 1184 1185 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq) 1186 { 1187 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1188 1189 lockdep_assert_held(&trans_pcie->mutex); 1190 1191 if (trans_pcie->is_down) 1192 return; 1193 1194 trans_pcie->is_down = true; 1195 1196 /* tell the device to stop sending interrupts */ 1197 iwl_disable_interrupts(trans); 1198 1199 /* device going down, Stop using ICT table */ 1200 iwl_pcie_disable_ict(trans); 1201 1202 /* 1203 * If a HW restart happens during firmware loading, 1204 * then the firmware loading might call this function 1205 * and later it might be called again due to the 1206 * restart. So don't process again if the device is 1207 * already dead. 1208 */ 1209 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1210 IWL_DEBUG_INFO(trans, 1211 "DEVICE_ENABLED bit was set and is now cleared\n"); 1212 if (!from_irq) 1213 iwl_pcie_synchronize_irqs(trans); 1214 iwl_pcie_rx_napi_sync(trans); 1215 iwl_pcie_tx_stop(trans); 1216 iwl_pcie_rx_stop(trans); 1217 1218 /* Power-down device's busmaster DMA clocks */ 1219 if (!trans->mac_cfg->base->apmg_not_supported) { 1220 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1221 APMG_CLK_VAL_DMA_CLK_RQT); 1222 udelay(5); 1223 } 1224 } 1225 1226 /* Make sure (redundant) we've released our request to stay awake */ 1227 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1228 iwl_clear_bit(trans, CSR_GP_CNTRL, 1229 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1230 else 1231 iwl_clear_bit(trans, CSR_GP_CNTRL, 1232 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1233 1234 /* Stop the device, and put it in low power state */ 1235 iwl_pcie_apm_stop(trans, false); 1236 1237 /* re-take ownership to prevent other users from stealing the device */ 1238 iwl_trans_pcie_sw_reset(trans, true); 1239 1240 /* 1241 * Upon stop, the IVAR table gets erased, so msi-x won't 1242 * work. This causes a bug in RF-KILL flows, since the interrupt 1243 * that enables radio won't fire on the correct irq, and the 1244 * driver won't be able to handle the interrupt. 1245 * Configure the IVAR table again after reset. 1246 */ 1247 iwl_pcie_conf_msix_hw(trans_pcie); 1248 1249 /* 1250 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1251 * This is a bug in certain verions of the hardware. 1252 * Certain devices also keep sending HW RF kill interrupt all 1253 * the time, unless the interrupt is ACKed even if the interrupt 1254 * should be masked. Re-ACK all the interrupts here. 1255 */ 1256 iwl_disable_interrupts(trans); 1257 1258 /* clear all status bits */ 1259 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1260 clear_bit(STATUS_INT_ENABLED, &trans->status); 1261 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1262 1263 /* 1264 * Even if we stop the HW, we still want the RF kill 1265 * interrupt 1266 */ 1267 iwl_enable_rfkill_int(trans); 1268 } 1269 1270 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1271 { 1272 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1273 1274 if (trans_pcie->msix_enabled) { 1275 int i; 1276 1277 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1278 synchronize_irq(trans_pcie->msix_entries[i].vector); 1279 } else { 1280 synchronize_irq(trans_pcie->pci_dev->irq); 1281 } 1282 } 1283 1284 int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1285 const struct iwl_fw *fw, 1286 const struct fw_img *img, 1287 bool run_in_rfkill) 1288 { 1289 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1290 bool hw_rfkill; 1291 int ret; 1292 1293 /* This may fail if AMT took ownership of the device */ 1294 if (iwl_pcie_prepare_card_hw(trans)) { 1295 IWL_WARN(trans, "Exit HW not ready\n"); 1296 return -EIO; 1297 } 1298 1299 iwl_enable_rfkill_int(trans); 1300 1301 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1302 1303 /* 1304 * We enabled the RF-Kill interrupt and the handler may very 1305 * well be running. Disable the interrupts to make sure no other 1306 * interrupt can be fired. 1307 */ 1308 iwl_disable_interrupts(trans); 1309 1310 /* Make sure it finished running */ 1311 iwl_pcie_synchronize_irqs(trans); 1312 1313 mutex_lock(&trans_pcie->mutex); 1314 1315 /* If platform's RF_KILL switch is NOT set to KILL */ 1316 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1317 if (hw_rfkill && !run_in_rfkill) { 1318 ret = -ERFKILL; 1319 goto out; 1320 } 1321 1322 /* Someone called stop_device, don't try to start_fw */ 1323 if (trans_pcie->is_down) { 1324 IWL_WARN(trans, 1325 "Can't start_fw since the HW hasn't been started\n"); 1326 ret = -EIO; 1327 goto out; 1328 } 1329 1330 /* make sure rfkill handshake bits are cleared */ 1331 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1332 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1333 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1334 1335 /* clear (again), then enable host interrupts */ 1336 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1337 1338 ret = iwl_pcie_nic_init(trans); 1339 if (ret) { 1340 IWL_ERR(trans, "Unable to init nic\n"); 1341 goto out; 1342 } 1343 1344 /* 1345 * Now, we load the firmware and don't want to be interrupted, even 1346 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1347 * FH_TX interrupt which is needed to load the firmware). If the 1348 * RF-Kill switch is toggled, we will find out after having loaded 1349 * the firmware and return the proper value to the caller. 1350 */ 1351 iwl_enable_fw_load_int(trans); 1352 1353 /* really make sure rfkill handshake bits are cleared */ 1354 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1355 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1356 1357 /* Load the given image to the HW */ 1358 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1359 ret = iwl_pcie_load_given_ucode_8000(trans, img); 1360 else 1361 ret = iwl_pcie_load_given_ucode(trans, img); 1362 1363 /* re-check RF-Kill state since we may have missed the interrupt */ 1364 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1365 if (hw_rfkill && !run_in_rfkill) 1366 ret = -ERFKILL; 1367 1368 out: 1369 mutex_unlock(&trans_pcie->mutex); 1370 return ret; 1371 } 1372 1373 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) 1374 { 1375 iwl_pcie_reset_ict(trans); 1376 iwl_pcie_tx_start(trans); 1377 } 1378 1379 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1380 bool was_in_rfkill) 1381 { 1382 bool hw_rfkill; 1383 1384 /* 1385 * Check again since the RF kill state may have changed while 1386 * all the interrupts were disabled, in this case we couldn't 1387 * receive the RF kill interrupt and update the state in the 1388 * op_mode. 1389 * Don't call the op_mode if the rkfill state hasn't changed. 1390 * This allows the op_mode to call stop_device from the rfkill 1391 * notification without endless recursion. Under very rare 1392 * circumstances, we might have a small recursion if the rfkill 1393 * state changed exactly now while we were called from stop_device. 1394 * This is very unlikely but can happen and is supported. 1395 */ 1396 hw_rfkill = iwl_is_rfkill_set(trans); 1397 if (hw_rfkill) { 1398 set_bit(STATUS_RFKILL_HW, &trans->status); 1399 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1400 } else { 1401 clear_bit(STATUS_RFKILL_HW, &trans->status); 1402 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1403 } 1404 if (hw_rfkill != was_in_rfkill) 1405 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false); 1406 } 1407 1408 void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1409 { 1410 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1411 bool was_in_rfkill; 1412 1413 iwl_op_mode_time_point(trans->op_mode, 1414 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1415 NULL); 1416 1417 mutex_lock(&trans_pcie->mutex); 1418 trans_pcie->opmode_down = true; 1419 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1420 _iwl_trans_pcie_stop_device(trans, false); 1421 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1422 mutex_unlock(&trans_pcie->mutex); 1423 } 1424 1425 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq) 1426 { 1427 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1428 IWL_TRANS_GET_PCIE_TRANS(trans); 1429 1430 lockdep_assert_held(&trans_pcie->mutex); 1431 1432 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1433 state ? "disabled" : "enabled"); 1434 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) && 1435 !WARN_ON(trans->mac_cfg->gen2)) 1436 _iwl_trans_pcie_stop_device(trans, from_irq); 1437 } 1438 1439 static void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1440 bool test, bool reset) 1441 { 1442 iwl_disable_interrupts(trans); 1443 1444 /* 1445 * in testing mode, the host stays awake and the 1446 * hardware won't be reset (not even partially) 1447 */ 1448 if (test) 1449 return; 1450 1451 iwl_pcie_disable_ict(trans); 1452 1453 iwl_pcie_synchronize_irqs(trans); 1454 1455 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1456 iwl_clear_bit(trans, CSR_GP_CNTRL, 1457 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1458 iwl_clear_bit(trans, CSR_GP_CNTRL, 1459 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 1460 } else { 1461 iwl_clear_bit(trans, CSR_GP_CNTRL, 1462 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1463 iwl_clear_bit(trans, CSR_GP_CNTRL, 1464 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1465 } 1466 1467 if (reset) { 1468 /* 1469 * reset TX queues -- some of their registers reset during S3 1470 * so if we don't reset everything here the D3 image would try 1471 * to execute some invalid memory upon resume 1472 */ 1473 iwl_trans_pcie_tx_reset(trans); 1474 } 1475 1476 iwl_pcie_set_pwr(trans, true); 1477 } 1478 1479 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1480 { 1481 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1482 int ret; 1483 1484 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1485 return 0; 1486 1487 trans_pcie->sx_state = IWL_SX_WAITING; 1488 1489 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1490 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1491 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1492 UREG_DOORBELL_TO_ISR6_RESUME); 1493 else 1494 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1495 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1496 CSR_IPC_SLEEP_CONTROL_RESUME); 1497 1498 ret = wait_event_timeout(trans_pcie->sx_waitq, 1499 trans_pcie->sx_state != IWL_SX_WAITING, 1500 2 * HZ); 1501 if (!ret) { 1502 IWL_ERR(trans, "Timeout %s D3\n", 1503 suspend ? "entering" : "exiting"); 1504 ret = -ETIMEDOUT; 1505 } else { 1506 ret = 0; 1507 } 1508 1509 if (trans_pcie->sx_state == IWL_SX_ERROR) { 1510 IWL_ERR(trans, "FW error while %s D3\n", 1511 suspend ? "entering" : "exiting"); 1512 ret = -EIO; 1513 } 1514 1515 /* Invalidate it toward next suspend or resume */ 1516 trans_pcie->sx_state = IWL_SX_INVALID; 1517 1518 return ret; 1519 } 1520 1521 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset) 1522 { 1523 int ret; 1524 1525 if (!reset) 1526 /* Enable persistence mode to avoid reset */ 1527 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1528 CSR_HW_IF_CONFIG_REG_PERSISTENCE); 1529 1530 ret = iwl_pcie_d3_handshake(trans, true); 1531 if (ret) 1532 return ret; 1533 1534 iwl_pcie_d3_complete_suspend(trans, test, reset); 1535 1536 return 0; 1537 } 1538 1539 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1540 enum iwl_d3_status *status, 1541 bool test, bool reset) 1542 { 1543 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1544 u32 val; 1545 int ret; 1546 1547 if (test) { 1548 iwl_enable_interrupts(trans); 1549 *status = IWL_D3_STATUS_ALIVE; 1550 ret = 0; 1551 goto out; 1552 } 1553 1554 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1555 iwl_set_bit(trans, CSR_GP_CNTRL, 1556 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1557 else 1558 iwl_set_bit(trans, CSR_GP_CNTRL, 1559 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1560 1561 ret = iwl_finish_nic_init(trans); 1562 if (ret) 1563 return ret; 1564 1565 /* 1566 * Reconfigure IVAR table in case of MSIX or reset ict table in 1567 * MSI mode since HW reset erased it. 1568 * Also enables interrupts - none will happen as 1569 * the device doesn't know we're waking it up, only when 1570 * the opmode actually tells it after this call. 1571 */ 1572 iwl_pcie_conf_msix_hw(trans_pcie); 1573 if (!trans_pcie->msix_enabled) 1574 iwl_pcie_reset_ict(trans); 1575 iwl_enable_interrupts(trans); 1576 1577 iwl_pcie_set_pwr(trans, false); 1578 1579 if (!reset) { 1580 iwl_clear_bit(trans, CSR_GP_CNTRL, 1581 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1582 } else { 1583 iwl_trans_pcie_tx_reset(trans); 1584 1585 ret = iwl_pcie_rx_init(trans); 1586 if (ret) { 1587 IWL_ERR(trans, 1588 "Failed to resume the device (RX reset)\n"); 1589 return ret; 1590 } 1591 } 1592 1593 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1594 iwl_read_umac_prph(trans, WFPM_GP2)); 1595 1596 val = iwl_read32(trans, CSR_RESET); 1597 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1598 *status = IWL_D3_STATUS_RESET; 1599 else 1600 *status = IWL_D3_STATUS_ALIVE; 1601 1602 out: 1603 if (*status == IWL_D3_STATUS_ALIVE) 1604 ret = iwl_pcie_d3_handshake(trans, false); 1605 else 1606 trans->state = IWL_TRANS_NO_FW; 1607 1608 return ret; 1609 } 1610 1611 static void 1612 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1613 struct iwl_trans *trans, 1614 const struct iwl_mac_cfg *mac_cfg, 1615 struct iwl_trans_info *info) 1616 { 1617 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1618 int max_irqs, num_irqs, i, ret; 1619 u16 pci_cmd; 1620 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1621 1622 if (!mac_cfg->mq_rx_supported) 1623 goto enable_msi; 1624 1625 if (mac_cfg->device_family <= IWL_DEVICE_FAMILY_9000) 1626 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1627 1628 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1629 for (i = 0; i < max_irqs; i++) 1630 trans_pcie->msix_entries[i].entry = i; 1631 1632 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1633 MSIX_MIN_INTERRUPT_VECTORS, 1634 max_irqs); 1635 if (num_irqs < 0) { 1636 IWL_DEBUG_INFO(trans, 1637 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1638 num_irqs); 1639 goto enable_msi; 1640 } 1641 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1642 1643 IWL_DEBUG_INFO(trans, 1644 "MSI-X enabled. %d interrupt vectors were allocated\n", 1645 num_irqs); 1646 1647 /* 1648 * In case the OS provides fewer interrupts than requested, different 1649 * causes will share the same interrupt vector as follows: 1650 * One interrupt less: non rx causes shared with FBQ. 1651 * Two interrupts less: non rx causes shared with FBQ and RSS. 1652 * More than two interrupts: we will use fewer RSS queues. 1653 */ 1654 if (num_irqs <= max_irqs - 2) { 1655 info->num_rxqs = num_irqs + 1; 1656 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1657 IWL_SHARED_IRQ_FIRST_RSS; 1658 } else if (num_irqs == max_irqs - 1) { 1659 info->num_rxqs = num_irqs; 1660 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1661 } else { 1662 info->num_rxqs = num_irqs - 1; 1663 } 1664 1665 IWL_DEBUG_INFO(trans, 1666 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1667 info->num_rxqs, trans_pcie->shared_vec_mask); 1668 1669 WARN_ON(info->num_rxqs > IWL_MAX_RX_HW_QUEUES); 1670 1671 trans_pcie->alloc_vecs = num_irqs; 1672 trans_pcie->msix_enabled = true; 1673 return; 1674 1675 enable_msi: 1676 info->num_rxqs = 1; 1677 ret = pci_enable_msi(pdev); 1678 if (ret) { 1679 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1680 /* enable rfkill interrupt: hw bug w/a */ 1681 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1682 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1683 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1684 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1685 } 1686 } 1687 } 1688 1689 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans, 1690 struct iwl_trans_info *info) 1691 { 1692 #if defined(CONFIG_SMP) 1693 int iter_rx_q, i, ret, cpu, offset; 1694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1695 1696 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1697 iter_rx_q = info->num_rxqs - 1 + i; 1698 offset = 1 + i; 1699 for (; i < iter_rx_q ; i++) { 1700 /* 1701 * Get the cpu prior to the place to search 1702 * (i.e. return will be > i - 1). 1703 */ 1704 cpu = cpumask_next(i - offset, cpu_online_mask); 1705 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1706 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1707 &trans_pcie->affinity_mask[i]); 1708 if (ret) 1709 IWL_ERR(trans_pcie->trans, 1710 "Failed to set affinity mask for IRQ %d\n", 1711 trans_pcie->msix_entries[i].vector); 1712 } 1713 #endif 1714 } 1715 1716 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1717 struct iwl_trans_pcie *trans_pcie, 1718 struct iwl_trans_info *info) 1719 { 1720 int i; 1721 1722 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1723 int ret; 1724 struct msix_entry *msix_entry; 1725 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1726 1727 if (!qname) 1728 return -ENOMEM; 1729 1730 msix_entry = &trans_pcie->msix_entries[i]; 1731 ret = devm_request_threaded_irq(&pdev->dev, 1732 msix_entry->vector, 1733 iwl_pcie_msix_isr, 1734 (i == trans_pcie->def_irq) ? 1735 iwl_pcie_irq_msix_handler : 1736 iwl_pcie_irq_rx_msix_handler, 1737 IRQF_SHARED, 1738 qname, 1739 msix_entry); 1740 if (ret) { 1741 IWL_ERR(trans_pcie->trans, 1742 "Error allocating IRQ %d\n", i); 1743 1744 return ret; 1745 } 1746 } 1747 iwl_pcie_irq_set_affinity(trans_pcie->trans, info); 1748 1749 return 0; 1750 } 1751 1752 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1753 { 1754 u32 hpm, wprot; 1755 1756 switch (trans->mac_cfg->device_family) { 1757 case IWL_DEVICE_FAMILY_9000: 1758 wprot = PREG_PRPH_WPROT_9000; 1759 break; 1760 case IWL_DEVICE_FAMILY_22000: 1761 wprot = PREG_PRPH_WPROT_22000; 1762 break; 1763 default: 1764 return 0; 1765 } 1766 1767 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1768 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { 1769 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1770 1771 if (wprot_val & PREG_WFPM_ACCESS) { 1772 IWL_ERR(trans, 1773 "Error, can not clear persistence bit\n"); 1774 return -EPERM; 1775 } 1776 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1777 hpm & ~PERSISTENCE_BIT); 1778 } 1779 1780 return 0; 1781 } 1782 1783 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1784 { 1785 int ret; 1786 1787 ret = iwl_finish_nic_init(trans); 1788 if (ret < 0) 1789 return ret; 1790 1791 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1792 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1793 udelay(20); 1794 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1795 HPM_HIPM_GEN_CFG_CR_PG_EN | 1796 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1797 udelay(20); 1798 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1799 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1800 1801 return iwl_trans_pcie_sw_reset(trans, true); 1802 } 1803 1804 int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1805 { 1806 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1807 int err; 1808 1809 lockdep_assert_held(&trans_pcie->mutex); 1810 1811 err = iwl_pcie_prepare_card_hw(trans); 1812 if (err) { 1813 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1814 return err; 1815 } 1816 1817 err = iwl_trans_pcie_clear_persistence_bit(trans); 1818 if (err) 1819 return err; 1820 1821 err = iwl_trans_pcie_sw_reset(trans, true); 1822 if (err) 1823 return err; 1824 1825 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1826 trans->mac_cfg->integrated) { 1827 err = iwl_pcie_gen2_force_power_gating(trans); 1828 if (err) 1829 return err; 1830 } 1831 1832 err = iwl_pcie_apm_init(trans); 1833 if (err) 1834 return err; 1835 1836 iwl_pcie_init_msix(trans_pcie); 1837 1838 /* From now on, the op_mode will be kept updated about RF kill state */ 1839 iwl_enable_rfkill_int(trans); 1840 1841 trans_pcie->opmode_down = false; 1842 1843 /* Set is_down to false here so that...*/ 1844 trans_pcie->is_down = false; 1845 1846 /* ...rfkill can call stop_device and set it false if needed */ 1847 iwl_pcie_check_hw_rf_kill(trans); 1848 1849 return 0; 1850 } 1851 1852 int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1853 { 1854 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1855 int ret; 1856 1857 mutex_lock(&trans_pcie->mutex); 1858 ret = _iwl_trans_pcie_start_hw(trans); 1859 mutex_unlock(&trans_pcie->mutex); 1860 1861 return ret; 1862 } 1863 1864 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1865 { 1866 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1867 1868 mutex_lock(&trans_pcie->mutex); 1869 1870 /* disable interrupts - don't enable HW RF kill interrupt */ 1871 iwl_disable_interrupts(trans); 1872 1873 iwl_pcie_apm_stop(trans, true); 1874 1875 iwl_disable_interrupts(trans); 1876 1877 iwl_pcie_disable_ict(trans); 1878 1879 mutex_unlock(&trans_pcie->mutex); 1880 1881 iwl_pcie_synchronize_irqs(trans); 1882 } 1883 1884 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1885 { 1886 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1887 } 1888 1889 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1890 { 1891 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1892 } 1893 1894 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1895 { 1896 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1897 } 1898 1899 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1900 { 1901 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1902 return 0x00FFFFFF; 1903 else 1904 return 0x000FFFFF; 1905 } 1906 1907 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1908 { 1909 u32 mask = iwl_trans_pcie_prph_msk(trans); 1910 1911 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1912 ((reg & mask) | (3 << 24))); 1913 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1914 } 1915 1916 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val) 1917 { 1918 u32 mask = iwl_trans_pcie_prph_msk(trans); 1919 1920 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1921 ((addr & mask) | (3 << 24))); 1922 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1923 } 1924 1925 void iwl_trans_pcie_op_mode_enter(struct iwl_trans *trans) 1926 { 1927 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1928 1929 /* free all first - we might be reconfigured for a different size */ 1930 iwl_pcie_free_rbs_pool(trans); 1931 1932 trans_pcie->rx_page_order = 1933 iwl_trans_get_rb_size_order(trans->conf.rx_buf_size); 1934 trans_pcie->rx_buf_bytes = 1935 iwl_trans_get_rb_size(trans->conf.rx_buf_size); 1936 } 1937 1938 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 1939 struct device *dev) 1940 { 1941 u8 i; 1942 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 1943 1944 /* free DRAM payloads */ 1945 for (i = 0; i < dram_regions->n_regions; i++) { 1946 dma_free_coherent(dev, dram_regions->drams[i].size, 1947 dram_regions->drams[i].block, 1948 dram_regions->drams[i].physical); 1949 } 1950 dram_regions->n_regions = 0; 1951 1952 /* free DRAM addresses array */ 1953 if (desc_dram->block) { 1954 dma_free_coherent(dev, desc_dram->size, 1955 desc_dram->block, 1956 desc_dram->physical); 1957 } 1958 memset(desc_dram, 0, sizeof(*desc_dram)); 1959 } 1960 1961 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) 1962 { 1963 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1964 1965 iwl_pcie_free_dma_ptr(trans, &trans_pcie->invalid_tx_cmd); 1966 } 1967 1968 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) 1969 { 1970 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1971 struct iwl_cmd_header_wide bad_cmd = { 1972 .cmd = INVALID_WR_PTR_CMD, 1973 .group_id = DEBUG_GROUP, 1974 .sequence = cpu_to_le16(0xffff), 1975 .length = cpu_to_le16(0), 1976 .version = 0, 1977 }; 1978 int ret; 1979 1980 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->invalid_tx_cmd, 1981 sizeof(bad_cmd)); 1982 if (ret) 1983 return ret; 1984 memcpy(trans_pcie->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); 1985 return 0; 1986 } 1987 1988 void iwl_trans_pcie_free(struct iwl_trans *trans) 1989 { 1990 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1991 int i; 1992 1993 iwl_pcie_synchronize_irqs(trans); 1994 1995 if (trans->mac_cfg->gen2) 1996 iwl_txq_gen2_tx_free(trans); 1997 else 1998 iwl_pcie_tx_free(trans); 1999 iwl_pcie_rx_free(trans); 2000 2001 if (trans_pcie->rba.alloc_wq) { 2002 destroy_workqueue(trans_pcie->rba.alloc_wq); 2003 trans_pcie->rba.alloc_wq = NULL; 2004 } 2005 2006 if (trans_pcie->msix_enabled) { 2007 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2008 irq_set_affinity_hint( 2009 trans_pcie->msix_entries[i].vector, 2010 NULL); 2011 } 2012 2013 trans_pcie->msix_enabled = false; 2014 } else { 2015 iwl_pcie_free_ict(trans); 2016 } 2017 2018 free_netdev(trans_pcie->napi_dev); 2019 2020 iwl_pcie_free_invalid_tx_cmd(trans); 2021 2022 iwl_pcie_free_fw_monitor(trans); 2023 2024 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, 2025 trans->dev); 2026 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, 2027 trans->dev); 2028 2029 mutex_destroy(&trans_pcie->mutex); 2030 2031 if (trans_pcie->txqs.tso_hdr_page) { 2032 for_each_possible_cpu(i) { 2033 struct iwl_tso_hdr_page *p = 2034 per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i); 2035 2036 if (p && p->page) 2037 __free_page(p->page); 2038 } 2039 2040 free_percpu(trans_pcie->txqs.tso_hdr_page); 2041 } 2042 2043 iwl_trans_free(trans); 2044 } 2045 2046 static union acpi_object * 2047 iwl_trans_pcie_call_prod_reset_dsm(struct pci_dev *pdev, u16 cmd, u16 value) 2048 { 2049 #ifdef CONFIG_ACPI 2050 struct iwl_dsm_internal_product_reset_cmd pldr_arg = { 2051 .cmd = cmd, 2052 .value = value, 2053 }; 2054 union acpi_object arg = { 2055 .buffer.type = ACPI_TYPE_BUFFER, 2056 .buffer.length = sizeof(pldr_arg), 2057 .buffer.pointer = (void *)&pldr_arg, 2058 }; 2059 static const guid_t dsm_guid = GUID_INIT(0x7266172C, 0x220B, 0x4B29, 2060 0x81, 0x4F, 0x75, 0xE4, 2061 0xDD, 0x26, 0xB5, 0xFD); 2062 2063 if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &dsm_guid, ACPI_DSM_REV, 2064 DSM_INTERNAL_FUNC_PRODUCT_RESET)) 2065 return ERR_PTR(-ENODEV); 2066 2067 return iwl_acpi_get_dsm_object(&pdev->dev, ACPI_DSM_REV, 2068 DSM_INTERNAL_FUNC_PRODUCT_RESET, 2069 &arg, &dsm_guid); 2070 #else 2071 return ERR_PTR(-EOPNOTSUPP); 2072 #endif 2073 } 2074 2075 void iwl_trans_pcie_check_product_reset_mode(struct pci_dev *pdev) 2076 { 2077 union acpi_object *res; 2078 2079 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2080 DSM_INTERNAL_PLDR_CMD_GET_MODE, 2081 0); 2082 if (IS_ERR(res)) 2083 return; 2084 2085 if (res->type != ACPI_TYPE_INTEGER) 2086 IWL_ERR_DEV(&pdev->dev, 2087 "unexpected return type from product reset DSM\n"); 2088 else 2089 IWL_DEBUG_DEV_POWER(&pdev->dev, 2090 "product reset mode is 0x%llx\n", 2091 res->integer.value); 2092 2093 ACPI_FREE(res); 2094 } 2095 2096 static void iwl_trans_pcie_set_product_reset(struct pci_dev *pdev, bool enable, 2097 bool integrated) 2098 { 2099 union acpi_object *res; 2100 u16 mode = enable ? DSM_INTERNAL_PLDR_MODE_EN_PROD_RESET : 0; 2101 2102 if (!integrated) 2103 mode |= DSM_INTERNAL_PLDR_MODE_EN_WIFI_FLR | 2104 DSM_INTERNAL_PLDR_MODE_EN_BT_OFF_ON; 2105 2106 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2107 DSM_INTERNAL_PLDR_CMD_SET_MODE, 2108 mode); 2109 if (IS_ERR(res)) { 2110 if (enable) 2111 IWL_ERR_DEV(&pdev->dev, 2112 "ACPI _DSM not available (%d), cannot do product reset\n", 2113 (int)PTR_ERR(res)); 2114 return; 2115 } 2116 2117 ACPI_FREE(res); 2118 IWL_DEBUG_DEV_POWER(&pdev->dev, "%sabled product reset via DSM\n", 2119 enable ? "En" : "Dis"); 2120 iwl_trans_pcie_check_product_reset_mode(pdev); 2121 } 2122 2123 void iwl_trans_pcie_check_product_reset_status(struct pci_dev *pdev) 2124 { 2125 union acpi_object *res; 2126 2127 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2128 DSM_INTERNAL_PLDR_CMD_GET_STATUS, 2129 0); 2130 if (IS_ERR(res)) 2131 return; 2132 2133 if (res->type != ACPI_TYPE_INTEGER) 2134 IWL_ERR_DEV(&pdev->dev, 2135 "unexpected return type from product reset DSM\n"); 2136 else 2137 IWL_DEBUG_DEV_POWER(&pdev->dev, 2138 "product reset status is 0x%llx\n", 2139 res->integer.value); 2140 2141 ACPI_FREE(res); 2142 } 2143 2144 static void iwl_trans_pcie_call_reset(struct pci_dev *pdev) 2145 { 2146 #ifdef CONFIG_ACPI 2147 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2148 union acpi_object *p, *ref; 2149 acpi_status status; 2150 int ret = -EINVAL; 2151 2152 status = acpi_evaluate_object(ACPI_HANDLE(&pdev->dev), 2153 "_PRR", NULL, &buffer); 2154 if (ACPI_FAILURE(status)) { 2155 IWL_DEBUG_DEV_POWER(&pdev->dev, "No _PRR method found\n"); 2156 goto out; 2157 } 2158 p = buffer.pointer; 2159 2160 if (p->type != ACPI_TYPE_PACKAGE || p->package.count != 1) { 2161 pci_err(pdev, "Bad _PRR return type\n"); 2162 goto out; 2163 } 2164 2165 ref = &p->package.elements[0]; 2166 if (ref->type != ACPI_TYPE_LOCAL_REFERENCE) { 2167 pci_err(pdev, "_PRR wasn't a reference\n"); 2168 goto out; 2169 } 2170 2171 status = acpi_evaluate_object(ref->reference.handle, 2172 "_RST", NULL, NULL); 2173 if (ACPI_FAILURE(status)) { 2174 pci_err(pdev, 2175 "Failed to call _RST on object returned by _PRR (%d)\n", 2176 status); 2177 goto out; 2178 } 2179 ret = 0; 2180 out: 2181 kfree(buffer.pointer); 2182 if (!ret) { 2183 IWL_DEBUG_DEV_POWER(&pdev->dev, "called _RST on _PRR object\n"); 2184 return; 2185 } 2186 IWL_DEBUG_DEV_POWER(&pdev->dev, 2187 "No BIOS support, using pci_reset_function()\n"); 2188 #endif 2189 pci_reset_function(pdev); 2190 } 2191 2192 struct iwl_trans_pcie_removal { 2193 struct pci_dev *pdev; 2194 struct work_struct work; 2195 enum iwl_reset_mode mode; 2196 bool integrated; 2197 }; 2198 2199 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2200 { 2201 struct iwl_trans_pcie_removal *removal = 2202 container_of(wk, struct iwl_trans_pcie_removal, work); 2203 struct pci_dev *pdev = removal->pdev; 2204 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2205 struct pci_bus *bus; 2206 2207 pci_lock_rescan_remove(); 2208 2209 bus = pdev->bus; 2210 /* in this case, something else already removed the device */ 2211 if (!bus) 2212 goto out; 2213 2214 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2215 2216 if (removal->mode == IWL_RESET_MODE_PROD_RESET) { 2217 struct pci_dev *bt = NULL; 2218 2219 if (!removal->integrated) { 2220 /* discrete devices have WiFi/BT at function 0/1 */ 2221 int slot = PCI_SLOT(pdev->devfn); 2222 int func = PCI_FUNC(pdev->devfn); 2223 2224 if (func == 0) 2225 bt = pci_get_slot(bus, PCI_DEVFN(slot, 1)); 2226 else 2227 pci_info(pdev, "Unexpected function %d\n", 2228 func); 2229 } else { 2230 /* on integrated we have to look up by ID (same bus) */ 2231 static const struct pci_device_id bt_device_ids[] = { 2232 #define BT_DEV(_id) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, _id) } 2233 BT_DEV(0xA876), /* LNL */ 2234 BT_DEV(0xE476), /* PTL-P */ 2235 BT_DEV(0xE376), /* PTL-H */ 2236 BT_DEV(0xD346), /* NVL-H */ 2237 BT_DEV(0x6E74), /* NVL-S */ 2238 BT_DEV(0x4D76), /* WCL */ 2239 BT_DEV(0xD246), /* RZL-H */ 2240 BT_DEV(0x6C46), /* RZL-M */ 2241 {} 2242 }; 2243 struct pci_dev *tmp = NULL; 2244 2245 for_each_pci_dev(tmp) { 2246 if (tmp->bus != bus) 2247 continue; 2248 2249 if (pci_match_id(bt_device_ids, tmp)) { 2250 bt = tmp; 2251 break; 2252 } 2253 } 2254 } 2255 2256 if (bt) { 2257 pci_info(bt, "Removal by WiFi due to product reset\n"); 2258 pci_stop_and_remove_bus_device(bt); 2259 pci_dev_put(bt); 2260 } 2261 } 2262 2263 iwl_trans_pcie_set_product_reset(pdev, 2264 removal->mode == 2265 IWL_RESET_MODE_PROD_RESET, 2266 removal->integrated); 2267 if (removal->mode >= IWL_RESET_MODE_FUNC_RESET) 2268 iwl_trans_pcie_call_reset(pdev); 2269 2270 pci_stop_and_remove_bus_device(pdev); 2271 pci_dev_put(pdev); 2272 2273 if (removal->mode >= IWL_RESET_MODE_RESCAN) { 2274 if (bus->parent) 2275 bus = bus->parent; 2276 pci_rescan_bus(bus); 2277 } 2278 2279 out: 2280 pci_unlock_rescan_remove(); 2281 2282 kfree(removal); 2283 module_put(THIS_MODULE); 2284 } 2285 2286 void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode) 2287 { 2288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2289 struct iwl_trans_pcie_removal *removal; 2290 char _msg = 0, *msg = &_msg; 2291 2292 if (WARN_ON(mode < IWL_RESET_MODE_REMOVE_ONLY || 2293 mode == IWL_RESET_MODE_BACKOFF)) 2294 return; 2295 2296 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2297 return; 2298 2299 if (trans_pcie->me_present && mode == IWL_RESET_MODE_PROD_RESET) { 2300 mode = IWL_RESET_MODE_FUNC_RESET; 2301 if (trans_pcie->me_present < 0) 2302 msg = " instead of product reset as ME may be present"; 2303 else 2304 msg = " instead of product reset as ME is present"; 2305 } 2306 2307 IWL_INFO(trans, "scheduling reset (mode=%d%s)\n", mode, msg); 2308 2309 iwl_pcie_dump_csr(trans); 2310 2311 /* 2312 * get a module reference to avoid doing this 2313 * while unloading anyway and to avoid 2314 * scheduling a work with code that's being 2315 * removed. 2316 */ 2317 if (!try_module_get(THIS_MODULE)) { 2318 IWL_ERR(trans, 2319 "Module is being unloaded - abort\n"); 2320 return; 2321 } 2322 2323 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2324 if (!removal) { 2325 module_put(THIS_MODULE); 2326 return; 2327 } 2328 /* 2329 * we don't need to clear this flag, because 2330 * the trans will be freed and reallocated. 2331 */ 2332 set_bit(STATUS_TRANS_DEAD, &trans->status); 2333 2334 removal->pdev = to_pci_dev(trans->dev); 2335 removal->mode = mode; 2336 removal->integrated = trans->mac_cfg->integrated; 2337 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2338 pci_dev_get(removal->pdev); 2339 schedule_work(&removal->work); 2340 } 2341 EXPORT_SYMBOL(iwl_trans_pcie_reset); 2342 2343 /* 2344 * This version doesn't disable BHs but rather assumes they're 2345 * already disabled. 2346 */ 2347 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent) 2348 { 2349 int ret; 2350 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2351 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2352 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2353 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2354 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2355 2356 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2357 return false; 2358 2359 spin_lock(&trans_pcie->reg_lock); 2360 2361 if (trans_pcie->cmd_hold_nic_awake) 2362 goto out; 2363 2364 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2365 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2366 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2367 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2368 } 2369 2370 /* this bit wakes up the NIC */ 2371 iwl_trans_set_bit(trans, CSR_GP_CNTRL, write); 2372 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2373 udelay(2); 2374 2375 /* 2376 * These bits say the device is running, and should keep running for 2377 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2378 * but they do not indicate that embedded SRAM is restored yet; 2379 * HW with volatile SRAM must save/restore contents to/from 2380 * host DRAM when sleeping/waking for power-saving. 2381 * Each direction takes approximately 1/4 millisecond; with this 2382 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2383 * series of register accesses are expected (e.g. reading Event Log), 2384 * to keep device from sleeping. 2385 * 2386 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2387 * SRAM is okay/restored. We don't check that here because this call 2388 * is just for hardware register access; but GP1 MAC_SLEEP 2389 * check is a good idea before accessing the SRAM of HW with 2390 * volatile SRAM (e.g. reading Event Log). 2391 * 2392 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2393 * and do not save/restore SRAM when power cycling. 2394 */ 2395 ret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000); 2396 if (unlikely(ret)) { 2397 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2398 2399 if (silent) { 2400 spin_unlock(&trans_pcie->reg_lock); 2401 return false; 2402 } 2403 2404 WARN_ONCE(1, 2405 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2406 cntrl); 2407 2408 iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev); 2409 2410 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2411 iwl_trans_pcie_reset(trans, 2412 IWL_RESET_MODE_REMOVE_ONLY); 2413 else 2414 iwl_write32(trans, CSR_RESET, 2415 CSR_RESET_REG_FLAG_FORCE_NMI); 2416 2417 spin_unlock(&trans_pcie->reg_lock); 2418 return false; 2419 } 2420 2421 out: 2422 /* 2423 * Fool sparse by faking we release the lock - sparse will 2424 * track nic_access anyway. 2425 */ 2426 __release(&trans_pcie->reg_lock); 2427 return true; 2428 } 2429 2430 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2431 { 2432 bool ret; 2433 2434 local_bh_disable(); 2435 ret = __iwl_trans_pcie_grab_nic_access(trans, false); 2436 if (ret) { 2437 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2438 return ret; 2439 } 2440 local_bh_enable(); 2441 return false; 2442 } 2443 2444 void __releases(nic_access_nobh) 2445 iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2446 { 2447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2448 2449 lockdep_assert_held(&trans_pcie->reg_lock); 2450 2451 /* 2452 * Fool sparse by faking we acquiring the lock - sparse will 2453 * track nic_access anyway. 2454 */ 2455 __acquire(&trans_pcie->reg_lock); 2456 2457 if (trans_pcie->cmd_hold_nic_awake) 2458 goto out; 2459 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2460 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 2461 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2462 else 2463 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 2464 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2465 /* 2466 * Above we read the CSR_GP_CNTRL register, which will flush 2467 * any previous writes, but we need the write that clears the 2468 * MAC_ACCESS_REQ bit to be performed before any other writes 2469 * scheduled on different CPUs (after we drop reg_lock). 2470 */ 2471 out: 2472 __release(nic_access_nobh); 2473 spin_unlock_bh(&trans_pcie->reg_lock); 2474 } 2475 2476 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2477 void *buf, int dwords) 2478 { 2479 #define IWL_MAX_HW_ERRS 5 2480 unsigned int num_consec_hw_errors = 0; 2481 int offs = 0; 2482 u32 *vals = buf; 2483 2484 while (offs < dwords) { 2485 /* limit the time we spin here under lock to 1/2s */ 2486 unsigned long end = jiffies + HZ / 2; 2487 bool resched = false; 2488 2489 if (iwl_trans_grab_nic_access(trans)) { 2490 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2491 addr + 4 * offs); 2492 2493 while (offs < dwords) { 2494 vals[offs] = iwl_read32(trans, 2495 HBUS_TARG_MEM_RDAT); 2496 2497 if (iwl_trans_is_hw_error_value(vals[offs])) 2498 num_consec_hw_errors++; 2499 else 2500 num_consec_hw_errors = 0; 2501 2502 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) { 2503 iwl_trans_release_nic_access(trans); 2504 return -EIO; 2505 } 2506 2507 offs++; 2508 2509 if (time_after(jiffies, end)) { 2510 resched = true; 2511 break; 2512 } 2513 } 2514 iwl_trans_release_nic_access(trans); 2515 2516 if (resched) 2517 cond_resched(); 2518 } else { 2519 return -EBUSY; 2520 } 2521 } 2522 2523 return 0; 2524 } 2525 2526 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2527 u32 *val) 2528 { 2529 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2530 ofs, val); 2531 } 2532 2533 #define IWL_FLUSH_WAIT_MS 2000 2534 2535 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2536 struct iwl_trans_rxq_dma_data *data) 2537 { 2538 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2539 2540 if (queue >= trans->info.num_rxqs || !trans_pcie->rxq) 2541 return -EINVAL; 2542 2543 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2544 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2545 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2546 data->fr_bd_wid = 0; 2547 2548 return 0; 2549 } 2550 2551 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2552 { 2553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2554 struct iwl_txq *txq; 2555 unsigned long now = jiffies; 2556 bool overflow_tx; 2557 u8 wr_ptr; 2558 2559 /* Make sure the NIC is still alive in the bus */ 2560 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2561 return -ENODEV; 2562 2563 if (!test_bit(txq_idx, trans_pcie->txqs.queue_used)) 2564 return -EINVAL; 2565 2566 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2567 txq = trans_pcie->txqs.txq[txq_idx]; 2568 2569 spin_lock_bh(&txq->lock); 2570 overflow_tx = txq->overflow_tx || 2571 !skb_queue_empty(&txq->overflow_q); 2572 spin_unlock_bh(&txq->lock); 2573 2574 wr_ptr = READ_ONCE(txq->write_ptr); 2575 2576 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2577 overflow_tx) && 2578 !time_after(jiffies, 2579 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2580 u8 write_ptr = READ_ONCE(txq->write_ptr); 2581 2582 /* 2583 * If write pointer moved during the wait, warn only 2584 * if the TX came from op mode. In case TX came from 2585 * trans layer (overflow TX) don't warn. 2586 */ 2587 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2588 "WR pointer moved while flushing %d -> %d\n", 2589 wr_ptr, write_ptr)) 2590 return -ETIMEDOUT; 2591 wr_ptr = write_ptr; 2592 2593 usleep_range(1000, 2000); 2594 2595 spin_lock_bh(&txq->lock); 2596 overflow_tx = txq->overflow_tx || 2597 !skb_queue_empty(&txq->overflow_q); 2598 spin_unlock_bh(&txq->lock); 2599 } 2600 2601 if (txq->read_ptr != txq->write_ptr) { 2602 IWL_ERR(trans, 2603 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2604 iwl_txq_log_scd_error(trans, txq); 2605 return -ETIMEDOUT; 2606 } 2607 2608 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2609 2610 return 0; 2611 } 2612 2613 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2614 { 2615 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2616 int cnt; 2617 int ret = 0; 2618 2619 /* waiting for all the tx frames complete might take a while */ 2620 for (cnt = 0; 2621 cnt < trans->mac_cfg->base->num_of_queues; 2622 cnt++) { 2623 2624 if (cnt == trans->conf.cmd_queue) 2625 continue; 2626 if (!test_bit(cnt, trans_pcie->txqs.queue_used)) 2627 continue; 2628 if (!(BIT(cnt) & txq_bm)) 2629 continue; 2630 2631 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2632 if (ret) 2633 break; 2634 } 2635 2636 return ret; 2637 } 2638 2639 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2640 u32 mask, u32 value) 2641 { 2642 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2643 2644 spin_lock_bh(&trans_pcie->reg_lock); 2645 _iwl_trans_set_bits_mask(trans, reg, mask, value); 2646 spin_unlock_bh(&trans_pcie->reg_lock); 2647 } 2648 2649 static const char *get_csr_string(int cmd) 2650 { 2651 #define IWL_CMD(x) case x: return #x 2652 switch (cmd) { 2653 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2654 IWL_CMD(CSR_INT_COALESCING); 2655 IWL_CMD(CSR_INT); 2656 IWL_CMD(CSR_INT_MASK); 2657 IWL_CMD(CSR_FH_INT_STATUS); 2658 IWL_CMD(CSR_GPIO_IN); 2659 IWL_CMD(CSR_RESET); 2660 IWL_CMD(CSR_GP_CNTRL); 2661 IWL_CMD(CSR_HW_REV); 2662 IWL_CMD(CSR_EEPROM_REG); 2663 IWL_CMD(CSR_EEPROM_GP); 2664 IWL_CMD(CSR_OTP_GP_REG); 2665 IWL_CMD(CSR_GIO_REG); 2666 IWL_CMD(CSR_GP_UCODE_REG); 2667 IWL_CMD(CSR_GP_DRIVER_REG); 2668 IWL_CMD(CSR_UCODE_DRV_GP1); 2669 IWL_CMD(CSR_UCODE_DRV_GP2); 2670 IWL_CMD(CSR_LED_REG); 2671 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2672 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2673 IWL_CMD(CSR_ANA_PLL_CFG); 2674 IWL_CMD(CSR_HW_REV_WA_REG); 2675 IWL_CMD(CSR_MONITOR_STATUS_REG); 2676 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2677 default: 2678 return "UNKNOWN"; 2679 } 2680 #undef IWL_CMD 2681 } 2682 2683 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2684 { 2685 int i; 2686 static const u32 csr_tbl[] = { 2687 CSR_HW_IF_CONFIG_REG, 2688 CSR_INT_COALESCING, 2689 CSR_INT, 2690 CSR_INT_MASK, 2691 CSR_FH_INT_STATUS, 2692 CSR_GPIO_IN, 2693 CSR_RESET, 2694 CSR_GP_CNTRL, 2695 CSR_HW_REV, 2696 CSR_EEPROM_REG, 2697 CSR_EEPROM_GP, 2698 CSR_OTP_GP_REG, 2699 CSR_GIO_REG, 2700 CSR_GP_UCODE_REG, 2701 CSR_GP_DRIVER_REG, 2702 CSR_UCODE_DRV_GP1, 2703 CSR_UCODE_DRV_GP2, 2704 CSR_LED_REG, 2705 CSR_DRAM_INT_TBL_REG, 2706 CSR_GIO_CHICKEN_BITS, 2707 CSR_ANA_PLL_CFG, 2708 CSR_MONITOR_STATUS_REG, 2709 CSR_HW_REV_WA_REG, 2710 CSR_DBG_HPET_MEM_REG 2711 }; 2712 IWL_ERR(trans, "CSR values:\n"); 2713 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2714 "CSR_INT_PERIODIC_REG)\n"); 2715 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2716 IWL_ERR(trans, " %25s: 0X%08x\n", 2717 get_csr_string(csr_tbl[i]), 2718 iwl_read32(trans, csr_tbl[i])); 2719 } 2720 } 2721 2722 #ifdef CONFIG_IWLWIFI_DEBUGFS 2723 /* create and remove of files */ 2724 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2725 debugfs_create_file(#name, mode, parent, trans, \ 2726 &iwl_dbgfs_##name##_ops); \ 2727 } while (0) 2728 2729 /* file operation */ 2730 #define DEBUGFS_READ_FILE_OPS(name) \ 2731 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2732 .read = iwl_dbgfs_##name##_read, \ 2733 .open = simple_open, \ 2734 .llseek = generic_file_llseek, \ 2735 }; 2736 2737 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2738 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2739 .write = iwl_dbgfs_##name##_write, \ 2740 .open = simple_open, \ 2741 .llseek = generic_file_llseek, \ 2742 }; 2743 2744 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2745 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2746 .write = iwl_dbgfs_##name##_write, \ 2747 .read = iwl_dbgfs_##name##_read, \ 2748 .open = simple_open, \ 2749 .llseek = generic_file_llseek, \ 2750 }; 2751 2752 struct iwl_dbgfs_tx_queue_priv { 2753 struct iwl_trans *trans; 2754 }; 2755 2756 struct iwl_dbgfs_tx_queue_state { 2757 loff_t pos; 2758 }; 2759 2760 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2761 { 2762 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2763 struct iwl_dbgfs_tx_queue_state *state; 2764 2765 if (*pos >= priv->trans->mac_cfg->base->num_of_queues) 2766 return NULL; 2767 2768 state = kmalloc(sizeof(*state), GFP_KERNEL); 2769 if (!state) 2770 return NULL; 2771 state->pos = *pos; 2772 return state; 2773 } 2774 2775 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2776 void *v, loff_t *pos) 2777 { 2778 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2779 struct iwl_dbgfs_tx_queue_state *state = v; 2780 2781 *pos = ++state->pos; 2782 2783 if (*pos >= priv->trans->mac_cfg->base->num_of_queues) 2784 return NULL; 2785 2786 return state; 2787 } 2788 2789 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2790 { 2791 kfree(v); 2792 } 2793 2794 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2795 { 2796 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2797 struct iwl_dbgfs_tx_queue_state *state = v; 2798 struct iwl_trans *trans = priv->trans; 2799 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2800 struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos]; 2801 2802 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2803 (unsigned int)state->pos, 2804 !!test_bit(state->pos, trans_pcie->txqs.queue_used), 2805 !!test_bit(state->pos, trans_pcie->txqs.queue_stopped)); 2806 if (txq) 2807 seq_printf(seq, 2808 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2809 txq->read_ptr, txq->write_ptr, 2810 txq->need_update, txq->frozen, 2811 txq->n_window, txq->ampdu); 2812 else 2813 seq_puts(seq, "(unallocated)"); 2814 2815 if (state->pos == trans->conf.cmd_queue) 2816 seq_puts(seq, " (HCMD)"); 2817 seq_puts(seq, "\n"); 2818 2819 return 0; 2820 } 2821 2822 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2823 .start = iwl_dbgfs_tx_queue_seq_start, 2824 .next = iwl_dbgfs_tx_queue_seq_next, 2825 .stop = iwl_dbgfs_tx_queue_seq_stop, 2826 .show = iwl_dbgfs_tx_queue_seq_show, 2827 }; 2828 2829 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2830 { 2831 struct iwl_dbgfs_tx_queue_priv *priv; 2832 2833 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2834 sizeof(*priv)); 2835 2836 if (!priv) 2837 return -ENOMEM; 2838 2839 priv->trans = inode->i_private; 2840 return 0; 2841 } 2842 2843 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2844 char __user *user_buf, 2845 size_t count, loff_t *ppos) 2846 { 2847 struct iwl_trans *trans = file->private_data; 2848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2849 char *buf; 2850 int pos = 0, i, ret; 2851 size_t bufsz; 2852 2853 bufsz = sizeof(char) * 121 * trans->info.num_rxqs; 2854 2855 if (!trans_pcie->rxq) 2856 return -EAGAIN; 2857 2858 buf = kzalloc(bufsz, GFP_KERNEL); 2859 if (!buf) 2860 return -ENOMEM; 2861 2862 for (i = 0; i < trans->info.num_rxqs && pos < bufsz; i++) { 2863 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2864 2865 spin_lock_bh(&rxq->lock); 2866 2867 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2868 i); 2869 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2870 rxq->read); 2871 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2872 rxq->write); 2873 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2874 rxq->write_actual); 2875 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2876 rxq->need_update); 2877 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2878 rxq->free_count); 2879 if (rxq->rb_stts) { 2880 u32 r = iwl_get_closed_rb_stts(trans, rxq); 2881 pos += scnprintf(buf + pos, bufsz - pos, 2882 "\tclosed_rb_num: %u\n", r); 2883 } else { 2884 pos += scnprintf(buf + pos, bufsz - pos, 2885 "\tclosed_rb_num: Not Allocated\n"); 2886 } 2887 spin_unlock_bh(&rxq->lock); 2888 } 2889 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2890 kfree(buf); 2891 2892 return ret; 2893 } 2894 2895 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2896 char __user *user_buf, 2897 size_t count, loff_t *ppos) 2898 { 2899 struct iwl_trans *trans = file->private_data; 2900 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2901 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2902 2903 int pos = 0; 2904 char *buf; 2905 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2906 ssize_t ret; 2907 2908 buf = kzalloc(bufsz, GFP_KERNEL); 2909 if (!buf) 2910 return -ENOMEM; 2911 2912 pos += scnprintf(buf + pos, bufsz - pos, 2913 "Interrupt Statistics Report:\n"); 2914 2915 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2916 isr_stats->hw); 2917 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2918 isr_stats->sw); 2919 if (isr_stats->sw || isr_stats->hw) { 2920 pos += scnprintf(buf + pos, bufsz - pos, 2921 "\tLast Restarting Code: 0x%X\n", 2922 isr_stats->err_code); 2923 } 2924 #ifdef CONFIG_IWLWIFI_DEBUG 2925 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2926 isr_stats->sch); 2927 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2928 isr_stats->alive); 2929 #endif 2930 pos += scnprintf(buf + pos, bufsz - pos, 2931 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2932 2933 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2934 isr_stats->ctkill); 2935 2936 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2937 isr_stats->wakeup); 2938 2939 pos += scnprintf(buf + pos, bufsz - pos, 2940 "Rx command responses:\t\t %u\n", isr_stats->rx); 2941 2942 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2943 isr_stats->tx); 2944 2945 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2946 isr_stats->unhandled); 2947 2948 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2949 kfree(buf); 2950 return ret; 2951 } 2952 2953 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2954 const char __user *user_buf, 2955 size_t count, loff_t *ppos) 2956 { 2957 struct iwl_trans *trans = file->private_data; 2958 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2959 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2960 u32 reset_flag; 2961 int ret; 2962 2963 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2964 if (ret) 2965 return ret; 2966 if (reset_flag == 0) 2967 memset(isr_stats, 0, sizeof(*isr_stats)); 2968 2969 return count; 2970 } 2971 2972 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2973 const char __user *user_buf, 2974 size_t count, loff_t *ppos) 2975 { 2976 struct iwl_trans *trans = file->private_data; 2977 2978 iwl_pcie_dump_csr(trans); 2979 2980 return count; 2981 } 2982 2983 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2984 char __user *user_buf, 2985 size_t count, loff_t *ppos) 2986 { 2987 struct iwl_trans *trans = file->private_data; 2988 char *buf = NULL; 2989 ssize_t ret; 2990 2991 ret = iwl_dump_fh(trans, &buf); 2992 if (ret < 0) 2993 return ret; 2994 if (!buf) 2995 return -EINVAL; 2996 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2997 kfree(buf); 2998 return ret; 2999 } 3000 3001 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 3002 char __user *user_buf, 3003 size_t count, loff_t *ppos) 3004 { 3005 struct iwl_trans *trans = file->private_data; 3006 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3007 char buf[100]; 3008 int pos; 3009 3010 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 3011 trans_pcie->debug_rfkill, 3012 !(iwl_read32(trans, CSR_GP_CNTRL) & 3013 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 3014 3015 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 3016 } 3017 3018 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 3019 const char __user *user_buf, 3020 size_t count, loff_t *ppos) 3021 { 3022 struct iwl_trans *trans = file->private_data; 3023 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3024 bool new_value; 3025 int ret; 3026 3027 ret = kstrtobool_from_user(user_buf, count, &new_value); 3028 if (ret) 3029 return ret; 3030 if (new_value == trans_pcie->debug_rfkill) 3031 return count; 3032 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 3033 trans_pcie->debug_rfkill, new_value); 3034 trans_pcie->debug_rfkill = new_value; 3035 iwl_pcie_handle_rfkill_irq(trans, false); 3036 3037 return count; 3038 } 3039 3040 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 3041 struct file *file) 3042 { 3043 struct iwl_trans *trans = inode->i_private; 3044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3045 3046 if (!trans->dbg.dest_tlv || 3047 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 3048 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 3049 return -ENOENT; 3050 } 3051 3052 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 3053 return -EBUSY; 3054 3055 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 3056 return simple_open(inode, file); 3057 } 3058 3059 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 3060 struct file *file) 3061 { 3062 struct iwl_trans_pcie *trans_pcie = 3063 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 3064 3065 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 3066 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3067 return 0; 3068 } 3069 3070 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 3071 void *buf, ssize_t *size, 3072 ssize_t *bytes_copied) 3073 { 3074 ssize_t buf_size_left = count - *bytes_copied; 3075 3076 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 3077 if (*size > buf_size_left) 3078 *size = buf_size_left; 3079 3080 *size -= copy_to_user(user_buf, buf, *size); 3081 *bytes_copied += *size; 3082 3083 if (buf_size_left == *size) 3084 return true; 3085 return false; 3086 } 3087 3088 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 3089 char __user *user_buf, 3090 size_t count, loff_t *ppos) 3091 { 3092 struct iwl_trans *trans = file->private_data; 3093 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3094 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 3095 struct cont_rec *data = &trans_pcie->fw_mon_data; 3096 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 3097 ssize_t size, bytes_copied = 0; 3098 bool b_full; 3099 3100 if (trans->dbg.dest_tlv) { 3101 write_ptr_addr = 3102 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3103 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3104 } else { 3105 write_ptr_addr = MON_BUFF_WRPTR; 3106 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 3107 } 3108 3109 if (unlikely(!trans->dbg.rec_on)) 3110 return 0; 3111 3112 mutex_lock(&data->mutex); 3113 if (data->state == 3114 IWL_FW_MON_DBGFS_STATE_DISABLED) { 3115 mutex_unlock(&data->mutex); 3116 return 0; 3117 } 3118 3119 /* write_ptr position in bytes rather then DW */ 3120 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 3121 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 3122 3123 if (data->prev_wrap_cnt == wrap_cnt) { 3124 size = write_ptr - data->prev_wr_ptr; 3125 curr_buf = cpu_addr + data->prev_wr_ptr; 3126 b_full = iwl_write_to_user_buf(user_buf, count, 3127 curr_buf, &size, 3128 &bytes_copied); 3129 data->prev_wr_ptr += size; 3130 3131 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 3132 write_ptr < data->prev_wr_ptr) { 3133 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 3134 curr_buf = cpu_addr + data->prev_wr_ptr; 3135 b_full = iwl_write_to_user_buf(user_buf, count, 3136 curr_buf, &size, 3137 &bytes_copied); 3138 data->prev_wr_ptr += size; 3139 3140 if (!b_full) { 3141 size = write_ptr; 3142 b_full = iwl_write_to_user_buf(user_buf, count, 3143 cpu_addr, &size, 3144 &bytes_copied); 3145 data->prev_wr_ptr = size; 3146 data->prev_wrap_cnt++; 3147 } 3148 } else { 3149 if (data->prev_wrap_cnt == wrap_cnt - 1 && 3150 write_ptr > data->prev_wr_ptr) 3151 IWL_WARN(trans, 3152 "write pointer passed previous write pointer, start copying from the beginning\n"); 3153 else if (!unlikely(data->prev_wrap_cnt == 0 && 3154 data->prev_wr_ptr == 0)) 3155 IWL_WARN(trans, 3156 "monitor data is out of sync, start copying from the beginning\n"); 3157 3158 size = write_ptr; 3159 b_full = iwl_write_to_user_buf(user_buf, count, 3160 cpu_addr, &size, 3161 &bytes_copied); 3162 data->prev_wr_ptr = size; 3163 data->prev_wrap_cnt = wrap_cnt; 3164 } 3165 3166 mutex_unlock(&data->mutex); 3167 3168 return bytes_copied; 3169 } 3170 3171 static ssize_t iwl_dbgfs_rf_read(struct file *file, 3172 char __user *user_buf, 3173 size_t count, loff_t *ppos) 3174 { 3175 struct iwl_trans *trans = file->private_data; 3176 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3177 3178 if (!trans_pcie->rf_name[0]) 3179 return -ENODEV; 3180 3181 return simple_read_from_buffer(user_buf, count, ppos, 3182 trans_pcie->rf_name, 3183 strlen(trans_pcie->rf_name)); 3184 } 3185 3186 static ssize_t iwl_dbgfs_reset_write(struct file *file, 3187 const char __user *user_buf, 3188 size_t count, loff_t *ppos) 3189 { 3190 struct iwl_trans *trans = file->private_data; 3191 static const char * const modes[] = { 3192 [IWL_RESET_MODE_SW_RESET] = "sw", 3193 [IWL_RESET_MODE_REPROBE] = "reprobe", 3194 [IWL_RESET_MODE_TOP_RESET] = "top", 3195 [IWL_RESET_MODE_REMOVE_ONLY] = "remove", 3196 [IWL_RESET_MODE_RESCAN] = "rescan", 3197 [IWL_RESET_MODE_FUNC_RESET] = "function", 3198 [IWL_RESET_MODE_PROD_RESET] = "product", 3199 }; 3200 char buf[10] = {}; 3201 int mode; 3202 3203 if (count > sizeof(buf) - 1) 3204 return -EINVAL; 3205 3206 if (copy_from_user(buf, user_buf, count)) 3207 return -EFAULT; 3208 3209 mode = sysfs_match_string(modes, buf); 3210 if (mode < 0) 3211 return mode; 3212 3213 if (mode < IWL_RESET_MODE_REMOVE_ONLY) { 3214 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 3215 return -EINVAL; 3216 if (mode == IWL_RESET_MODE_TOP_RESET) { 3217 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_SC) 3218 return -EINVAL; 3219 trans->request_top_reset = 1; 3220 } 3221 iwl_op_mode_nic_error(trans->op_mode, IWL_ERR_TYPE_DEBUGFS); 3222 iwl_trans_schedule_reset(trans, IWL_ERR_TYPE_DEBUGFS); 3223 return count; 3224 } 3225 3226 iwl_trans_pcie_reset(trans, mode); 3227 3228 return count; 3229 } 3230 3231 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3232 DEBUGFS_READ_FILE_OPS(fh_reg); 3233 DEBUGFS_READ_FILE_OPS(rx_queue); 3234 DEBUGFS_WRITE_FILE_OPS(csr); 3235 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3236 DEBUGFS_READ_FILE_OPS(rf); 3237 DEBUGFS_WRITE_FILE_OPS(reset); 3238 3239 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3240 .owner = THIS_MODULE, 3241 .open = iwl_dbgfs_tx_queue_open, 3242 .read = seq_read, 3243 .llseek = seq_lseek, 3244 .release = seq_release_private, 3245 }; 3246 3247 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3248 .read = iwl_dbgfs_monitor_data_read, 3249 .open = iwl_dbgfs_monitor_data_open, 3250 .release = iwl_dbgfs_monitor_data_release, 3251 }; 3252 3253 /* Create the debugfs files and directories */ 3254 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3255 { 3256 struct dentry *dir = trans->dbgfs_dir; 3257 3258 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3259 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3260 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3261 DEBUGFS_ADD_FILE(csr, dir, 0200); 3262 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3263 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3264 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3265 DEBUGFS_ADD_FILE(rf, dir, 0400); 3266 DEBUGFS_ADD_FILE(reset, dir, 0200); 3267 } 3268 3269 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3270 { 3271 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3272 struct cont_rec *data = &trans_pcie->fw_mon_data; 3273 3274 mutex_lock(&data->mutex); 3275 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3276 mutex_unlock(&data->mutex); 3277 } 3278 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3279 3280 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3281 { 3282 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3283 u32 cmdlen = 0; 3284 int i; 3285 3286 for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++) 3287 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3288 3289 return cmdlen; 3290 } 3291 3292 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3293 struct iwl_fw_error_dump_data **data, 3294 int allocated_rb_nums) 3295 { 3296 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3297 int max_len = trans_pcie->rx_buf_bytes; 3298 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3299 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3300 u32 i, r, j, rb_len = 0; 3301 3302 spin_lock_bh(&rxq->lock); 3303 3304 r = iwl_get_closed_rb_stts(trans, rxq); 3305 3306 for (i = rxq->read, j = 0; 3307 i != r && j < allocated_rb_nums; 3308 i = (i + 1) & RX_QUEUE_MASK, j++) { 3309 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3310 struct iwl_fw_error_dump_rb *rb; 3311 3312 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3313 max_len, DMA_FROM_DEVICE); 3314 3315 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3316 3317 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3318 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3319 rb = (void *)(*data)->data; 3320 rb->index = cpu_to_le32(i); 3321 memcpy(rb->data, page_address(rxb->page), max_len); 3322 3323 *data = iwl_fw_error_next_data(*data); 3324 } 3325 3326 spin_unlock_bh(&rxq->lock); 3327 3328 return rb_len; 3329 } 3330 #define IWL_CSR_TO_DUMP (0x250) 3331 3332 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3333 struct iwl_fw_error_dump_data **data) 3334 { 3335 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3336 __le32 *val; 3337 int i; 3338 3339 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3340 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3341 val = (void *)(*data)->data; 3342 3343 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3344 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3345 3346 *data = iwl_fw_error_next_data(*data); 3347 3348 return csr_len; 3349 } 3350 3351 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3352 struct iwl_fw_error_dump_data **data) 3353 { 3354 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3355 __le32 *val; 3356 int i; 3357 3358 if (!iwl_trans_grab_nic_access(trans)) 3359 return 0; 3360 3361 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3362 (*data)->len = cpu_to_le32(fh_regs_len); 3363 val = (void *)(*data)->data; 3364 3365 if (!trans->mac_cfg->gen2) 3366 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3367 i += sizeof(u32)) 3368 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3369 else 3370 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3371 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3372 i += sizeof(u32)) 3373 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3374 i)); 3375 3376 iwl_trans_release_nic_access(trans); 3377 3378 *data = iwl_fw_error_next_data(*data); 3379 3380 return sizeof(**data) + fh_regs_len; 3381 } 3382 3383 static u32 3384 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3385 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3386 u32 monitor_len) 3387 { 3388 u32 buf_size_in_dwords = (monitor_len >> 2); 3389 u32 *buffer = (u32 *)fw_mon_data->data; 3390 u32 i; 3391 3392 if (!iwl_trans_grab_nic_access(trans)) 3393 return 0; 3394 3395 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3396 for (i = 0; i < buf_size_in_dwords; i++) 3397 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3398 MON_DMARB_RD_DATA_ADDR); 3399 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3400 3401 iwl_trans_release_nic_access(trans); 3402 3403 return monitor_len; 3404 } 3405 3406 static void 3407 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3408 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3409 { 3410 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3411 3412 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3413 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3414 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3415 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3416 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3417 } else if (trans->dbg.dest_tlv) { 3418 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3419 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3420 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3421 } else { 3422 base = MON_BUFF_BASE_ADDR; 3423 write_ptr = MON_BUFF_WRPTR; 3424 wrap_cnt = MON_BUFF_CYCLE_CNT; 3425 } 3426 3427 write_ptr_val = iwl_read_prph(trans, write_ptr); 3428 fw_mon_data->fw_mon_cycle_cnt = 3429 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3430 fw_mon_data->fw_mon_base_ptr = 3431 cpu_to_le32(iwl_read_prph(trans, base)); 3432 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3433 fw_mon_data->fw_mon_base_high_ptr = 3434 cpu_to_le32(iwl_read_prph(trans, base_high)); 3435 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3436 /* convert wrtPtr to DWs, to align with all HWs */ 3437 write_ptr_val >>= 2; 3438 } 3439 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3440 } 3441 3442 static u32 3443 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3444 struct iwl_fw_error_dump_data **data, 3445 u32 monitor_len) 3446 { 3447 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3448 u32 len = 0; 3449 3450 if (trans->dbg.dest_tlv || 3451 (fw_mon->size && 3452 (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3453 trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3454 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3455 3456 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3457 fw_mon_data = (void *)(*data)->data; 3458 3459 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3460 3461 len += sizeof(**data) + sizeof(*fw_mon_data); 3462 if (fw_mon->size) { 3463 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3464 monitor_len = fw_mon->size; 3465 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3466 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3467 /* 3468 * Update pointers to reflect actual values after 3469 * shifting 3470 */ 3471 if (trans->dbg.dest_tlv->version) { 3472 base = (iwl_read_prph(trans, base) & 3473 IWL_LDBG_M2S_BUF_BA_MSK) << 3474 trans->dbg.dest_tlv->base_shift; 3475 base *= IWL_M2S_UNIT_SIZE; 3476 base += trans->mac_cfg->base->smem_offset; 3477 } else { 3478 base = iwl_read_prph(trans, base) << 3479 trans->dbg.dest_tlv->base_shift; 3480 } 3481 3482 iwl_trans_pcie_read_mem(trans, base, fw_mon_data->data, 3483 monitor_len / sizeof(u32)); 3484 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3485 monitor_len = 3486 iwl_trans_pci_dump_marbh_monitor(trans, 3487 fw_mon_data, 3488 monitor_len); 3489 } else { 3490 /* Didn't match anything - output no monitor data */ 3491 monitor_len = 0; 3492 } 3493 3494 len += monitor_len; 3495 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3496 } 3497 3498 return len; 3499 } 3500 3501 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3502 { 3503 if (trans->dbg.fw_mon.size) { 3504 *len += sizeof(struct iwl_fw_error_dump_data) + 3505 sizeof(struct iwl_fw_error_dump_fw_mon) + 3506 trans->dbg.fw_mon.size; 3507 return trans->dbg.fw_mon.size; 3508 } else if (trans->dbg.dest_tlv) { 3509 u32 base, end, cfg_reg, monitor_len; 3510 3511 if (trans->dbg.dest_tlv->version == 1) { 3512 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3513 cfg_reg = iwl_read_prph(trans, cfg_reg); 3514 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3515 trans->dbg.dest_tlv->base_shift; 3516 base *= IWL_M2S_UNIT_SIZE; 3517 base += trans->mac_cfg->base->smem_offset; 3518 3519 monitor_len = 3520 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3521 trans->dbg.dest_tlv->end_shift; 3522 monitor_len *= IWL_M2S_UNIT_SIZE; 3523 } else { 3524 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3525 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3526 3527 base = iwl_read_prph(trans, base) << 3528 trans->dbg.dest_tlv->base_shift; 3529 end = iwl_read_prph(trans, end) << 3530 trans->dbg.dest_tlv->end_shift; 3531 3532 /* Make "end" point to the actual end */ 3533 if (trans->mac_cfg->device_family >= 3534 IWL_DEVICE_FAMILY_8000 || 3535 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3536 end += (1 << trans->dbg.dest_tlv->end_shift); 3537 monitor_len = end - base; 3538 } 3539 *len += sizeof(struct iwl_fw_error_dump_data) + 3540 sizeof(struct iwl_fw_error_dump_fw_mon) + 3541 monitor_len; 3542 return monitor_len; 3543 } 3544 return 0; 3545 } 3546 3547 struct iwl_trans_dump_data * 3548 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask, 3549 const struct iwl_dump_sanitize_ops *sanitize_ops, 3550 void *sanitize_ctx) 3551 { 3552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3553 struct iwl_fw_error_dump_data *data; 3554 struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans->conf.cmd_queue]; 3555 struct iwl_fw_error_dump_txcmd *txcmd; 3556 struct iwl_trans_dump_data *dump_data; 3557 u32 len, num_rbs = 0, monitor_len = 0; 3558 int i, ptr; 3559 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3560 !trans->mac_cfg->mq_rx_supported && 3561 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3562 3563 if (!dump_mask) 3564 return NULL; 3565 3566 /* transport dump header */ 3567 len = sizeof(*dump_data); 3568 3569 /* host commands */ 3570 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3571 len += sizeof(*data) + 3572 cmdq->n_window * (sizeof(*txcmd) + 3573 TFD_MAX_PAYLOAD_SIZE); 3574 3575 /* FW monitor */ 3576 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3577 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3578 3579 /* CSR registers */ 3580 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3581 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3582 3583 /* FH registers */ 3584 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3585 if (trans->mac_cfg->gen2) 3586 len += sizeof(*data) + 3587 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3588 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3589 else 3590 len += sizeof(*data) + 3591 (FH_MEM_UPPER_BOUND - 3592 FH_MEM_LOWER_BOUND); 3593 } 3594 3595 if (dump_rbs) { 3596 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3597 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3598 /* RBs */ 3599 spin_lock_bh(&rxq->lock); 3600 num_rbs = iwl_get_closed_rb_stts(trans, rxq); 3601 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3602 spin_unlock_bh(&rxq->lock); 3603 3604 len += num_rbs * (sizeof(*data) + 3605 sizeof(struct iwl_fw_error_dump_rb) + 3606 (PAGE_SIZE << trans_pcie->rx_page_order)); 3607 } 3608 3609 /* Paged memory for gen2 HW */ 3610 if (trans->mac_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3611 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3612 len += sizeof(*data) + 3613 sizeof(struct iwl_fw_error_dump_paging) + 3614 trans->init_dram.paging[i].size; 3615 3616 dump_data = vzalloc(len); 3617 if (!dump_data) 3618 return NULL; 3619 3620 len = 0; 3621 data = (void *)dump_data->data; 3622 3623 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3624 u16 tfd_size = trans_pcie->txqs.tfd.size; 3625 3626 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3627 txcmd = (void *)data->data; 3628 spin_lock_bh(&cmdq->lock); 3629 ptr = cmdq->write_ptr; 3630 for (i = 0; i < cmdq->n_window; i++) { 3631 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3632 u8 tfdidx; 3633 u32 caplen, cmdlen; 3634 3635 if (trans->mac_cfg->gen2) 3636 tfdidx = idx; 3637 else 3638 tfdidx = ptr; 3639 3640 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3641 (u8 *)cmdq->tfds + 3642 tfd_size * tfdidx); 3643 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3644 3645 if (cmdlen) { 3646 len += sizeof(*txcmd) + caplen; 3647 txcmd->cmdlen = cpu_to_le32(cmdlen); 3648 txcmd->caplen = cpu_to_le32(caplen); 3649 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3650 caplen); 3651 if (sanitize_ops && sanitize_ops->frob_hcmd) 3652 sanitize_ops->frob_hcmd(sanitize_ctx, 3653 txcmd->data, 3654 caplen); 3655 txcmd = (void *)((u8 *)txcmd->data + caplen); 3656 } 3657 3658 ptr = iwl_txq_dec_wrap(trans, ptr); 3659 } 3660 spin_unlock_bh(&cmdq->lock); 3661 3662 data->len = cpu_to_le32(len); 3663 len += sizeof(*data); 3664 data = iwl_fw_error_next_data(data); 3665 } 3666 3667 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3668 len += iwl_trans_pcie_dump_csr(trans, &data); 3669 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3670 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3671 if (dump_rbs) 3672 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3673 3674 /* Paged memory for gen2 HW */ 3675 if (trans->mac_cfg->gen2 && 3676 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3677 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3678 struct iwl_fw_error_dump_paging *paging; 3679 u32 page_len = trans->init_dram.paging[i].size; 3680 3681 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3682 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3683 paging = (void *)data->data; 3684 paging->index = cpu_to_le32(i); 3685 memcpy(paging->data, 3686 trans->init_dram.paging[i].block, page_len); 3687 data = iwl_fw_error_next_data(data); 3688 3689 len += sizeof(*data) + sizeof(*paging) + page_len; 3690 } 3691 } 3692 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3693 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3694 3695 dump_data->len = len; 3696 3697 return dump_data; 3698 } 3699 3700 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3701 { 3702 if (enable) 3703 iwl_enable_interrupts(trans); 3704 else 3705 iwl_disable_interrupts(trans); 3706 } 3707 3708 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3709 { 3710 u32 inta_addr, sw_err_bit; 3711 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3712 3713 if (trans_pcie->msix_enabled) { 3714 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3715 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3716 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3717 else 3718 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3719 } else { 3720 inta_addr = CSR_INT; 3721 sw_err_bit = CSR_INT_BIT_SW_ERR; 3722 } 3723 3724 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3725 } 3726 3727 static int iwl_trans_pcie_set_txcmd_info(const struct iwl_mac_cfg *mac_cfg, 3728 unsigned int *txcmd_size, 3729 unsigned int *txcmd_align) 3730 { 3731 if (!mac_cfg->gen2) { 3732 *txcmd_size = sizeof(struct iwl_tx_cmd_v6); 3733 *txcmd_align = sizeof(void *); 3734 } else if (mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 3735 *txcmd_size = sizeof(struct iwl_tx_cmd_v9); 3736 *txcmd_align = 64; 3737 } else { 3738 *txcmd_size = sizeof(struct iwl_tx_cmd); 3739 *txcmd_align = 128; 3740 } 3741 3742 *txcmd_size += sizeof(struct iwl_cmd_header); 3743 *txcmd_size += 36; /* biggest possible 802.11 header */ 3744 3745 /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */ 3746 if (WARN_ON((mac_cfg->gen2 && *txcmd_size >= *txcmd_align))) 3747 return -EINVAL; 3748 3749 return 0; 3750 } 3751 3752 static struct iwl_trans * 3753 iwl_trans_pcie_alloc(struct pci_dev *pdev, 3754 const struct iwl_mac_cfg *mac_cfg, 3755 struct iwl_trans_info *info, u8 __iomem *hw_base) 3756 { 3757 struct iwl_trans_pcie *trans_pcie, **priv; 3758 unsigned int txcmd_size, txcmd_align; 3759 struct iwl_trans *trans; 3760 unsigned int bc_tbl_n_entries; 3761 int ret, addr_size; 3762 3763 ret = iwl_trans_pcie_set_txcmd_info(mac_cfg, &txcmd_size, 3764 &txcmd_align); 3765 if (ret) 3766 return ERR_PTR(ret); 3767 3768 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, 3769 mac_cfg, txcmd_size, txcmd_align); 3770 if (!trans) 3771 return ERR_PTR(-ENOMEM); 3772 3773 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3774 3775 trans_pcie->hw_base = hw_base; 3776 3777 /* Initialize the wait queue for commands */ 3778 init_waitqueue_head(&trans_pcie->wait_command_queue); 3779 3780 if (trans->mac_cfg->gen2) { 3781 trans_pcie->txqs.tfd.addr_size = 64; 3782 trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS; 3783 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd); 3784 } else { 3785 trans_pcie->txqs.tfd.addr_size = 36; 3786 trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS; 3787 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd); 3788 } 3789 3790 trans_pcie->supported_dma_mask = (u32)DMA_BIT_MASK(12); 3791 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 3792 trans_pcie->supported_dma_mask = (u32)DMA_BIT_MASK(11); 3793 3794 info->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie); 3795 3796 trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3797 if (!trans_pcie->txqs.tso_hdr_page) { 3798 ret = -ENOMEM; 3799 goto out_free_trans; 3800 } 3801 3802 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3803 bc_tbl_n_entries = TFD_QUEUE_BC_SIZE_BZ; 3804 else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 3805 bc_tbl_n_entries = TFD_QUEUE_BC_SIZE_AX210; 3806 else 3807 bc_tbl_n_entries = TFD_QUEUE_BC_SIZE; 3808 3809 trans_pcie->txqs.bc_tbl_size = 3810 sizeof(struct iwl_bc_tbl_entry) * bc_tbl_n_entries; 3811 /* 3812 * For gen2 devices, we use a single allocation for each byte-count 3813 * table, but they're pretty small (1k) so use a DMA pool that we 3814 * allocate here. 3815 */ 3816 if (trans->mac_cfg->gen2) { 3817 trans_pcie->txqs.bc_pool = 3818 dmam_pool_create("iwlwifi:bc", trans->dev, 3819 trans_pcie->txqs.bc_tbl_size, 3820 256, 0); 3821 if (!trans_pcie->txqs.bc_pool) { 3822 ret = -ENOMEM; 3823 goto out_free_tso; 3824 } 3825 } 3826 3827 /* Some things must not change even if the config does */ 3828 WARN_ON(trans_pcie->txqs.tfd.addr_size != 3829 (trans->mac_cfg->gen2 ? 64 : 36)); 3830 3831 /* Initialize NAPI here - it should be before registering to mac80211 3832 * in the opmode but after the HW struct is allocated. 3833 */ 3834 trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *)); 3835 if (!trans_pcie->napi_dev) { 3836 ret = -ENOMEM; 3837 goto out_free_tso; 3838 } 3839 /* The private struct in netdev is a pointer to struct iwl_trans_pcie */ 3840 priv = netdev_priv(trans_pcie->napi_dev); 3841 *priv = trans_pcie; 3842 3843 trans_pcie->trans = trans; 3844 trans_pcie->opmode_down = true; 3845 spin_lock_init(&trans_pcie->irq_lock); 3846 spin_lock_init(&trans_pcie->reg_lock); 3847 spin_lock_init(&trans_pcie->alloc_page_lock); 3848 mutex_init(&trans_pcie->mutex); 3849 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3850 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3851 init_waitqueue_head(&trans_pcie->imr_waitq); 3852 3853 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3854 WQ_HIGHPRI | WQ_UNBOUND, 0); 3855 if (!trans_pcie->rba.alloc_wq) { 3856 ret = -ENOMEM; 3857 goto out_free_ndev; 3858 } 3859 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3860 3861 trans_pcie->debug_rfkill = -1; 3862 3863 if (!mac_cfg->base->pcie_l1_allowed) { 3864 /* 3865 * W/A - seems to solve weird behavior. We need to remove this 3866 * if we don't want to stay in L1 all the time. This wastes a 3867 * lot of power. 3868 */ 3869 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3870 PCIE_LINK_STATE_L1 | 3871 PCIE_LINK_STATE_CLKPM); 3872 } 3873 3874 addr_size = trans_pcie->txqs.tfd.addr_size; 3875 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3876 if (ret) { 3877 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3878 /* both attempts failed: */ 3879 if (ret) { 3880 dev_err(&pdev->dev, "No suitable DMA available\n"); 3881 goto out_no_pci; 3882 } 3883 } 3884 3885 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3886 * PCI Tx retries from interfering with C3 CPU state */ 3887 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3888 3889 trans_pcie->pci_dev = pdev; 3890 iwl_disable_interrupts(trans); 3891 3892 /* 3893 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3894 * changed, and now the revision step also includes bit 0-1 (no more 3895 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3896 * in the old format. 3897 */ 3898 if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 3899 info->hw_rev_step = info->hw_rev & 0xF; 3900 else 3901 info->hw_rev_step = (info->hw_rev & 0xC) >> 2; 3902 3903 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", info->hw_rev); 3904 3905 iwl_pcie_set_interrupt_capa(pdev, trans, mac_cfg, info); 3906 3907 init_waitqueue_head(&trans_pcie->sx_waitq); 3908 3909 ret = iwl_pcie_alloc_invalid_tx_cmd(trans); 3910 if (ret) 3911 goto out_no_pci; 3912 3913 if (trans_pcie->msix_enabled) { 3914 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie, info); 3915 if (ret) 3916 goto out_no_pci; 3917 } else { 3918 ret = iwl_pcie_alloc_ict(trans); 3919 if (ret) 3920 goto out_no_pci; 3921 3922 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3923 iwl_pcie_isr, 3924 iwl_pcie_irq_handler, 3925 IRQF_SHARED, DRV_NAME, trans); 3926 if (ret) { 3927 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3928 goto out_free_ict; 3929 } 3930 } 3931 3932 #ifdef CONFIG_IWLWIFI_DEBUGFS 3933 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3934 mutex_init(&trans_pcie->fw_mon_data.mutex); 3935 #endif 3936 3937 iwl_dbg_tlv_init(trans); 3938 3939 return trans; 3940 3941 out_free_ict: 3942 iwl_pcie_free_ict(trans); 3943 out_no_pci: 3944 destroy_workqueue(trans_pcie->rba.alloc_wq); 3945 out_free_ndev: 3946 free_netdev(trans_pcie->napi_dev); 3947 out_free_tso: 3948 free_percpu(trans_pcie->txqs.tso_hdr_page); 3949 out_free_trans: 3950 iwl_trans_free(trans); 3951 return ERR_PTR(ret); 3952 } 3953 3954 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3955 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3956 { 3957 iwl_write_prph(trans, IMR_UREG_CHICK, 3958 iwl_read_prph(trans, IMR_UREG_CHICK) | 3959 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3960 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3961 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3962 (u32)(src_addr & 0xFFFFFFFF)); 3963 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3964 iwl_get_dma_hi_addr(src_addr)); 3965 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3966 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3967 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3968 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3969 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3970 } 3971 3972 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3973 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3974 { 3975 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3976 int ret = -1; 3977 3978 trans_pcie->imr_status = IMR_D2S_REQUESTED; 3979 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3980 ret = wait_event_timeout(trans_pcie->imr_waitq, 3981 trans_pcie->imr_status != 3982 IMR_D2S_REQUESTED, 5 * HZ); 3983 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3984 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3985 iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev); 3986 return -ETIMEDOUT; 3987 } 3988 trans_pcie->imr_status = IMR_D2S_IDLE; 3989 return 0; 3990 } 3991 3992 /* 3993 * Read rf id and cdb info from prph register and store it 3994 */ 3995 static void get_crf_id(struct iwl_trans *iwl_trans, 3996 struct iwl_trans_info *info) 3997 { 3998 u32 sd_reg_ver_addr; 3999 u32 hw_wfpm_id; 4000 u32 val = 0; 4001 u8 step; 4002 4003 if (iwl_trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 4004 sd_reg_ver_addr = SD_REG_VER_GEN2; 4005 else 4006 sd_reg_ver_addr = SD_REG_VER; 4007 4008 /* Enable access to peripheral registers */ 4009 val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG); 4010 val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK; 4011 iwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val); 4012 4013 /* Read crf info */ 4014 info->hw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr); 4015 4016 /* Read cnv info */ 4017 info->hw_cnv_id = iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP); 4018 4019 /* For BZ-W, take B step also when A step is indicated */ 4020 if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W) 4021 step = SILICON_B_STEP; 4022 4023 /* In BZ, the MAC step must be read from the CNVI aux register */ 4024 if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ) { 4025 step = CNVI_AUX_MISC_CHIP_MAC_STEP(info->hw_cnv_id); 4026 4027 /* For BZ-U, take B step also when A step is indicated */ 4028 if ((CNVI_AUX_MISC_CHIP_PROD_TYPE(info->hw_cnv_id) == 4029 CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U) && 4030 step == SILICON_A_STEP) 4031 step = SILICON_B_STEP; 4032 } 4033 4034 if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ || 4035 CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W) { 4036 info->hw_rev_step = step; 4037 info->hw_rev |= step; 4038 } 4039 4040 /* Read cdb info (also contains the jacket info if needed in the future */ 4041 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR); 4042 IWL_INFO(iwl_trans, "Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\n", 4043 info->hw_crf_id, info->hw_cnv_id, hw_wfpm_id); 4044 } 4045 4046 /* 4047 * In case that there is no OTP on the NIC, map the rf id and cdb info 4048 * from the prph registers. 4049 */ 4050 static int map_crf_id(struct iwl_trans *iwl_trans, 4051 struct iwl_trans_info *info) 4052 { 4053 int ret = 0; 4054 u32 val = info->hw_crf_id; 4055 u32 step_id = REG_CRF_ID_STEP(val); 4056 u32 slave_id = REG_CRF_ID_SLAVE(val); 4057 u32 jacket_id_cnv = REG_CRF_ID_SLAVE(info->hw_cnv_id); 4058 u32 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, 4059 WFPM_OTP_CFG1_ADDR); 4060 u32 jacket_id_wfpm = WFPM_OTP_CFG1_IS_JACKET(hw_wfpm_id); 4061 u32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(hw_wfpm_id); 4062 4063 /* Map between crf id to rf id */ 4064 switch (REG_CRF_ID_TYPE(val)) { 4065 case REG_CRF_ID_TYPE_JF_1: 4066 info->hw_rf_id = (IWL_CFG_RF_TYPE_JF1 << 12); 4067 break; 4068 case REG_CRF_ID_TYPE_JF_2: 4069 info->hw_rf_id = (IWL_CFG_RF_TYPE_JF2 << 12); 4070 break; 4071 case REG_CRF_ID_TYPE_HR_NONE_CDB_1X1: 4072 info->hw_rf_id = (IWL_CFG_RF_TYPE_HR1 << 12); 4073 break; 4074 case REG_CRF_ID_TYPE_HR_NONE_CDB: 4075 info->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12); 4076 break; 4077 case REG_CRF_ID_TYPE_HR_CDB: 4078 info->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12); 4079 break; 4080 case REG_CRF_ID_TYPE_GF: 4081 info->hw_rf_id = (IWL_CFG_RF_TYPE_GF << 12); 4082 break; 4083 case REG_CRF_ID_TYPE_FM: 4084 info->hw_rf_id = (IWL_CFG_RF_TYPE_FM << 12); 4085 break; 4086 case REG_CRF_ID_TYPE_WHP: 4087 info->hw_rf_id = (IWL_CFG_RF_TYPE_WH << 12); 4088 break; 4089 case REG_CRF_ID_TYPE_PE: 4090 info->hw_rf_id = (IWL_CFG_RF_TYPE_PE << 12); 4091 break; 4092 default: 4093 ret = -EIO; 4094 IWL_ERR(iwl_trans, 4095 "Can't find a correct rfid for crf id 0x%x\n", 4096 REG_CRF_ID_TYPE(val)); 4097 goto out; 4098 } 4099 4100 /* Set Step-id */ 4101 info->hw_rf_id |= (step_id << 8); 4102 4103 /* Set CDB capabilities */ 4104 if (cdb_id_wfpm || slave_id) { 4105 info->hw_rf_id += BIT(28); 4106 IWL_INFO(iwl_trans, "Adding cdb to rf id\n"); 4107 } 4108 4109 /* Set Jacket capabilities */ 4110 if (jacket_id_wfpm || jacket_id_cnv) { 4111 info->hw_rf_id += BIT(29); 4112 IWL_INFO(iwl_trans, "Adding jacket to rf id\n"); 4113 } 4114 4115 IWL_INFO(iwl_trans, 4116 "Detected rf-type 0x%x step-id 0x%x slave-id 0x%x from crf id 0x%x\n", 4117 REG_CRF_ID_TYPE(val), step_id, slave_id, info->hw_rf_id); 4118 IWL_INFO(iwl_trans, 4119 "Detected cdb-id 0x%x jacket-id 0x%x from wfpm id 0x%x\n", 4120 cdb_id_wfpm, jacket_id_wfpm, hw_wfpm_id); 4121 IWL_INFO(iwl_trans, "Detected jacket-id 0x%x from cnvi id 0x%x\n", 4122 jacket_id_cnv, info->hw_cnv_id); 4123 4124 out: 4125 return ret; 4126 } 4127 4128 static void iwl_pcie_recheck_me_status(struct work_struct *wk) 4129 { 4130 struct iwl_trans_pcie *trans_pcie = container_of(wk, 4131 typeof(*trans_pcie), 4132 me_recheck_wk.work); 4133 u32 val; 4134 4135 val = iwl_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG); 4136 trans_pcie->me_present = !!(val & CSR_HW_IF_CONFIG_REG_IAMT_UP); 4137 } 4138 4139 static void iwl_pcie_check_me_status(struct iwl_trans *trans) 4140 { 4141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4142 u32 val; 4143 4144 trans_pcie->me_present = -1; 4145 4146 INIT_DELAYED_WORK(&trans_pcie->me_recheck_wk, 4147 iwl_pcie_recheck_me_status); 4148 4149 /* we don't have a good way of determining this until BZ */ 4150 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ) 4151 return; 4152 4153 val = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1); 4154 if (val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_KNOWN) { 4155 trans_pcie->me_present = 4156 !!(val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_PRESENT); 4157 return; 4158 } 4159 4160 val = iwl_read32(trans, CSR_HW_IF_CONFIG_REG); 4161 if (val & (CSR_HW_IF_CONFIG_REG_ME_OWN | 4162 CSR_HW_IF_CONFIG_REG_IAMT_UP)) { 4163 trans_pcie->me_present = 1; 4164 return; 4165 } 4166 4167 /* recheck again later, ME might still be initializing */ 4168 schedule_delayed_work(&trans_pcie->me_recheck_wk, HZ); 4169 } 4170 4171 int iwl_pci_gen1_2_probe(struct pci_dev *pdev, 4172 const struct pci_device_id *ent, 4173 const struct iwl_mac_cfg *mac_cfg, 4174 u8 __iomem *hw_base, u32 hw_rev) 4175 { 4176 const struct iwl_dev_info *dev_info; 4177 struct iwl_trans_info info = { 4178 .hw_id = (pdev->device << 16) + pdev->subsystem_device, 4179 .hw_rev = hw_rev, 4180 }; 4181 struct iwl_trans *iwl_trans; 4182 struct iwl_trans_pcie *trans_pcie; 4183 int ret; 4184 4185 iwl_trans = iwl_trans_pcie_alloc(pdev, mac_cfg, &info, hw_base); 4186 if (IS_ERR(iwl_trans)) 4187 return PTR_ERR(iwl_trans); 4188 4189 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(iwl_trans); 4190 4191 iwl_trans_pcie_check_product_reset_status(pdev); 4192 iwl_trans_pcie_check_product_reset_mode(pdev); 4193 4194 /* set the things we know so far for the grab NIC access */ 4195 iwl_trans_set_info(iwl_trans, &info); 4196 4197 /* 4198 * Let's try to grab NIC access early here. Sometimes, NICs may 4199 * fail to initialize, and if that happens it's better if we see 4200 * issues early on (and can reprobe, per the logic inside), than 4201 * first trying to load the firmware etc. and potentially only 4202 * detecting any problems when the first interface is brought up. 4203 */ 4204 ret = iwl_pcie_prepare_card_hw(iwl_trans); 4205 if (!ret) { 4206 ret = iwl_finish_nic_init(iwl_trans); 4207 if (ret) 4208 goto out_free_trans; 4209 if (iwl_trans_grab_nic_access(iwl_trans)) { 4210 get_crf_id(iwl_trans, &info); 4211 /* all good */ 4212 iwl_trans_release_nic_access(iwl_trans); 4213 } else { 4214 ret = -EIO; 4215 goto out_free_trans; 4216 } 4217 } 4218 4219 info.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID); 4220 4221 /* 4222 * The RF_ID is set to zero in blank OTP so read version to 4223 * extract the RF_ID. 4224 * This is relevant only for family 9000 and up. 4225 */ 4226 if (iwl_trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_9000 && 4227 !CSR_HW_RFID_TYPE(info.hw_rf_id) && map_crf_id(iwl_trans, &info)) { 4228 ret = -EINVAL; 4229 goto out_free_trans; 4230 } 4231 4232 IWL_INFO(iwl_trans, "PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n", 4233 pdev->device, pdev->subsystem_device, 4234 info.hw_rev, info.hw_rf_id); 4235 4236 dev_info = iwl_pci_find_dev_info(pdev->device, pdev->subsystem_device, 4237 CSR_HW_RFID_TYPE(info.hw_rf_id), 4238 CSR_HW_RFID_IS_CDB(info.hw_rf_id), 4239 IWL_SUBDEVICE_RF_ID(pdev->subsystem_device), 4240 IWL_SUBDEVICE_BW_LIM(pdev->subsystem_device), 4241 !iwl_trans->mac_cfg->integrated); 4242 if (dev_info) { 4243 iwl_trans->cfg = dev_info->cfg; 4244 info.name = dev_info->name; 4245 } 4246 4247 #if IS_ENABLED(CONFIG_IWLMVM) 4248 4249 /* 4250 * special-case 7265D, it has the same PCI IDs. 4251 * 4252 * Note that because we already pass the cfg to the transport above, 4253 * all the parameters that the transport uses must, until that is 4254 * changed, be identical to the ones in the 7265D configuration. 4255 */ 4256 if (iwl_trans->cfg == &iwl7265_cfg && 4257 (info.hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_7265D) 4258 iwl_trans->cfg = &iwl7265d_cfg; 4259 #endif 4260 if (!iwl_trans->cfg) { 4261 pr_err("No config found for PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n", 4262 pdev->device, pdev->subsystem_device, 4263 info.hw_rev, info.hw_rf_id); 4264 ret = -EINVAL; 4265 goto out_free_trans; 4266 } 4267 4268 IWL_INFO(iwl_trans, "Detected %s\n", info.name); 4269 4270 if (iwl_trans->mac_cfg->mq_rx_supported) { 4271 if (WARN_ON(!iwl_trans->cfg->num_rbds)) { 4272 ret = -EINVAL; 4273 goto out_free_trans; 4274 } 4275 trans_pcie->num_rx_bufs = iwl_trans_get_num_rbds(iwl_trans); 4276 } else { 4277 trans_pcie->num_rx_bufs = RX_QUEUE_SIZE; 4278 } 4279 4280 if (!iwl_trans->mac_cfg->integrated) { 4281 u16 link_status; 4282 4283 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &link_status); 4284 4285 info.pcie_link_speed = 4286 u16_get_bits(link_status, PCI_EXP_LNKSTA_CLS); 4287 } 4288 4289 iwl_trans_set_info(iwl_trans, &info); 4290 4291 pci_set_drvdata(pdev, iwl_trans); 4292 4293 iwl_pcie_check_me_status(iwl_trans); 4294 4295 /* try to get ownership so that we'll know if we don't own it */ 4296 iwl_pcie_prepare_card_hw(iwl_trans); 4297 4298 iwl_trans->drv = iwl_drv_start(iwl_trans); 4299 4300 if (IS_ERR(iwl_trans->drv)) { 4301 ret = PTR_ERR(iwl_trans->drv); 4302 goto out_free_trans; 4303 } 4304 4305 /* register transport layer debugfs here */ 4306 iwl_trans_pcie_dbgfs_register(iwl_trans); 4307 4308 return 0; 4309 4310 out_free_trans: 4311 iwl_trans_pcie_free(iwl_trans); 4312 return ret; 4313 } 4314 4315 int iwl_pcie_gen1_2_finish_nic_init(struct iwl_trans *trans) 4316 { 4317 const struct iwl_mac_cfg *mac_cfg = trans->mac_cfg; 4318 u32 poll_ready; 4319 int err; 4320 4321 if (mac_cfg->bisr_workaround) { 4322 /* ensure the TOP FSM isn't still in previous reset */ 4323 mdelay(2); 4324 } 4325 4326 /* 4327 * Set "initialization complete" bit to move adapter from 4328 * D0U* --> D0A* (powered-up active) state. 4329 */ 4330 if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4331 iwl_set_bit(trans, CSR_GP_CNTRL, 4332 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ | 4333 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 4334 poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 4335 } else { 4336 iwl_set_bit(trans, CSR_GP_CNTRL, 4337 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 4338 poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY; 4339 } 4340 4341 if (mac_cfg->device_family == IWL_DEVICE_FAMILY_8000) 4342 udelay(2); 4343 4344 /* 4345 * Wait for clock stabilization; once stabilized, access to 4346 * device-internal resources is supported, e.g. iwl_write_prph() 4347 * and accesses to uCode SRAM. 4348 */ 4349 err = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000); 4350 if (err < 0) { 4351 IWL_DEBUG_INFO(trans, "Failed to wake NIC\n"); 4352 4353 iwl_pcie_dump_host_monitor(trans); 4354 } 4355 4356 if (mac_cfg->bisr_workaround) { 4357 /* ensure BISR shift has finished */ 4358 udelay(200); 4359 } 4360 4361 return err; 4362 } 4363