1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2024 Intel Corporation 4 */ 5 #include <linux/dmi.h> 6 #include "iwl-trans.h" 7 #include "iwl-fh.h" 8 #include "iwl-context-info-gen3.h" 9 #include "internal.h" 10 #include "iwl-prph.h" 11 12 static const struct dmi_system_id dmi_force_scu_active_approved_list[] = { 13 { .ident = "DELL", 14 .matches = { 15 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 16 }, 17 }, 18 { .ident = "DELL", 19 .matches = { 20 DMI_MATCH(DMI_SYS_VENDOR, "Alienware"), 21 }, 22 }, 23 /* keep last */ 24 {} 25 }; 26 27 static bool iwl_is_force_scu_active_approved(void) 28 { 29 return !!dmi_check_system(dmi_force_scu_active_approved_list); 30 } 31 32 static void 33 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 34 struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 35 u32 *control_flags) 36 { 37 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 38 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 39 u32 dbg_flags = 0; 40 41 if (!iwl_trans_dbg_ini_valid(trans)) { 42 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 43 44 iwl_pcie_alloc_fw_monitor(trans, 0); 45 46 if (fw_mon->size) { 47 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 48 49 IWL_DEBUG_FW(trans, 50 "WRT: Applying DRAM buffer destination\n"); 51 52 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 53 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 54 } 55 56 goto out; 57 } 58 59 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 60 61 switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 62 case IWL_FW_INI_LOCATION_SRAM_PATH: 63 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 64 IWL_DEBUG_FW(trans, 65 "WRT: Applying SMEM buffer destination\n"); 66 break; 67 68 case IWL_FW_INI_LOCATION_NPK_PATH: 69 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 70 IWL_DEBUG_FW(trans, 71 "WRT: Applying NPK buffer destination\n"); 72 break; 73 74 case IWL_FW_INI_LOCATION_DRAM_PATH: 75 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 76 struct iwl_dram_data *frag = 77 &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 78 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 79 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 80 dbg_cfg->hwm_size = cpu_to_le32(frag->size); 81 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); 82 IWL_DEBUG_FW(trans, 83 "WRT: Applying DRAM destination (debug_token_config=%u)\n", 84 dbg_cfg->debug_token_config); 85 IWL_DEBUG_FW(trans, 86 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 87 alloc_id, 88 trans->dbg.fw_mon_ini[alloc_id].num_frags); 89 } 90 break; 91 default: 92 IWL_ERR(trans, "WRT: Invalid buffer destination\n"); 93 } 94 out: 95 if (dbg_flags) 96 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 97 } 98 99 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 100 const struct fw_img *fw) 101 { 102 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 103 struct iwl_context_info_gen3 *ctxt_info_gen3; 104 struct iwl_prph_scratch *prph_scratch; 105 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 106 struct iwl_prph_info *prph_info; 107 u32 control_flags = 0; 108 int ret; 109 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 110 trans->cfg->min_txq_size); 111 112 switch (trans_pcie->rx_buf_size) { 113 case IWL_AMSDU_DEF: 114 return -EINVAL; 115 case IWL_AMSDU_2K: 116 break; 117 case IWL_AMSDU_4K: 118 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 119 break; 120 case IWL_AMSDU_8K: 121 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 122 /* if firmware supports the ext size, tell it */ 123 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 124 break; 125 case IWL_AMSDU_12K: 126 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 127 /* if firmware supports the ext size, tell it */ 128 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 129 break; 130 } 131 132 /* Allocate prph scratch */ 133 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 134 &trans_pcie->prph_scratch_dma_addr, 135 GFP_KERNEL); 136 if (!prph_scratch) 137 return -ENOMEM; 138 139 prph_sc_ctrl = &prph_scratch->ctrl_cfg; 140 141 prph_sc_ctrl->version.version = 0; 142 prph_sc_ctrl->version.mac_id = 143 cpu_to_le16((u16)trans->hw_rev); 144 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 145 146 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 147 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 148 149 if (trans->trans_cfg->imr_enabled) 150 control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN; 151 152 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL && 153 iwl_is_force_scu_active_approved()) { 154 control_flags |= IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE; 155 IWL_DEBUG_FW(trans, 156 "Context Info: Set SCU_FORCE_ACTIVE (0x%x) in control_flags\n", 157 IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE); 158 } 159 160 /* initialize RX default queue */ 161 prph_sc_ctrl->rbd_cfg.free_rbd_addr = 162 cpu_to_le64(trans_pcie->rxq->bd_dma); 163 164 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 165 &control_flags); 166 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 167 168 /* initialize the Step equalizer data */ 169 prph_sc_ctrl->step_cfg.mbx_addr_0 = cpu_to_le32(trans->mbx_addr_0_step); 170 prph_sc_ctrl->step_cfg.mbx_addr_1 = cpu_to_le32(trans->mbx_addr_1_step); 171 172 /* allocate ucode sections in dram and set addresses */ 173 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 174 if (ret) 175 goto err_free_prph_scratch; 176 177 178 /* Allocate prph information 179 * currently we don't assign to the prph info anything, but it would get 180 * assigned later 181 * 182 * We also use the second half of this page to give the device some 183 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't 184 * use this, but the hardware still reads/writes there and we can't let 185 * it go do that with a NULL pointer. 186 */ 187 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2); 188 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, 189 &trans_pcie->prph_info_dma_addr, 190 GFP_KERNEL); 191 if (!prph_info) { 192 ret = -ENOMEM; 193 goto err_free_prph_scratch; 194 } 195 196 /* Allocate context info */ 197 ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 198 sizeof(*ctxt_info_gen3), 199 &trans_pcie->ctxt_info_dma_addr, 200 GFP_KERNEL); 201 if (!ctxt_info_gen3) { 202 ret = -ENOMEM; 203 goto err_free_prph_info; 204 } 205 206 ctxt_info_gen3->prph_info_base_addr = 207 cpu_to_le64(trans_pcie->prph_info_dma_addr); 208 ctxt_info_gen3->prph_scratch_base_addr = 209 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 210 ctxt_info_gen3->prph_scratch_size = 211 cpu_to_le32(sizeof(*prph_scratch)); 212 ctxt_info_gen3->cr_head_idx_arr_base_addr = 213 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 214 ctxt_info_gen3->tr_tail_idx_arr_base_addr = 215 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); 216 ctxt_info_gen3->cr_tail_idx_arr_base_addr = 217 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); 218 ctxt_info_gen3->mtr_base_addr = 219 cpu_to_le64(trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]->dma_addr); 220 ctxt_info_gen3->mcr_base_addr = 221 cpu_to_le64(trans_pcie->rxq->used_bd_dma); 222 ctxt_info_gen3->mtr_size = 223 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 224 ctxt_info_gen3->mcr_size = 225 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 226 227 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 228 trans_pcie->prph_info = prph_info; 229 trans_pcie->prph_scratch = prph_scratch; 230 231 /* Allocate IML */ 232 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len, 233 &trans_pcie->iml_dma_addr, 234 GFP_KERNEL); 235 if (!trans_pcie->iml) { 236 ret = -ENOMEM; 237 goto err_free_ctxt_info; 238 } 239 240 memcpy(trans_pcie->iml, trans->iml, trans->iml_len); 241 242 iwl_enable_fw_load_int_ctx_info(trans); 243 244 /* kick FW self load */ 245 iwl_write64(trans, CSR_CTXT_INFO_ADDR, 246 trans_pcie->ctxt_info_dma_addr); 247 iwl_write64(trans, CSR_IML_DATA_ADDR, 248 trans_pcie->iml_dma_addr); 249 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 250 251 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 252 CSR_AUTO_FUNC_BOOT_ENA); 253 254 return 0; 255 256 err_free_ctxt_info: 257 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 258 trans_pcie->ctxt_info_gen3, 259 trans_pcie->ctxt_info_dma_addr); 260 trans_pcie->ctxt_info_gen3 = NULL; 261 err_free_prph_info: 262 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, 263 trans_pcie->prph_info_dma_addr); 264 265 err_free_prph_scratch: 266 dma_free_coherent(trans->dev, 267 sizeof(*prph_scratch), 268 prph_scratch, 269 trans_pcie->prph_scratch_dma_addr); 270 return ret; 271 272 } 273 274 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive) 275 { 276 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 277 278 if (trans_pcie->iml) { 279 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml, 280 trans_pcie->iml_dma_addr); 281 trans_pcie->iml_dma_addr = 0; 282 trans_pcie->iml = NULL; 283 } 284 285 iwl_pcie_ctxt_info_free_fw_img(trans); 286 287 if (alive) 288 return; 289 290 if (!trans_pcie->ctxt_info_gen3) 291 return; 292 293 /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */ 294 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 295 trans_pcie->ctxt_info_gen3, 296 trans_pcie->ctxt_info_dma_addr); 297 trans_pcie->ctxt_info_dma_addr = 0; 298 trans_pcie->ctxt_info_gen3 = NULL; 299 300 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 301 trans_pcie->prph_scratch, 302 trans_pcie->prph_scratch_dma_addr); 303 trans_pcie->prph_scratch_dma_addr = 0; 304 trans_pcie->prph_scratch = NULL; 305 306 /* this is needed for the entire lifetime */ 307 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, 308 trans_pcie->prph_info_dma_addr); 309 trans_pcie->prph_info_dma_addr = 0; 310 trans_pcie->prph_info = NULL; 311 } 312 313 static int iwl_pcie_load_payloads_continuously(struct iwl_trans *trans, 314 const struct iwl_pnvm_image *pnvm_data, 315 struct iwl_dram_data *dram) 316 { 317 u32 len, len0, len1; 318 319 if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) { 320 IWL_DEBUG_FW(trans, "expected 2 payloads, got %d.\n", 321 pnvm_data->n_chunks); 322 return -EINVAL; 323 } 324 325 len0 = pnvm_data->chunks[0].len; 326 len1 = pnvm_data->chunks[1].len; 327 if (len1 > 0xFFFFFFFF - len0) { 328 IWL_DEBUG_FW(trans, "sizes of payloads overflow.\n"); 329 return -EINVAL; 330 } 331 len = len0 + len1; 332 333 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, 334 &dram->physical); 335 if (!dram->block) { 336 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 337 return -ENOMEM; 338 } 339 340 dram->size = len; 341 memcpy(dram->block, pnvm_data->chunks[0].data, len0); 342 memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1); 343 344 return 0; 345 } 346 347 static int iwl_pcie_load_payloads_segments 348 (struct iwl_trans *trans, 349 struct iwl_dram_regions *dram_regions, 350 const struct iwl_pnvm_image *pnvm_data) 351 { 352 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0]; 353 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 354 struct iwl_prph_scrath_mem_desc_addr_array *addresses; 355 const void *data; 356 u32 len; 357 int i; 358 359 /* allocate and init DRAM descriptors array */ 360 len = sizeof(struct iwl_prph_scrath_mem_desc_addr_array); 361 desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent 362 (trans, 363 len, 364 &desc_dram->physical); 365 if (!desc_dram->block) { 366 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 367 return -ENOMEM; 368 } 369 desc_dram->size = len; 370 memset(desc_dram->block, 0, len); 371 372 /* allocate DRAM region for each payload */ 373 dram_regions->n_regions = 0; 374 for (i = 0; i < pnvm_data->n_chunks; i++) { 375 len = pnvm_data->chunks[i].len; 376 data = pnvm_data->chunks[i].data; 377 378 if (iwl_pcie_ctxt_info_alloc_dma(trans, 379 data, 380 len, 381 cur_payload_dram)) { 382 iwl_trans_pcie_free_pnvm_dram_regions(dram_regions, 383 trans->dev); 384 return -ENOMEM; 385 } 386 387 dram_regions->n_regions++; 388 cur_payload_dram++; 389 } 390 391 /* fill desc with the DRAM payloads addresses */ 392 addresses = desc_dram->block; 393 for (i = 0; i < pnvm_data->n_chunks; i++) { 394 addresses->mem_descs[i] = 395 cpu_to_le64(dram_regions->drams[i].physical); 396 } 397 398 return 0; 399 400 } 401 402 int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, 403 const struct iwl_pnvm_image *pnvm_payloads, 404 const struct iwl_ucode_capabilities *capa) 405 { 406 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 407 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 408 &trans_pcie->prph_scratch->ctrl_cfg; 409 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; 410 int ret = 0; 411 412 /* only allocate the DRAM if not allocated yet */ 413 if (trans->pnvm_loaded) 414 return 0; 415 416 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 417 return -EBUSY; 418 419 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 420 return 0; 421 422 if (!pnvm_payloads->n_chunks) { 423 IWL_DEBUG_FW(trans, "no payloads\n"); 424 return -EINVAL; 425 } 426 427 /* save payloads in several DRAM sections */ 428 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) { 429 ret = iwl_pcie_load_payloads_segments(trans, 430 dram_regions, 431 pnvm_payloads); 432 if (!ret) 433 trans->pnvm_loaded = true; 434 } else { 435 /* save only in one DRAM section */ 436 ret = iwl_pcie_load_payloads_continuously 437 (trans, 438 pnvm_payloads, 439 &dram_regions->drams[0]); 440 if (!ret) { 441 dram_regions->n_regions = 1; 442 trans->pnvm_loaded = true; 443 } 444 } 445 446 return ret; 447 } 448 449 static inline size_t 450 iwl_dram_regions_size(const struct iwl_dram_regions *dram_regions) 451 { 452 size_t total_size = 0; 453 int i; 454 455 for (i = 0; i < dram_regions->n_regions; i++) 456 total_size += dram_regions->drams[i].size; 457 458 return total_size; 459 } 460 461 static void iwl_pcie_set_pnvm_segments(struct iwl_trans *trans) 462 { 463 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 464 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 465 &trans_pcie->prph_scratch->ctrl_cfg; 466 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; 467 468 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 469 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); 470 prph_sc_ctrl->pnvm_cfg.pnvm_size = 471 cpu_to_le32(iwl_dram_regions_size(dram_regions)); 472 } 473 474 static void iwl_pcie_set_continuous_pnvm(struct iwl_trans *trans) 475 { 476 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 477 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 478 &trans_pcie->prph_scratch->ctrl_cfg; 479 480 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 481 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical); 482 prph_sc_ctrl->pnvm_cfg.pnvm_size = 483 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size); 484 } 485 486 void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 487 const struct iwl_ucode_capabilities *capa) 488 { 489 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 490 return; 491 492 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 493 iwl_pcie_set_pnvm_segments(trans); 494 else 495 iwl_pcie_set_continuous_pnvm(trans); 496 } 497 498 int iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans, 499 const struct iwl_pnvm_image *payloads, 500 const struct iwl_ucode_capabilities *capa) 501 { 502 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 503 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 504 &trans_pcie->prph_scratch->ctrl_cfg; 505 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; 506 int ret = 0; 507 508 /* only allocate the DRAM if not allocated yet */ 509 if (trans->reduce_power_loaded) 510 return 0; 511 512 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 513 return 0; 514 515 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) 516 return -EBUSY; 517 518 if (!payloads->n_chunks) { 519 IWL_DEBUG_FW(trans, "no payloads\n"); 520 return -EINVAL; 521 } 522 523 /* save payloads in several DRAM sections */ 524 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) { 525 ret = iwl_pcie_load_payloads_segments(trans, 526 dram_regions, 527 payloads); 528 if (!ret) 529 trans->reduce_power_loaded = true; 530 } else { 531 /* save only in one DRAM section */ 532 ret = iwl_pcie_load_payloads_continuously 533 (trans, 534 payloads, 535 &dram_regions->drams[0]); 536 if (!ret) { 537 dram_regions->n_regions = 1; 538 trans->reduce_power_loaded = true; 539 } 540 } 541 542 return ret; 543 } 544 545 static void iwl_pcie_set_reduce_power_segments(struct iwl_trans *trans) 546 { 547 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 548 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 549 &trans_pcie->prph_scratch->ctrl_cfg; 550 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; 551 552 prph_sc_ctrl->reduce_power_cfg.base_addr = 553 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); 554 prph_sc_ctrl->reduce_power_cfg.size = 555 cpu_to_le32(iwl_dram_regions_size(dram_regions)); 556 } 557 558 static void iwl_pcie_set_continuous_reduce_power(struct iwl_trans *trans) 559 { 560 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 561 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 562 &trans_pcie->prph_scratch->ctrl_cfg; 563 564 prph_sc_ctrl->reduce_power_cfg.base_addr = 565 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical); 566 prph_sc_ctrl->reduce_power_cfg.size = 567 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size); 568 } 569 570 void 571 iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 572 const struct iwl_ucode_capabilities *capa) 573 { 574 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 575 return; 576 577 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 578 iwl_pcie_set_reduce_power_segments(trans); 579 else 580 iwl_pcie_set_continuous_reduce_power(trans); 581 } 582 583