xref: /linux/drivers/net/wireless/intel/iwlwifi/mvm/rs.h (revision 855f492f655711259becb7d34978063ffc40fe12)
1e705c121SKalle Valo /******************************************************************************
2e705c121SKalle Valo  *
3e705c121SKalle Valo  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4e705c121SKalle Valo  * Copyright(c) 2015 Intel Mobile Communications GmbH
5e705c121SKalle Valo  *
6e705c121SKalle Valo  * This program is free software; you can redistribute it and/or modify it
7e705c121SKalle Valo  * under the terms of version 2 of the GNU General Public License as
8e705c121SKalle Valo  * published by the Free Software Foundation.
9e705c121SKalle Valo  *
10e705c121SKalle Valo  * This program is distributed in the hope that it will be useful, but WITHOUT
11e705c121SKalle Valo  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12e705c121SKalle Valo  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13e705c121SKalle Valo  * more details.
14e705c121SKalle Valo  *
15e705c121SKalle Valo  * You should have received a copy of the GNU General Public License along with
16e705c121SKalle Valo  * this program; if not, write to the Free Software Foundation, Inc.,
17e705c121SKalle Valo  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18e705c121SKalle Valo  *
19e705c121SKalle Valo  * The full GNU General Public License is included in this distribution in the
20e705c121SKalle Valo  * file called LICENSE.
21e705c121SKalle Valo  *
22e705c121SKalle Valo  * Contact Information:
23cb2f8277SEmmanuel Grumbach  *  Intel Linux Wireless <linuxwifi@intel.com>
24e705c121SKalle Valo  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25e705c121SKalle Valo  *
26e705c121SKalle Valo  *****************************************************************************/
27e705c121SKalle Valo 
28e705c121SKalle Valo #ifndef __rs_h__
29e705c121SKalle Valo #define __rs_h__
30e705c121SKalle Valo 
31e705c121SKalle Valo #include <net/mac80211.h>
32e705c121SKalle Valo 
33e705c121SKalle Valo #include "iwl-config.h"
34e705c121SKalle Valo 
35e705c121SKalle Valo #include "fw-api.h"
36e705c121SKalle Valo #include "iwl-trans.h"
37e705c121SKalle Valo 
38e705c121SKalle Valo struct iwl_rs_rate_info {
39e705c121SKalle Valo 	u8 plcp;	  /* uCode API:  IWL_RATE_6M_PLCP, etc. */
40e705c121SKalle Valo 	u8 plcp_ht_siso;  /* uCode API:  IWL_RATE_SISO_6M_PLCP, etc. */
41e705c121SKalle Valo 	u8 plcp_ht_mimo2; /* uCode API:  IWL_RATE_MIMO2_6M_PLCP, etc. */
42e705c121SKalle Valo 	u8 plcp_vht_siso;
43e705c121SKalle Valo 	u8 plcp_vht_mimo2;
44e705c121SKalle Valo 	u8 prev_rs;      /* previous rate used in rs algo */
45e705c121SKalle Valo 	u8 next_rs;      /* next rate used in rs algo */
46e705c121SKalle Valo };
47e705c121SKalle Valo 
48e705c121SKalle Valo #define IWL_RATE_60M_PLCP 3
49e705c121SKalle Valo 
50e705c121SKalle Valo enum {
51e705c121SKalle Valo 	IWL_RATE_INVM_INDEX = IWL_RATE_COUNT,
52e705c121SKalle Valo 	IWL_RATE_INVALID = IWL_RATE_COUNT,
53e705c121SKalle Valo };
54e705c121SKalle Valo 
55e705c121SKalle Valo #define LINK_QUAL_MAX_RETRY_NUM 16
56e705c121SKalle Valo 
57e705c121SKalle Valo enum {
58e705c121SKalle Valo 	IWL_RATE_6M_INDEX_TABLE = 0,
59e705c121SKalle Valo 	IWL_RATE_9M_INDEX_TABLE,
60e705c121SKalle Valo 	IWL_RATE_12M_INDEX_TABLE,
61e705c121SKalle Valo 	IWL_RATE_18M_INDEX_TABLE,
62e705c121SKalle Valo 	IWL_RATE_24M_INDEX_TABLE,
63e705c121SKalle Valo 	IWL_RATE_36M_INDEX_TABLE,
64e705c121SKalle Valo 	IWL_RATE_48M_INDEX_TABLE,
65e705c121SKalle Valo 	IWL_RATE_54M_INDEX_TABLE,
66e705c121SKalle Valo 	IWL_RATE_1M_INDEX_TABLE,
67e705c121SKalle Valo 	IWL_RATE_2M_INDEX_TABLE,
68e705c121SKalle Valo 	IWL_RATE_5M_INDEX_TABLE,
69e705c121SKalle Valo 	IWL_RATE_11M_INDEX_TABLE,
70e705c121SKalle Valo 	IWL_RATE_INVM_INDEX_TABLE = IWL_RATE_INVM_INDEX - 1,
71e705c121SKalle Valo };
72e705c121SKalle Valo 
73e705c121SKalle Valo /* #define vs. enum to keep from defaulting to 'large integer' */
74e705c121SKalle Valo #define	IWL_RATE_6M_MASK   (1 << IWL_RATE_6M_INDEX)
75e705c121SKalle Valo #define	IWL_RATE_9M_MASK   (1 << IWL_RATE_9M_INDEX)
76e705c121SKalle Valo #define	IWL_RATE_12M_MASK  (1 << IWL_RATE_12M_INDEX)
77e705c121SKalle Valo #define	IWL_RATE_18M_MASK  (1 << IWL_RATE_18M_INDEX)
78e705c121SKalle Valo #define	IWL_RATE_24M_MASK  (1 << IWL_RATE_24M_INDEX)
79e705c121SKalle Valo #define	IWL_RATE_36M_MASK  (1 << IWL_RATE_36M_INDEX)
80e705c121SKalle Valo #define	IWL_RATE_48M_MASK  (1 << IWL_RATE_48M_INDEX)
81e705c121SKalle Valo #define	IWL_RATE_54M_MASK  (1 << IWL_RATE_54M_INDEX)
82e705c121SKalle Valo #define IWL_RATE_60M_MASK  (1 << IWL_RATE_60M_INDEX)
83e705c121SKalle Valo #define	IWL_RATE_1M_MASK   (1 << IWL_RATE_1M_INDEX)
84e705c121SKalle Valo #define	IWL_RATE_2M_MASK   (1 << IWL_RATE_2M_INDEX)
85e705c121SKalle Valo #define	IWL_RATE_5M_MASK   (1 << IWL_RATE_5M_INDEX)
86e705c121SKalle Valo #define	IWL_RATE_11M_MASK  (1 << IWL_RATE_11M_INDEX)
87e705c121SKalle Valo 
88e705c121SKalle Valo 
89e705c121SKalle Valo /* uCode API values for HT/VHT bit rates */
90e705c121SKalle Valo enum {
91e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_0_PLCP = 0,
92e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_1_PLCP = 1,
93e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_2_PLCP = 2,
94e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_3_PLCP = 3,
95e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_4_PLCP = 4,
96e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_5_PLCP = 5,
97e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_6_PLCP = 6,
98e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_7_PLCP = 7,
99e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_0_PLCP = 0x8,
100e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_1_PLCP = 0x9,
101e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_2_PLCP = 0xA,
102e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_3_PLCP = 0xB,
103e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_4_PLCP = 0xC,
104e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_5_PLCP = 0xD,
105e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_6_PLCP = 0xE,
106e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_7_PLCP = 0xF,
107e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_0_PLCP = 0,
108e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_1_PLCP = 1,
109e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_2_PLCP = 2,
110e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_3_PLCP = 3,
111e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_4_PLCP = 4,
112e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_5_PLCP = 5,
113e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_6_PLCP = 6,
114e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_7_PLCP = 7,
115e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_8_PLCP = 8,
116e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_9_PLCP = 9,
117e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_0_PLCP = 0x10,
118e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_1_PLCP = 0x11,
119e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_2_PLCP = 0x12,
120e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_3_PLCP = 0x13,
121e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_4_PLCP = 0x14,
122e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_5_PLCP = 0x15,
123e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_6_PLCP = 0x16,
124e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_7_PLCP = 0x17,
125e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_8_PLCP = 0x18,
126e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_9_PLCP = 0x19,
127e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_INV_PLCP,
128e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_INV_PLCP = IWL_RATE_HT_SISO_MCS_INV_PLCP,
129e705c121SKalle Valo 	IWL_RATE_VHT_SISO_MCS_INV_PLCP = IWL_RATE_HT_SISO_MCS_INV_PLCP,
130e705c121SKalle Valo 	IWL_RATE_VHT_MIMO2_MCS_INV_PLCP = IWL_RATE_HT_SISO_MCS_INV_PLCP,
131e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_8_PLCP = IWL_RATE_HT_SISO_MCS_INV_PLCP,
132e705c121SKalle Valo 	IWL_RATE_HT_SISO_MCS_9_PLCP = IWL_RATE_HT_SISO_MCS_INV_PLCP,
133e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_8_PLCP = IWL_RATE_HT_SISO_MCS_INV_PLCP,
134e705c121SKalle Valo 	IWL_RATE_HT_MIMO2_MCS_9_PLCP = IWL_RATE_HT_SISO_MCS_INV_PLCP,
135e705c121SKalle Valo };
136e705c121SKalle Valo 
137e705c121SKalle Valo #define IWL_RATES_MASK ((1 << IWL_RATE_COUNT) - 1)
138e705c121SKalle Valo 
139e705c121SKalle Valo #define IWL_INVALID_VALUE    -1
140e705c121SKalle Valo 
141e705c121SKalle Valo #define TPC_MAX_REDUCTION		15
142e705c121SKalle Valo #define TPC_NO_REDUCTION		0
143e705c121SKalle Valo #define TPC_INVALID			0xff
144e705c121SKalle Valo 
145e705c121SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_DEF	(63)
146e705c121SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_MAX	(63)
147e705c121SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_MIN	(0)
148e705c121SKalle Valo 
149e705c121SKalle Valo #define LQ_SIZE		2	/* 2 mode tables:  "Active" and "Search" */
150e705c121SKalle Valo 
151e705c121SKalle Valo /* load per tid defines for A-MPDU activation */
152e705c121SKalle Valo #define IWL_AGG_TPT_THREHOLD	0
153e705c121SKalle Valo #define IWL_AGG_ALL_TID		0xff
154e705c121SKalle Valo 
155e705c121SKalle Valo enum iwl_table_type {
156e705c121SKalle Valo 	LQ_NONE,
157e705c121SKalle Valo 	LQ_LEGACY_G,	/* legacy types */
158e705c121SKalle Valo 	LQ_LEGACY_A,
159e705c121SKalle Valo 	LQ_HT_SISO,	/* HT types */
160e705c121SKalle Valo 	LQ_HT_MIMO2,
161e705c121SKalle Valo 	LQ_VHT_SISO,    /* VHT types */
162e705c121SKalle Valo 	LQ_VHT_MIMO2,
163e705c121SKalle Valo 	LQ_MAX,
164e705c121SKalle Valo };
165e705c121SKalle Valo 
166e705c121SKalle Valo struct rs_rate {
167e705c121SKalle Valo 	int index;
168e705c121SKalle Valo 	enum iwl_table_type type;
169e705c121SKalle Valo 	u8 ant;
170e705c121SKalle Valo 	u32 bw;
171e705c121SKalle Valo 	bool sgi;
172e705c121SKalle Valo 	bool ldpc;
173e705c121SKalle Valo 	bool stbc;
174e705c121SKalle Valo 	bool bfer;
175e705c121SKalle Valo };
176e705c121SKalle Valo 
177e705c121SKalle Valo 
178e705c121SKalle Valo #define is_type_legacy(type) (((type) == LQ_LEGACY_G) || \
179e705c121SKalle Valo 			      ((type) == LQ_LEGACY_A))
180e705c121SKalle Valo #define is_type_ht_siso(type) ((type) == LQ_HT_SISO)
181e705c121SKalle Valo #define is_type_ht_mimo2(type) ((type) == LQ_HT_MIMO2)
182e705c121SKalle Valo #define is_type_vht_siso(type) ((type) == LQ_VHT_SISO)
183e705c121SKalle Valo #define is_type_vht_mimo2(type) ((type) == LQ_VHT_MIMO2)
184e705c121SKalle Valo #define is_type_siso(type) (is_type_ht_siso(type) || is_type_vht_siso(type))
185e705c121SKalle Valo #define is_type_mimo2(type) (is_type_ht_mimo2(type) || is_type_vht_mimo2(type))
186e705c121SKalle Valo #define is_type_mimo(type) (is_type_mimo2(type))
187e705c121SKalle Valo #define is_type_ht(type) (is_type_ht_siso(type) || is_type_ht_mimo2(type))
188e705c121SKalle Valo #define is_type_vht(type) (is_type_vht_siso(type) || is_type_vht_mimo2(type))
189e705c121SKalle Valo #define is_type_a_band(type) ((type) == LQ_LEGACY_A)
190e705c121SKalle Valo #define is_type_g_band(type) ((type) == LQ_LEGACY_G)
191e705c121SKalle Valo 
192e705c121SKalle Valo #define is_legacy(rate)       is_type_legacy((rate)->type)
193e705c121SKalle Valo #define is_ht_siso(rate)      is_type_ht_siso((rate)->type)
194e705c121SKalle Valo #define is_ht_mimo2(rate)     is_type_ht_mimo2((rate)->type)
195e705c121SKalle Valo #define is_vht_siso(rate)     is_type_vht_siso((rate)->type)
196e705c121SKalle Valo #define is_vht_mimo2(rate)    is_type_vht_mimo2((rate)->type)
197e705c121SKalle Valo #define is_siso(rate)         is_type_siso((rate)->type)
198e705c121SKalle Valo #define is_mimo2(rate)        is_type_mimo2((rate)->type)
199e705c121SKalle Valo #define is_mimo(rate)         is_type_mimo((rate)->type)
200e705c121SKalle Valo #define is_ht(rate)           is_type_ht((rate)->type)
201e705c121SKalle Valo #define is_vht(rate)          is_type_vht((rate)->type)
202e705c121SKalle Valo #define is_a_band(rate)       is_type_a_band((rate)->type)
203e705c121SKalle Valo #define is_g_band(rate)       is_type_g_band((rate)->type)
204e705c121SKalle Valo 
205e705c121SKalle Valo #define is_ht20(rate)         ((rate)->bw == RATE_MCS_CHAN_WIDTH_20)
206e705c121SKalle Valo #define is_ht40(rate)         ((rate)->bw == RATE_MCS_CHAN_WIDTH_40)
207e705c121SKalle Valo #define is_ht80(rate)         ((rate)->bw == RATE_MCS_CHAN_WIDTH_80)
208*855f492fSGregory Greenman #define is_ht160(rate)        ((rate)->bw == RATE_MCS_CHAN_WIDTH_160)
209e705c121SKalle Valo 
210e705c121SKalle Valo #define IWL_MAX_MCS_DISPLAY_SIZE	12
211e705c121SKalle Valo 
212e705c121SKalle Valo struct iwl_rate_mcs_info {
213e705c121SKalle Valo 	char	mbps[IWL_MAX_MCS_DISPLAY_SIZE];
214e705c121SKalle Valo 	char	mcs[IWL_MAX_MCS_DISPLAY_SIZE];
215e705c121SKalle Valo };
216e705c121SKalle Valo 
217e705c121SKalle Valo /**
218e705c121SKalle Valo  * struct iwl_rate_scale_data -- tx success history for one rate
219e705c121SKalle Valo  */
220e705c121SKalle Valo struct iwl_rate_scale_data {
221e705c121SKalle Valo 	u64 data;		/* bitmap of successful frames */
222e705c121SKalle Valo 	s32 success_counter;	/* number of frames successful */
223e705c121SKalle Valo 	s32 success_ratio;	/* per-cent * 128  */
224e705c121SKalle Valo 	s32 counter;		/* number of frames attempted */
225e705c121SKalle Valo 	s32 average_tpt;	/* success ratio * expected throughput */
226e705c121SKalle Valo };
227e705c121SKalle Valo 
228e705c121SKalle Valo /* Possible Tx columns
229e705c121SKalle Valo  * Tx Column = a combo of legacy/siso/mimo x antenna x SGI
230e705c121SKalle Valo  */
231e705c121SKalle Valo enum rs_column {
232e705c121SKalle Valo 	RS_COLUMN_LEGACY_ANT_A = 0,
233e705c121SKalle Valo 	RS_COLUMN_LEGACY_ANT_B,
234e705c121SKalle Valo 	RS_COLUMN_SISO_ANT_A,
235e705c121SKalle Valo 	RS_COLUMN_SISO_ANT_B,
236e705c121SKalle Valo 	RS_COLUMN_SISO_ANT_A_SGI,
237e705c121SKalle Valo 	RS_COLUMN_SISO_ANT_B_SGI,
238e705c121SKalle Valo 	RS_COLUMN_MIMO2,
239e705c121SKalle Valo 	RS_COLUMN_MIMO2_SGI,
240e705c121SKalle Valo 
241e705c121SKalle Valo 	RS_COLUMN_LAST = RS_COLUMN_MIMO2_SGI,
242e705c121SKalle Valo 	RS_COLUMN_COUNT = RS_COLUMN_LAST + 1,
243e705c121SKalle Valo 	RS_COLUMN_INVALID,
244e705c121SKalle Valo };
245e705c121SKalle Valo 
246e705c121SKalle Valo enum rs_ss_force_opt {
247e705c121SKalle Valo 	RS_SS_FORCE_NONE = 0,
248e705c121SKalle Valo 	RS_SS_FORCE_STBC,
249e705c121SKalle Valo 	RS_SS_FORCE_BFER,
250e705c121SKalle Valo 	RS_SS_FORCE_SISO,
251e705c121SKalle Valo };
252e705c121SKalle Valo 
253e705c121SKalle Valo /* Packet stats per rate */
254e705c121SKalle Valo struct rs_rate_stats {
255e705c121SKalle Valo 	u64 success;
256e705c121SKalle Valo 	u64 total;
257e705c121SKalle Valo };
258e705c121SKalle Valo 
259e705c121SKalle Valo /**
260e705c121SKalle Valo  * struct iwl_scale_tbl_info -- tx params and success history for all rates
261e705c121SKalle Valo  *
262e705c121SKalle Valo  * There are two of these in struct iwl_lq_sta,
263e705c121SKalle Valo  * one for "active", and one for "search".
264e705c121SKalle Valo  */
265e705c121SKalle Valo struct iwl_scale_tbl_info {
266e705c121SKalle Valo 	struct rs_rate rate;
267e705c121SKalle Valo 	enum rs_column column;
268e705c121SKalle Valo 	const u16 *expected_tpt;	/* throughput metrics; expected_tpt_G, etc. */
269e705c121SKalle Valo 	struct iwl_rate_scale_data win[IWL_RATE_COUNT]; /* rate histories */
270e705c121SKalle Valo 	/* per txpower-reduction history */
271e705c121SKalle Valo 	struct iwl_rate_scale_data tpc_win[TPC_MAX_REDUCTION + 1];
272e705c121SKalle Valo };
273e705c121SKalle Valo 
274e705c121SKalle Valo enum {
275e705c121SKalle Valo 	RS_STATE_SEARCH_CYCLE_STARTED,
276e705c121SKalle Valo 	RS_STATE_SEARCH_CYCLE_ENDED,
277e705c121SKalle Valo 	RS_STATE_STAY_IN_COLUMN,
278e705c121SKalle Valo };
279e705c121SKalle Valo 
280e705c121SKalle Valo /**
281e705c121SKalle Valo  * struct iwl_lq_sta -- driver's rate scaling private structure
282e705c121SKalle Valo  *
283e705c121SKalle Valo  * Pointer to this gets passed back and forth between driver and mac80211.
284e705c121SKalle Valo  */
285e705c121SKalle Valo struct iwl_lq_sta {
286e705c121SKalle Valo 	u8 active_tbl;		/* index of active table, range 0-1 */
287e705c121SKalle Valo 	u8 rs_state;            /* RS_STATE_* */
288e705c121SKalle Valo 	u8 search_better_tbl;	/* 1: currently trying alternate mode */
289e705c121SKalle Valo 	s32 last_tpt;
290e705c121SKalle Valo 
291e705c121SKalle Valo 	/* The following determine when to search for a new mode */
292e705c121SKalle Valo 	u32 table_count_limit;
293e705c121SKalle Valo 	u32 max_failure_limit;	/* # failed frames before new search */
294e705c121SKalle Valo 	u32 max_success_limit;	/* # successful frames before new search */
295e705c121SKalle Valo 	u32 table_count;
296e705c121SKalle Valo 	u32 total_failed;	/* total failed frames, any/all rates */
297e705c121SKalle Valo 	u32 total_success;	/* total successful frames, any/all rates */
298e705c121SKalle Valo 	u64 flush_timer;	/* time staying in mode before new search */
299e705c121SKalle Valo 
300e705c121SKalle Valo 	u32 visited_columns;    /* Bitmask marking which Tx columns were
301e705c121SKalle Valo 				 * explored during a search cycle
302e705c121SKalle Valo 				 */
303e705c121SKalle Valo 	u64 last_tx;
304e705c121SKalle Valo 	bool is_vht;
305e705c121SKalle Valo 	bool ldpc;              /* LDPC Rx is supported by the STA */
306e705c121SKalle Valo 	bool stbc_capable;      /* Tx STBC is supported by chip and Rx by STA */
307e705c121SKalle Valo 	bool bfer_capable;      /* Remote supports beamformee and we BFer */
308e705c121SKalle Valo 
30957fbcce3SJohannes Berg 	enum nl80211_band band;
310e705c121SKalle Valo 
311e705c121SKalle Valo 	/* The following are bitmaps of rates; IWL_RATE_6M_MASK, etc. */
312e705c121SKalle Valo 	unsigned long active_legacy_rate;
313e705c121SKalle Valo 	unsigned long active_siso_rate;
314e705c121SKalle Valo 	unsigned long active_mimo2_rate;
315e705c121SKalle Valo 
316e705c121SKalle Valo 	/* Highest rate per Tx mode */
317e705c121SKalle Valo 	u8 max_legacy_rate_idx;
318e705c121SKalle Valo 	u8 max_siso_rate_idx;
319e705c121SKalle Valo 	u8 max_mimo2_rate_idx;
320e705c121SKalle Valo 
321e705c121SKalle Valo 	/* Optimal rate based on RSSI and STA caps.
322e705c121SKalle Valo 	 * Used only to reflect link speed to userspace.
323e705c121SKalle Valo 	 */
324e705c121SKalle Valo 	struct rs_rate optimal_rate;
325e705c121SKalle Valo 	unsigned long optimal_rate_mask;
326e705c121SKalle Valo 	const struct rs_init_rate_info *optimal_rates;
327e705c121SKalle Valo 	int optimal_nentries;
328e705c121SKalle Valo 
329e705c121SKalle Valo 	u8 missed_rate_counter;
330e705c121SKalle Valo 
331e705c121SKalle Valo 	struct iwl_lq_cmd lq;
332e705c121SKalle Valo 	struct iwl_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
333e705c121SKalle Valo 	u8 tx_agg_tid_en;
334e705c121SKalle Valo 
335e705c121SKalle Valo 	/* last tx rate_n_flags */
336e705c121SKalle Valo 	u32 last_rate_n_flags;
337e705c121SKalle Valo 	/* packets destined for this STA are aggregated */
338e705c121SKalle Valo 	u8 is_agg;
339e705c121SKalle Valo 
340e705c121SKalle Valo 	/* tx power reduce for this sta */
341e705c121SKalle Valo 	int tpc_reduce;
342e705c121SKalle Valo 
343e705c121SKalle Valo 	/* persistent fields - initialized only once - keep last! */
344e705c121SKalle Valo 	struct lq_sta_pers {
345e705c121SKalle Valo #ifdef CONFIG_MAC80211_DEBUGFS
346e705c121SKalle Valo 		u32 dbg_fixed_rate;
347e705c121SKalle Valo 		u8 dbg_fixed_txp_reduction;
348e705c121SKalle Valo 
349e705c121SKalle Valo 		/* force STBC/BFER/SISO for testing */
350e705c121SKalle Valo 		enum rs_ss_force_opt ss_force;
351e705c121SKalle Valo #endif
352e705c121SKalle Valo 		u8 chains;
353e705c121SKalle Valo 		s8 chain_signal[IEEE80211_MAX_CHAINS];
354e705c121SKalle Valo 		s8 last_rssi;
355e705c121SKalle Valo 		struct rs_rate_stats tx_stats[RS_COLUMN_COUNT][IWL_RATE_COUNT];
356e705c121SKalle Valo 		struct iwl_mvm *drv;
357e705c121SKalle Valo 	} pers;
358e705c121SKalle Valo };
359e705c121SKalle Valo 
360e705c121SKalle Valo /* Initialize station's rate scaling information after adding station */
361e705c121SKalle Valo void iwl_mvm_rs_rate_init(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
36257fbcce3SJohannes Berg 			  enum nl80211_band band, bool init);
363e705c121SKalle Valo 
364e705c121SKalle Valo /* Notify RS about Tx status */
365e705c121SKalle Valo void iwl_mvm_rs_tx_status(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
366ff7a68d0SMatti Gottlieb 			  int tid, struct ieee80211_tx_info *info, bool ndp);
367e705c121SKalle Valo 
368e705c121SKalle Valo /**
369e705c121SKalle Valo  * iwl_rate_control_register - Register the rate control algorithm callbacks
370e705c121SKalle Valo  *
371e705c121SKalle Valo  * Since the rate control algorithm is hardware specific, there is no need
372e705c121SKalle Valo  * or reason to place it as a stand alone module.  The driver can call
373e705c121SKalle Valo  * iwl_rate_control_register in order to register the rate control callbacks
374e705c121SKalle Valo  * with the mac80211 subsystem.  This should be performed prior to calling
375e705c121SKalle Valo  * ieee80211_register_hw
376e705c121SKalle Valo  *
377e705c121SKalle Valo  */
378e705c121SKalle Valo int iwl_mvm_rate_control_register(void);
379e705c121SKalle Valo 
380e705c121SKalle Valo /**
381e705c121SKalle Valo  * iwl_rate_control_unregister - Unregister the rate control callbacks
382e705c121SKalle Valo  *
383e705c121SKalle Valo  * This should be called after calling ieee80211_unregister_hw, but before
384e705c121SKalle Valo  * the driver is unloaded.
385e705c121SKalle Valo  */
386e705c121SKalle Valo void iwl_mvm_rate_control_unregister(void);
387e705c121SKalle Valo 
388e705c121SKalle Valo struct iwl_mvm_sta;
389e705c121SKalle Valo 
390e705c121SKalle Valo int iwl_mvm_tx_protection(struct iwl_mvm *mvm, struct iwl_mvm_sta *mvmsta,
391e705c121SKalle Valo 			  bool enable);
392e705c121SKalle Valo 
393e705c121SKalle Valo #endif /* __rs__ */
394