xref: /linux/drivers/net/wireless/intel/iwlwifi/mld/constants.h (revision 1a9239bb4253f9076b5b4b2a1a4e8d7defd77a95)
1d1e879ecSMiri Korenblit /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2d1e879ecSMiri Korenblit /*
3d1e879ecSMiri Korenblit  * Copyright (C) 2024-2025 Intel Corporation
4d1e879ecSMiri Korenblit  */
5d1e879ecSMiri Korenblit #ifndef __iwl_mld_constants_h__
6d1e879ecSMiri Korenblit #define __iwl_mld_constants_h__
7d1e879ecSMiri Korenblit 
8d1e879ecSMiri Korenblit #define IWL_MLD_MISSED_BEACONS_SINCE_RX_THOLD			4
9d1e879ecSMiri Korenblit #define IWL_MLD_MISSED_BEACONS_THRESHOLD			8
10d1e879ecSMiri Korenblit #define IWL_MLD_MISSED_BEACONS_THRESHOLD_LONG			19
11d1e879ecSMiri Korenblit #define IWL_MLD_BCN_LOSS_EXIT_ESR_THRESH_2_LINKS		5
12d1e879ecSMiri Korenblit #define IWL_MLD_BCN_LOSS_EXIT_ESR_THRESH			15
13d1e879ecSMiri Korenblit #define IWL_MLD_BCN_LOSS_EXIT_ESR_THRESH_BSS_PARAM_CHANGED	11
14d1e879ecSMiri Korenblit #define IWL_MLD_LOW_RSSI_MLO_SCAN_THRESH			-72
15d1e879ecSMiri Korenblit 
16d1e879ecSMiri Korenblit #define IWL_MLD_DEFAULT_PS_TX_DATA_TIMEOUT	(100 * USEC_PER_MSEC)
17d1e879ecSMiri Korenblit #define IWL_MLD_DEFAULT_PS_RX_DATA_TIMEOUT	(100 * USEC_PER_MSEC)
18d1e879ecSMiri Korenblit #define IWL_MLD_WOWLAN_PS_TX_DATA_TIMEOUT	(10 * USEC_PER_MSEC)
19d1e879ecSMiri Korenblit #define IWL_MLD_WOWLAN_PS_RX_DATA_TIMEOUT	(10 * USEC_PER_MSEC)
20d1e879ecSMiri Korenblit #define IWL_MLD_SHORT_PS_TX_DATA_TIMEOUT	(2 * 1024) /* defined in TU */
21d1e879ecSMiri Korenblit #define IWL_MLD_SHORT_PS_RX_DATA_TIMEOUT	(40 * 1024) /* defined in TU */
22d1e879ecSMiri Korenblit 
23d1e879ecSMiri Korenblit #define IWL_MLD_UAPSD_RX_DATA_TIMEOUT		(50 * USEC_PER_MSEC)
24d1e879ecSMiri Korenblit #define IWL_MLD_UAPSD_TX_DATA_TIMEOUT		(50 * USEC_PER_MSEC)
25d1e879ecSMiri Korenblit 
26d1e879ecSMiri Korenblit #define IWL_MLD_PS_SNOOZE_INTERVAL		25
27d1e879ecSMiri Korenblit #define IWL_MLD_PS_SNOOZE_INTERVAL		25
28d1e879ecSMiri Korenblit #define IWL_MLD_PS_SNOOZE_WINDOW		50
29d1e879ecSMiri Korenblit 
30d1e879ecSMiri Korenblit #define IWL_MLD_PS_SNOOZE_HEAVY_TX_THLD_PACKETS	30
31d1e879ecSMiri Korenblit #define IWL_MLD_PS_SNOOZE_HEAVY_RX_THLD_PACKETS	20
32d1e879ecSMiri Korenblit 
33d1e879ecSMiri Korenblit #define IWL_MLD_PS_HEAVY_TX_THLD_PERCENT	50
34d1e879ecSMiri Korenblit #define IWL_MLD_PS_HEAVY_RX_THLD_PERCENT	50
35d1e879ecSMiri Korenblit #define IWL_MLD_PS_HEAVY_TX_THLD_PACKETS	20
36d1e879ecSMiri Korenblit #define IWL_MLD_PS_HEAVY_RX_THLD_PACKETS	8
37d1e879ecSMiri Korenblit 
38d1e879ecSMiri Korenblit #define IWL_MLD_TRIGGER_LINK_SEL_TIME_SEC	30
39d1e879ecSMiri Korenblit #define IWL_MLD_SCAN_EXPIRE_TIME_SEC		20
40d1e879ecSMiri Korenblit 
41d1e879ecSMiri Korenblit #define IWL_MLD_TPT_COUNT_WINDOW (5 * HZ)
42d1e879ecSMiri Korenblit 
43d1e879ecSMiri Korenblit /* OMI reduced BW thresholds (channel load percentage) */
44d1e879ecSMiri Korenblit #define IWL_MLD_OMI_ENTER_CHAN_LOAD		10
45d1e879ecSMiri Korenblit #define IWL_MLD_OMI_EXIT_CHAN_LOAD_160		20
46d1e879ecSMiri Korenblit #define IWL_MLD_OMI_EXIT_CHAN_LOAD_320		30
47d1e879ecSMiri Korenblit /* time (in milliseconds) to let AP "settle" the OMI */
48d1e879ecSMiri Korenblit #define IWL_MLD_OMI_AP_SETTLE_DELAY		27
49d1e879ecSMiri Korenblit /* time (in milliseconds) to not enter OMI reduced BW after leaving */
50d1e879ecSMiri Korenblit #define IWL_MLD_OMI_EXIT_PROTECTION		5000
51d1e879ecSMiri Korenblit 
52d1e879ecSMiri Korenblit #define IWL_MLD_DIS_RANDOM_FW_ID                false
53d1e879ecSMiri Korenblit #define IWL_MLD_D3_DEBUG                        false
54d1e879ecSMiri Korenblit #define IWL_MLD_NON_TRANSMITTING_AP	        false
55d1e879ecSMiri Korenblit #define IWL_MLD_6GHZ_PASSIVE_SCAN_TIMEOUT       3000 /* in seconds */
56d1e879ecSMiri Korenblit #define IWL_MLD_6GHZ_PASSIVE_SCAN_ASSOC_TIMEOUT 60   /* in seconds */
57d1e879ecSMiri Korenblit #define IWL_MLD_CONN_LISTEN_INTERVAL		10
58d1e879ecSMiri Korenblit #define IWL_MLD_ADAPTIVE_DWELL_NUM_APS_OVERRIDE 0
59d1e879ecSMiri Korenblit #define IWL_MLD_AUTO_EML_ENABLE			true
60d1e879ecSMiri Korenblit 
61d1e879ecSMiri Korenblit #define IWL_MLD_HIGH_RSSI_THRESH_20MHZ		-67
62d1e879ecSMiri Korenblit #define IWL_MLD_LOW_RSSI_THRESH_20MHZ		-72
63d1e879ecSMiri Korenblit #define IWL_MLD_HIGH_RSSI_THRESH_40MHZ		-64
64d1e879ecSMiri Korenblit #define IWL_MLD_LOW_RSSI_THRESH_40MHZ		-72
65d1e879ecSMiri Korenblit #define IWL_MLD_HIGH_RSSI_THRESH_80MHZ		-61
66d1e879ecSMiri Korenblit #define IWL_MLD_LOW_RSSI_THRESH_80MHZ		-72
67d1e879ecSMiri Korenblit #define IWL_MLD_HIGH_RSSI_THRESH_160MHZ		-58
68d1e879ecSMiri Korenblit #define IWL_MLD_LOW_RSSI_THRESH_160MHZ		-72
69d1e879ecSMiri Korenblit 
70d1e879ecSMiri Korenblit #define IWL_MLD_ENTER_EMLSR_TPT_THRESH		400
71*4d7236f9SMiri Korenblit #define IWL_MLD_EXIT_EMLSR_CHAN_LOAD		2 /* in percentage */
72d1e879ecSMiri Korenblit 
73d1e879ecSMiri Korenblit #define IWL_MLD_FTM_INITIATOR_ALGO		IWL_TOF_ALGO_TYPE_MAX_LIKE
74d1e879ecSMiri Korenblit #define IWL_MLD_FTM_INITIATOR_DYNACK		true
75d1e879ecSMiri Korenblit #define IWL_MLD_FTM_LMR_FEEDBACK_TERMINATE	false
76d1e879ecSMiri Korenblit #define IWL_MLD_FTM_TEST_INCORRECT_SAC		false
77d1e879ecSMiri Korenblit #define IWL_MLD_FTM_R2I_MAX_REP			7
78d1e879ecSMiri Korenblit #define IWL_MLD_FTM_I2R_MAX_REP			7
79d1e879ecSMiri Korenblit #define IWL_MLD_FTM_R2I_MAX_STS			1
80d1e879ecSMiri Korenblit #define IWL_MLD_FTM_I2R_MAX_STS			1
81d1e879ecSMiri Korenblit #define IWL_MLD_FTM_R2I_MAX_TOTAL_LTF		3
82d1e879ecSMiri Korenblit #define IWL_MLD_FTM_I2R_MAX_TOTAL_LTF		3
83d1e879ecSMiri Korenblit #define IWL_MLD_FTM_RESP_NDP_SUPPORT		true
84d1e879ecSMiri Korenblit #define IWL_MLD_FTM_RESP_LMR_FEEDBACK_SUPPORT	true
85d1e879ecSMiri Korenblit #define IWL_MLD_FTM_NON_TB_MIN_TIME_BETWEEN_MSR	7
86d1e879ecSMiri Korenblit #define IWL_MLD_FTM_NON_TB_MAX_TIME_BETWEEN_MSR	1000
87d1e879ecSMiri Korenblit 
88d1e879ecSMiri Korenblit #endif /* __iwl_mld_constants_h__ */
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