1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_trans_h__ 8 #define __iwl_trans_h__ 9 10 #include <linux/ieee80211.h> 11 #include <linux/mm.h> /* for page_address */ 12 #include <linux/lockdep.h> 13 #include <linux/kernel.h> 14 15 #include "iwl-debug.h" 16 #include "iwl-config.h" 17 #include "fw/img.h" 18 #include "iwl-op-mode.h" 19 #include <linux/firmware.h> 20 #include "fw/api/cmdhdr.h" 21 #include "fw/api/txq.h" 22 #include "fw/api/dbg-tlv.h" 23 #include "iwl-dbg-tlv.h" 24 25 /** 26 * DOC: Transport layer - what is it ? 27 * 28 * The transport layer is the layer that deals with the HW directly. It provides 29 * an abstraction of the underlying HW to the upper layer. The transport layer 30 * doesn't provide any policy, algorithm or anything of this kind, but only 31 * mechanisms to make the HW do something. It is not completely stateless but 32 * close to it. 33 * We will have an implementation for each different supported bus. 34 */ 35 36 /** 37 * DOC: Life cycle of the transport layer 38 * 39 * The transport layer has a very precise life cycle. 40 * 41 * 1) A helper function is called during the module initialization and 42 * registers the bus driver's ops with the transport's alloc function. 43 * 2) Bus's probe calls to the transport layer's allocation functions. 44 * Of course this function is bus specific. 45 * 3) This allocation functions will spawn the upper layer which will 46 * register mac80211. 47 * 48 * 4) At some point (i.e. mac80211's start call), the op_mode will call 49 * the following sequence: 50 * start_hw 51 * start_fw 52 * 53 * 5) Then when finished (or reset): 54 * stop_device 55 * 56 * 6) Eventually, the free function will be called. 57 */ 58 59 /* default preset 0 (start from bit 16)*/ 60 #define IWL_FW_DBG_DOMAIN_POS 16 61 #define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS) 62 63 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 64 65 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 66 #define FH_RSCSR_FRAME_INVALID 0x55550000 67 #define FH_RSCSR_FRAME_ALIGN 0x40 68 #define FH_RSCSR_RPA_EN BIT(25) 69 #define FH_RSCSR_RADA_EN BIT(26) 70 #define FH_RSCSR_RXQ_POS 16 71 #define FH_RSCSR_RXQ_MASK 0x3F0000 72 73 struct iwl_rx_packet { 74 /* 75 * The first 4 bytes of the RX frame header contain both the RX frame 76 * size and some flags. 77 * Bit fields: 78 * 31: flag flush RB request 79 * 30: flag ignore TC (terminal counter) request 80 * 29: flag fast IRQ request 81 * 28-27: Reserved 82 * 26: RADA enabled 83 * 25: Offload enabled 84 * 24: RPF enabled 85 * 23: RSS enabled 86 * 22: Checksum enabled 87 * 21-16: RX queue 88 * 15-14: Reserved 89 * 13-00: RX frame size 90 */ 91 __le32 len_n_flags; 92 struct iwl_cmd_header hdr; 93 u8 data[]; 94 } __packed; 95 96 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 97 { 98 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 99 } 100 101 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 102 { 103 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 104 } 105 106 /** 107 * enum CMD_MODE - how to send the host commands ? 108 * 109 * @CMD_ASYNC: Return right away and don't wait for the response 110 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 111 * the response. The caller needs to call iwl_free_resp when done. 112 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill. 113 * @CMD_BLOCK_TXQS: Block TXQs while the comment is executing. 114 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to 115 * SUSPEND and RESUME commands. We are in D3 mode when we set 116 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3. 117 */ 118 enum CMD_MODE { 119 CMD_ASYNC = BIT(0), 120 CMD_WANT_SKB = BIT(1), 121 CMD_SEND_IN_RFKILL = BIT(2), 122 CMD_BLOCK_TXQS = BIT(3), 123 CMD_SEND_IN_D3 = BIT(4), 124 }; 125 126 #define DEF_CMD_PAYLOAD_SIZE 320 127 128 /** 129 * struct iwl_device_cmd 130 * 131 * For allocation of the command and tx queues, this establishes the overall 132 * size of the largest command we send to uCode, except for commands that 133 * aren't fully copied and use other TFD space. 134 */ 135 struct iwl_device_cmd { 136 union { 137 struct { 138 struct iwl_cmd_header hdr; /* uCode API */ 139 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 140 }; 141 struct { 142 struct iwl_cmd_header_wide hdr_wide; 143 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 144 sizeof(struct iwl_cmd_header_wide) + 145 sizeof(struct iwl_cmd_header)]; 146 }; 147 }; 148 } __packed; 149 150 /** 151 * struct iwl_device_tx_cmd - buffer for TX command 152 * @hdr: the header 153 * @payload: the payload placeholder 154 * 155 * The actual structure is sized dynamically according to need. 156 */ 157 struct iwl_device_tx_cmd { 158 struct iwl_cmd_header hdr; 159 u8 payload[]; 160 } __packed; 161 162 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 163 164 /* 165 * number of transfer buffers (fragments) per transmit frame descriptor; 166 * this is just the driver's idea, the hardware supports 20 167 */ 168 #define IWL_MAX_CMD_TBS_PER_TFD 2 169 170 /* We need 2 entries for the TX command and header, and another one might 171 * be needed for potential data in the SKB's head. The remaining ones can 172 * be used for frags. 173 */ 174 #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 175 176 /** 177 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 178 * 179 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 180 * ring. The transport layer doesn't map the command's buffer to DMA, but 181 * rather copies it to a previously allocated DMA buffer. This flag tells 182 * the transport layer not to copy the command, but to map the existing 183 * buffer (that is passed in) instead. This saves the memcpy and allows 184 * commands that are bigger than the fixed buffer to be submitted. 185 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 186 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 187 * chunk internally and free it again after the command completes. This 188 * can (currently) be used only once per command. 189 * Note that a TFD entry after a DUP one cannot be a normal copied one. 190 */ 191 enum iwl_hcmd_dataflag { 192 IWL_HCMD_DFL_NOCOPY = BIT(0), 193 IWL_HCMD_DFL_DUP = BIT(1), 194 }; 195 196 enum iwl_error_event_table_status { 197 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 198 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 199 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 200 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3), 201 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4), 202 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5), 203 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6), 204 }; 205 206 /** 207 * struct iwl_host_cmd - Host command to the uCode 208 * 209 * @data: array of chunks that composes the data of the host command 210 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 211 * @_rx_page_order: (internally used to free response packet) 212 * @_rx_page_addr: (internally used to free response packet) 213 * @flags: can be CMD_* 214 * @len: array of the lengths of the chunks in data 215 * @dataflags: IWL_HCMD_DFL_* 216 * @id: command id of the host command, for wide commands encoding the 217 * version and group as well 218 */ 219 struct iwl_host_cmd { 220 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 221 struct iwl_rx_packet *resp_pkt; 222 unsigned long _rx_page_addr; 223 u32 _rx_page_order; 224 225 u32 flags; 226 u32 id; 227 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 228 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 229 }; 230 231 static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 232 { 233 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 234 } 235 236 struct iwl_rx_cmd_buffer { 237 struct page *_page; 238 int _offset; 239 bool _page_stolen; 240 u32 _rx_page_order; 241 unsigned int truesize; 242 }; 243 244 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 245 { 246 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 247 } 248 249 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 250 { 251 return r->_offset; 252 } 253 254 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 255 { 256 r->_page_stolen = true; 257 get_page(r->_page); 258 return r->_page; 259 } 260 261 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 262 { 263 __free_pages(r->_page, r->_rx_page_order); 264 } 265 266 #define MAX_NO_RECLAIM_CMDS 6 267 268 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 269 270 /* 271 * Maximum number of HW queues the transport layer 272 * currently supports 273 */ 274 #define IWL_MAX_HW_QUEUES 32 275 #define IWL_MAX_TVQM_QUEUES 512 276 277 #define IWL_MAX_TID_COUNT 8 278 #define IWL_MGMT_TID 15 279 #define IWL_FRAME_LIMIT 64 280 #define IWL_MAX_RX_HW_QUEUES 16 281 #define IWL_9000_MAX_RX_HW_QUEUES 1 282 283 /** 284 * enum iwl_wowlan_status - WoWLAN image/device status 285 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 286 * @IWL_D3_STATUS_RESET: device was reset while suspended 287 */ 288 enum iwl_d3_status { 289 IWL_D3_STATUS_ALIVE, 290 IWL_D3_STATUS_RESET, 291 }; 292 293 /** 294 * enum iwl_trans_status: transport status flags 295 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 296 * @STATUS_DEVICE_ENABLED: APM is enabled 297 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 298 * @STATUS_INT_ENABLED: interrupts are enabled 299 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 300 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 301 * @STATUS_FW_ERROR: the fw is in error state 302 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 303 * are sent 304 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 305 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 306 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once, 307 * e.g. for testing 308 */ 309 enum iwl_trans_status { 310 STATUS_SYNC_HCMD_ACTIVE, 311 STATUS_DEVICE_ENABLED, 312 STATUS_TPOWER_PMI, 313 STATUS_INT_ENABLED, 314 STATUS_RFKILL_HW, 315 STATUS_RFKILL_OPMODE, 316 STATUS_FW_ERROR, 317 STATUS_TRANS_GOING_IDLE, 318 STATUS_TRANS_IDLE, 319 STATUS_TRANS_DEAD, 320 STATUS_SUPPRESS_CMD_ERROR_ONCE, 321 }; 322 323 static inline int 324 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 325 { 326 switch (rb_size) { 327 case IWL_AMSDU_2K: 328 return get_order(2 * 1024); 329 case IWL_AMSDU_4K: 330 return get_order(4 * 1024); 331 case IWL_AMSDU_8K: 332 return get_order(8 * 1024); 333 case IWL_AMSDU_12K: 334 return get_order(16 * 1024); 335 default: 336 WARN_ON(1); 337 return -1; 338 } 339 } 340 341 static inline int 342 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 343 { 344 switch (rb_size) { 345 case IWL_AMSDU_2K: 346 return 2 * 1024; 347 case IWL_AMSDU_4K: 348 return 4 * 1024; 349 case IWL_AMSDU_8K: 350 return 8 * 1024; 351 case IWL_AMSDU_12K: 352 return 16 * 1024; 353 default: 354 WARN_ON(1); 355 return 0; 356 } 357 } 358 359 struct iwl_hcmd_names { 360 u8 cmd_id; 361 const char *const cmd_name; 362 }; 363 364 #define HCMD_NAME(x) \ 365 { .cmd_id = x, .cmd_name = #x } 366 367 struct iwl_hcmd_arr { 368 const struct iwl_hcmd_names *arr; 369 int size; 370 }; 371 372 #define HCMD_ARR(x) \ 373 { .arr = x, .size = ARRAY_SIZE(x) } 374 375 /** 376 * struct iwl_dump_sanitize_ops - dump sanitization operations 377 * @frob_txf: Scrub the TX FIFO data 378 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header 379 * but that might be short or long (&struct iwl_cmd_header or 380 * &struct iwl_cmd_header_wide) 381 * @frob_mem: Scrub memory data 382 */ 383 struct iwl_dump_sanitize_ops { 384 void (*frob_txf)(void *ctx, void *buf, size_t buflen); 385 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen); 386 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen); 387 }; 388 389 /** 390 * struct iwl_trans_config - transport configuration 391 * 392 * @op_mode: pointer to the upper layer. 393 * @cmd_queue: the index of the command queue. 394 * Must be set before start_fw. 395 * @cmd_fifo: the fifo for host commands 396 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 397 * @no_reclaim_cmds: Some devices erroneously don't set the 398 * SEQ_RX_FRAME bit on some notifications, this is the 399 * list of such notifications to filter. Max length is 400 * %MAX_NO_RECLAIM_CMDS. 401 * @n_no_reclaim_cmds: # of commands in list 402 * @rx_buf_size: RX buffer size needed for A-MSDUs 403 * if unset 4k will be the RX buffer size 404 * @bc_table_dword: set to true if the BC table expects the byte count to be 405 * in DWORD (as opposed to bytes) 406 * @scd_set_active: should the transport configure the SCD for HCMD queue 407 * @command_groups: array of command groups, each member is an array of the 408 * commands in the group; for debugging only 409 * @command_groups_size: number of command groups, to avoid illegal access 410 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 411 * space for at least two pointers 412 * @fw_reset_handshake: firmware supports reset flow handshake 413 * @queue_alloc_cmd_ver: queue allocation command version, set to 0 414 * for using the older SCD_QUEUE_CFG, set to the version of 415 * SCD_QUEUE_CONFIG_CMD otherwise. 416 */ 417 struct iwl_trans_config { 418 struct iwl_op_mode *op_mode; 419 420 u8 cmd_queue; 421 u8 cmd_fifo; 422 unsigned int cmd_q_wdg_timeout; 423 const u8 *no_reclaim_cmds; 424 unsigned int n_no_reclaim_cmds; 425 426 enum iwl_amsdu_size rx_buf_size; 427 bool bc_table_dword; 428 bool scd_set_active; 429 const struct iwl_hcmd_arr *command_groups; 430 int command_groups_size; 431 432 u8 cb_data_offs; 433 bool fw_reset_handshake; 434 u8 queue_alloc_cmd_ver; 435 }; 436 437 struct iwl_trans_dump_data { 438 u32 len; 439 u8 data[]; 440 }; 441 442 struct iwl_trans; 443 444 struct iwl_trans_txq_scd_cfg { 445 u8 fifo; 446 u8 sta_id; 447 u8 tid; 448 bool aggregate; 449 int frame_limit; 450 }; 451 452 /** 453 * struct iwl_trans_rxq_dma_data - RX queue DMA data 454 * @fr_bd_cb: DMA address of free BD cyclic buffer 455 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 456 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 457 * @ur_bd_cb: DMA address of used BD cyclic buffer 458 */ 459 struct iwl_trans_rxq_dma_data { 460 u64 fr_bd_cb; 461 u32 fr_bd_wid; 462 u64 urbd_stts_wrptr; 463 u64 ur_bd_cb; 464 }; 465 466 /* maximal number of DRAM MAP entries supported by FW */ 467 #define IPC_DRAM_MAP_ENTRY_NUM_MAX 64 468 469 /** 470 * struct iwl_pnvm_image - contains info about the parsed pnvm image 471 * @chunks: array of pointers to pnvm payloads and their sizes 472 * @n_chunks: the number of the pnvm payloads. 473 * @version: the version of the loaded PNVM image 474 */ 475 struct iwl_pnvm_image { 476 struct { 477 const void *data; 478 u32 len; 479 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 480 u32 n_chunks; 481 u32 version; 482 }; 483 484 /** 485 * struct iwl_trans_ops - transport specific operations 486 * 487 * All the handlers MUST be implemented 488 * 489 * @start_hw: starts the HW. From that point on, the HW can send interrupts. 490 * May sleep. 491 * @op_mode_leave: Turn off the HW RF kill indication if on 492 * May sleep 493 * @start_fw: allocates and inits all the resources for the transport 494 * layer. Also kick a fw image. 495 * May sleep 496 * @fw_alive: called when the fw sends alive notification. If the fw provides 497 * the SCD base address in SRAM, then provide it here, or 0 otherwise. 498 * May sleep 499 * @stop_device: stops the whole device (embedded CPU put to reset) and stops 500 * the HW. From that point on, the HW will be stopped but will still issue 501 * an interrupt if the HW RF kill switch is triggered. 502 * This callback must do the right thing and not crash even if %start_hw() 503 * was called but not &start_fw(). May sleep. 504 * @d3_suspend: put the device into the correct mode for WoWLAN during 505 * suspend. This is optional, if not implemented WoWLAN will not be 506 * supported. This callback may sleep. 507 * @d3_resume: resume the device after WoWLAN, enabling the opmode to 508 * talk to the WoWLAN image to get its status. This is optional, if not 509 * implemented WoWLAN will not be supported. This callback may sleep. 510 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 511 * If RFkill is asserted in the middle of a SYNC host command, it must 512 * return -ERFKILL straight away. 513 * May sleep only if CMD_ASYNC is not set 514 * @tx: send an skb. The transport relies on the op_mode to zero the 515 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 516 * the CSUM will be taken care of (TCP CSUM and IP header in case of 517 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 518 * header if it is IPv4. 519 * Must be atomic 520 * @reclaim: free packet until ssn. Returns a list of freed packets. 521 * Must be atomic 522 * @txq_enable: setup a queue. To setup an AC queue, use the 523 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 524 * this one. The op_mode must not configure the HCMD queue. The scheduler 525 * configuration may be %NULL, in which case the hardware will not be 526 * configured. If true is returned, the operation mode needs to increment 527 * the sequence number of the packets routed to this queue because of a 528 * hardware scheduler bug. May sleep. 529 * @txq_disable: de-configure a Tx queue to send AMPDUs 530 * Must be atomic 531 * @txq_set_shared_mode: change Tx queue shared/unshared marking 532 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 533 * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 534 * @freeze_txq_timer: prevents the timer of the queue from firing until the 535 * queue is set to awake. Must be atomic. 536 * @write8: write a u8 to a register at offset ofs from the BAR 537 * @write32: write a u32 to a register at offset ofs from the BAR 538 * @read32: read a u32 register at offset ofs from the BAR 539 * @read_prph: read a DWORD from a periphery register 540 * @write_prph: write a DWORD to a periphery register 541 * @read_mem: read device's SRAM in DWORD 542 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 543 * will be zeroed. 544 * @read_config32: read a u32 value from the device's config space at 545 * the given offset. 546 * @configure: configure parameters required by the transport layer from 547 * the op_mode. May be called several times before start_fw, can't be 548 * called after that. 549 * @set_pmi: set the power pmi state 550 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 551 * Sleeping is not allowed between grab_nic_access and 552 * release_nic_access. 553 * @release_nic_access: let the NIC go to sleep. The "flags" parameter 554 * must be the same one that was sent before to the grab_nic_access. 555 * @set_bits_mask - set SRAM register according to value and mask. 556 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 557 * TX'ed commands and similar. The buffer will be vfree'd by the caller. 558 * Note that the transport must fill in the proper file headers. 559 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 560 * of the trans debugfs 561 * @load_pnvm: save the pnvm data in DRAM 562 * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the 563 * context info. 564 * @load_reduce_power: copy reduce power table to the corresponding DRAM memory 565 * @set_reduce_power: set reduce power table addresses in the sratch buffer 566 * @interrupts: disable/enable interrupts to transport 567 */ 568 struct iwl_trans_ops { 569 570 int (*start_hw)(struct iwl_trans *iwl_trans); 571 void (*op_mode_leave)(struct iwl_trans *iwl_trans); 572 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 573 bool run_in_rfkill); 574 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 575 void (*stop_device)(struct iwl_trans *trans); 576 577 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 578 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 579 bool test, bool reset); 580 581 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 582 583 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 584 struct iwl_device_tx_cmd *dev_cmd, int queue); 585 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 586 struct sk_buff_head *skbs, bool is_flush); 587 588 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 589 590 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 591 const struct iwl_trans_txq_scd_cfg *cfg, 592 unsigned int queue_wdg_timeout); 593 void (*txq_disable)(struct iwl_trans *trans, int queue, 594 bool configure_scd); 595 /* 22000 functions */ 596 int (*txq_alloc)(struct iwl_trans *trans, u32 flags, 597 u32 sta_mask, u8 tid, 598 int size, unsigned int queue_wdg_timeout); 599 void (*txq_free)(struct iwl_trans *trans, int queue); 600 int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 601 struct iwl_trans_rxq_dma_data *data); 602 603 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 604 bool shared); 605 606 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 607 int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 608 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 609 bool freeze); 610 611 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 612 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 613 u32 (*read32)(struct iwl_trans *trans, u32 ofs); 614 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 615 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 616 int (*read_mem)(struct iwl_trans *trans, u32 addr, 617 void *buf, int dwords); 618 int (*write_mem)(struct iwl_trans *trans, u32 addr, 619 const void *buf, int dwords); 620 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 621 void (*configure)(struct iwl_trans *trans, 622 const struct iwl_trans_config *trans_cfg); 623 void (*set_pmi)(struct iwl_trans *trans, bool state); 624 int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership); 625 bool (*grab_nic_access)(struct iwl_trans *trans); 626 void (*release_nic_access)(struct iwl_trans *trans); 627 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 628 u32 value); 629 630 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 631 u32 dump_mask, 632 const struct iwl_dump_sanitize_ops *sanitize_ops, 633 void *sanitize_ctx); 634 void (*debugfs_cleanup)(struct iwl_trans *trans); 635 void (*sync_nmi)(struct iwl_trans *trans); 636 int (*load_pnvm)(struct iwl_trans *trans, 637 const struct iwl_pnvm_image *pnvm_payloads, 638 const struct iwl_ucode_capabilities *capa); 639 void (*set_pnvm)(struct iwl_trans *trans, 640 const struct iwl_ucode_capabilities *capa); 641 int (*load_reduce_power)(struct iwl_trans *trans, 642 const struct iwl_pnvm_image *payloads, 643 const struct iwl_ucode_capabilities *capa); 644 void (*set_reduce_power)(struct iwl_trans *trans, 645 const struct iwl_ucode_capabilities *capa); 646 647 void (*interrupts)(struct iwl_trans *trans, bool enable); 648 int (*imr_dma_data)(struct iwl_trans *trans, 649 u32 dst_addr, u64 src_addr, 650 u32 byte_cnt); 651 652 }; 653 654 /** 655 * enum iwl_trans_state - state of the transport layer 656 * 657 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 658 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 659 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 660 */ 661 enum iwl_trans_state { 662 IWL_TRANS_NO_FW, 663 IWL_TRANS_FW_STARTED, 664 IWL_TRANS_FW_ALIVE, 665 }; 666 667 /** 668 * DOC: Platform power management 669 * 670 * In system-wide power management the entire platform goes into a low 671 * power state (e.g. idle or suspend to RAM) at the same time and the 672 * device is configured as a wakeup source for the entire platform. 673 * This is usually triggered by userspace activity (e.g. the user 674 * presses the suspend button or a power management daemon decides to 675 * put the platform in low power mode). The device's behavior in this 676 * mode is dictated by the wake-on-WLAN configuration. 677 * 678 * The terms used for the device's behavior are as follows: 679 * 680 * - D0: the device is fully powered and the host is awake; 681 * - D3: the device is in low power mode and only reacts to 682 * specific events (e.g. magic-packet received or scan 683 * results found); 684 * 685 * These terms reflect the power modes in the firmware and are not to 686 * be confused with the physical device power state. 687 */ 688 689 /** 690 * enum iwl_plat_pm_mode - platform power management mode 691 * 692 * This enumeration describes the device's platform power management 693 * behavior when in system-wide suspend (i.e WoWLAN). 694 * 695 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 696 * device. In system-wide suspend mode, it means that the all 697 * connections will be closed automatically by mac80211 before 698 * the platform is suspended. 699 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 700 */ 701 enum iwl_plat_pm_mode { 702 IWL_PLAT_PM_MODE_DISABLED, 703 IWL_PLAT_PM_MODE_D3, 704 }; 705 706 /** 707 * enum iwl_ini_cfg_state 708 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 709 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 710 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 711 * are corrupted. The rest of the debug TLVs will still be used 712 */ 713 enum iwl_ini_cfg_state { 714 IWL_INI_CFG_STATE_NOT_LOADED, 715 IWL_INI_CFG_STATE_LOADED, 716 IWL_INI_CFG_STATE_CORRUPTED, 717 }; 718 719 /* Max time to wait for nmi interrupt */ 720 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 721 722 /** 723 * struct iwl_dram_data 724 * @physical: page phy pointer 725 * @block: pointer to the allocated block/page 726 * @size: size of the block/page 727 */ 728 struct iwl_dram_data { 729 dma_addr_t physical; 730 void *block; 731 int size; 732 }; 733 734 /** 735 * struct iwl_dram_regions - DRAM regions container structure 736 * @drams: array of several DRAM areas that contains the pnvm and power 737 * reduction table payloads. 738 * @n_regions: number of DRAM regions that were allocated 739 * @prph_scratch_mem_desc: points to a structure allocated in dram, 740 * designed to show FW where all the payloads are. 741 */ 742 struct iwl_dram_regions { 743 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 744 struct iwl_dram_data prph_scratch_mem_desc; 745 u8 n_regions; 746 }; 747 748 /** 749 * struct iwl_fw_mon - fw monitor per allocation id 750 * @num_frags: number of fragments 751 * @frags: an array of DRAM buffer fragments 752 */ 753 struct iwl_fw_mon { 754 u32 num_frags; 755 struct iwl_dram_data *frags; 756 }; 757 758 /** 759 * struct iwl_self_init_dram - dram data used by self init process 760 * @fw: lmac and umac dram data 761 * @fw_cnt: total number of items in array 762 * @paging: paging dram data 763 * @paging_cnt: total number of items in array 764 */ 765 struct iwl_self_init_dram { 766 struct iwl_dram_data *fw; 767 int fw_cnt; 768 struct iwl_dram_data *paging; 769 int paging_cnt; 770 }; 771 772 /** 773 * struct iwl_imr_data - imr dram data used during debug process 774 * @imr_enable: imr enable status received from fw 775 * @imr_size: imr dram size received from fw 776 * @sram_addr: sram address from debug tlv 777 * @sram_size: sram size from debug tlv 778 * @imr2sram_remainbyte`: size remained after each dma transfer 779 * @imr_curr_addr: current dst address used during dma transfer 780 * @imr_base_addr: imr address received from fw 781 */ 782 struct iwl_imr_data { 783 u32 imr_enable; 784 u32 imr_size; 785 u32 sram_addr; 786 u32 sram_size; 787 u32 imr2sram_remainbyte; 788 u64 imr_curr_addr; 789 __le64 imr_base_addr; 790 }; 791 792 #define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32 793 794 /** 795 * struct iwl_pc_data - program counter details 796 * @pc_name: cpu name 797 * @pc_address: cpu program counter 798 */ 799 struct iwl_pc_data { 800 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES]; 801 u32 pc_address; 802 }; 803 804 /** 805 * struct iwl_trans_debug - transport debug related data 806 * 807 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 808 * @rec_on: true iff there is a fw debug recording currently active 809 * @dest_tlv: points to the destination TLV for debug 810 * @conf_tlv: array of pointers to configuration TLVs for debug 811 * @trigger_tlv: array of pointers to triggers TLVs for debug 812 * @lmac_error_event_table: addrs of lmacs error tables 813 * @umac_error_event_table: addr of umac error table 814 * @tcm_error_event_table: address(es) of TCM error table(s) 815 * @rcm_error_event_table: address(es) of RCM error table(s) 816 * @error_event_table_tlv_status: bitmap that indicates what error table 817 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 818 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 819 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 820 * @fw_mon_cfg: debug buffer allocation configuration 821 * @fw_mon_ini: DRAM buffer fragments per allocation id 822 * @fw_mon: DRAM buffer for firmware monitor 823 * @hw_error: equals true if hw error interrupt was received from the FW 824 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 825 * @active_regions: active regions 826 * @debug_info_tlv_list: list of debug info TLVs 827 * @time_point: array of debug time points 828 * @periodic_trig_list: periodic triggers list 829 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON 830 * @ucode_preset: preset based on ucode 831 * @dump_file_name_ext: dump file name extension 832 * @dump_file_name_ext_valid: dump file name extension if valid or not 833 * @num_pc: number of program counter for cpu 834 * @pc_data: details of the program counter 835 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded 836 */ 837 struct iwl_trans_debug { 838 u8 n_dest_reg; 839 bool rec_on; 840 841 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 842 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 843 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 844 845 u32 lmac_error_event_table[2]; 846 u32 umac_error_event_table; 847 u32 tcm_error_event_table[2]; 848 u32 rcm_error_event_table[2]; 849 unsigned int error_event_table_tlv_status; 850 851 enum iwl_ini_cfg_state internal_ini_cfg; 852 enum iwl_ini_cfg_state external_ini_cfg; 853 854 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 855 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 856 857 struct iwl_dram_data fw_mon; 858 859 bool hw_error; 860 enum iwl_fw_ini_buffer_location ini_dest; 861 862 u64 unsupported_region_msk; 863 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 864 struct list_head debug_info_tlv_list; 865 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM]; 866 struct list_head periodic_trig_list; 867 868 u32 domains_bitmap; 869 u32 ucode_preset; 870 bool restart_required; 871 u32 last_tp_resetfw; 872 struct iwl_imr_data imr_data; 873 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME]; 874 bool dump_file_name_ext_valid; 875 u32 num_pc; 876 struct iwl_pc_data *pc_data; 877 bool yoyo_bin_loaded; 878 }; 879 880 struct iwl_dma_ptr { 881 dma_addr_t dma; 882 void *addr; 883 size_t size; 884 }; 885 886 struct iwl_cmd_meta { 887 /* only for SYNC commands, iff the reply skb is wanted */ 888 struct iwl_host_cmd *source; 889 u32 flags; 890 u32 tbs; 891 }; 892 893 /* 894 * The FH will write back to the first TB only, so we need to copy some data 895 * into the buffer regardless of whether it should be mapped or not. 896 * This indicates how big the first TB must be to include the scratch buffer 897 * and the assigned PN. 898 * Since PN location is 8 bytes at offset 12, it's 20 now. 899 * If we make it bigger then allocations will be bigger and copy slower, so 900 * that's probably not useful. 901 */ 902 #define IWL_FIRST_TB_SIZE 20 903 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 904 905 struct iwl_pcie_txq_entry { 906 void *cmd; 907 struct sk_buff *skb; 908 /* buffer to free after command completes */ 909 const void *free_buf; 910 struct iwl_cmd_meta meta; 911 }; 912 913 struct iwl_pcie_first_tb_buf { 914 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 915 }; 916 917 /** 918 * struct iwl_txq - Tx Queue for DMA 919 * @tfds: transmit frame descriptors (DMA memory) 920 * @first_tb_bufs: start of command headers, including scratch buffers, for 921 * the writeback -- this is DMA memory and an array holding one buffer 922 * for each command on the queue 923 * @first_tb_dma: DMA address for the first_tb_bufs start 924 * @entries: transmit entries (driver state) 925 * @lock: queue lock 926 * @stuck_timer: timer that fires if queue gets stuck 927 * @trans: pointer back to transport (for timer) 928 * @need_update: indicates need to update read/write index 929 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 930 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 931 * @frozen: tx stuck queue timer is frozen 932 * @frozen_expiry_remainder: remember how long until the timer fires 933 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 934 * @write_ptr: 1-st empty entry (index) host_w 935 * @read_ptr: last used entry (index) host_r 936 * @dma_addr: physical addr for BD's 937 * @n_window: safe queue window 938 * @id: queue id 939 * @low_mark: low watermark, resume queue if free space more than this 940 * @high_mark: high watermark, stop queue if free space less than this 941 * 942 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 943 * descriptors) and required locking structures. 944 * 945 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 946 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 947 * there might be HW changes in the future). For the normal TX 948 * queues, n_window, which is the size of the software queue data 949 * is also 256; however, for the command queue, n_window is only 950 * 32 since we don't need so many commands pending. Since the HW 951 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 952 * This means that we end up with the following: 953 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 954 * SW entries: | 0 | ... | 31 | 955 * where N is a number between 0 and 7. This means that the SW 956 * data is a window overlayed over the HW queue. 957 */ 958 struct iwl_txq { 959 void *tfds; 960 struct iwl_pcie_first_tb_buf *first_tb_bufs; 961 dma_addr_t first_tb_dma; 962 struct iwl_pcie_txq_entry *entries; 963 /* lock for syncing changes on the queue */ 964 spinlock_t lock; 965 unsigned long frozen_expiry_remainder; 966 struct timer_list stuck_timer; 967 struct iwl_trans *trans; 968 bool need_update; 969 bool frozen; 970 bool ampdu; 971 int block; 972 unsigned long wd_timeout; 973 struct sk_buff_head overflow_q; 974 struct iwl_dma_ptr bc_tbl; 975 976 int write_ptr; 977 int read_ptr; 978 dma_addr_t dma_addr; 979 int n_window; 980 u32 id; 981 int low_mark; 982 int high_mark; 983 984 bool overflow_tx; 985 }; 986 987 /** 988 * struct iwl_trans_txqs - transport tx queues data 989 * 990 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 991 * @page_offs: offset from skb->cb to mac header page pointer 992 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 993 * @queue_used - bit mask of used queues 994 * @queue_stopped - bit mask of stopped queues 995 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 996 * @queue_alloc_cmd_ver: queue allocation command version 997 */ 998 struct iwl_trans_txqs { 999 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 1000 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 1001 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 1002 struct dma_pool *bc_pool; 1003 size_t bc_tbl_size; 1004 bool bc_table_dword; 1005 u8 page_offs; 1006 u8 dev_cmd_offs; 1007 struct iwl_tso_hdr_page __percpu *tso_hdr_page; 1008 1009 struct { 1010 u8 fifo; 1011 u8 q_id; 1012 unsigned int wdg_timeout; 1013 } cmd; 1014 1015 struct { 1016 u8 max_tbs; 1017 u16 size; 1018 u8 addr_size; 1019 } tfd; 1020 1021 struct iwl_dma_ptr scd_bc_tbls; 1022 1023 u8 queue_alloc_cmd_ver; 1024 }; 1025 1026 /** 1027 * struct iwl_trans - transport common data 1028 * 1029 * @csme_own - true if we couldn't get ownership on the device 1030 * @ops - pointer to iwl_trans_ops 1031 * @op_mode - pointer to the op_mode 1032 * @trans_cfg: the trans-specific configuration part 1033 * @cfg - pointer to the configuration 1034 * @drv - pointer to iwl_drv 1035 * @status: a bit-mask of transport status flags 1036 * @dev - pointer to struct device * that represents the device 1037 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 1038 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 1039 * @hw_rf_id a u32 with the device RF ID 1040 * @hw_crf_id a u32 with the device CRF ID 1041 * @hw_wfpm_id a u32 with the device wfpm ID 1042 * @hw_id: a u32 with the ID of the device / sub-device. 1043 * Set during transport allocation. 1044 * @hw_id_str: a string with info about HW ID. Set during transport allocation. 1045 * @hw_rev_step: The mac step of the HW 1046 * @pm_support: set to true in start_hw if link pm is supported 1047 * @ltr_enabled: set to true if the LTR is enabled 1048 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed 1049 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed 1050 * @wide_cmd_header: true when ucode supports wide command header format 1051 * @wait_command_queue: wait queue for sync commands 1052 * @num_rx_queues: number of RX queues allocated by the transport; 1053 * the transport must set this before calling iwl_drv_start() 1054 * @iml_len: the length of the image loader 1055 * @iml: a pointer to the image loader itself 1056 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 1057 * The user should use iwl_trans_{alloc,free}_tx_cmd. 1058 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 1059 * starting the firmware, used for tracing 1060 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 1061 * start of the 802.11 header in the @rx_mpdu_cmd 1062 * @system_pm_mode: the system-wide power management mode in use. 1063 * This mode is set dynamically, depending on the WoWLAN values 1064 * configured from the userspace at runtime. 1065 * @txqs: transport tx queues data. 1066 * @mbx_addr_0_step: step address data 0 1067 * @mbx_addr_1_step: step address data 1 1068 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*), 1069 * only valid for discrete (not integrated) NICs 1070 * @invalid_tx_cmd: invalid TX command buffer 1071 */ 1072 struct iwl_trans { 1073 bool csme_own; 1074 const struct iwl_trans_ops *ops; 1075 struct iwl_op_mode *op_mode; 1076 const struct iwl_cfg_trans_params *trans_cfg; 1077 const struct iwl_cfg *cfg; 1078 struct iwl_drv *drv; 1079 enum iwl_trans_state state; 1080 unsigned long status; 1081 1082 struct device *dev; 1083 u32 max_skb_frags; 1084 u32 hw_rev; 1085 u32 hw_rev_step; 1086 u32 hw_rf_id; 1087 u32 hw_crf_id; 1088 u32 hw_cnv_id; 1089 u32 hw_wfpm_id; 1090 u32 hw_id; 1091 char hw_id_str[52]; 1092 u32 sku_id[3]; 1093 1094 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 1095 1096 bool pm_support; 1097 bool ltr_enabled; 1098 u8 pnvm_loaded:1; 1099 u8 fail_to_parse_pnvm_image:1; 1100 u8 reduce_power_loaded:1; 1101 u8 failed_to_load_reduce_power_image:1; 1102 1103 const struct iwl_hcmd_arr *command_groups; 1104 int command_groups_size; 1105 bool wide_cmd_header; 1106 1107 wait_queue_head_t wait_command_queue; 1108 u8 num_rx_queues; 1109 1110 size_t iml_len; 1111 u8 *iml; 1112 1113 /* The following fields are internal only */ 1114 struct kmem_cache *dev_cmd_pool; 1115 char dev_cmd_pool_name[50]; 1116 1117 struct dentry *dbgfs_dir; 1118 1119 #ifdef CONFIG_LOCKDEP 1120 struct lockdep_map sync_cmd_lockdep_map; 1121 #endif 1122 1123 struct iwl_trans_debug dbg; 1124 struct iwl_self_init_dram init_dram; 1125 1126 enum iwl_plat_pm_mode system_pm_mode; 1127 1128 const char *name; 1129 struct iwl_trans_txqs txqs; 1130 u32 mbx_addr_0_step; 1131 u32 mbx_addr_1_step; 1132 1133 u8 pcie_link_speed; 1134 1135 struct iwl_dma_ptr invalid_tx_cmd; 1136 1137 /* pointer to trans specific struct */ 1138 /*Ensure that this pointer will always be aligned to sizeof pointer */ 1139 char trans_specific[] __aligned(sizeof(void *)); 1140 }; 1141 1142 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 1143 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 1144 1145 static inline void iwl_trans_configure(struct iwl_trans *trans, 1146 const struct iwl_trans_config *trans_cfg) 1147 { 1148 trans->op_mode = trans_cfg->op_mode; 1149 1150 trans->ops->configure(trans, trans_cfg); 1151 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1152 } 1153 1154 static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1155 { 1156 might_sleep(); 1157 1158 return trans->ops->start_hw(trans); 1159 } 1160 1161 static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1162 { 1163 might_sleep(); 1164 1165 if (trans->ops->op_mode_leave) 1166 trans->ops->op_mode_leave(trans); 1167 1168 trans->op_mode = NULL; 1169 1170 trans->state = IWL_TRANS_NO_FW; 1171 } 1172 1173 static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1174 { 1175 might_sleep(); 1176 1177 trans->state = IWL_TRANS_FW_ALIVE; 1178 1179 trans->ops->fw_alive(trans, scd_addr); 1180 } 1181 1182 static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1183 const struct fw_img *fw, 1184 bool run_in_rfkill) 1185 { 1186 int ret; 1187 1188 might_sleep(); 1189 1190 WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1191 1192 clear_bit(STATUS_FW_ERROR, &trans->status); 1193 ret = trans->ops->start_fw(trans, fw, run_in_rfkill); 1194 if (ret == 0) 1195 trans->state = IWL_TRANS_FW_STARTED; 1196 1197 return ret; 1198 } 1199 1200 static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1201 { 1202 might_sleep(); 1203 1204 trans->ops->stop_device(trans); 1205 1206 trans->state = IWL_TRANS_NO_FW; 1207 } 1208 1209 static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 1210 bool reset) 1211 { 1212 might_sleep(); 1213 if (!trans->ops->d3_suspend) 1214 return -EOPNOTSUPP; 1215 1216 return trans->ops->d3_suspend(trans, test, reset); 1217 } 1218 1219 static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1220 enum iwl_d3_status *status, 1221 bool test, bool reset) 1222 { 1223 might_sleep(); 1224 if (!trans->ops->d3_resume) 1225 return -EOPNOTSUPP; 1226 1227 return trans->ops->d3_resume(trans, status, test, reset); 1228 } 1229 1230 static inline struct iwl_trans_dump_data * 1231 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask, 1232 const struct iwl_dump_sanitize_ops *sanitize_ops, 1233 void *sanitize_ctx) 1234 { 1235 if (!trans->ops->dump_data) 1236 return NULL; 1237 return trans->ops->dump_data(trans, dump_mask, 1238 sanitize_ops, sanitize_ctx); 1239 } 1240 1241 static inline struct iwl_device_tx_cmd * 1242 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1243 { 1244 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1245 } 1246 1247 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 1248 1249 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1250 struct iwl_device_tx_cmd *dev_cmd) 1251 { 1252 kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1253 } 1254 1255 static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1256 struct iwl_device_tx_cmd *dev_cmd, int queue) 1257 { 1258 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1259 return -EIO; 1260 1261 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1262 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1263 return -EIO; 1264 } 1265 1266 return trans->ops->tx(trans, skb, dev_cmd, queue); 1267 } 1268 1269 static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1270 int ssn, struct sk_buff_head *skbs, 1271 bool is_flush) 1272 { 1273 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1274 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1275 return; 1276 } 1277 1278 trans->ops->reclaim(trans, queue, ssn, skbs, is_flush); 1279 } 1280 1281 static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1282 int ptr) 1283 { 1284 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1285 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1286 return; 1287 } 1288 1289 trans->ops->set_q_ptrs(trans, queue, ptr); 1290 } 1291 1292 static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1293 bool configure_scd) 1294 { 1295 trans->ops->txq_disable(trans, queue, configure_scd); 1296 } 1297 1298 static inline bool 1299 iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1300 const struct iwl_trans_txq_scd_cfg *cfg, 1301 unsigned int queue_wdg_timeout) 1302 { 1303 might_sleep(); 1304 1305 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1306 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1307 return false; 1308 } 1309 1310 return trans->ops->txq_enable(trans, queue, ssn, 1311 cfg, queue_wdg_timeout); 1312 } 1313 1314 static inline int 1315 iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 1316 struct iwl_trans_rxq_dma_data *data) 1317 { 1318 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 1319 return -EOPNOTSUPP; 1320 1321 return trans->ops->rxq_dma_data(trans, queue, data); 1322 } 1323 1324 static inline void 1325 iwl_trans_txq_free(struct iwl_trans *trans, int queue) 1326 { 1327 if (WARN_ON_ONCE(!trans->ops->txq_free)) 1328 return; 1329 1330 trans->ops->txq_free(trans, queue); 1331 } 1332 1333 static inline int 1334 iwl_trans_txq_alloc(struct iwl_trans *trans, 1335 u32 flags, u32 sta_mask, u8 tid, 1336 int size, unsigned int wdg_timeout) 1337 { 1338 might_sleep(); 1339 1340 if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 1341 return -EOPNOTSUPP; 1342 1343 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1344 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1345 return -EIO; 1346 } 1347 1348 return trans->ops->txq_alloc(trans, flags, sta_mask, tid, 1349 size, wdg_timeout); 1350 } 1351 1352 static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 1353 int queue, bool shared_mode) 1354 { 1355 if (trans->ops->txq_set_shared_mode) 1356 trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 1357 } 1358 1359 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1360 int fifo, int sta_id, int tid, 1361 int frame_limit, u16 ssn, 1362 unsigned int queue_wdg_timeout) 1363 { 1364 struct iwl_trans_txq_scd_cfg cfg = { 1365 .fifo = fifo, 1366 .sta_id = sta_id, 1367 .tid = tid, 1368 .frame_limit = frame_limit, 1369 .aggregate = sta_id >= 0, 1370 }; 1371 1372 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1373 } 1374 1375 static inline 1376 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1377 unsigned int queue_wdg_timeout) 1378 { 1379 struct iwl_trans_txq_scd_cfg cfg = { 1380 .fifo = fifo, 1381 .sta_id = -1, 1382 .tid = IWL_MAX_TID_COUNT, 1383 .frame_limit = IWL_FRAME_LIMIT, 1384 .aggregate = false, 1385 }; 1386 1387 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1388 } 1389 1390 static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1391 unsigned long txqs, 1392 bool freeze) 1393 { 1394 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1395 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1396 return; 1397 } 1398 1399 if (trans->ops->freeze_txq_timer) 1400 trans->ops->freeze_txq_timer(trans, txqs, freeze); 1401 } 1402 1403 static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1404 u32 txqs) 1405 { 1406 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1407 return -EOPNOTSUPP; 1408 1409 /* No need to wait if the firmware is not alive */ 1410 if (trans->state != IWL_TRANS_FW_ALIVE) { 1411 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1412 return -EIO; 1413 } 1414 1415 return trans->ops->wait_tx_queues_empty(trans, txqs); 1416 } 1417 1418 static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1419 { 1420 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1421 return -EOPNOTSUPP; 1422 1423 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1424 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1425 return -EIO; 1426 } 1427 1428 return trans->ops->wait_txq_empty(trans, queue); 1429 } 1430 1431 static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1432 { 1433 trans->ops->write8(trans, ofs, val); 1434 } 1435 1436 static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1437 { 1438 trans->ops->write32(trans, ofs, val); 1439 } 1440 1441 static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1442 { 1443 return trans->ops->read32(trans, ofs); 1444 } 1445 1446 static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1447 { 1448 return trans->ops->read_prph(trans, ofs); 1449 } 1450 1451 static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1452 u32 val) 1453 { 1454 return trans->ops->write_prph(trans, ofs, val); 1455 } 1456 1457 static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1458 void *buf, int dwords) 1459 { 1460 return trans->ops->read_mem(trans, addr, buf, dwords); 1461 } 1462 1463 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1464 do { \ 1465 if (__builtin_constant_p(bufsize)) \ 1466 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1467 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1468 } while (0) 1469 1470 static inline int iwl_trans_write_imr_mem(struct iwl_trans *trans, 1471 u32 dst_addr, u64 src_addr, 1472 u32 byte_cnt) 1473 { 1474 if (trans->ops->imr_dma_data) 1475 return trans->ops->imr_dma_data(trans, dst_addr, src_addr, byte_cnt); 1476 return 0; 1477 } 1478 1479 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1480 { 1481 u32 value; 1482 1483 if (iwl_trans_read_mem(trans, addr, &value, 1)) 1484 return 0xa5a5a5a5; 1485 1486 return value; 1487 } 1488 1489 static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1490 const void *buf, int dwords) 1491 { 1492 return trans->ops->write_mem(trans, addr, buf, dwords); 1493 } 1494 1495 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1496 u32 val) 1497 { 1498 return iwl_trans_write_mem(trans, addr, &val, 1); 1499 } 1500 1501 static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1502 { 1503 if (trans->ops->set_pmi) 1504 trans->ops->set_pmi(trans, state); 1505 } 1506 1507 static inline int iwl_trans_sw_reset(struct iwl_trans *trans, 1508 bool retake_ownership) 1509 { 1510 if (trans->ops->sw_reset) 1511 return trans->ops->sw_reset(trans, retake_ownership); 1512 return 0; 1513 } 1514 1515 static inline void 1516 iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1517 { 1518 trans->ops->set_bits_mask(trans, reg, mask, value); 1519 } 1520 1521 #define iwl_trans_grab_nic_access(trans) \ 1522 __cond_lock(nic_access, \ 1523 likely((trans)->ops->grab_nic_access(trans))) 1524 1525 static inline void __releases(nic_access) 1526 iwl_trans_release_nic_access(struct iwl_trans *trans) 1527 { 1528 trans->ops->release_nic_access(trans); 1529 __release(nic_access); 1530 } 1531 1532 static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync) 1533 { 1534 if (WARN_ON_ONCE(!trans->op_mode)) 1535 return; 1536 1537 /* prevent double restarts due to the same erroneous FW */ 1538 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1539 iwl_op_mode_nic_error(trans->op_mode, sync); 1540 trans->state = IWL_TRANS_NO_FW; 1541 } 1542 } 1543 1544 static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1545 { 1546 return trans->state == IWL_TRANS_FW_ALIVE; 1547 } 1548 1549 static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1550 { 1551 if (trans->ops->sync_nmi) 1552 trans->ops->sync_nmi(trans); 1553 } 1554 1555 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 1556 u32 sw_err_bit); 1557 1558 static inline int iwl_trans_load_pnvm(struct iwl_trans *trans, 1559 const struct iwl_pnvm_image *pnvm_data, 1560 const struct iwl_ucode_capabilities *capa) 1561 { 1562 return trans->ops->load_pnvm(trans, pnvm_data, capa); 1563 } 1564 1565 static inline void iwl_trans_set_pnvm(struct iwl_trans *trans, 1566 const struct iwl_ucode_capabilities *capa) 1567 { 1568 if (trans->ops->set_pnvm) 1569 trans->ops->set_pnvm(trans, capa); 1570 } 1571 1572 static inline int iwl_trans_load_reduce_power 1573 (struct iwl_trans *trans, 1574 const struct iwl_pnvm_image *payloads, 1575 const struct iwl_ucode_capabilities *capa) 1576 { 1577 return trans->ops->load_reduce_power(trans, payloads, capa); 1578 } 1579 1580 static inline void 1581 iwl_trans_set_reduce_power(struct iwl_trans *trans, 1582 const struct iwl_ucode_capabilities *capa) 1583 { 1584 if (trans->ops->set_reduce_power) 1585 trans->ops->set_reduce_power(trans, capa); 1586 } 1587 1588 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1589 { 1590 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1591 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1592 } 1593 1594 static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable) 1595 { 1596 if (trans->ops->interrupts) 1597 trans->ops->interrupts(trans, enable); 1598 } 1599 1600 /***************************************************** 1601 * transport helper functions 1602 *****************************************************/ 1603 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1604 struct device *dev, 1605 const struct iwl_trans_ops *ops, 1606 const struct iwl_cfg_trans_params *cfg_trans); 1607 int iwl_trans_init(struct iwl_trans *trans); 1608 void iwl_trans_free(struct iwl_trans *trans); 1609 1610 static inline bool iwl_trans_is_hw_error_value(u32 val) 1611 { 1612 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50); 1613 } 1614 1615 /***************************************************** 1616 * driver (transport) register/unregister functions 1617 ******************************************************/ 1618 int __must_check iwl_pci_register_driver(void); 1619 void iwl_pci_unregister_driver(void); 1620 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan); 1621 1622 #endif /* __iwl_trans_h__ */ 1623