1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_trans_h__ 8 #define __iwl_trans_h__ 9 10 #include <linux/ieee80211.h> 11 #include <linux/mm.h> /* for page_address */ 12 #include <linux/lockdep.h> 13 #include <linux/kernel.h> 14 15 #include "iwl-debug.h" 16 #include "iwl-config.h" 17 #include "fw/img.h" 18 #include "iwl-op-mode.h" 19 #include <linux/firmware.h> 20 #include "fw/api/cmdhdr.h" 21 #include "fw/api/txq.h" 22 #include "fw/api/dbg-tlv.h" 23 #include "iwl-dbg-tlv.h" 24 25 /** 26 * DOC: Transport layer - what is it ? 27 * 28 * The transport layer is the layer that deals with the HW directly. It provides 29 * the PCIe access to the underlying hardwarwe. The transport layer doesn't 30 * provide any policy, algorithm or anything of this kind, but only mechanisms 31 * to make the HW do something. It is not completely stateless but close to it. 32 */ 33 34 /** 35 * DOC: Life cycle of the transport layer 36 * 37 * The transport layer has a very precise life cycle. 38 * 39 * 1) A helper function is called during the module initialization and 40 * registers the bus driver's ops with the transport's alloc function. 41 * 2) Bus's probe calls to the transport layer's allocation functions. 42 * Of course this function is bus specific. 43 * 3) This allocation functions will spawn the upper layer which will 44 * register mac80211. 45 * 46 * 4) At some point (i.e. mac80211's start call), the op_mode will call 47 * the following sequence: 48 * start_hw 49 * start_fw 50 * 51 * 5) Then when finished (or reset): 52 * stop_device 53 * 54 * 6) Eventually, the free function will be called. 55 */ 56 57 /* default preset 0 (start from bit 16)*/ 58 #define IWL_FW_DBG_DOMAIN_POS 16 59 #define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS) 60 61 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 62 63 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 64 #define FH_RSCSR_FRAME_INVALID 0x55550000 65 #define FH_RSCSR_FRAME_ALIGN 0x40 66 #define FH_RSCSR_RPA_EN BIT(25) 67 #define FH_RSCSR_RADA_EN BIT(26) 68 #define FH_RSCSR_RXQ_POS 16 69 #define FH_RSCSR_RXQ_MASK 0x3F0000 70 71 struct iwl_rx_packet { 72 /* 73 * The first 4 bytes of the RX frame header contain both the RX frame 74 * size and some flags. 75 * Bit fields: 76 * 31: flag flush RB request 77 * 30: flag ignore TC (terminal counter) request 78 * 29: flag fast IRQ request 79 * 28-27: Reserved 80 * 26: RADA enabled 81 * 25: Offload enabled 82 * 24: RPF enabled 83 * 23: RSS enabled 84 * 22: Checksum enabled 85 * 21-16: RX queue 86 * 15-14: Reserved 87 * 13-00: RX frame size 88 */ 89 __le32 len_n_flags; 90 struct iwl_cmd_header hdr; 91 u8 data[]; 92 } __packed; 93 94 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 95 { 96 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 97 } 98 99 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 100 { 101 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 102 } 103 104 /** 105 * enum CMD_MODE - how to send the host commands ? 106 * 107 * @CMD_ASYNC: Return right away and don't wait for the response 108 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 109 * the response. The caller needs to call iwl_free_resp when done. 110 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill. 111 * @CMD_BLOCK_TXQS: Block TXQs while the comment is executing. 112 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to 113 * SUSPEND and RESUME commands. We are in D3 mode when we set 114 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3. 115 */ 116 enum CMD_MODE { 117 CMD_ASYNC = BIT(0), 118 CMD_WANT_SKB = BIT(1), 119 CMD_SEND_IN_RFKILL = BIT(2), 120 CMD_BLOCK_TXQS = BIT(3), 121 CMD_SEND_IN_D3 = BIT(4), 122 }; 123 #define CMD_MODE_BITS 5 124 125 #define DEF_CMD_PAYLOAD_SIZE 320 126 127 /** 128 * struct iwl_device_cmd 129 * 130 * For allocation of the command and tx queues, this establishes the overall 131 * size of the largest command we send to uCode, except for commands that 132 * aren't fully copied and use other TFD space. 133 * 134 * @hdr: command header 135 * @payload: payload for the command 136 * @hdr_wide: wide command header 137 * @payload_wide: payload for the wide command 138 */ 139 struct iwl_device_cmd { 140 union { 141 struct { 142 struct iwl_cmd_header hdr; /* uCode API */ 143 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 144 }; 145 struct { 146 struct iwl_cmd_header_wide hdr_wide; 147 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 148 sizeof(struct iwl_cmd_header_wide) + 149 sizeof(struct iwl_cmd_header)]; 150 }; 151 }; 152 } __packed; 153 154 /** 155 * struct iwl_device_tx_cmd - buffer for TX command 156 * @hdr: the header 157 * @payload: the payload placeholder 158 * 159 * The actual structure is sized dynamically according to need. 160 */ 161 struct iwl_device_tx_cmd { 162 struct iwl_cmd_header hdr; 163 u8 payload[]; 164 } __packed; 165 166 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 167 168 /* 169 * number of transfer buffers (fragments) per transmit frame descriptor; 170 * this is just the driver's idea, the hardware supports 20 171 */ 172 #define IWL_MAX_CMD_TBS_PER_TFD 2 173 174 /** 175 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 176 * 177 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 178 * ring. The transport layer doesn't map the command's buffer to DMA, but 179 * rather copies it to a previously allocated DMA buffer. This flag tells 180 * the transport layer not to copy the command, but to map the existing 181 * buffer (that is passed in) instead. This saves the memcpy and allows 182 * commands that are bigger than the fixed buffer to be submitted. 183 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 184 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 185 * chunk internally and free it again after the command completes. This 186 * can (currently) be used only once per command. 187 * Note that a TFD entry after a DUP one cannot be a normal copied one. 188 */ 189 enum iwl_hcmd_dataflag { 190 IWL_HCMD_DFL_NOCOPY = BIT(0), 191 IWL_HCMD_DFL_DUP = BIT(1), 192 }; 193 194 enum iwl_error_event_table_status { 195 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 196 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 197 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 198 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3), 199 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4), 200 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5), 201 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6), 202 }; 203 204 /** 205 * struct iwl_host_cmd - Host command to the uCode 206 * 207 * @data: array of chunks that composes the data of the host command 208 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 209 * @_rx_page_order: (internally used to free response packet) 210 * @_rx_page_addr: (internally used to free response packet) 211 * @flags: can be CMD_* 212 * @len: array of the lengths of the chunks in data 213 * @dataflags: IWL_HCMD_DFL_* 214 * @id: command id of the host command, for wide commands encoding the 215 * version and group as well 216 */ 217 struct iwl_host_cmd { 218 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 219 struct iwl_rx_packet *resp_pkt; 220 unsigned long _rx_page_addr; 221 u32 _rx_page_order; 222 223 u32 flags; 224 u32 id; 225 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 226 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 227 }; 228 229 static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 230 { 231 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 232 } 233 234 struct iwl_rx_cmd_buffer { 235 struct page *_page; 236 int _offset; 237 bool _page_stolen; 238 u32 _rx_page_order; 239 unsigned int truesize; 240 }; 241 242 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 243 { 244 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 245 } 246 247 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 248 { 249 return r->_offset; 250 } 251 252 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 253 { 254 r->_page_stolen = true; 255 get_page(r->_page); 256 return r->_page; 257 } 258 259 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 260 { 261 __free_pages(r->_page, r->_rx_page_order); 262 } 263 264 #define MAX_NO_RECLAIM_CMDS 6 265 266 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 267 268 /* 269 * Maximum number of HW queues the transport layer 270 * currently supports 271 */ 272 #define IWL_MAX_HW_QUEUES 32 273 #define IWL_MAX_TVQM_QUEUES 512 274 275 #define IWL_MAX_TID_COUNT 8 276 #define IWL_MGMT_TID 15 277 #define IWL_FRAME_LIMIT 64 278 #define IWL_MAX_RX_HW_QUEUES 16 279 #define IWL_9000_MAX_RX_HW_QUEUES 1 280 281 /** 282 * enum iwl_d3_status - WoWLAN image/device status 283 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 284 * @IWL_D3_STATUS_RESET: device was reset while suspended 285 */ 286 enum iwl_d3_status { 287 IWL_D3_STATUS_ALIVE, 288 IWL_D3_STATUS_RESET, 289 }; 290 291 /** 292 * enum iwl_trans_status: transport status flags 293 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 294 * @STATUS_DEVICE_ENABLED: APM is enabled 295 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 296 * @STATUS_INT_ENABLED: interrupts are enabled 297 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 298 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 299 * @STATUS_FW_ERROR: the fw is in error state 300 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 301 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once, 302 * e.g. for testing 303 */ 304 enum iwl_trans_status { 305 STATUS_SYNC_HCMD_ACTIVE, 306 STATUS_DEVICE_ENABLED, 307 STATUS_TPOWER_PMI, 308 STATUS_INT_ENABLED, 309 STATUS_RFKILL_HW, 310 STATUS_RFKILL_OPMODE, 311 STATUS_FW_ERROR, 312 STATUS_TRANS_DEAD, 313 STATUS_SUPPRESS_CMD_ERROR_ONCE, 314 }; 315 316 static inline int 317 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 318 { 319 switch (rb_size) { 320 case IWL_AMSDU_2K: 321 return get_order(2 * 1024); 322 case IWL_AMSDU_4K: 323 return get_order(4 * 1024); 324 case IWL_AMSDU_8K: 325 return get_order(8 * 1024); 326 case IWL_AMSDU_12K: 327 return get_order(16 * 1024); 328 default: 329 WARN_ON(1); 330 return -1; 331 } 332 } 333 334 static inline int 335 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 336 { 337 switch (rb_size) { 338 case IWL_AMSDU_2K: 339 return 2 * 1024; 340 case IWL_AMSDU_4K: 341 return 4 * 1024; 342 case IWL_AMSDU_8K: 343 return 8 * 1024; 344 case IWL_AMSDU_12K: 345 return 16 * 1024; 346 default: 347 WARN_ON(1); 348 return 0; 349 } 350 } 351 352 struct iwl_hcmd_names { 353 u8 cmd_id; 354 const char *const cmd_name; 355 }; 356 357 #define HCMD_NAME(x) \ 358 { .cmd_id = x, .cmd_name = #x } 359 360 struct iwl_hcmd_arr { 361 const struct iwl_hcmd_names *arr; 362 int size; 363 }; 364 365 #define HCMD_ARR(x) \ 366 { .arr = x, .size = ARRAY_SIZE(x) } 367 368 /** 369 * struct iwl_dump_sanitize_ops - dump sanitization operations 370 * @frob_txf: Scrub the TX FIFO data 371 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header 372 * but that might be short or long (&struct iwl_cmd_header or 373 * &struct iwl_cmd_header_wide) 374 * @frob_mem: Scrub memory data 375 */ 376 struct iwl_dump_sanitize_ops { 377 void (*frob_txf)(void *ctx, void *buf, size_t buflen); 378 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen); 379 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen); 380 }; 381 382 /** 383 * struct iwl_trans_config - transport configuration 384 * 385 * @op_mode: pointer to the upper layer. 386 * @cmd_queue: the index of the command queue. 387 * Must be set before start_fw. 388 * @cmd_fifo: the fifo for host commands 389 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 390 * @no_reclaim_cmds: Some devices erroneously don't set the 391 * SEQ_RX_FRAME bit on some notifications, this is the 392 * list of such notifications to filter. Max length is 393 * %MAX_NO_RECLAIM_CMDS. 394 * @n_no_reclaim_cmds: # of commands in list 395 * @rx_buf_size: RX buffer size needed for A-MSDUs 396 * if unset 4k will be the RX buffer size 397 * @bc_table_dword: set to true if the BC table expects the byte count to be 398 * in DWORD (as opposed to bytes) 399 * @scd_set_active: should the transport configure the SCD for HCMD queue 400 * @command_groups: array of command groups, each member is an array of the 401 * commands in the group; for debugging only 402 * @command_groups_size: number of command groups, to avoid illegal access 403 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 404 * space for at least two pointers 405 * @fw_reset_handshake: firmware supports reset flow handshake 406 * @queue_alloc_cmd_ver: queue allocation command version, set to 0 407 * for using the older SCD_QUEUE_CFG, set to the version of 408 * SCD_QUEUE_CONFIG_CMD otherwise. 409 */ 410 struct iwl_trans_config { 411 struct iwl_op_mode *op_mode; 412 413 u8 cmd_queue; 414 u8 cmd_fifo; 415 unsigned int cmd_q_wdg_timeout; 416 const u8 *no_reclaim_cmds; 417 unsigned int n_no_reclaim_cmds; 418 419 enum iwl_amsdu_size rx_buf_size; 420 bool bc_table_dword; 421 bool scd_set_active; 422 const struct iwl_hcmd_arr *command_groups; 423 int command_groups_size; 424 425 u8 cb_data_offs; 426 bool fw_reset_handshake; 427 u8 queue_alloc_cmd_ver; 428 }; 429 430 struct iwl_trans_dump_data { 431 u32 len; 432 u8 data[]; 433 }; 434 435 struct iwl_trans; 436 437 struct iwl_trans_txq_scd_cfg { 438 u8 fifo; 439 u8 sta_id; 440 u8 tid; 441 bool aggregate; 442 int frame_limit; 443 }; 444 445 /** 446 * struct iwl_trans_rxq_dma_data - RX queue DMA data 447 * @fr_bd_cb: DMA address of free BD cyclic buffer 448 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 449 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 450 * @ur_bd_cb: DMA address of used BD cyclic buffer 451 */ 452 struct iwl_trans_rxq_dma_data { 453 u64 fr_bd_cb; 454 u32 fr_bd_wid; 455 u64 urbd_stts_wrptr; 456 u64 ur_bd_cb; 457 }; 458 459 /* maximal number of DRAM MAP entries supported by FW */ 460 #define IPC_DRAM_MAP_ENTRY_NUM_MAX 64 461 462 /** 463 * struct iwl_pnvm_image - contains info about the parsed pnvm image 464 * @chunks: array of pointers to pnvm payloads and their sizes 465 * @n_chunks: the number of the pnvm payloads. 466 * @version: the version of the loaded PNVM image 467 */ 468 struct iwl_pnvm_image { 469 struct { 470 const void *data; 471 u32 len; 472 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 473 u32 n_chunks; 474 u32 version; 475 }; 476 477 /** 478 * enum iwl_trans_state - state of the transport layer 479 * 480 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 481 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 482 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 483 */ 484 enum iwl_trans_state { 485 IWL_TRANS_NO_FW, 486 IWL_TRANS_FW_STARTED, 487 IWL_TRANS_FW_ALIVE, 488 }; 489 490 /** 491 * DOC: Platform power management 492 * 493 * In system-wide power management the entire platform goes into a low 494 * power state (e.g. idle or suspend to RAM) at the same time and the 495 * device is configured as a wakeup source for the entire platform. 496 * This is usually triggered by userspace activity (e.g. the user 497 * presses the suspend button or a power management daemon decides to 498 * put the platform in low power mode). The device's behavior in this 499 * mode is dictated by the wake-on-WLAN configuration. 500 * 501 * The terms used for the device's behavior are as follows: 502 * 503 * - D0: the device is fully powered and the host is awake; 504 * - D3: the device is in low power mode and only reacts to 505 * specific events (e.g. magic-packet received or scan 506 * results found); 507 * 508 * These terms reflect the power modes in the firmware and are not to 509 * be confused with the physical device power state. 510 */ 511 512 /** 513 * enum iwl_plat_pm_mode - platform power management mode 514 * 515 * This enumeration describes the device's platform power management 516 * behavior when in system-wide suspend (i.e WoWLAN). 517 * 518 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 519 * device. In system-wide suspend mode, it means that the all 520 * connections will be closed automatically by mac80211 before 521 * the platform is suspended. 522 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 523 */ 524 enum iwl_plat_pm_mode { 525 IWL_PLAT_PM_MODE_DISABLED, 526 IWL_PLAT_PM_MODE_D3, 527 }; 528 529 /** 530 * enum iwl_ini_cfg_state 531 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 532 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 533 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 534 * are corrupted. The rest of the debug TLVs will still be used 535 */ 536 enum iwl_ini_cfg_state { 537 IWL_INI_CFG_STATE_NOT_LOADED, 538 IWL_INI_CFG_STATE_LOADED, 539 IWL_INI_CFG_STATE_CORRUPTED, 540 }; 541 542 /* Max time to wait for nmi interrupt */ 543 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 544 545 /** 546 * struct iwl_dram_data 547 * @physical: page phy pointer 548 * @block: pointer to the allocated block/page 549 * @size: size of the block/page 550 */ 551 struct iwl_dram_data { 552 dma_addr_t physical; 553 void *block; 554 int size; 555 }; 556 557 /** 558 * struct iwl_dram_regions - DRAM regions container structure 559 * @drams: array of several DRAM areas that contains the pnvm and power 560 * reduction table payloads. 561 * @n_regions: number of DRAM regions that were allocated 562 * @prph_scratch_mem_desc: points to a structure allocated in dram, 563 * designed to show FW where all the payloads are. 564 */ 565 struct iwl_dram_regions { 566 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 567 struct iwl_dram_data prph_scratch_mem_desc; 568 u8 n_regions; 569 }; 570 571 /** 572 * struct iwl_fw_mon - fw monitor per allocation id 573 * @num_frags: number of fragments 574 * @frags: an array of DRAM buffer fragments 575 */ 576 struct iwl_fw_mon { 577 u32 num_frags; 578 struct iwl_dram_data *frags; 579 }; 580 581 /** 582 * struct iwl_self_init_dram - dram data used by self init process 583 * @fw: lmac and umac dram data 584 * @fw_cnt: total number of items in array 585 * @paging: paging dram data 586 * @paging_cnt: total number of items in array 587 */ 588 struct iwl_self_init_dram { 589 struct iwl_dram_data *fw; 590 int fw_cnt; 591 struct iwl_dram_data *paging; 592 int paging_cnt; 593 }; 594 595 /** 596 * struct iwl_imr_data - imr dram data used during debug process 597 * @imr_enable: imr enable status received from fw 598 * @imr_size: imr dram size received from fw 599 * @sram_addr: sram address from debug tlv 600 * @sram_size: sram size from debug tlv 601 * @imr2sram_remainbyte: size remained after each dma transfer 602 * @imr_curr_addr: current dst address used during dma transfer 603 * @imr_base_addr: imr address received from fw 604 */ 605 struct iwl_imr_data { 606 u32 imr_enable; 607 u32 imr_size; 608 u32 sram_addr; 609 u32 sram_size; 610 u32 imr2sram_remainbyte; 611 u64 imr_curr_addr; 612 __le64 imr_base_addr; 613 }; 614 615 #define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32 616 617 /** 618 * struct iwl_pc_data - program counter details 619 * @pc_name: cpu name 620 * @pc_address: cpu program counter 621 */ 622 struct iwl_pc_data { 623 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES]; 624 u32 pc_address; 625 }; 626 627 /** 628 * struct iwl_trans_debug - transport debug related data 629 * 630 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 631 * @rec_on: true iff there is a fw debug recording currently active 632 * @dest_tlv: points to the destination TLV for debug 633 * @conf_tlv: array of pointers to configuration TLVs for debug 634 * @trigger_tlv: array of pointers to triggers TLVs for debug 635 * @lmac_error_event_table: addrs of lmacs error tables 636 * @umac_error_event_table: addr of umac error table 637 * @tcm_error_event_table: address(es) of TCM error table(s) 638 * @rcm_error_event_table: address(es) of RCM error table(s) 639 * @error_event_table_tlv_status: bitmap that indicates what error table 640 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 641 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 642 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 643 * @fw_mon_cfg: debug buffer allocation configuration 644 * @fw_mon_ini: DRAM buffer fragments per allocation id 645 * @fw_mon: DRAM buffer for firmware monitor 646 * @hw_error: equals true if hw error interrupt was received from the FW 647 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 648 * @unsupported_region_msk: unsupported regions out of active_regions 649 * @active_regions: active regions 650 * @debug_info_tlv_list: list of debug info TLVs 651 * @time_point: array of debug time points 652 * @periodic_trig_list: periodic triggers list 653 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON 654 * @ucode_preset: preset based on ucode 655 * @restart_required: indicates debug restart is required 656 * @last_tp_resetfw: last handling of reset during debug timepoint 657 * @imr_data: IMR debug data allocation 658 * @dump_file_name_ext: dump file name extension 659 * @dump_file_name_ext_valid: dump file name extension if valid or not 660 * @num_pc: number of program counter for cpu 661 * @pc_data: details of the program counter 662 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded 663 */ 664 struct iwl_trans_debug { 665 u8 n_dest_reg; 666 bool rec_on; 667 668 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 669 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 670 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 671 672 u32 lmac_error_event_table[2]; 673 u32 umac_error_event_table; 674 u32 tcm_error_event_table[2]; 675 u32 rcm_error_event_table[2]; 676 unsigned int error_event_table_tlv_status; 677 678 enum iwl_ini_cfg_state internal_ini_cfg; 679 enum iwl_ini_cfg_state external_ini_cfg; 680 681 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 682 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 683 684 struct iwl_dram_data fw_mon; 685 686 bool hw_error; 687 enum iwl_fw_ini_buffer_location ini_dest; 688 689 u64 unsupported_region_msk; 690 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 691 struct list_head debug_info_tlv_list; 692 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM]; 693 struct list_head periodic_trig_list; 694 695 u32 domains_bitmap; 696 u32 ucode_preset; 697 bool restart_required; 698 u32 last_tp_resetfw; 699 struct iwl_imr_data imr_data; 700 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME]; 701 bool dump_file_name_ext_valid; 702 u32 num_pc; 703 struct iwl_pc_data *pc_data; 704 bool yoyo_bin_loaded; 705 }; 706 707 struct iwl_dma_ptr { 708 dma_addr_t dma; 709 void *addr; 710 size_t size; 711 }; 712 713 struct iwl_cmd_meta { 714 /* only for SYNC commands, iff the reply skb is wanted */ 715 struct iwl_host_cmd *source; 716 u32 flags: CMD_MODE_BITS; 717 /* sg_offset is valid if it is non-zero */ 718 u32 sg_offset: PAGE_SHIFT; 719 u32 tbs; 720 }; 721 722 /* 723 * The FH will write back to the first TB only, so we need to copy some data 724 * into the buffer regardless of whether it should be mapped or not. 725 * This indicates how big the first TB must be to include the scratch buffer 726 * and the assigned PN. 727 * Since PN location is 8 bytes at offset 12, it's 20 now. 728 * If we make it bigger then allocations will be bigger and copy slower, so 729 * that's probably not useful. 730 */ 731 #define IWL_FIRST_TB_SIZE 20 732 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 733 734 struct iwl_pcie_txq_entry { 735 void *cmd; 736 struct sk_buff *skb; 737 /* buffer to free after command completes */ 738 const void *free_buf; 739 struct iwl_cmd_meta meta; 740 }; 741 742 struct iwl_pcie_first_tb_buf { 743 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 744 }; 745 746 /** 747 * struct iwl_txq - Tx Queue for DMA 748 * @tfds: transmit frame descriptors (DMA memory) 749 * @first_tb_bufs: start of command headers, including scratch buffers, for 750 * the writeback -- this is DMA memory and an array holding one buffer 751 * for each command on the queue 752 * @first_tb_dma: DMA address for the first_tb_bufs start 753 * @entries: transmit entries (driver state) 754 * @lock: queue lock 755 * @reclaim_lock: reclaim lock 756 * @stuck_timer: timer that fires if queue gets stuck 757 * @trans: pointer back to transport (for timer) 758 * @need_update: indicates need to update read/write index 759 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 760 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 761 * @frozen: tx stuck queue timer is frozen 762 * @frozen_expiry_remainder: remember how long until the timer fires 763 * @block: queue is blocked 764 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 765 * @write_ptr: 1-st empty entry (index) host_w 766 * @read_ptr: last used entry (index) host_r 767 * @dma_addr: physical addr for BD's 768 * @n_window: safe queue window 769 * @id: queue id 770 * @low_mark: low watermark, resume queue if free space more than this 771 * @high_mark: high watermark, stop queue if free space less than this 772 * @overflow_q: overflow queue for handling frames that didn't fit on HW queue 773 * @overflow_tx: need to transmit from overflow 774 * 775 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 776 * descriptors) and required locking structures. 777 * 778 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 779 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 780 * there might be HW changes in the future). For the normal TX 781 * queues, n_window, which is the size of the software queue data 782 * is also 256; however, for the command queue, n_window is only 783 * 32 since we don't need so many commands pending. Since the HW 784 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 785 * This means that we end up with the following: 786 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 787 * SW entries: | 0 | ... | 31 | 788 * where N is a number between 0 and 7. This means that the SW 789 * data is a window overlayed over the HW queue. 790 */ 791 struct iwl_txq { 792 void *tfds; 793 struct iwl_pcie_first_tb_buf *first_tb_bufs; 794 dma_addr_t first_tb_dma; 795 struct iwl_pcie_txq_entry *entries; 796 /* lock for syncing changes on the queue */ 797 spinlock_t lock; 798 /* lock to prevent concurrent reclaim */ 799 spinlock_t reclaim_lock; 800 unsigned long frozen_expiry_remainder; 801 struct timer_list stuck_timer; 802 struct iwl_trans *trans; 803 bool need_update; 804 bool frozen; 805 bool ampdu; 806 int block; 807 unsigned long wd_timeout; 808 struct sk_buff_head overflow_q; 809 struct iwl_dma_ptr bc_tbl; 810 811 int write_ptr; 812 int read_ptr; 813 dma_addr_t dma_addr; 814 int n_window; 815 u32 id; 816 int low_mark; 817 int high_mark; 818 819 bool overflow_tx; 820 }; 821 822 /** 823 * struct iwl_trans - transport common data 824 * 825 * @csme_own: true if we couldn't get ownership on the device 826 * @op_mode: pointer to the op_mode 827 * @trans_cfg: the trans-specific configuration part 828 * @cfg: pointer to the configuration 829 * @drv: pointer to iwl_drv 830 * @state: current device state 831 * @status: a bit-mask of transport status flags 832 * @dev: pointer to struct device * that represents the device 833 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 834 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 835 * @hw_rf_id: a u32 with the device RF ID 836 * @hw_cnv_id: a u32 with the device CNV ID 837 * @hw_crf_id: a u32 with the device CRF ID 838 * @hw_wfpm_id: a u32 with the device wfpm ID 839 * @hw_id: a u32 with the ID of the device / sub-device. 840 * Set during transport allocation. 841 * @hw_id_str: a string with info about HW ID. Set during transport allocation. 842 * @sku_id: the SKU identifier (for PNVM matching) 843 * @pnvm_loaded: indicates PNVM was loaded 844 * @hw_rev: the revision data of the HW 845 * @hw_rev_step: The mac step of the HW 846 * @pm_support: set to true in start_hw if link pm is supported 847 * @ltr_enabled: set to true if the LTR is enabled 848 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed 849 * @reduce_power_loaded: indicates reduced power section was loaded 850 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed 851 * @command_groups: pointer to command group name list array 852 * @command_groups_size: array size of @command_groups 853 * @wide_cmd_header: true when ucode supports wide command header format 854 * @wait_command_queue: wait queue for sync commands 855 * @num_rx_queues: number of RX queues allocated by the transport; 856 * the transport must set this before calling iwl_drv_start() 857 * @iml_len: the length of the image loader 858 * @iml: a pointer to the image loader itself 859 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 860 * The user should use iwl_trans_{alloc,free}_tx_cmd. 861 * @dev_cmd_pool_name: name for the TX command allocation pool 862 * @dbgfs_dir: iwlwifi debugfs base dir for this device 863 * @sync_cmd_lockdep_map: lockdep map for checking sync commands 864 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 865 * starting the firmware, used for tracing 866 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 867 * start of the 802.11 header in the @rx_mpdu_cmd 868 * @dbg: additional debug data, see &struct iwl_trans_debug 869 * @init_dram: FW initialization DMA data 870 * @system_pm_mode: the system-wide power management mode in use. 871 * This mode is set dynamically, depending on the WoWLAN values 872 * configured from the userspace at runtime. 873 * @name: the device name 874 * @mbx_addr_0_step: step address data 0 875 * @mbx_addr_1_step: step address data 1 876 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*), 877 * only valid for discrete (not integrated) NICs 878 * @invalid_tx_cmd: invalid TX command buffer 879 * @reduced_cap_sku: reduced capability supported SKU 880 * @no_160: device not supporting 160 MHz 881 * @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz 882 * @trans_specific: data for the specific transport this is allocated for/with 883 */ 884 struct iwl_trans { 885 bool csme_own; 886 struct iwl_op_mode *op_mode; 887 const struct iwl_cfg_trans_params *trans_cfg; 888 const struct iwl_cfg *cfg; 889 struct iwl_drv *drv; 890 enum iwl_trans_state state; 891 unsigned long status; 892 893 struct device *dev; 894 u32 max_skb_frags; 895 u32 hw_rev; 896 u32 hw_rev_step; 897 u32 hw_rf_id; 898 u32 hw_crf_id; 899 u32 hw_cnv_id; 900 u32 hw_wfpm_id; 901 u32 hw_id; 902 char hw_id_str[52]; 903 u32 sku_id[3]; 904 bool reduced_cap_sku; 905 u8 no_160:1, step_urm:1; 906 907 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 908 909 bool pm_support; 910 bool ltr_enabled; 911 u8 pnvm_loaded:1; 912 u8 fail_to_parse_pnvm_image:1; 913 u8 reduce_power_loaded:1; 914 u8 failed_to_load_reduce_power_image:1; 915 916 const struct iwl_hcmd_arr *command_groups; 917 int command_groups_size; 918 bool wide_cmd_header; 919 920 wait_queue_head_t wait_command_queue; 921 u8 num_rx_queues; 922 923 size_t iml_len; 924 u8 *iml; 925 926 /* The following fields are internal only */ 927 struct kmem_cache *dev_cmd_pool; 928 char dev_cmd_pool_name[50]; 929 930 struct dentry *dbgfs_dir; 931 932 #ifdef CONFIG_LOCKDEP 933 struct lockdep_map sync_cmd_lockdep_map; 934 #endif 935 936 struct iwl_trans_debug dbg; 937 struct iwl_self_init_dram init_dram; 938 939 enum iwl_plat_pm_mode system_pm_mode; 940 941 const char *name; 942 u32 mbx_addr_0_step; 943 u32 mbx_addr_1_step; 944 945 u8 pcie_link_speed; 946 947 struct iwl_dma_ptr invalid_tx_cmd; 948 949 /* pointer to trans specific struct */ 950 /*Ensure that this pointer will always be aligned to sizeof pointer */ 951 char trans_specific[] __aligned(sizeof(void *)); 952 }; 953 954 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 955 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 956 957 void iwl_trans_configure(struct iwl_trans *trans, 958 const struct iwl_trans_config *trans_cfg); 959 960 int iwl_trans_start_hw(struct iwl_trans *trans); 961 962 void iwl_trans_op_mode_leave(struct iwl_trans *trans); 963 964 void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr); 965 966 int iwl_trans_start_fw(struct iwl_trans *trans, const struct fw_img *fw, 967 bool run_in_rfkill); 968 969 void iwl_trans_stop_device(struct iwl_trans *trans); 970 971 int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, bool reset); 972 973 int iwl_trans_d3_resume(struct iwl_trans *trans, enum iwl_d3_status *status, 974 bool test, bool reset); 975 976 struct iwl_trans_dump_data * 977 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask, 978 const struct iwl_dump_sanitize_ops *sanitize_ops, 979 void *sanitize_ctx); 980 981 static inline struct iwl_device_tx_cmd * 982 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 983 { 984 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 985 } 986 987 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 988 989 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 990 struct iwl_device_tx_cmd *dev_cmd) 991 { 992 kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 993 } 994 995 int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 996 struct iwl_device_tx_cmd *dev_cmd, int queue); 997 998 void iwl_trans_reclaim(struct iwl_trans *trans, int queue, int ssn, 999 struct sk_buff_head *skbs, bool is_flush); 1000 1001 void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, int ptr); 1002 1003 void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1004 bool configure_scd); 1005 1006 bool iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1007 const struct iwl_trans_txq_scd_cfg *cfg, 1008 unsigned int queue_wdg_timeout); 1009 1010 int iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 1011 struct iwl_trans_rxq_dma_data *data); 1012 1013 void iwl_trans_txq_free(struct iwl_trans *trans, int queue); 1014 1015 int iwl_trans_txq_alloc(struct iwl_trans *trans, u32 flags, u32 sta_mask, 1016 u8 tid, int size, unsigned int wdg_timeout); 1017 1018 void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 1019 int txq_id, bool shared_mode); 1020 1021 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1022 int fifo, int sta_id, int tid, 1023 int frame_limit, u16 ssn, 1024 unsigned int queue_wdg_timeout) 1025 { 1026 struct iwl_trans_txq_scd_cfg cfg = { 1027 .fifo = fifo, 1028 .sta_id = sta_id, 1029 .tid = tid, 1030 .frame_limit = frame_limit, 1031 .aggregate = sta_id >= 0, 1032 }; 1033 1034 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1035 } 1036 1037 static inline 1038 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1039 unsigned int queue_wdg_timeout) 1040 { 1041 struct iwl_trans_txq_scd_cfg cfg = { 1042 .fifo = fifo, 1043 .sta_id = -1, 1044 .tid = IWL_MAX_TID_COUNT, 1045 .frame_limit = IWL_FRAME_LIMIT, 1046 .aggregate = false, 1047 }; 1048 1049 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1050 } 1051 1052 void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1053 unsigned long txqs, bool freeze); 1054 1055 int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs); 1056 1057 int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue); 1058 1059 void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val); 1060 1061 void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val); 1062 1063 u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs); 1064 1065 u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs); 1066 1067 void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val); 1068 1069 int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1070 void *buf, int dwords); 1071 1072 int iwl_trans_read_config32(struct iwl_trans *trans, u32 ofs, 1073 u32 *val); 1074 1075 #ifdef CONFIG_IWLWIFI_DEBUGFS 1076 void iwl_trans_debugfs_cleanup(struct iwl_trans *trans); 1077 #endif 1078 1079 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1080 do { \ 1081 if (__builtin_constant_p(bufsize)) \ 1082 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1083 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1084 } while (0) 1085 1086 int iwl_trans_write_imr_mem(struct iwl_trans *trans, u32 dst_addr, 1087 u64 src_addr, u32 byte_cnt); 1088 1089 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1090 { 1091 u32 value; 1092 1093 if (iwl_trans_read_mem(trans, addr, &value, 1)) 1094 return 0xa5a5a5a5; 1095 1096 return value; 1097 } 1098 1099 int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1100 const void *buf, int dwords); 1101 1102 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1103 u32 val) 1104 { 1105 return iwl_trans_write_mem(trans, addr, &val, 1); 1106 } 1107 1108 void iwl_trans_set_pmi(struct iwl_trans *trans, bool state); 1109 1110 int iwl_trans_sw_reset(struct iwl_trans *trans, bool retake_ownership); 1111 1112 void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, 1113 u32 mask, u32 value); 1114 1115 bool _iwl_trans_grab_nic_access(struct iwl_trans *trans); 1116 1117 #define iwl_trans_grab_nic_access(trans) \ 1118 __cond_lock(nic_access, \ 1119 likely(_iwl_trans_grab_nic_access(trans))) 1120 1121 void __releases(nic_access) 1122 iwl_trans_release_nic_access(struct iwl_trans *trans); 1123 1124 static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync) 1125 { 1126 if (WARN_ON_ONCE(!trans->op_mode)) 1127 return; 1128 1129 /* prevent double restarts due to the same erroneous FW */ 1130 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1131 iwl_op_mode_nic_error(trans->op_mode, sync); 1132 trans->state = IWL_TRANS_NO_FW; 1133 } 1134 } 1135 1136 static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1137 { 1138 return trans->state == IWL_TRANS_FW_ALIVE; 1139 } 1140 1141 void iwl_trans_sync_nmi(struct iwl_trans *trans); 1142 1143 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 1144 u32 sw_err_bit); 1145 1146 int iwl_trans_load_pnvm(struct iwl_trans *trans, 1147 const struct iwl_pnvm_image *pnvm_data, 1148 const struct iwl_ucode_capabilities *capa); 1149 1150 void iwl_trans_set_pnvm(struct iwl_trans *trans, 1151 const struct iwl_ucode_capabilities *capa); 1152 1153 int iwl_trans_load_reduce_power(struct iwl_trans *trans, 1154 const struct iwl_pnvm_image *payloads, 1155 const struct iwl_ucode_capabilities *capa); 1156 1157 void iwl_trans_set_reduce_power(struct iwl_trans *trans, 1158 const struct iwl_ucode_capabilities *capa); 1159 1160 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1161 { 1162 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1163 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1164 } 1165 1166 void iwl_trans_interrupts(struct iwl_trans *trans, bool enable); 1167 1168 /***************************************************** 1169 * transport helper functions 1170 *****************************************************/ 1171 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1172 struct device *dev, 1173 const struct iwl_cfg_trans_params *cfg_trans); 1174 int iwl_trans_init(struct iwl_trans *trans); 1175 void iwl_trans_free(struct iwl_trans *trans); 1176 1177 static inline bool iwl_trans_is_hw_error_value(u32 val) 1178 { 1179 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50); 1180 } 1181 1182 /***************************************************** 1183 * PCIe handling 1184 *****************************************************/ 1185 int __must_check iwl_pci_register_driver(void); 1186 void iwl_pci_unregister_driver(void); 1187 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan); 1188 1189 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, 1190 struct iwl_host_cmd *cmd); 1191 1192 #endif /* __iwl_trans_h__ */ 1193