1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_trans_h__ 8 #define __iwl_trans_h__ 9 10 #include <linux/ieee80211.h> 11 #include <linux/mm.h> /* for page_address */ 12 #include <linux/lockdep.h> 13 #include <linux/kernel.h> 14 15 #include "iwl-debug.h" 16 #include "iwl-config.h" 17 #include "fw/img.h" 18 #include "iwl-op-mode.h" 19 #include <linux/firmware.h> 20 #include "fw/api/cmdhdr.h" 21 #include "fw/api/txq.h" 22 #include "fw/api/dbg-tlv.h" 23 #include "iwl-dbg-tlv.h" 24 25 /** 26 * DOC: Transport layer - what is it ? 27 * 28 * The transport layer is the layer that deals with the HW directly. It provides 29 * the PCIe access to the underlying hardwarwe. The transport layer doesn't 30 * provide any policy, algorithm or anything of this kind, but only mechanisms 31 * to make the HW do something. It is not completely stateless but close to it. 32 */ 33 34 /** 35 * DOC: Life cycle of the transport layer 36 * 37 * The transport layer has a very precise life cycle. 38 * 39 * 1) A helper function is called during the module initialization and 40 * registers the bus driver's ops with the transport's alloc function. 41 * 2) Bus's probe calls to the transport layer's allocation functions. 42 * Of course this function is bus specific. 43 * 3) This allocation functions will spawn the upper layer which will 44 * register mac80211. 45 * 46 * 4) At some point (i.e. mac80211's start call), the op_mode will call 47 * the following sequence: 48 * start_hw 49 * start_fw 50 * 51 * 5) Then when finished (or reset): 52 * stop_device 53 * 54 * 6) Eventually, the free function will be called. 55 */ 56 57 /* default preset 0 (start from bit 16)*/ 58 #define IWL_FW_DBG_DOMAIN_POS 16 59 #define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS) 60 61 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 62 63 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 64 #define FH_RSCSR_FRAME_INVALID 0x55550000 65 #define FH_RSCSR_FRAME_ALIGN 0x40 66 #define FH_RSCSR_RPA_EN BIT(25) 67 #define FH_RSCSR_RADA_EN BIT(26) 68 #define FH_RSCSR_RXQ_POS 16 69 #define FH_RSCSR_RXQ_MASK 0x3F0000 70 71 struct iwl_rx_packet { 72 /* 73 * The first 4 bytes of the RX frame header contain both the RX frame 74 * size and some flags. 75 * Bit fields: 76 * 31: flag flush RB request 77 * 30: flag ignore TC (terminal counter) request 78 * 29: flag fast IRQ request 79 * 28-27: Reserved 80 * 26: RADA enabled 81 * 25: Offload enabled 82 * 24: RPF enabled 83 * 23: RSS enabled 84 * 22: Checksum enabled 85 * 21-16: RX queue 86 * 15-14: Reserved 87 * 13-00: RX frame size 88 */ 89 __le32 len_n_flags; 90 struct iwl_cmd_header hdr; 91 u8 data[]; 92 } __packed; 93 94 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 95 { 96 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 97 } 98 99 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 100 { 101 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 102 } 103 104 /** 105 * enum CMD_MODE - how to send the host commands ? 106 * 107 * @CMD_ASYNC: Return right away and don't wait for the response 108 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 109 * the response. The caller needs to call iwl_free_resp when done. 110 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill. 111 * @CMD_BLOCK_TXQS: Block TXQs while the comment is executing. 112 */ 113 enum CMD_MODE { 114 CMD_ASYNC = BIT(0), 115 CMD_WANT_SKB = BIT(1), 116 CMD_SEND_IN_RFKILL = BIT(2), 117 CMD_BLOCK_TXQS = BIT(3), 118 }; 119 #define CMD_MODE_BITS 5 120 121 #define DEF_CMD_PAYLOAD_SIZE 320 122 123 /** 124 * struct iwl_device_cmd 125 * 126 * For allocation of the command and tx queues, this establishes the overall 127 * size of the largest command we send to uCode, except for commands that 128 * aren't fully copied and use other TFD space. 129 * 130 * @hdr: command header 131 * @payload: payload for the command 132 * @hdr_wide: wide command header 133 * @payload_wide: payload for the wide command 134 */ 135 struct iwl_device_cmd { 136 union { 137 struct { 138 struct iwl_cmd_header hdr; /* uCode API */ 139 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 140 }; 141 struct { 142 struct iwl_cmd_header_wide hdr_wide; 143 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 144 sizeof(struct iwl_cmd_header_wide) + 145 sizeof(struct iwl_cmd_header)]; 146 }; 147 }; 148 } __packed; 149 150 /** 151 * struct iwl_device_tx_cmd - buffer for TX command 152 * @hdr: the header 153 * @payload: the payload placeholder 154 * 155 * The actual structure is sized dynamically according to need. 156 */ 157 struct iwl_device_tx_cmd { 158 struct iwl_cmd_header hdr; 159 u8 payload[]; 160 } __packed; 161 162 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 163 164 /* 165 * number of transfer buffers (fragments) per transmit frame descriptor; 166 * this is just the driver's idea, the hardware supports 20 167 */ 168 #define IWL_MAX_CMD_TBS_PER_TFD 2 169 170 /** 171 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 172 * 173 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 174 * ring. The transport layer doesn't map the command's buffer to DMA, but 175 * rather copies it to a previously allocated DMA buffer. This flag tells 176 * the transport layer not to copy the command, but to map the existing 177 * buffer (that is passed in) instead. This saves the memcpy and allows 178 * commands that are bigger than the fixed buffer to be submitted. 179 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 180 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 181 * chunk internally and free it again after the command completes. This 182 * can (currently) be used only once per command. 183 * Note that a TFD entry after a DUP one cannot be a normal copied one. 184 */ 185 enum iwl_hcmd_dataflag { 186 IWL_HCMD_DFL_NOCOPY = BIT(0), 187 IWL_HCMD_DFL_DUP = BIT(1), 188 }; 189 190 enum iwl_error_event_table_status { 191 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 192 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 193 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 194 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3), 195 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4), 196 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5), 197 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6), 198 }; 199 200 /** 201 * struct iwl_host_cmd - Host command to the uCode 202 * 203 * @data: array of chunks that composes the data of the host command 204 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 205 * @_rx_page_order: (internally used to free response packet) 206 * @_rx_page_addr: (internally used to free response packet) 207 * @flags: can be CMD_* 208 * @len: array of the lengths of the chunks in data 209 * @dataflags: IWL_HCMD_DFL_* 210 * @id: command id of the host command, for wide commands encoding the 211 * version and group as well 212 */ 213 struct iwl_host_cmd { 214 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 215 struct iwl_rx_packet *resp_pkt; 216 unsigned long _rx_page_addr; 217 u32 _rx_page_order; 218 219 u32 flags; 220 u32 id; 221 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 222 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 223 }; 224 225 static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 226 { 227 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 228 } 229 230 struct iwl_rx_cmd_buffer { 231 struct page *_page; 232 int _offset; 233 bool _page_stolen; 234 u32 _rx_page_order; 235 unsigned int truesize; 236 }; 237 238 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 239 { 240 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 241 } 242 243 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 244 { 245 return r->_offset; 246 } 247 248 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 249 { 250 r->_page_stolen = true; 251 get_page(r->_page); 252 return r->_page; 253 } 254 255 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 256 { 257 __free_pages(r->_page, r->_rx_page_order); 258 } 259 260 #define MAX_NO_RECLAIM_CMDS 6 261 262 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 263 264 /* 265 * Maximum number of HW queues the transport layer 266 * currently supports 267 */ 268 #define IWL_MAX_HW_QUEUES 32 269 #define IWL_MAX_TVQM_QUEUES 512 270 271 #define IWL_MAX_TID_COUNT 8 272 #define IWL_MGMT_TID 15 273 #define IWL_FRAME_LIMIT 64 274 #define IWL_MAX_RX_HW_QUEUES 16 275 #define IWL_9000_MAX_RX_HW_QUEUES 1 276 277 /** 278 * enum iwl_d3_status - WoWLAN image/device status 279 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 280 * @IWL_D3_STATUS_RESET: device was reset while suspended 281 */ 282 enum iwl_d3_status { 283 IWL_D3_STATUS_ALIVE, 284 IWL_D3_STATUS_RESET, 285 }; 286 287 /** 288 * enum iwl_trans_status: transport status flags 289 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 290 * @STATUS_DEVICE_ENABLED: APM is enabled 291 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 292 * @STATUS_INT_ENABLED: interrupts are enabled 293 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 294 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 295 * @STATUS_FW_ERROR: the fw is in error state 296 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 297 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once, 298 * e.g. for testing 299 * @STATUS_IN_SW_RESET: device is undergoing reset, cleared by opmode 300 * via iwl_trans_finish_sw_reset() 301 * @STATUS_RESET_PENDING: reset worker was scheduled, but didn't dump 302 * the firmware state yet 303 * @STATUS_TRANS_RESET_IN_PROGRESS: reset is still in progress, don't 304 * attempt another reset yet 305 * @STATUS_SUSPENDED: device is suspended, don't send commands that 306 * aren't marked accordingly 307 */ 308 enum iwl_trans_status { 309 STATUS_SYNC_HCMD_ACTIVE, 310 STATUS_DEVICE_ENABLED, 311 STATUS_TPOWER_PMI, 312 STATUS_INT_ENABLED, 313 STATUS_RFKILL_HW, 314 STATUS_RFKILL_OPMODE, 315 STATUS_FW_ERROR, 316 STATUS_TRANS_DEAD, 317 STATUS_SUPPRESS_CMD_ERROR_ONCE, 318 STATUS_IN_SW_RESET, 319 STATUS_RESET_PENDING, 320 STATUS_TRANS_RESET_IN_PROGRESS, 321 STATUS_SUSPENDED, 322 }; 323 324 static inline int 325 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 326 { 327 switch (rb_size) { 328 case IWL_AMSDU_2K: 329 return get_order(2 * 1024); 330 case IWL_AMSDU_4K: 331 return get_order(4 * 1024); 332 case IWL_AMSDU_8K: 333 return get_order(8 * 1024); 334 case IWL_AMSDU_12K: 335 return get_order(16 * 1024); 336 default: 337 WARN_ON(1); 338 return -1; 339 } 340 } 341 342 static inline int 343 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 344 { 345 switch (rb_size) { 346 case IWL_AMSDU_2K: 347 return 2 * 1024; 348 case IWL_AMSDU_4K: 349 return 4 * 1024; 350 case IWL_AMSDU_8K: 351 return 8 * 1024; 352 case IWL_AMSDU_12K: 353 return 16 * 1024; 354 default: 355 WARN_ON(1); 356 return 0; 357 } 358 } 359 360 struct iwl_hcmd_names { 361 u8 cmd_id; 362 const char *const cmd_name; 363 }; 364 365 #define HCMD_NAME(x) \ 366 { .cmd_id = x, .cmd_name = #x } 367 368 struct iwl_hcmd_arr { 369 const struct iwl_hcmd_names *arr; 370 int size; 371 }; 372 373 #define HCMD_ARR(x) \ 374 { .arr = x, .size = ARRAY_SIZE(x) } 375 376 /** 377 * struct iwl_dump_sanitize_ops - dump sanitization operations 378 * @frob_txf: Scrub the TX FIFO data 379 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header 380 * but that might be short or long (&struct iwl_cmd_header or 381 * &struct iwl_cmd_header_wide) 382 * @frob_mem: Scrub memory data 383 */ 384 struct iwl_dump_sanitize_ops { 385 void (*frob_txf)(void *ctx, void *buf, size_t buflen); 386 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen); 387 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen); 388 }; 389 390 /** 391 * struct iwl_trans_config - transport configuration 392 * 393 * These values should be set before iwl_trans_op_mode_enter(). 394 * 395 * @cmd_queue: the index of the command queue. 396 * Must be set before start_fw. 397 * @cmd_fifo: the fifo for host commands 398 * @no_reclaim_cmds: Some devices erroneously don't set the 399 * SEQ_RX_FRAME bit on some notifications, this is the 400 * list of such notifications to filter. Max length is 401 * %MAX_NO_RECLAIM_CMDS. 402 * @n_no_reclaim_cmds: # of commands in list 403 * @rx_buf_size: RX buffer size needed for A-MSDUs 404 * if unset 4k will be the RX buffer size 405 * @scd_set_active: should the transport configure the SCD for HCMD queue 406 * @command_groups: array of command groups, each member is an array of the 407 * commands in the group; for debugging only 408 * @command_groups_size: number of command groups, to avoid illegal access 409 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 410 * space for at least two pointers 411 * @fw_reset_handshake: firmware supports reset flow handshake 412 * @queue_alloc_cmd_ver: queue allocation command version, set to 0 413 * for using the older SCD_QUEUE_CFG, set to the version of 414 * SCD_QUEUE_CONFIG_CMD otherwise. 415 * @wide_cmd_header: true when ucode supports wide command header format 416 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 417 * starting the firmware, used for tracing 418 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 419 * start of the 802.11 header in the @rx_mpdu_cmd 420 * @dsbr_urm_fw_dependent: switch to URM based on fw settings 421 * @dsbr_urm_permanent: switch to URM permanently 422 * @mbx_addr_0_step: step address data 0 423 * @mbx_addr_1_step: step address data 1 424 * @ext_32khz_clock_valid: if true, the external 32 KHz clock can be used 425 */ 426 struct iwl_trans_config { 427 u8 cmd_queue; 428 u8 cmd_fifo; 429 u8 n_no_reclaim_cmds; 430 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 431 432 enum iwl_amsdu_size rx_buf_size; 433 bool scd_set_active; 434 const struct iwl_hcmd_arr *command_groups; 435 int command_groups_size; 436 437 u8 cb_data_offs; 438 bool fw_reset_handshake; 439 u8 queue_alloc_cmd_ver; 440 441 bool wide_cmd_header; 442 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 443 444 u8 dsbr_urm_fw_dependent:1, 445 dsbr_urm_permanent:1, 446 ext_32khz_clock_valid:1; 447 448 u32 mbx_addr_0_step; 449 u32 mbx_addr_1_step; 450 }; 451 452 struct iwl_trans_dump_data { 453 u32 len; 454 u8 data[]; 455 }; 456 457 struct iwl_trans; 458 459 struct iwl_trans_txq_scd_cfg { 460 u8 fifo; 461 u8 sta_id; 462 u8 tid; 463 bool aggregate; 464 int frame_limit; 465 }; 466 467 /** 468 * struct iwl_trans_rxq_dma_data - RX queue DMA data 469 * @fr_bd_cb: DMA address of free BD cyclic buffer 470 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 471 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 472 * @ur_bd_cb: DMA address of used BD cyclic buffer 473 */ 474 struct iwl_trans_rxq_dma_data { 475 u64 fr_bd_cb; 476 u32 fr_bd_wid; 477 u64 urbd_stts_wrptr; 478 u64 ur_bd_cb; 479 }; 480 481 /* maximal number of DRAM MAP entries supported by FW */ 482 #define IPC_DRAM_MAP_ENTRY_NUM_MAX 64 483 484 /** 485 * struct iwl_pnvm_image - contains info about the parsed pnvm image 486 * @chunks: array of pointers to pnvm payloads and their sizes 487 * @n_chunks: the number of the pnvm payloads. 488 * @version: the version of the loaded PNVM image 489 */ 490 struct iwl_pnvm_image { 491 struct { 492 const void *data; 493 u32 len; 494 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 495 u32 n_chunks; 496 u32 version; 497 }; 498 499 /** 500 * enum iwl_trans_state - state of the transport layer 501 * 502 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 503 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 504 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 505 */ 506 enum iwl_trans_state { 507 IWL_TRANS_NO_FW, 508 IWL_TRANS_FW_STARTED, 509 IWL_TRANS_FW_ALIVE, 510 }; 511 512 /** 513 * DOC: Platform power management 514 * 515 * In system-wide power management the entire platform goes into a low 516 * power state (e.g. idle or suspend to RAM) at the same time and the 517 * device is configured as a wakeup source for the entire platform. 518 * This is usually triggered by userspace activity (e.g. the user 519 * presses the suspend button or a power management daemon decides to 520 * put the platform in low power mode). The device's behavior in this 521 * mode is dictated by the wake-on-WLAN configuration. 522 * 523 * The terms used for the device's behavior are as follows: 524 * 525 * - D0: the device is fully powered and the host is awake; 526 * - D3: the device is in low power mode and only reacts to 527 * specific events (e.g. magic-packet received or scan 528 * results found); 529 * 530 * These terms reflect the power modes in the firmware and are not to 531 * be confused with the physical device power state. 532 */ 533 534 /** 535 * enum iwl_ini_cfg_state 536 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 537 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 538 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 539 * are corrupted. The rest of the debug TLVs will still be used 540 */ 541 enum iwl_ini_cfg_state { 542 IWL_INI_CFG_STATE_NOT_LOADED, 543 IWL_INI_CFG_STATE_LOADED, 544 IWL_INI_CFG_STATE_CORRUPTED, 545 }; 546 547 /* Max time to wait for nmi interrupt */ 548 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 549 550 /** 551 * struct iwl_dram_data 552 * @physical: page phy pointer 553 * @block: pointer to the allocated block/page 554 * @size: size of the block/page 555 */ 556 struct iwl_dram_data { 557 dma_addr_t physical; 558 void *block; 559 int size; 560 }; 561 562 /** 563 * struct iwl_dram_regions - DRAM regions container structure 564 * @drams: array of several DRAM areas that contains the pnvm and power 565 * reduction table payloads. 566 * @n_regions: number of DRAM regions that were allocated 567 * @prph_scratch_mem_desc: points to a structure allocated in dram, 568 * designed to show FW where all the payloads are. 569 */ 570 struct iwl_dram_regions { 571 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 572 struct iwl_dram_data prph_scratch_mem_desc; 573 u8 n_regions; 574 }; 575 576 /** 577 * struct iwl_fw_mon - fw monitor per allocation id 578 * @num_frags: number of fragments 579 * @frags: an array of DRAM buffer fragments 580 */ 581 struct iwl_fw_mon { 582 u32 num_frags; 583 struct iwl_dram_data *frags; 584 }; 585 586 /** 587 * struct iwl_self_init_dram - dram data used by self init process 588 * @fw: lmac and umac dram data 589 * @fw_cnt: total number of items in array 590 * @paging: paging dram data 591 * @paging_cnt: total number of items in array 592 */ 593 struct iwl_self_init_dram { 594 struct iwl_dram_data *fw; 595 int fw_cnt; 596 struct iwl_dram_data *paging; 597 int paging_cnt; 598 }; 599 600 /** 601 * struct iwl_imr_data - imr dram data used during debug process 602 * @imr_enable: imr enable status received from fw 603 * @imr_size: imr dram size received from fw 604 * @sram_addr: sram address from debug tlv 605 * @sram_size: sram size from debug tlv 606 * @imr2sram_remainbyte: size remained after each dma transfer 607 * @imr_curr_addr: current dst address used during dma transfer 608 * @imr_base_addr: imr address received from fw 609 */ 610 struct iwl_imr_data { 611 u32 imr_enable; 612 u32 imr_size; 613 u32 sram_addr; 614 u32 sram_size; 615 u32 imr2sram_remainbyte; 616 u64 imr_curr_addr; 617 __le64 imr_base_addr; 618 }; 619 620 #define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32 621 622 /** 623 * struct iwl_pc_data - program counter details 624 * @pc_name: cpu name 625 * @pc_address: cpu program counter 626 */ 627 struct iwl_pc_data { 628 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES]; 629 u32 pc_address; 630 }; 631 632 /** 633 * struct iwl_trans_debug - transport debug related data 634 * 635 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 636 * @rec_on: true iff there is a fw debug recording currently active 637 * @dest_tlv: points to the destination TLV for debug 638 * @lmac_error_event_table: addrs of lmacs error tables 639 * @umac_error_event_table: addr of umac error table 640 * @tcm_error_event_table: address(es) of TCM error table(s) 641 * @rcm_error_event_table: address(es) of RCM error table(s) 642 * @error_event_table_tlv_status: bitmap that indicates what error table 643 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 644 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 645 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 646 * @fw_mon_cfg: debug buffer allocation configuration 647 * @fw_mon_ini: DRAM buffer fragments per allocation id 648 * @fw_mon: DRAM buffer for firmware monitor 649 * @hw_error: equals true if hw error interrupt was received from the FW 650 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 651 * @unsupported_region_msk: unsupported regions out of active_regions 652 * @active_regions: active regions 653 * @debug_info_tlv_list: list of debug info TLVs 654 * @time_point: array of debug time points 655 * @periodic_trig_list: periodic triggers list 656 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON 657 * @ucode_preset: preset based on ucode 658 * @restart_required: indicates debug restart is required 659 * @last_tp_resetfw: last handling of reset during debug timepoint 660 * @imr_data: IMR debug data allocation 661 * @num_pc: number of program counter for cpu 662 * @pc_data: details of the program counter 663 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded 664 */ 665 struct iwl_trans_debug { 666 u8 n_dest_reg; 667 bool rec_on; 668 669 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 670 671 u32 lmac_error_event_table[2]; 672 u32 umac_error_event_table; 673 u32 tcm_error_event_table[2]; 674 u32 rcm_error_event_table[2]; 675 unsigned int error_event_table_tlv_status; 676 677 enum iwl_ini_cfg_state internal_ini_cfg; 678 enum iwl_ini_cfg_state external_ini_cfg; 679 680 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 681 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 682 683 struct iwl_dram_data fw_mon; 684 685 bool hw_error; 686 enum iwl_fw_ini_buffer_location ini_dest; 687 688 u64 unsupported_region_msk; 689 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 690 struct list_head debug_info_tlv_list; 691 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM]; 692 struct list_head periodic_trig_list; 693 694 u32 domains_bitmap; 695 u32 ucode_preset; 696 bool restart_required; 697 u32 last_tp_resetfw; 698 struct iwl_imr_data imr_data; 699 u32 num_pc; 700 struct iwl_pc_data *pc_data; 701 bool yoyo_bin_loaded; 702 }; 703 704 struct iwl_dma_ptr { 705 dma_addr_t dma; 706 void *addr; 707 size_t size; 708 }; 709 710 struct iwl_cmd_meta { 711 /* only for SYNC commands, iff the reply skb is wanted */ 712 struct iwl_host_cmd *source; 713 u32 flags: CMD_MODE_BITS; 714 /* sg_offset is valid if it is non-zero */ 715 u32 sg_offset: PAGE_SHIFT; 716 u32 tbs; 717 }; 718 719 /* 720 * The FH will write back to the first TB only, so we need to copy some data 721 * into the buffer regardless of whether it should be mapped or not. 722 * This indicates how big the first TB must be to include the scratch buffer 723 * and the assigned PN. 724 * Since PN location is 8 bytes at offset 12, it's 20 now. 725 * If we make it bigger then allocations will be bigger and copy slower, so 726 * that's probably not useful. 727 */ 728 #define IWL_FIRST_TB_SIZE 20 729 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 730 731 struct iwl_pcie_txq_entry { 732 void *cmd; 733 struct sk_buff *skb; 734 /* buffer to free after command completes */ 735 const void *free_buf; 736 struct iwl_cmd_meta meta; 737 }; 738 739 struct iwl_pcie_first_tb_buf { 740 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 741 }; 742 743 /** 744 * struct iwl_txq - Tx Queue for DMA 745 * @tfds: transmit frame descriptors (DMA memory) 746 * @first_tb_bufs: start of command headers, including scratch buffers, for 747 * the writeback -- this is DMA memory and an array holding one buffer 748 * for each command on the queue 749 * @first_tb_dma: DMA address for the first_tb_bufs start 750 * @entries: transmit entries (driver state) 751 * @lock: queue lock 752 * @reclaim_lock: reclaim lock 753 * @stuck_timer: timer that fires if queue gets stuck 754 * @trans: pointer back to transport (for timer) 755 * @need_update: indicates need to update read/write index 756 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 757 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 758 * @frozen: tx stuck queue timer is frozen 759 * @frozen_expiry_remainder: remember how long until the timer fires 760 * @block: queue is blocked 761 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 762 * @write_ptr: 1-st empty entry (index) host_w 763 * @read_ptr: last used entry (index) host_r 764 * @dma_addr: physical addr for BD's 765 * @n_window: safe queue window 766 * @id: queue id 767 * @low_mark: low watermark, resume queue if free space more than this 768 * @high_mark: high watermark, stop queue if free space less than this 769 * @overflow_q: overflow queue for handling frames that didn't fit on HW queue 770 * @overflow_tx: need to transmit from overflow 771 * 772 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 773 * descriptors) and required locking structures. 774 * 775 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 776 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 777 * there might be HW changes in the future). For the normal TX 778 * queues, n_window, which is the size of the software queue data 779 * is also 256; however, for the command queue, n_window is only 780 * 32 since we don't need so many commands pending. Since the HW 781 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 782 * This means that we end up with the following: 783 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 784 * SW entries: | 0 | ... | 31 | 785 * where N is a number between 0 and 7. This means that the SW 786 * data is a window overlayed over the HW queue. 787 */ 788 struct iwl_txq { 789 void *tfds; 790 struct iwl_pcie_first_tb_buf *first_tb_bufs; 791 dma_addr_t first_tb_dma; 792 struct iwl_pcie_txq_entry *entries; 793 /* lock for syncing changes on the queue */ 794 spinlock_t lock; 795 /* lock to prevent concurrent reclaim */ 796 spinlock_t reclaim_lock; 797 unsigned long frozen_expiry_remainder; 798 struct timer_list stuck_timer; 799 struct iwl_trans *trans; 800 bool need_update; 801 bool frozen; 802 bool ampdu; 803 int block; 804 unsigned long wd_timeout; 805 struct sk_buff_head overflow_q; 806 struct iwl_dma_ptr bc_tbl; 807 808 int write_ptr; 809 int read_ptr; 810 dma_addr_t dma_addr; 811 int n_window; 812 u32 id; 813 int low_mark; 814 int high_mark; 815 816 bool overflow_tx; 817 }; 818 819 /** 820 * struct iwl_trans_info - transport info for outside use 821 * @name: the device name 822 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 823 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 824 * @hw_rev: the revision data of the HW 825 * @hw_rev_step: The mac step of the HW 826 * @hw_rf_id: the device RF ID 827 * @hw_cnv_id: the device CNV ID 828 * @hw_crf_id: the device CRF ID 829 * @hw_wfpm_id: the device wfpm ID 830 * @hw_id: the ID of the device / sub-device 831 * Bits 0:15 represent the sub-device ID 832 * Bits 16:31 represent the device ID. 833 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*), 834 * only valid for discrete (not integrated) NICs 835 * @num_rxqs: number of RX queues allocated by the transport 836 */ 837 struct iwl_trans_info { 838 const char *name; 839 u32 max_skb_frags; 840 u32 hw_rev; 841 u32 hw_rev_step; 842 u32 hw_rf_id; 843 u32 hw_crf_id; 844 u32 hw_cnv_id; 845 u32 hw_wfpm_id; 846 u32 hw_id; 847 u8 pcie_link_speed; 848 u8 num_rxqs; 849 }; 850 851 /** 852 * struct iwl_trans - transport common data 853 * 854 * @csme_own: true if we couldn't get ownership on the device 855 * @op_mode: pointer to the op_mode 856 * @mac_cfg: the trans-specific configuration part 857 * @cfg: pointer to the configuration 858 * @drv: pointer to iwl_drv 859 * @conf: configuration set by the opmode before enter 860 * @state: current device state 861 * @status: a bit-mask of transport status flags 862 * @dev: pointer to struct device * that represents the device 863 * @info: device information for use by other layers 864 * @pnvm_loaded: indicates PNVM was loaded 865 * @pm_support: set to true in start_hw if link pm is supported 866 * @ltr_enabled: set to true if the LTR is enabled 867 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed 868 * @reduce_power_loaded: indicates reduced power section was loaded 869 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed 870 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 871 * The user should use iwl_trans_{alloc,free}_tx_cmd. 872 * @dev_cmd_pool_name: name for the TX command allocation pool 873 * @dbgfs_dir: iwlwifi debugfs base dir for this device 874 * @sync_cmd_lockdep_map: lockdep map for checking sync commands 875 * @dbg: additional debug data, see &struct iwl_trans_debug 876 * @init_dram: FW initialization DMA data 877 * @reduced_cap_sku: reduced capability supported SKU 878 * @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz 879 * @restart: restart worker data 880 * @restart.wk: restart worker 881 * @restart.mode: reset/restart error mode information 882 * @restart.during_reset: error occurred during previous software reset 883 * @trans_specific: data for the specific transport this is allocated for/with 884 * @request_top_reset: TOP reset was requested, used by the reset 885 * worker that should be scheduled (with appropriate reason) 886 * @do_top_reset: indication to the (PCIe) transport/context-info 887 * to do the TOP reset 888 */ 889 struct iwl_trans { 890 bool csme_own; 891 struct iwl_op_mode *op_mode; 892 const struct iwl_mac_cfg *mac_cfg; 893 const struct iwl_rf_cfg *cfg; 894 struct iwl_drv *drv; 895 struct iwl_trans_config conf; 896 enum iwl_trans_state state; 897 unsigned long status; 898 899 struct device *dev; 900 901 const struct iwl_trans_info info; 902 bool reduced_cap_sku; 903 bool step_urm; 904 905 bool pm_support; 906 bool ltr_enabled; 907 u8 pnvm_loaded:1; 908 u8 fail_to_parse_pnvm_image:1; 909 u8 reduce_power_loaded:1; 910 u8 failed_to_load_reduce_power_image:1; 911 912 /* The following fields are internal only */ 913 struct kmem_cache *dev_cmd_pool; 914 char dev_cmd_pool_name[50]; 915 916 struct dentry *dbgfs_dir; 917 918 #ifdef CONFIG_LOCKDEP 919 struct lockdep_map sync_cmd_lockdep_map; 920 #endif 921 922 struct iwl_trans_debug dbg; 923 struct iwl_self_init_dram init_dram; 924 925 struct { 926 struct delayed_work wk; 927 struct iwl_fw_error_dump_mode mode; 928 bool during_reset; 929 } restart; 930 931 u8 request_top_reset:1, 932 do_top_reset:1; 933 934 /* pointer to trans specific struct */ 935 /*Ensure that this pointer will always be aligned to sizeof pointer */ 936 char trans_specific[] __aligned(sizeof(void *)); 937 }; 938 939 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 940 941 void iwl_trans_op_mode_enter(struct iwl_trans *trans, 942 struct iwl_op_mode *op_mode); 943 944 int iwl_trans_start_hw(struct iwl_trans *trans); 945 946 void iwl_trans_op_mode_leave(struct iwl_trans *trans); 947 948 void iwl_trans_fw_alive(struct iwl_trans *trans); 949 950 int iwl_trans_start_fw(struct iwl_trans *trans, const struct iwl_fw *fw, 951 enum iwl_ucode_type ucode_type, bool run_in_rfkill); 952 953 void iwl_trans_stop_device(struct iwl_trans *trans); 954 955 int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, bool reset); 956 957 int iwl_trans_d3_resume(struct iwl_trans *trans, enum iwl_d3_status *status, 958 bool test, bool reset); 959 960 struct iwl_trans_dump_data * 961 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask, 962 const struct iwl_dump_sanitize_ops *sanitize_ops, 963 void *sanitize_ctx); 964 965 static inline struct iwl_device_tx_cmd * 966 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 967 { 968 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 969 } 970 971 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 972 973 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 974 struct iwl_device_tx_cmd *dev_cmd) 975 { 976 kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 977 } 978 979 int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 980 struct iwl_device_tx_cmd *dev_cmd, int queue); 981 982 void iwl_trans_reclaim(struct iwl_trans *trans, int queue, int ssn, 983 struct sk_buff_head *skbs, bool is_flush); 984 985 void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, int ptr); 986 987 void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 988 bool configure_scd); 989 990 bool iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 991 const struct iwl_trans_txq_scd_cfg *cfg, 992 unsigned int queue_wdg_timeout); 993 994 int iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 995 struct iwl_trans_rxq_dma_data *data); 996 997 void iwl_trans_txq_free(struct iwl_trans *trans, int queue); 998 999 int iwl_trans_txq_alloc(struct iwl_trans *trans, u32 flags, u32 sta_mask, 1000 u8 tid, int size, unsigned int wdg_timeout); 1001 1002 void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 1003 int txq_id, bool shared_mode); 1004 1005 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1006 int fifo, int sta_id, int tid, 1007 int frame_limit, u16 ssn, 1008 unsigned int queue_wdg_timeout) 1009 { 1010 struct iwl_trans_txq_scd_cfg cfg = { 1011 .fifo = fifo, 1012 .sta_id = sta_id, 1013 .tid = tid, 1014 .frame_limit = frame_limit, 1015 .aggregate = sta_id >= 0, 1016 }; 1017 1018 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1019 } 1020 1021 static inline 1022 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1023 unsigned int queue_wdg_timeout) 1024 { 1025 struct iwl_trans_txq_scd_cfg cfg = { 1026 .fifo = fifo, 1027 .sta_id = -1, 1028 .tid = IWL_MAX_TID_COUNT, 1029 .frame_limit = IWL_FRAME_LIMIT, 1030 .aggregate = false, 1031 }; 1032 1033 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1034 } 1035 1036 void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1037 unsigned long txqs, bool freeze); 1038 1039 int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs); 1040 1041 int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue); 1042 1043 void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val); 1044 1045 void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val); 1046 1047 u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs); 1048 1049 u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs); 1050 1051 void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val); 1052 1053 int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1054 void *buf, int dwords); 1055 1056 int iwl_trans_read_config32(struct iwl_trans *trans, u32 ofs, 1057 u32 *val); 1058 1059 #ifdef CONFIG_IWLWIFI_DEBUGFS 1060 void iwl_trans_debugfs_cleanup(struct iwl_trans *trans); 1061 #endif 1062 1063 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1064 ({ \ 1065 if (__builtin_constant_p(bufsize)) \ 1066 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1067 iwl_trans_read_mem(trans, addr, buf, \ 1068 (bufsize) / sizeof(u32)); \ 1069 }) 1070 1071 int iwl_trans_write_imr_mem(struct iwl_trans *trans, u32 dst_addr, 1072 u64 src_addr, u32 byte_cnt); 1073 1074 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1075 { 1076 u32 value; 1077 1078 if (iwl_trans_read_mem(trans, addr, &value, 1)) 1079 return 0xa5a5a5a5; 1080 1081 return value; 1082 } 1083 1084 int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1085 const void *buf, int dwords); 1086 1087 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1088 u32 val) 1089 { 1090 return iwl_trans_write_mem(trans, addr, &val, 1); 1091 } 1092 1093 void iwl_trans_set_pmi(struct iwl_trans *trans, bool state); 1094 1095 int iwl_trans_sw_reset(struct iwl_trans *trans); 1096 1097 void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, 1098 u32 mask, u32 value); 1099 1100 bool _iwl_trans_grab_nic_access(struct iwl_trans *trans); 1101 1102 #define iwl_trans_grab_nic_access(trans) \ 1103 __cond_lock(nic_access, \ 1104 likely(_iwl_trans_grab_nic_access(trans))) 1105 1106 void __releases(nic_access) 1107 iwl_trans_release_nic_access(struct iwl_trans *trans); 1108 1109 static inline void iwl_trans_schedule_reset(struct iwl_trans *trans, 1110 enum iwl_fw_error_type type) 1111 { 1112 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1113 return; 1114 /* clear this on device init, not cleared on any unbind/reprobe */ 1115 if (test_and_set_bit(STATUS_TRANS_RESET_IN_PROGRESS, &trans->status)) 1116 return; 1117 1118 trans->restart.mode.type = type; 1119 trans->restart.mode.context = IWL_ERR_CONTEXT_WORKER; 1120 1121 set_bit(STATUS_RESET_PENDING, &trans->status); 1122 1123 /* 1124 * keep track of whether or not this happened while resetting, 1125 * by the timer the worker runs it might have finished 1126 */ 1127 trans->restart.during_reset = test_bit(STATUS_IN_SW_RESET, 1128 &trans->status); 1129 queue_delayed_work(system_unbound_wq, &trans->restart.wk, 0); 1130 } 1131 1132 static inline void iwl_trans_fw_error(struct iwl_trans *trans, 1133 enum iwl_fw_error_type type) 1134 { 1135 if (WARN_ON_ONCE(!trans->op_mode)) 1136 return; 1137 1138 /* prevent double restarts due to the same erroneous FW */ 1139 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1140 trans->state = IWL_TRANS_NO_FW; 1141 iwl_op_mode_nic_error(trans->op_mode, type); 1142 iwl_trans_schedule_reset(trans, type); 1143 } 1144 } 1145 1146 static inline void iwl_trans_opmode_sw_reset(struct iwl_trans *trans, 1147 enum iwl_fw_error_type type) 1148 { 1149 if (WARN_ON_ONCE(!trans->op_mode)) 1150 return; 1151 1152 set_bit(STATUS_IN_SW_RESET, &trans->status); 1153 1154 if (WARN_ON(type == IWL_ERR_TYPE_TOP_RESET_BY_BT)) 1155 return; 1156 1157 if (!trans->op_mode->ops->sw_reset || 1158 !trans->op_mode->ops->sw_reset(trans->op_mode, type)) 1159 clear_bit(STATUS_IN_SW_RESET, &trans->status); 1160 } 1161 1162 static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1163 { 1164 return trans->state == IWL_TRANS_FW_ALIVE; 1165 } 1166 1167 void iwl_trans_sync_nmi(struct iwl_trans *trans); 1168 1169 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 1170 u32 sw_err_bit); 1171 1172 int iwl_trans_load_pnvm(struct iwl_trans *trans, 1173 const struct iwl_pnvm_image *pnvm_data, 1174 const struct iwl_ucode_capabilities *capa); 1175 1176 void iwl_trans_set_pnvm(struct iwl_trans *trans, 1177 const struct iwl_ucode_capabilities *capa); 1178 1179 int iwl_trans_load_reduce_power(struct iwl_trans *trans, 1180 const struct iwl_pnvm_image *payloads, 1181 const struct iwl_ucode_capabilities *capa); 1182 1183 void iwl_trans_set_reduce_power(struct iwl_trans *trans, 1184 const struct iwl_ucode_capabilities *capa); 1185 1186 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1187 { 1188 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1189 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1190 } 1191 1192 void iwl_trans_interrupts(struct iwl_trans *trans, bool enable); 1193 1194 static inline void iwl_trans_finish_sw_reset(struct iwl_trans *trans) 1195 { 1196 clear_bit(STATUS_IN_SW_RESET, &trans->status); 1197 } 1198 1199 /***************************************************** 1200 * transport helper functions 1201 *****************************************************/ 1202 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1203 struct device *dev, 1204 const struct iwl_mac_cfg *mac_cfg, 1205 unsigned int txcmd_size, 1206 unsigned int txcmd_align); 1207 void iwl_trans_free(struct iwl_trans *trans); 1208 1209 static inline bool iwl_trans_is_hw_error_value(u32 val) 1210 { 1211 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50); 1212 } 1213 1214 void iwl_trans_free_restart_list(void); 1215 1216 static inline u16 iwl_trans_get_num_rbds(struct iwl_trans *trans) 1217 { 1218 u16 result = trans->cfg->num_rbds; 1219 1220 /* 1221 * Since AX210 family (So/Ty) the device cannot put mutliple 1222 * frames into the same buffer, so double the value for them. 1223 */ 1224 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1225 return 2 * result; 1226 return result; 1227 } 1228 1229 static inline void iwl_trans_suppress_cmd_error_once(struct iwl_trans *trans) 1230 { 1231 set_bit(STATUS_SUPPRESS_CMD_ERROR_ONCE, &trans->status); 1232 } 1233 1234 static inline bool iwl_trans_device_enabled(struct iwl_trans *trans) 1235 { 1236 return test_bit(STATUS_DEVICE_ENABLED, &trans->status); 1237 } 1238 1239 static inline bool iwl_trans_is_dead(struct iwl_trans *trans) 1240 { 1241 return test_bit(STATUS_TRANS_DEAD, &trans->status); 1242 } 1243 1244 /***************************************************** 1245 * PCIe handling 1246 *****************************************************/ 1247 int __must_check iwl_pci_register_driver(void); 1248 void iwl_pci_unregister_driver(void); 1249 1250 /* Note: order matters */ 1251 enum iwl_reset_mode { 1252 /* upper level modes: */ 1253 IWL_RESET_MODE_SW_RESET, 1254 IWL_RESET_MODE_REPROBE, 1255 /* TOP reset doesn't require PCIe remove */ 1256 IWL_RESET_MODE_TOP_RESET, 1257 /* PCIE level modes: */ 1258 IWL_RESET_MODE_REMOVE_ONLY, 1259 IWL_RESET_MODE_RESCAN, 1260 IWL_RESET_MODE_FUNC_RESET, 1261 IWL_RESET_MODE_PROD_RESET, 1262 1263 /* keep last - special backoff value */ 1264 IWL_RESET_MODE_BACKOFF, 1265 }; 1266 1267 void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode); 1268 void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans); 1269 1270 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, 1271 struct iwl_host_cmd *cmd); 1272 1273 /* Internal helper */ 1274 static inline void iwl_trans_set_info(struct iwl_trans *trans, 1275 struct iwl_trans_info *info) 1276 { 1277 struct iwl_trans_info *write; 1278 1279 write = (void *)(uintptr_t)&trans->info; 1280 *write = *info; 1281 } 1282 1283 static inline u16 iwl_trans_get_device_id(struct iwl_trans *trans) 1284 { 1285 return u32_get_bits(trans->info.hw_id, GENMASK(31, 16)); 1286 } 1287 1288 #endif /* __iwl_trans_h__ */ 1289