1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_trans_h__ 8 #define __iwl_trans_h__ 9 10 #include <linux/ieee80211.h> 11 #include <linux/mm.h> /* for page_address */ 12 #include <linux/lockdep.h> 13 #include <linux/kernel.h> 14 15 #include "iwl-debug.h" 16 #include "iwl-config.h" 17 #include "fw/img.h" 18 #include "iwl-op-mode.h" 19 #include <linux/firmware.h> 20 #include "fw/api/cmdhdr.h" 21 #include "fw/api/txq.h" 22 #include "fw/api/dbg-tlv.h" 23 #include "iwl-dbg-tlv.h" 24 25 /** 26 * DOC: Transport layer - what is it ? 27 * 28 * The transport layer is the layer that deals with the HW directly. It provides 29 * an abstraction of the underlying HW to the upper layer. The transport layer 30 * doesn't provide any policy, algorithm or anything of this kind, but only 31 * mechanisms to make the HW do something. It is not completely stateless but 32 * close to it. 33 * We will have an implementation for each different supported bus. 34 */ 35 36 /** 37 * DOC: Life cycle of the transport layer 38 * 39 * The transport layer has a very precise life cycle. 40 * 41 * 1) A helper function is called during the module initialization and 42 * registers the bus driver's ops with the transport's alloc function. 43 * 2) Bus's probe calls to the transport layer's allocation functions. 44 * Of course this function is bus specific. 45 * 3) This allocation functions will spawn the upper layer which will 46 * register mac80211. 47 * 48 * 4) At some point (i.e. mac80211's start call), the op_mode will call 49 * the following sequence: 50 * start_hw 51 * start_fw 52 * 53 * 5) Then when finished (or reset): 54 * stop_device 55 * 56 * 6) Eventually, the free function will be called. 57 */ 58 59 /* default preset 0 (start from bit 16)*/ 60 #define IWL_FW_DBG_DOMAIN_POS 16 61 #define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS) 62 63 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 64 65 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 66 #define FH_RSCSR_FRAME_INVALID 0x55550000 67 #define FH_RSCSR_FRAME_ALIGN 0x40 68 #define FH_RSCSR_RPA_EN BIT(25) 69 #define FH_RSCSR_RADA_EN BIT(26) 70 #define FH_RSCSR_RXQ_POS 16 71 #define FH_RSCSR_RXQ_MASK 0x3F0000 72 73 struct iwl_rx_packet { 74 /* 75 * The first 4 bytes of the RX frame header contain both the RX frame 76 * size and some flags. 77 * Bit fields: 78 * 31: flag flush RB request 79 * 30: flag ignore TC (terminal counter) request 80 * 29: flag fast IRQ request 81 * 28-27: Reserved 82 * 26: RADA enabled 83 * 25: Offload enabled 84 * 24: RPF enabled 85 * 23: RSS enabled 86 * 22: Checksum enabled 87 * 21-16: RX queue 88 * 15-14: Reserved 89 * 13-00: RX frame size 90 */ 91 __le32 len_n_flags; 92 struct iwl_cmd_header hdr; 93 u8 data[]; 94 } __packed; 95 96 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 97 { 98 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 99 } 100 101 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 102 { 103 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 104 } 105 106 /** 107 * enum CMD_MODE - how to send the host commands ? 108 * 109 * @CMD_ASYNC: Return right away and don't wait for the response 110 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 111 * the response. The caller needs to call iwl_free_resp when done. 112 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill. 113 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 114 * called after this command completes. Valid only with CMD_ASYNC. 115 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to 116 * SUSPEND and RESUME commands. We are in D3 mode when we set 117 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3. 118 */ 119 enum CMD_MODE { 120 CMD_ASYNC = BIT(0), 121 CMD_WANT_SKB = BIT(1), 122 CMD_SEND_IN_RFKILL = BIT(2), 123 CMD_WANT_ASYNC_CALLBACK = BIT(3), 124 CMD_SEND_IN_D3 = BIT(4), 125 }; 126 127 #define DEF_CMD_PAYLOAD_SIZE 320 128 129 /** 130 * struct iwl_device_cmd 131 * 132 * For allocation of the command and tx queues, this establishes the overall 133 * size of the largest command we send to uCode, except for commands that 134 * aren't fully copied and use other TFD space. 135 */ 136 struct iwl_device_cmd { 137 union { 138 struct { 139 struct iwl_cmd_header hdr; /* uCode API */ 140 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 141 }; 142 struct { 143 struct iwl_cmd_header_wide hdr_wide; 144 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 145 sizeof(struct iwl_cmd_header_wide) + 146 sizeof(struct iwl_cmd_header)]; 147 }; 148 }; 149 } __packed; 150 151 /** 152 * struct iwl_device_tx_cmd - buffer for TX command 153 * @hdr: the header 154 * @payload: the payload placeholder 155 * 156 * The actual structure is sized dynamically according to need. 157 */ 158 struct iwl_device_tx_cmd { 159 struct iwl_cmd_header hdr; 160 u8 payload[]; 161 } __packed; 162 163 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 164 165 /* 166 * number of transfer buffers (fragments) per transmit frame descriptor; 167 * this is just the driver's idea, the hardware supports 20 168 */ 169 #define IWL_MAX_CMD_TBS_PER_TFD 2 170 171 /* We need 2 entries for the TX command and header, and another one might 172 * be needed for potential data in the SKB's head. The remaining ones can 173 * be used for frags. 174 */ 175 #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 176 177 /** 178 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 179 * 180 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 181 * ring. The transport layer doesn't map the command's buffer to DMA, but 182 * rather copies it to a previously allocated DMA buffer. This flag tells 183 * the transport layer not to copy the command, but to map the existing 184 * buffer (that is passed in) instead. This saves the memcpy and allows 185 * commands that are bigger than the fixed buffer to be submitted. 186 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 187 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 188 * chunk internally and free it again after the command completes. This 189 * can (currently) be used only once per command. 190 * Note that a TFD entry after a DUP one cannot be a normal copied one. 191 */ 192 enum iwl_hcmd_dataflag { 193 IWL_HCMD_DFL_NOCOPY = BIT(0), 194 IWL_HCMD_DFL_DUP = BIT(1), 195 }; 196 197 enum iwl_error_event_table_status { 198 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 199 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 200 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 201 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3), 202 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4), 203 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5), 204 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6), 205 }; 206 207 /** 208 * struct iwl_host_cmd - Host command to the uCode 209 * 210 * @data: array of chunks that composes the data of the host command 211 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 212 * @_rx_page_order: (internally used to free response packet) 213 * @_rx_page_addr: (internally used to free response packet) 214 * @flags: can be CMD_* 215 * @len: array of the lengths of the chunks in data 216 * @dataflags: IWL_HCMD_DFL_* 217 * @id: command id of the host command, for wide commands encoding the 218 * version and group as well 219 */ 220 struct iwl_host_cmd { 221 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 222 struct iwl_rx_packet *resp_pkt; 223 unsigned long _rx_page_addr; 224 u32 _rx_page_order; 225 226 u32 flags; 227 u32 id; 228 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 229 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 230 }; 231 232 static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 233 { 234 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 235 } 236 237 struct iwl_rx_cmd_buffer { 238 struct page *_page; 239 int _offset; 240 bool _page_stolen; 241 u32 _rx_page_order; 242 unsigned int truesize; 243 }; 244 245 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 246 { 247 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 248 } 249 250 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 251 { 252 return r->_offset; 253 } 254 255 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 256 { 257 r->_page_stolen = true; 258 get_page(r->_page); 259 return r->_page; 260 } 261 262 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 263 { 264 __free_pages(r->_page, r->_rx_page_order); 265 } 266 267 #define MAX_NO_RECLAIM_CMDS 6 268 269 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 270 271 /* 272 * Maximum number of HW queues the transport layer 273 * currently supports 274 */ 275 #define IWL_MAX_HW_QUEUES 32 276 #define IWL_MAX_TVQM_QUEUES 512 277 278 #define IWL_MAX_TID_COUNT 8 279 #define IWL_MGMT_TID 15 280 #define IWL_FRAME_LIMIT 64 281 #define IWL_MAX_RX_HW_QUEUES 16 282 #define IWL_9000_MAX_RX_HW_QUEUES 1 283 284 /** 285 * enum iwl_wowlan_status - WoWLAN image/device status 286 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 287 * @IWL_D3_STATUS_RESET: device was reset while suspended 288 */ 289 enum iwl_d3_status { 290 IWL_D3_STATUS_ALIVE, 291 IWL_D3_STATUS_RESET, 292 }; 293 294 /** 295 * enum iwl_trans_status: transport status flags 296 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 297 * @STATUS_DEVICE_ENABLED: APM is enabled 298 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 299 * @STATUS_INT_ENABLED: interrupts are enabled 300 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 301 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 302 * @STATUS_FW_ERROR: the fw is in error state 303 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 304 * are sent 305 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 306 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 307 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once, 308 * e.g. for testing 309 */ 310 enum iwl_trans_status { 311 STATUS_SYNC_HCMD_ACTIVE, 312 STATUS_DEVICE_ENABLED, 313 STATUS_TPOWER_PMI, 314 STATUS_INT_ENABLED, 315 STATUS_RFKILL_HW, 316 STATUS_RFKILL_OPMODE, 317 STATUS_FW_ERROR, 318 STATUS_TRANS_GOING_IDLE, 319 STATUS_TRANS_IDLE, 320 STATUS_TRANS_DEAD, 321 STATUS_SUPPRESS_CMD_ERROR_ONCE, 322 }; 323 324 static inline int 325 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 326 { 327 switch (rb_size) { 328 case IWL_AMSDU_2K: 329 return get_order(2 * 1024); 330 case IWL_AMSDU_4K: 331 return get_order(4 * 1024); 332 case IWL_AMSDU_8K: 333 return get_order(8 * 1024); 334 case IWL_AMSDU_12K: 335 return get_order(16 * 1024); 336 default: 337 WARN_ON(1); 338 return -1; 339 } 340 } 341 342 static inline int 343 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 344 { 345 switch (rb_size) { 346 case IWL_AMSDU_2K: 347 return 2 * 1024; 348 case IWL_AMSDU_4K: 349 return 4 * 1024; 350 case IWL_AMSDU_8K: 351 return 8 * 1024; 352 case IWL_AMSDU_12K: 353 return 16 * 1024; 354 default: 355 WARN_ON(1); 356 return 0; 357 } 358 } 359 360 struct iwl_hcmd_names { 361 u8 cmd_id; 362 const char *const cmd_name; 363 }; 364 365 #define HCMD_NAME(x) \ 366 { .cmd_id = x, .cmd_name = #x } 367 368 struct iwl_hcmd_arr { 369 const struct iwl_hcmd_names *arr; 370 int size; 371 }; 372 373 #define HCMD_ARR(x) \ 374 { .arr = x, .size = ARRAY_SIZE(x) } 375 376 /** 377 * struct iwl_dump_sanitize_ops - dump sanitization operations 378 * @frob_txf: Scrub the TX FIFO data 379 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header 380 * but that might be short or long (&struct iwl_cmd_header or 381 * &struct iwl_cmd_header_wide) 382 * @frob_mem: Scrub memory data 383 */ 384 struct iwl_dump_sanitize_ops { 385 void (*frob_txf)(void *ctx, void *buf, size_t buflen); 386 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen); 387 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen); 388 }; 389 390 /** 391 * struct iwl_trans_config - transport configuration 392 * 393 * @op_mode: pointer to the upper layer. 394 * @cmd_queue: the index of the command queue. 395 * Must be set before start_fw. 396 * @cmd_fifo: the fifo for host commands 397 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 398 * @no_reclaim_cmds: Some devices erroneously don't set the 399 * SEQ_RX_FRAME bit on some notifications, this is the 400 * list of such notifications to filter. Max length is 401 * %MAX_NO_RECLAIM_CMDS. 402 * @n_no_reclaim_cmds: # of commands in list 403 * @rx_buf_size: RX buffer size needed for A-MSDUs 404 * if unset 4k will be the RX buffer size 405 * @bc_table_dword: set to true if the BC table expects the byte count to be 406 * in DWORD (as opposed to bytes) 407 * @scd_set_active: should the transport configure the SCD for HCMD queue 408 * @command_groups: array of command groups, each member is an array of the 409 * commands in the group; for debugging only 410 * @command_groups_size: number of command groups, to avoid illegal access 411 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 412 * space for at least two pointers 413 * @fw_reset_handshake: firmware supports reset flow handshake 414 * @queue_alloc_cmd_ver: queue allocation command version, set to 0 415 * for using the older SCD_QUEUE_CFG, set to the version of 416 * SCD_QUEUE_CONFIG_CMD otherwise. 417 */ 418 struct iwl_trans_config { 419 struct iwl_op_mode *op_mode; 420 421 u8 cmd_queue; 422 u8 cmd_fifo; 423 unsigned int cmd_q_wdg_timeout; 424 const u8 *no_reclaim_cmds; 425 unsigned int n_no_reclaim_cmds; 426 427 enum iwl_amsdu_size rx_buf_size; 428 bool bc_table_dword; 429 bool scd_set_active; 430 const struct iwl_hcmd_arr *command_groups; 431 int command_groups_size; 432 433 u8 cb_data_offs; 434 bool fw_reset_handshake; 435 u8 queue_alloc_cmd_ver; 436 }; 437 438 struct iwl_trans_dump_data { 439 u32 len; 440 u8 data[]; 441 }; 442 443 struct iwl_trans; 444 445 struct iwl_trans_txq_scd_cfg { 446 u8 fifo; 447 u8 sta_id; 448 u8 tid; 449 bool aggregate; 450 int frame_limit; 451 }; 452 453 /** 454 * struct iwl_trans_rxq_dma_data - RX queue DMA data 455 * @fr_bd_cb: DMA address of free BD cyclic buffer 456 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 457 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 458 * @ur_bd_cb: DMA address of used BD cyclic buffer 459 */ 460 struct iwl_trans_rxq_dma_data { 461 u64 fr_bd_cb; 462 u32 fr_bd_wid; 463 u64 urbd_stts_wrptr; 464 u64 ur_bd_cb; 465 }; 466 467 /* maximal number of DRAM MAP entries supported by FW */ 468 #define IPC_DRAM_MAP_ENTRY_NUM_MAX 64 469 470 /** 471 * struct iwl_pnvm_image - contains info about the parsed pnvm image 472 * @chunks: array of pointers to pnvm payloads and their sizes 473 * @n_chunks: the number of the pnvm payloads. 474 * @version: the version of the loaded PNVM image 475 */ 476 struct iwl_pnvm_image { 477 struct { 478 const void *data; 479 u32 len; 480 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 481 u32 n_chunks; 482 u32 version; 483 }; 484 485 /** 486 * struct iwl_trans_ops - transport specific operations 487 * 488 * All the handlers MUST be implemented 489 * 490 * @start_hw: starts the HW. From that point on, the HW can send interrupts. 491 * May sleep. 492 * @op_mode_leave: Turn off the HW RF kill indication if on 493 * May sleep 494 * @start_fw: allocates and inits all the resources for the transport 495 * layer. Also kick a fw image. 496 * May sleep 497 * @fw_alive: called when the fw sends alive notification. If the fw provides 498 * the SCD base address in SRAM, then provide it here, or 0 otherwise. 499 * May sleep 500 * @stop_device: stops the whole device (embedded CPU put to reset) and stops 501 * the HW. From that point on, the HW will be stopped but will still issue 502 * an interrupt if the HW RF kill switch is triggered. 503 * This callback must do the right thing and not crash even if %start_hw() 504 * was called but not &start_fw(). May sleep. 505 * @d3_suspend: put the device into the correct mode for WoWLAN during 506 * suspend. This is optional, if not implemented WoWLAN will not be 507 * supported. This callback may sleep. 508 * @d3_resume: resume the device after WoWLAN, enabling the opmode to 509 * talk to the WoWLAN image to get its status. This is optional, if not 510 * implemented WoWLAN will not be supported. This callback may sleep. 511 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 512 * If RFkill is asserted in the middle of a SYNC host command, it must 513 * return -ERFKILL straight away. 514 * May sleep only if CMD_ASYNC is not set 515 * @tx: send an skb. The transport relies on the op_mode to zero the 516 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 517 * the CSUM will be taken care of (TCP CSUM and IP header in case of 518 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 519 * header if it is IPv4. 520 * Must be atomic 521 * @reclaim: free packet until ssn. Returns a list of freed packets. 522 * Must be atomic 523 * @txq_enable: setup a queue. To setup an AC queue, use the 524 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 525 * this one. The op_mode must not configure the HCMD queue. The scheduler 526 * configuration may be %NULL, in which case the hardware will not be 527 * configured. If true is returned, the operation mode needs to increment 528 * the sequence number of the packets routed to this queue because of a 529 * hardware scheduler bug. May sleep. 530 * @txq_disable: de-configure a Tx queue to send AMPDUs 531 * Must be atomic 532 * @txq_set_shared_mode: change Tx queue shared/unshared marking 533 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 534 * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 535 * @freeze_txq_timer: prevents the timer of the queue from firing until the 536 * queue is set to awake. Must be atomic. 537 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 538 * that the transport needs to refcount the calls since this function 539 * will be called several times with block = true, and then the queues 540 * need to be unblocked only after the same number of calls with 541 * block = false. 542 * @write8: write a u8 to a register at offset ofs from the BAR 543 * @write32: write a u32 to a register at offset ofs from the BAR 544 * @read32: read a u32 register at offset ofs from the BAR 545 * @read_prph: read a DWORD from a periphery register 546 * @write_prph: write a DWORD to a periphery register 547 * @read_mem: read device's SRAM in DWORD 548 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 549 * will be zeroed. 550 * @read_config32: read a u32 value from the device's config space at 551 * the given offset. 552 * @configure: configure parameters required by the transport layer from 553 * the op_mode. May be called several times before start_fw, can't be 554 * called after that. 555 * @set_pmi: set the power pmi state 556 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 557 * Sleeping is not allowed between grab_nic_access and 558 * release_nic_access. 559 * @release_nic_access: let the NIC go to sleep. The "flags" parameter 560 * must be the same one that was sent before to the grab_nic_access. 561 * @set_bits_mask - set SRAM register according to value and mask. 562 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 563 * TX'ed commands and similar. The buffer will be vfree'd by the caller. 564 * Note that the transport must fill in the proper file headers. 565 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 566 * of the trans debugfs 567 * @load_pnvm: save the pnvm data in DRAM 568 * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the 569 * context info. 570 * @load_reduce_power: copy reduce power table to the corresponding DRAM memory 571 * @set_reduce_power: set reduce power table addresses in the sratch buffer 572 * @interrupts: disable/enable interrupts to transport 573 */ 574 struct iwl_trans_ops { 575 576 int (*start_hw)(struct iwl_trans *iwl_trans); 577 void (*op_mode_leave)(struct iwl_trans *iwl_trans); 578 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 579 bool run_in_rfkill); 580 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 581 void (*stop_device)(struct iwl_trans *trans); 582 583 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 584 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 585 bool test, bool reset); 586 587 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 588 589 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 590 struct iwl_device_tx_cmd *dev_cmd, int queue); 591 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 592 struct sk_buff_head *skbs, bool is_flush); 593 594 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 595 596 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 597 const struct iwl_trans_txq_scd_cfg *cfg, 598 unsigned int queue_wdg_timeout); 599 void (*txq_disable)(struct iwl_trans *trans, int queue, 600 bool configure_scd); 601 /* 22000 functions */ 602 int (*txq_alloc)(struct iwl_trans *trans, u32 flags, 603 u32 sta_mask, u8 tid, 604 int size, unsigned int queue_wdg_timeout); 605 void (*txq_free)(struct iwl_trans *trans, int queue); 606 int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 607 struct iwl_trans_rxq_dma_data *data); 608 609 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 610 bool shared); 611 612 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 613 int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 614 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 615 bool freeze); 616 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 617 618 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 619 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 620 u32 (*read32)(struct iwl_trans *trans, u32 ofs); 621 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 622 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 623 int (*read_mem)(struct iwl_trans *trans, u32 addr, 624 void *buf, int dwords); 625 int (*write_mem)(struct iwl_trans *trans, u32 addr, 626 const void *buf, int dwords); 627 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 628 void (*configure)(struct iwl_trans *trans, 629 const struct iwl_trans_config *trans_cfg); 630 void (*set_pmi)(struct iwl_trans *trans, bool state); 631 int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership); 632 bool (*grab_nic_access)(struct iwl_trans *trans); 633 void (*release_nic_access)(struct iwl_trans *trans); 634 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 635 u32 value); 636 637 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 638 u32 dump_mask, 639 const struct iwl_dump_sanitize_ops *sanitize_ops, 640 void *sanitize_ctx); 641 void (*debugfs_cleanup)(struct iwl_trans *trans); 642 void (*sync_nmi)(struct iwl_trans *trans); 643 int (*load_pnvm)(struct iwl_trans *trans, 644 const struct iwl_pnvm_image *pnvm_payloads, 645 const struct iwl_ucode_capabilities *capa); 646 void (*set_pnvm)(struct iwl_trans *trans, 647 const struct iwl_ucode_capabilities *capa); 648 int (*load_reduce_power)(struct iwl_trans *trans, 649 const struct iwl_pnvm_image *payloads, 650 const struct iwl_ucode_capabilities *capa); 651 void (*set_reduce_power)(struct iwl_trans *trans, 652 const struct iwl_ucode_capabilities *capa); 653 654 void (*interrupts)(struct iwl_trans *trans, bool enable); 655 int (*imr_dma_data)(struct iwl_trans *trans, 656 u32 dst_addr, u64 src_addr, 657 u32 byte_cnt); 658 659 }; 660 661 /** 662 * enum iwl_trans_state - state of the transport layer 663 * 664 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 665 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 666 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 667 */ 668 enum iwl_trans_state { 669 IWL_TRANS_NO_FW, 670 IWL_TRANS_FW_STARTED, 671 IWL_TRANS_FW_ALIVE, 672 }; 673 674 /** 675 * DOC: Platform power management 676 * 677 * In system-wide power management the entire platform goes into a low 678 * power state (e.g. idle or suspend to RAM) at the same time and the 679 * device is configured as a wakeup source for the entire platform. 680 * This is usually triggered by userspace activity (e.g. the user 681 * presses the suspend button or a power management daemon decides to 682 * put the platform in low power mode). The device's behavior in this 683 * mode is dictated by the wake-on-WLAN configuration. 684 * 685 * The terms used for the device's behavior are as follows: 686 * 687 * - D0: the device is fully powered and the host is awake; 688 * - D3: the device is in low power mode and only reacts to 689 * specific events (e.g. magic-packet received or scan 690 * results found); 691 * 692 * These terms reflect the power modes in the firmware and are not to 693 * be confused with the physical device power state. 694 */ 695 696 /** 697 * enum iwl_plat_pm_mode - platform power management mode 698 * 699 * This enumeration describes the device's platform power management 700 * behavior when in system-wide suspend (i.e WoWLAN). 701 * 702 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 703 * device. In system-wide suspend mode, it means that the all 704 * connections will be closed automatically by mac80211 before 705 * the platform is suspended. 706 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 707 */ 708 enum iwl_plat_pm_mode { 709 IWL_PLAT_PM_MODE_DISABLED, 710 IWL_PLAT_PM_MODE_D3, 711 }; 712 713 /** 714 * enum iwl_ini_cfg_state 715 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 716 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 717 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 718 * are corrupted. The rest of the debug TLVs will still be used 719 */ 720 enum iwl_ini_cfg_state { 721 IWL_INI_CFG_STATE_NOT_LOADED, 722 IWL_INI_CFG_STATE_LOADED, 723 IWL_INI_CFG_STATE_CORRUPTED, 724 }; 725 726 /* Max time to wait for nmi interrupt */ 727 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 728 729 /** 730 * struct iwl_dram_data 731 * @physical: page phy pointer 732 * @block: pointer to the allocated block/page 733 * @size: size of the block/page 734 */ 735 struct iwl_dram_data { 736 dma_addr_t physical; 737 void *block; 738 int size; 739 }; 740 741 /** 742 * struct iwl_dram_regions - DRAM regions container structure 743 * @drams: array of several DRAM areas that contains the pnvm and power 744 * reduction table payloads. 745 * @n_regions: number of DRAM regions that were allocated 746 * @prph_scratch_mem_desc: points to a structure allocated in dram, 747 * designed to show FW where all the payloads are. 748 */ 749 struct iwl_dram_regions { 750 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 751 struct iwl_dram_data prph_scratch_mem_desc; 752 u8 n_regions; 753 }; 754 755 /** 756 * struct iwl_fw_mon - fw monitor per allocation id 757 * @num_frags: number of fragments 758 * @frags: an array of DRAM buffer fragments 759 */ 760 struct iwl_fw_mon { 761 u32 num_frags; 762 struct iwl_dram_data *frags; 763 }; 764 765 /** 766 * struct iwl_self_init_dram - dram data used by self init process 767 * @fw: lmac and umac dram data 768 * @fw_cnt: total number of items in array 769 * @paging: paging dram data 770 * @paging_cnt: total number of items in array 771 */ 772 struct iwl_self_init_dram { 773 struct iwl_dram_data *fw; 774 int fw_cnt; 775 struct iwl_dram_data *paging; 776 int paging_cnt; 777 }; 778 779 /** 780 * struct iwl_imr_data - imr dram data used during debug process 781 * @imr_enable: imr enable status received from fw 782 * @imr_size: imr dram size received from fw 783 * @sram_addr: sram address from debug tlv 784 * @sram_size: sram size from debug tlv 785 * @imr2sram_remainbyte`: size remained after each dma transfer 786 * @imr_curr_addr: current dst address used during dma transfer 787 * @imr_base_addr: imr address received from fw 788 */ 789 struct iwl_imr_data { 790 u32 imr_enable; 791 u32 imr_size; 792 u32 sram_addr; 793 u32 sram_size; 794 u32 imr2sram_remainbyte; 795 u64 imr_curr_addr; 796 __le64 imr_base_addr; 797 }; 798 799 #define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32 800 801 /** 802 * struct iwl_pc_data - program counter details 803 * @pc_name: cpu name 804 * @pc_address: cpu program counter 805 */ 806 struct iwl_pc_data { 807 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES]; 808 u32 pc_address; 809 }; 810 811 /** 812 * struct iwl_trans_debug - transport debug related data 813 * 814 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 815 * @rec_on: true iff there is a fw debug recording currently active 816 * @dest_tlv: points to the destination TLV for debug 817 * @conf_tlv: array of pointers to configuration TLVs for debug 818 * @trigger_tlv: array of pointers to triggers TLVs for debug 819 * @lmac_error_event_table: addrs of lmacs error tables 820 * @umac_error_event_table: addr of umac error table 821 * @tcm_error_event_table: address(es) of TCM error table(s) 822 * @rcm_error_event_table: address(es) of RCM error table(s) 823 * @error_event_table_tlv_status: bitmap that indicates what error table 824 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 825 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 826 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 827 * @fw_mon_cfg: debug buffer allocation configuration 828 * @fw_mon_ini: DRAM buffer fragments per allocation id 829 * @fw_mon: DRAM buffer for firmware monitor 830 * @hw_error: equals true if hw error interrupt was received from the FW 831 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 832 * @active_regions: active regions 833 * @debug_info_tlv_list: list of debug info TLVs 834 * @time_point: array of debug time points 835 * @periodic_trig_list: periodic triggers list 836 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON 837 * @ucode_preset: preset based on ucode 838 * @dump_file_name_ext: dump file name extension 839 * @dump_file_name_ext_valid: dump file name extension if valid or not 840 * @num_pc: number of program counter for cpu 841 * @pc_data: details of the program counter 842 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded 843 */ 844 struct iwl_trans_debug { 845 u8 n_dest_reg; 846 bool rec_on; 847 848 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 849 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 850 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 851 852 u32 lmac_error_event_table[2]; 853 u32 umac_error_event_table; 854 u32 tcm_error_event_table[2]; 855 u32 rcm_error_event_table[2]; 856 unsigned int error_event_table_tlv_status; 857 858 enum iwl_ini_cfg_state internal_ini_cfg; 859 enum iwl_ini_cfg_state external_ini_cfg; 860 861 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 862 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 863 864 struct iwl_dram_data fw_mon; 865 866 bool hw_error; 867 enum iwl_fw_ini_buffer_location ini_dest; 868 869 u64 unsupported_region_msk; 870 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 871 struct list_head debug_info_tlv_list; 872 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM]; 873 struct list_head periodic_trig_list; 874 875 u32 domains_bitmap; 876 u32 ucode_preset; 877 bool restart_required; 878 u32 last_tp_resetfw; 879 struct iwl_imr_data imr_data; 880 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME]; 881 bool dump_file_name_ext_valid; 882 u32 num_pc; 883 struct iwl_pc_data *pc_data; 884 bool yoyo_bin_loaded; 885 }; 886 887 struct iwl_dma_ptr { 888 dma_addr_t dma; 889 void *addr; 890 size_t size; 891 }; 892 893 struct iwl_cmd_meta { 894 /* only for SYNC commands, iff the reply skb is wanted */ 895 struct iwl_host_cmd *source; 896 u32 flags; 897 u32 tbs; 898 }; 899 900 /* 901 * The FH will write back to the first TB only, so we need to copy some data 902 * into the buffer regardless of whether it should be mapped or not. 903 * This indicates how big the first TB must be to include the scratch buffer 904 * and the assigned PN. 905 * Since PN location is 8 bytes at offset 12, it's 20 now. 906 * If we make it bigger then allocations will be bigger and copy slower, so 907 * that's probably not useful. 908 */ 909 #define IWL_FIRST_TB_SIZE 20 910 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 911 912 struct iwl_pcie_txq_entry { 913 void *cmd; 914 struct sk_buff *skb; 915 /* buffer to free after command completes */ 916 const void *free_buf; 917 struct iwl_cmd_meta meta; 918 }; 919 920 struct iwl_pcie_first_tb_buf { 921 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 922 }; 923 924 /** 925 * struct iwl_txq - Tx Queue for DMA 926 * @tfds: transmit frame descriptors (DMA memory) 927 * @first_tb_bufs: start of command headers, including scratch buffers, for 928 * the writeback -- this is DMA memory and an array holding one buffer 929 * for each command on the queue 930 * @first_tb_dma: DMA address for the first_tb_bufs start 931 * @entries: transmit entries (driver state) 932 * @lock: queue lock 933 * @stuck_timer: timer that fires if queue gets stuck 934 * @trans: pointer back to transport (for timer) 935 * @need_update: indicates need to update read/write index 936 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 937 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 938 * @frozen: tx stuck queue timer is frozen 939 * @frozen_expiry_remainder: remember how long until the timer fires 940 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 941 * @write_ptr: 1-st empty entry (index) host_w 942 * @read_ptr: last used entry (index) host_r 943 * @dma_addr: physical addr for BD's 944 * @n_window: safe queue window 945 * @id: queue id 946 * @low_mark: low watermark, resume queue if free space more than this 947 * @high_mark: high watermark, stop queue if free space less than this 948 * 949 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 950 * descriptors) and required locking structures. 951 * 952 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 953 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 954 * there might be HW changes in the future). For the normal TX 955 * queues, n_window, which is the size of the software queue data 956 * is also 256; however, for the command queue, n_window is only 957 * 32 since we don't need so many commands pending. Since the HW 958 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 959 * This means that we end up with the following: 960 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 961 * SW entries: | 0 | ... | 31 | 962 * where N is a number between 0 and 7. This means that the SW 963 * data is a window overlayed over the HW queue. 964 */ 965 struct iwl_txq { 966 void *tfds; 967 struct iwl_pcie_first_tb_buf *first_tb_bufs; 968 dma_addr_t first_tb_dma; 969 struct iwl_pcie_txq_entry *entries; 970 /* lock for syncing changes on the queue */ 971 spinlock_t lock; 972 unsigned long frozen_expiry_remainder; 973 struct timer_list stuck_timer; 974 struct iwl_trans *trans; 975 bool need_update; 976 bool frozen; 977 bool ampdu; 978 int block; 979 unsigned long wd_timeout; 980 struct sk_buff_head overflow_q; 981 struct iwl_dma_ptr bc_tbl; 982 983 int write_ptr; 984 int read_ptr; 985 dma_addr_t dma_addr; 986 int n_window; 987 u32 id; 988 int low_mark; 989 int high_mark; 990 991 bool overflow_tx; 992 }; 993 994 /** 995 * struct iwl_trans_txqs - transport tx queues data 996 * 997 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 998 * @page_offs: offset from skb->cb to mac header page pointer 999 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 1000 * @queue_used - bit mask of used queues 1001 * @queue_stopped - bit mask of stopped queues 1002 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 1003 * @queue_alloc_cmd_ver: queue allocation command version 1004 */ 1005 struct iwl_trans_txqs { 1006 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 1007 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 1008 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 1009 struct dma_pool *bc_pool; 1010 size_t bc_tbl_size; 1011 bool bc_table_dword; 1012 u8 page_offs; 1013 u8 dev_cmd_offs; 1014 struct iwl_tso_hdr_page __percpu *tso_hdr_page; 1015 1016 struct { 1017 u8 fifo; 1018 u8 q_id; 1019 unsigned int wdg_timeout; 1020 } cmd; 1021 1022 struct { 1023 u8 max_tbs; 1024 u16 size; 1025 u8 addr_size; 1026 } tfd; 1027 1028 struct iwl_dma_ptr scd_bc_tbls; 1029 1030 u8 queue_alloc_cmd_ver; 1031 }; 1032 1033 /** 1034 * struct iwl_trans - transport common data 1035 * 1036 * @csme_own - true if we couldn't get ownership on the device 1037 * @ops - pointer to iwl_trans_ops 1038 * @op_mode - pointer to the op_mode 1039 * @trans_cfg: the trans-specific configuration part 1040 * @cfg - pointer to the configuration 1041 * @drv - pointer to iwl_drv 1042 * @status: a bit-mask of transport status flags 1043 * @dev - pointer to struct device * that represents the device 1044 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 1045 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 1046 * @hw_rf_id a u32 with the device RF ID 1047 * @hw_crf_id a u32 with the device CRF ID 1048 * @hw_wfpm_id a u32 with the device wfpm ID 1049 * @hw_id: a u32 with the ID of the device / sub-device. 1050 * Set during transport allocation. 1051 * @hw_id_str: a string with info about HW ID. Set during transport allocation. 1052 * @hw_rev_step: The mac step of the HW 1053 * @pm_support: set to true in start_hw if link pm is supported 1054 * @ltr_enabled: set to true if the LTR is enabled 1055 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed 1056 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed 1057 * @wide_cmd_header: true when ucode supports wide command header format 1058 * @wait_command_queue: wait queue for sync commands 1059 * @num_rx_queues: number of RX queues allocated by the transport; 1060 * the transport must set this before calling iwl_drv_start() 1061 * @iml_len: the length of the image loader 1062 * @iml: a pointer to the image loader itself 1063 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 1064 * The user should use iwl_trans_{alloc,free}_tx_cmd. 1065 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 1066 * starting the firmware, used for tracing 1067 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 1068 * start of the 802.11 header in the @rx_mpdu_cmd 1069 * @system_pm_mode: the system-wide power management mode in use. 1070 * This mode is set dynamically, depending on the WoWLAN values 1071 * configured from the userspace at runtime. 1072 * @txqs: transport tx queues data. 1073 * @mbx_addr_0_step: step address data 0 1074 * @mbx_addr_1_step: step address data 1 1075 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*), 1076 * only valid for discrete (not integrated) NICs 1077 * @invalid_tx_cmd: invalid TX command buffer 1078 */ 1079 struct iwl_trans { 1080 bool csme_own; 1081 const struct iwl_trans_ops *ops; 1082 struct iwl_op_mode *op_mode; 1083 const struct iwl_cfg_trans_params *trans_cfg; 1084 const struct iwl_cfg *cfg; 1085 struct iwl_drv *drv; 1086 enum iwl_trans_state state; 1087 unsigned long status; 1088 1089 struct device *dev; 1090 u32 max_skb_frags; 1091 u32 hw_rev; 1092 u32 hw_rev_step; 1093 u32 hw_rf_id; 1094 u32 hw_crf_id; 1095 u32 hw_cnv_id; 1096 u32 hw_wfpm_id; 1097 u32 hw_id; 1098 char hw_id_str[52]; 1099 u32 sku_id[3]; 1100 1101 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 1102 1103 bool pm_support; 1104 bool ltr_enabled; 1105 u8 pnvm_loaded:1; 1106 u8 fail_to_parse_pnvm_image:1; 1107 u8 reduce_power_loaded:1; 1108 u8 failed_to_load_reduce_power_image:1; 1109 1110 const struct iwl_hcmd_arr *command_groups; 1111 int command_groups_size; 1112 bool wide_cmd_header; 1113 1114 wait_queue_head_t wait_command_queue; 1115 u8 num_rx_queues; 1116 1117 size_t iml_len; 1118 u8 *iml; 1119 1120 /* The following fields are internal only */ 1121 struct kmem_cache *dev_cmd_pool; 1122 char dev_cmd_pool_name[50]; 1123 1124 struct dentry *dbgfs_dir; 1125 1126 #ifdef CONFIG_LOCKDEP 1127 struct lockdep_map sync_cmd_lockdep_map; 1128 #endif 1129 1130 struct iwl_trans_debug dbg; 1131 struct iwl_self_init_dram init_dram; 1132 1133 enum iwl_plat_pm_mode system_pm_mode; 1134 1135 const char *name; 1136 struct iwl_trans_txqs txqs; 1137 u32 mbx_addr_0_step; 1138 u32 mbx_addr_1_step; 1139 1140 u8 pcie_link_speed; 1141 1142 struct iwl_dma_ptr invalid_tx_cmd; 1143 1144 /* pointer to trans specific struct */ 1145 /*Ensure that this pointer will always be aligned to sizeof pointer */ 1146 char trans_specific[] __aligned(sizeof(void *)); 1147 }; 1148 1149 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 1150 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 1151 1152 static inline void iwl_trans_configure(struct iwl_trans *trans, 1153 const struct iwl_trans_config *trans_cfg) 1154 { 1155 trans->op_mode = trans_cfg->op_mode; 1156 1157 trans->ops->configure(trans, trans_cfg); 1158 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1159 } 1160 1161 static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1162 { 1163 might_sleep(); 1164 1165 return trans->ops->start_hw(trans); 1166 } 1167 1168 static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1169 { 1170 might_sleep(); 1171 1172 if (trans->ops->op_mode_leave) 1173 trans->ops->op_mode_leave(trans); 1174 1175 trans->op_mode = NULL; 1176 1177 trans->state = IWL_TRANS_NO_FW; 1178 } 1179 1180 static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1181 { 1182 might_sleep(); 1183 1184 trans->state = IWL_TRANS_FW_ALIVE; 1185 1186 trans->ops->fw_alive(trans, scd_addr); 1187 } 1188 1189 static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1190 const struct fw_img *fw, 1191 bool run_in_rfkill) 1192 { 1193 int ret; 1194 1195 might_sleep(); 1196 1197 WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1198 1199 clear_bit(STATUS_FW_ERROR, &trans->status); 1200 ret = trans->ops->start_fw(trans, fw, run_in_rfkill); 1201 if (ret == 0) 1202 trans->state = IWL_TRANS_FW_STARTED; 1203 1204 return ret; 1205 } 1206 1207 static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1208 { 1209 might_sleep(); 1210 1211 trans->ops->stop_device(trans); 1212 1213 trans->state = IWL_TRANS_NO_FW; 1214 } 1215 1216 static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 1217 bool reset) 1218 { 1219 might_sleep(); 1220 if (!trans->ops->d3_suspend) 1221 return -EOPNOTSUPP; 1222 1223 return trans->ops->d3_suspend(trans, test, reset); 1224 } 1225 1226 static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1227 enum iwl_d3_status *status, 1228 bool test, bool reset) 1229 { 1230 might_sleep(); 1231 if (!trans->ops->d3_resume) 1232 return -EOPNOTSUPP; 1233 1234 return trans->ops->d3_resume(trans, status, test, reset); 1235 } 1236 1237 static inline struct iwl_trans_dump_data * 1238 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask, 1239 const struct iwl_dump_sanitize_ops *sanitize_ops, 1240 void *sanitize_ctx) 1241 { 1242 if (!trans->ops->dump_data) 1243 return NULL; 1244 return trans->ops->dump_data(trans, dump_mask, 1245 sanitize_ops, sanitize_ctx); 1246 } 1247 1248 static inline struct iwl_device_tx_cmd * 1249 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1250 { 1251 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1252 } 1253 1254 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 1255 1256 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1257 struct iwl_device_tx_cmd *dev_cmd) 1258 { 1259 kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1260 } 1261 1262 static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1263 struct iwl_device_tx_cmd *dev_cmd, int queue) 1264 { 1265 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1266 return -EIO; 1267 1268 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1269 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1270 return -EIO; 1271 } 1272 1273 return trans->ops->tx(trans, skb, dev_cmd, queue); 1274 } 1275 1276 static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1277 int ssn, struct sk_buff_head *skbs, 1278 bool is_flush) 1279 { 1280 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1281 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1282 return; 1283 } 1284 1285 trans->ops->reclaim(trans, queue, ssn, skbs, is_flush); 1286 } 1287 1288 static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1289 int ptr) 1290 { 1291 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1292 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1293 return; 1294 } 1295 1296 trans->ops->set_q_ptrs(trans, queue, ptr); 1297 } 1298 1299 static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1300 bool configure_scd) 1301 { 1302 trans->ops->txq_disable(trans, queue, configure_scd); 1303 } 1304 1305 static inline bool 1306 iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1307 const struct iwl_trans_txq_scd_cfg *cfg, 1308 unsigned int queue_wdg_timeout) 1309 { 1310 might_sleep(); 1311 1312 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1313 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1314 return false; 1315 } 1316 1317 return trans->ops->txq_enable(trans, queue, ssn, 1318 cfg, queue_wdg_timeout); 1319 } 1320 1321 static inline int 1322 iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 1323 struct iwl_trans_rxq_dma_data *data) 1324 { 1325 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 1326 return -ENOTSUPP; 1327 1328 return trans->ops->rxq_dma_data(trans, queue, data); 1329 } 1330 1331 static inline void 1332 iwl_trans_txq_free(struct iwl_trans *trans, int queue) 1333 { 1334 if (WARN_ON_ONCE(!trans->ops->txq_free)) 1335 return; 1336 1337 trans->ops->txq_free(trans, queue); 1338 } 1339 1340 static inline int 1341 iwl_trans_txq_alloc(struct iwl_trans *trans, 1342 u32 flags, u32 sta_mask, u8 tid, 1343 int size, unsigned int wdg_timeout) 1344 { 1345 might_sleep(); 1346 1347 if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 1348 return -ENOTSUPP; 1349 1350 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1351 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1352 return -EIO; 1353 } 1354 1355 return trans->ops->txq_alloc(trans, flags, sta_mask, tid, 1356 size, wdg_timeout); 1357 } 1358 1359 static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 1360 int queue, bool shared_mode) 1361 { 1362 if (trans->ops->txq_set_shared_mode) 1363 trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 1364 } 1365 1366 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1367 int fifo, int sta_id, int tid, 1368 int frame_limit, u16 ssn, 1369 unsigned int queue_wdg_timeout) 1370 { 1371 struct iwl_trans_txq_scd_cfg cfg = { 1372 .fifo = fifo, 1373 .sta_id = sta_id, 1374 .tid = tid, 1375 .frame_limit = frame_limit, 1376 .aggregate = sta_id >= 0, 1377 }; 1378 1379 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1380 } 1381 1382 static inline 1383 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1384 unsigned int queue_wdg_timeout) 1385 { 1386 struct iwl_trans_txq_scd_cfg cfg = { 1387 .fifo = fifo, 1388 .sta_id = -1, 1389 .tid = IWL_MAX_TID_COUNT, 1390 .frame_limit = IWL_FRAME_LIMIT, 1391 .aggregate = false, 1392 }; 1393 1394 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1395 } 1396 1397 static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1398 unsigned long txqs, 1399 bool freeze) 1400 { 1401 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1402 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1403 return; 1404 } 1405 1406 if (trans->ops->freeze_txq_timer) 1407 trans->ops->freeze_txq_timer(trans, txqs, freeze); 1408 } 1409 1410 static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 1411 bool block) 1412 { 1413 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1414 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1415 return; 1416 } 1417 1418 if (trans->ops->block_txq_ptrs) 1419 trans->ops->block_txq_ptrs(trans, block); 1420 } 1421 1422 static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1423 u32 txqs) 1424 { 1425 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1426 return -ENOTSUPP; 1427 1428 /* No need to wait if the firmware is not alive */ 1429 if (trans->state != IWL_TRANS_FW_ALIVE) { 1430 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1431 return -EIO; 1432 } 1433 1434 return trans->ops->wait_tx_queues_empty(trans, txqs); 1435 } 1436 1437 static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1438 { 1439 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1440 return -ENOTSUPP; 1441 1442 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1443 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1444 return -EIO; 1445 } 1446 1447 return trans->ops->wait_txq_empty(trans, queue); 1448 } 1449 1450 static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1451 { 1452 trans->ops->write8(trans, ofs, val); 1453 } 1454 1455 static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1456 { 1457 trans->ops->write32(trans, ofs, val); 1458 } 1459 1460 static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1461 { 1462 return trans->ops->read32(trans, ofs); 1463 } 1464 1465 static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1466 { 1467 return trans->ops->read_prph(trans, ofs); 1468 } 1469 1470 static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1471 u32 val) 1472 { 1473 return trans->ops->write_prph(trans, ofs, val); 1474 } 1475 1476 static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1477 void *buf, int dwords) 1478 { 1479 return trans->ops->read_mem(trans, addr, buf, dwords); 1480 } 1481 1482 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1483 do { \ 1484 if (__builtin_constant_p(bufsize)) \ 1485 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1486 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1487 } while (0) 1488 1489 static inline int iwl_trans_write_imr_mem(struct iwl_trans *trans, 1490 u32 dst_addr, u64 src_addr, 1491 u32 byte_cnt) 1492 { 1493 if (trans->ops->imr_dma_data) 1494 return trans->ops->imr_dma_data(trans, dst_addr, src_addr, byte_cnt); 1495 return 0; 1496 } 1497 1498 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1499 { 1500 u32 value; 1501 1502 if (iwl_trans_read_mem(trans, addr, &value, 1)) 1503 return 0xa5a5a5a5; 1504 1505 return value; 1506 } 1507 1508 static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1509 const void *buf, int dwords) 1510 { 1511 return trans->ops->write_mem(trans, addr, buf, dwords); 1512 } 1513 1514 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1515 u32 val) 1516 { 1517 return iwl_trans_write_mem(trans, addr, &val, 1); 1518 } 1519 1520 static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1521 { 1522 if (trans->ops->set_pmi) 1523 trans->ops->set_pmi(trans, state); 1524 } 1525 1526 static inline int iwl_trans_sw_reset(struct iwl_trans *trans, 1527 bool retake_ownership) 1528 { 1529 if (trans->ops->sw_reset) 1530 return trans->ops->sw_reset(trans, retake_ownership); 1531 return 0; 1532 } 1533 1534 static inline void 1535 iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1536 { 1537 trans->ops->set_bits_mask(trans, reg, mask, value); 1538 } 1539 1540 #define iwl_trans_grab_nic_access(trans) \ 1541 __cond_lock(nic_access, \ 1542 likely((trans)->ops->grab_nic_access(trans))) 1543 1544 static inline void __releases(nic_access) 1545 iwl_trans_release_nic_access(struct iwl_trans *trans) 1546 { 1547 trans->ops->release_nic_access(trans); 1548 __release(nic_access); 1549 } 1550 1551 static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync) 1552 { 1553 if (WARN_ON_ONCE(!trans->op_mode)) 1554 return; 1555 1556 /* prevent double restarts due to the same erroneous FW */ 1557 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1558 iwl_op_mode_nic_error(trans->op_mode, sync); 1559 trans->state = IWL_TRANS_NO_FW; 1560 } 1561 } 1562 1563 static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1564 { 1565 return trans->state == IWL_TRANS_FW_ALIVE; 1566 } 1567 1568 static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1569 { 1570 if (trans->ops->sync_nmi) 1571 trans->ops->sync_nmi(trans); 1572 } 1573 1574 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 1575 u32 sw_err_bit); 1576 1577 static inline int iwl_trans_load_pnvm(struct iwl_trans *trans, 1578 const struct iwl_pnvm_image *pnvm_data, 1579 const struct iwl_ucode_capabilities *capa) 1580 { 1581 return trans->ops->load_pnvm(trans, pnvm_data, capa); 1582 } 1583 1584 static inline void iwl_trans_set_pnvm(struct iwl_trans *trans, 1585 const struct iwl_ucode_capabilities *capa) 1586 { 1587 if (trans->ops->set_pnvm) 1588 trans->ops->set_pnvm(trans, capa); 1589 } 1590 1591 static inline int iwl_trans_load_reduce_power 1592 (struct iwl_trans *trans, 1593 const struct iwl_pnvm_image *payloads, 1594 const struct iwl_ucode_capabilities *capa) 1595 { 1596 return trans->ops->load_reduce_power(trans, payloads, capa); 1597 } 1598 1599 static inline void 1600 iwl_trans_set_reduce_power(struct iwl_trans *trans, 1601 const struct iwl_ucode_capabilities *capa) 1602 { 1603 if (trans->ops->set_reduce_power) 1604 trans->ops->set_reduce_power(trans, capa); 1605 } 1606 1607 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1608 { 1609 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1610 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1611 } 1612 1613 static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable) 1614 { 1615 if (trans->ops->interrupts) 1616 trans->ops->interrupts(trans, enable); 1617 } 1618 1619 /***************************************************** 1620 * transport helper functions 1621 *****************************************************/ 1622 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1623 struct device *dev, 1624 const struct iwl_trans_ops *ops, 1625 const struct iwl_cfg_trans_params *cfg_trans); 1626 int iwl_trans_init(struct iwl_trans *trans); 1627 void iwl_trans_free(struct iwl_trans *trans); 1628 1629 static inline bool iwl_trans_is_hw_error_value(u32 val) 1630 { 1631 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50); 1632 } 1633 1634 /***************************************************** 1635 * driver (transport) register/unregister functions 1636 ******************************************************/ 1637 int __must_check iwl_pci_register_driver(void); 1638 void iwl_pci_unregister_driver(void); 1639 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan); 1640 1641 #endif /* __iwl_trans_h__ */ 1642